JP2011257966A - Cache device and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a software error correction method exerting a little influence on the performance of a processor performing a pipeline processing.SOLUTION: A data array 43 stores data and a parity bit, and a check bit array 46 stores a ECC bit of the data. A parity check unit 44 acquires, by a read request from a processor 1, read object data and the parity bit thereof from the data array 43 to perform the parity check of the read object data using the parity bit. When detecting data error, the parity check unit outputs a stall command signal to command a pipeline stall to the processor 1. An error correction unit 47 acquires the ECC bit of the read object data from the check bit array 46 during the pipeline stall, corrects the error of the read object data using the ECC bit and outputs the read object data after the error correction and a stall cancel signal to command the cancel of the pipeline stall to the processor 1.

Description

  The present invention relates to a method of correcting a soft error in a cache device.

Utilizing the progress of miniaturization of semiconductor processes year by year, the microprocessor (hereinafter referred to as processor), which is the key of the information processing apparatus, has been increased in speed and functionality.
Specifically, for example,
1) Improvement of processor operating frequency by speeding up transistors and logic circuits by miniaturization of semiconductor processes,
2) Implementation of a cache device by increasing the number of transistors that can be mounted, increasing its capacity and stratification,
3) Pipelining of processing due to the advancement of processor architecture and increasing the number of stages,
Is the main technology for high performance

As described above, the miniaturization of the semiconductor process supports the speeding up of the processor, but the internal voltage of the processor is lowered due to the miniaturization, and the margin for noise from inside and outside the chip is reduced.
In particular, the SRAM (Static Random Access Memory) margin that constitutes the cache is reduced, it becomes vulnerable to noise, and the information (bits) held by the SRAM is inverted, and the information is likely to be erroneous. Yes. This is called a soft error.
Soft errors occur due to voltage fluctuations inside the chip and neutrons from space.
As described above, a cache is indispensable for improving the performance of a processor, and its capacity tends to increase.
In recent years, high-performance processors generally have caches at two levels, a primary cache and a secondary cache.
The primary cache is tightly coupled to the processor and must operate at high speed.
The primary cache is difficult to increase in capacity for high-speed operation.
Therefore, a structure is adopted in which data that does not enter the primary cache is received by the secondary cache.
The secondary cache operates at a lower speed than the primary cache and takes a long time to access from the processor, but has a large capacity and a high cache hit rate (ratio of the desired data in the cache).
Conventionally, there are techniques of parity check and ECC (Error Check and Correction) as measures for preventing the processor from malfunctioning when the primary cache and the secondary cache generate a soft error.

In the parity check, a redundant bit called a parity bit of 1 bit is added to a group of data of about 1 byte.
When the data or parity bit is inverted by 1 bit, the phenomenon (parity error) can be detected. However, it cannot be detected which bit is inverted.
The ECC adds a plurality of check bits (for example, 8 bits) to a group of data of about 8 bytes.
When the data or check bit is inverted by 1 bit, the phenomenon can be detected, the inverted bit can be detected, and the original data can be restored (error correction).
A general ECC method can correct a 1-bit error and detect a 2-bit error.
In this specification, the discussion regarding detection of 2-bit errors is not essential and will not be mentioned.
The parity check can only detect errors, but the circuit is simple and suitable for high-speed operation.
On the other hand, the ECC method is capable of error correction, but the circuit is complicated, error detection requires a longer time than parity check, and error correction requires more time, so it is suitable for high-speed operation. Absent.
However, a method of using a parity check for a primary cache requiring high speed and adding an ECC check bit to a secondary cache having a large capacity is common.
Furthermore, in Patent Document 1, in order to realize data restoration of the primary cache, both parity and ECC check bits are added to the primary cache, parity check is performed during normal primary cache access, and a parity error is detected. A method is described in which when ECC is detected, data of the ECC check bit is read and the data is restored.

Special table 2004-514184 gazette

However, since the primary cache is closely related to the processor pipeline, the parity check timing, parity bit generation timing, ECC check bit generation timing, and data restoration timing using the ECC check bits are pipelined. The performance and cost of the processor are affected depending on which stage of the processor is implemented.
Patent Document 1 does not describe this point.
The main object of the present invention is to realize a soft error correction method that has little influence on processor performance in a cache device used in a processor that performs pipeline processing.

The cache device according to the present invention includes:
A cache device that transmits and receives data to and from a processor that performs pipeline processing,
A data array for storing data along with parity bits;
A check bit array for storing ECC (Error Check and Correction) bits of data stored in the data array;
When there is a read request from the processor, a parity check is performed on the read target data that is the target of the read request using the parity bit of the read target data, and when a data error in the read target data is detected, A parity check unit that outputs a stall instruction signal for instructing the processor to install a pipeline;
When a data error in the read target data is detected by the parity check unit, error correction of the read target data is performed using the ECC bit of the read target data, and the read target data after the error correction and release of the pipeline installation are performed. And an error correction unit that outputs a stall release signal instructing to the processor.

In the present invention, when a data error is detected by a parity check, a stall instruction signal is output to stall the pipeline, and error correction using the ECC bits is performed.
The frequency of data errors is low, and data errors occur without providing a dedicated pipeline stage for reading ECC bits and correcting errors using ECC bits for infrequent data errors. Since the error correction is performed by stalling the pipeline only in some cases, it is possible to suppress an increase in the implementation cost of the processor and the complexity of the pipeline configuration, and the processor pipeline progresses efficiently in a situation where there is no data error. Can be made.

FIG. 3 illustrates a configuration example of an information processing apparatus according to Embodiment 1; FIG. 3 is a diagram illustrating a configuration example of a data primary cache according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of a data primary cache according to the first embodiment. FIG. 4 is a diagram illustrating a relationship among data, parity bits, and ECC check bits according to the first embodiment. FIG. 3 is a flowchart showing an example of a read operation of the data primary cache according to the first embodiment. FIG. 3 is a flowchart showing an example of a write operation of a data primary cache according to the first embodiment. The figure which shows the pipeline stage when the parity error does not generate | occur | produce in the read from the primary cache for data which concerns on Embodiment 1. FIG. The figure which shows the pipeline stage when the parity error generate | occur | produces in the read from the primary cache for data which concerns on Embodiment 1. FIG. The figure which shows the pipeline stage when the parity error does not generate | occur | produce in the write to the data primary cache which concerns on Embodiment 1. FIG. The figure which shows the pipeline stage when the parity error generate | occur | produces in the write to the data primary cache which concerns on Embodiment 1. FIG. FIG. 3 illustrates a configuration example of an information processing apparatus according to a second embodiment. FIG. 10 illustrates a configuration example of an information processing apparatus according to a third embodiment. FIG. 10 illustrates a configuration example of an information processing device according to a fourth embodiment.

  In the first to fourth embodiments, a processor pipeline configuration, a parity check related mechanism, and an ECC related mechanism for maximizing processor performance and minimizing cost will be described.

Embodiment 1 FIG.
The information processing apparatus according to the present embodiment will be described with reference to FIGS.
FIG. 1 shows a configuration example of an information processing apparatus 100 according to the present embodiment.

In FIG. 1, 1 is a processor, 2 is a memory, 3 is a primary cache for instructions, 4 is a primary cache for data, and 5 is a secondary cache for sharing instructions and data.
The processor 1 performs pipeline processing.
The memory 2 and the secondary cache 5 are added with an ECC check bit (hereinafter also referred to as an ECC bit) as a countermeasure against a soft error.
The instruction primary cache 3 adds only parity.
This is because the contents of the primary cache for instructions are not changed by a write from the processor, so that it is guaranteed that correct data is always stored in the memory 2.
Therefore, when a parity error is detected in the instruction primary cache 3, a correct instruction can be obtained by fetching the instruction from the memory 2.
On the other hand, the data primary cache 4 adds both a parity bit and an ECC check bit.
This is because the data primary cache 4 becomes different data from the secondary cache 5 and the memory 2 by rewriting data from the processor (at this time, this cache line is called a Dirty state). Even if the data is taken, correct data cannot be obtained, and the processor cannot continue processing correctly.
Therefore, an ECC check bit that can be corrected is added to a 1-bit error in the data primary cache.
However, if error detection is performed using ECC check bits, high-speed operation of the processor becomes difficult, so a parity bit that can detect a 1-bit error in a shorter time is also added.
The data primary cache 4 corresponds to an example of a cache device.

Next, a configuration example of the data primary cache 4 is shown in FIGS.
2 and 3 show the same primary cache for data 4, but FIG. 2 shows elements in the primary cache for data 4 when the processor 1 makes a read request to the primary cache for data 4. FIG. 3 shows the signal input / output relationship between elements in the data primary cache 4 when the processor 1 makes a write request to the data primary cache 4. Is shown.
Therefore, although the components shown in FIGS. 2 and 3 are the same, the direction of the signal line (the direction of the arrow) and the type of input / output signal are different between FIGS.
Note that signal lines that are not necessarily important in the description are not shown in FIGS. 2 and 3 in order to avoid overcomplicating the drawing.

2 and 3, 1 is a processor, 4 is a primary cache for data, and 5 is a secondary cache.
The data primary cache 4 includes a tag array 41, a hit determination unit 42, a data array 43, a reading unit 431, a writing unit 432, a parity check unit 44, a parity bit generation unit 45, a check bit array 46, a reading unit 461, and a writing unit. 462, an error correction unit 47, and an ECC bit generation unit 48.

  Of the components shown in FIG. 2 and FIG. 3, the main components will be described below.

The data array 43 stores data together with parity bits.
The check bit array 46 stores ECC bits of data stored in the data array 43.

When there is a read request from the processor 1 (FIG. 2), the parity check unit 44 receives the read target data that is the target of the read request and the parity bit of the read target data via the read unit 431 and the data array 43. To check the parity of the read target data using the parity bit.
If there is no data error in the read target data, the read target data is output to the processor 1.
On the other hand, when a data error in the read target data is detected, a stall instruction signal for instructing the pipeline installation to the processor 1 is output.
When the parity check unit 44 detects a data error in the read target data, the error correction unit 47 acquires the ECC bit of the read target data from the check bit array 46 via the reading unit 461 during the pipeline installation. Error correction of the read target data is performed using the ECC bit, and the read target data after the error correction and a stall release signal instructing release of the pipeline installation are output to the processor 1.

In addition, the parity check unit 44 merges data that is already stored in the data array 43 and is merged with the write target data that is the target of the write request when a write request is received from the processor 1 (FIG. 3). The target data and the parity bit of the merge target data are acquired from the data array 43 via the reading unit 431.
Then, the parity check unit 44 performs a parity check of the data to be merged using the parity bit.
If there is no data error in the merge target data, the merge target data is output to the writing unit 432 via the parity bit generation unit 45 and merged with the write target data.
On the other hand, when a data error in the merge target data is detected, a stall instruction signal for instructing the pipeline installation to the processor 1 is output.
When the parity check unit 44 detects a data error in the merge target data, the error correction unit 47 acquires the ECC bits of the merge target data from the check bit array 46 via the read unit 461 during the pipeline installation. Error correction of the data to be merged is performed using the ECC bits.
The parity bit generation unit 45 inputs data to be merged after error correction by the error correction unit 47 during pipeline installation, and generates parity bits.
Further, the parity check unit 44 confirms that there is no data error in the data to be merged using the parity bit generated by the parity bit generation unit 45 during the pipeline installation, and instructs the cancellation of the pipeline installation. Is output to the processor 1.
When the parity check unit 44 confirms that the data to be merged has no data error, the writing unit 432 merges the write target data and the merge target data into the data array 43 and merges with the write target data. The parity bit of the merge data with the target data is written to the data array 43.
The ECC bit generation unit 48 generates ECC bits of merge data of write target data and merge target data when the parity check unit 44 confirms that there is no data error in the merge target data.
The writing unit 462 writes the ECC bits of the merge data generated by the ECC bit generation unit 48 in the check bit array 46.

  Next, FIG. 4 shows the relationship between the data and parity bits stored in the data array 43 and the ECC check bits stored in the check bit array 46.

The data array 43 holds a plurality of lines.
For example, when the cache capacity is 32 KB and the cache line size is 32 bytes, 1K = 1024 cache lines are provided.
FIG. 4 shows one of them.
The line has a data portion and a parity bit portion.
In this example, one line = 32 bytes, and one byte (8 bits) has one parity bit.
A parity check for one byte of data can be executed by reading the corresponding parity bit.
In addition, an ECC check bit is provided corresponding to the line.
The check bit array 46 has 32 ECC check bits corresponding to each cache line.
An 8-bit ECC check bit is added to 8-byte (64-bit) data.
A method of correcting a 1-bit error and detecting a 2-bit error by having 8-bit check bits in 64-bit data is generally known.

Next, an operation example of the data primary cache 4 will be described.
First, the data primary cache read operation will be described.
FIG. 2 shows a signal input / output relationship in the data read operation, and FIG. 5 shows an operation flow in the data read operation.

When a read request is issued from the processor 1 together with an address (S101), the tag array 41 is read by the corresponding address, and the hit determination unit 42 determines whether or not the cache is hit (S102).
If there is no hit (in the case of a miss in S103), the data goes to the secondary cache 5 (S111).
If there is a hit (in the case of hit in S103), the address of the data array is input to the data array 43, the data is read out together with the parity bit from the reading unit 431, and the parity check unit 44 calculates the parity ( S104).
If no error (inversion of 1 bit) has occurred in the data (NO in S105), the data is sent to the processor 1 (S112).
If a parity error is detected as a result of the parity calculation (YES in S105), a signal (stall instruction signal) instructing pipeline installation is transmitted from the parity check unit 44 to the processor 1 (S106), and at the same time, an ECC check bit array 46 The address of the array is input to and the ECC check bit is read from the reading unit 461.
Then, the data including the 1-bit error and the ECC check bit are input to the error correction unit 47, the data is corrected by the error correction unit 47 (S107), and the corrected data is transmitted from the error correction unit 47 to the processor 1. (S108).
At the same time, the corrected data is input to the parity bit generation unit 45, and the correct parity is generated by the parity bit generation unit 45, and is written back to the data array 43 via the writing unit 432 (S109).
When these processes are completed, a stall release signal instructing the release of the pipeline installation is transmitted from the error correction unit 47 to the processor 1, and the pipeline installation is released (S110).

Next, a write operation to the data primary cache will be described.
FIG. 3 shows a signal input / output relationship in the data write operation, and FIG. 6 shows an operation flow in the data write operation.

When a write request is issued from the processor 1 together with an address and data (data to be written) (S201), the tag array 41 is read by the corresponding address, and the hit determination unit 42 determines whether or not the cache is hit. (S202).
If there is no hit (in the case of a miss in S203), the data is transmitted to the secondary cache 5 together with the address (S208).
If there is a hit (hit in S203), the address of the data array is input to the data array 43, the data (merging target data) is read out along with the parity bit from the reading unit 431, and the parity check unit 44 calculates the parity. Made.
This data (merging target data) is a group of data from the viewpoint of ECC including the address of the write data (write target data). In this example, the data is 8 bytes.
If no error (inversion of 1 bit) has occurred in the data (NO in S205), the data (merge target data) and the data to be written (write target data) are merged, and the merged data (merge data) ) Is generated by the parity bit generation unit 45, and the writing unit 432 writes the merged data and parity bits back to the data array 43 (S210).
Further, the ECC bit generation unit 48 generates an ECC check bit corresponding to the merged data (merge data).
In this example, since an ECC check bit of 8 bits is added to 64 bits, even if a 16-bit write request is sent from the processor 1, the data array 43 reads 64 bits, and 16-bit change data ( 8 bits of new ECC check bits are generated for the total 64-bit data (merge data) obtained by merging the write target data) and the original 48-bit data (merge target data).
The ECC check bit is written in the check bit array 46 by the writing unit 462 (S211).

When a parity error is detected in the parity check unit 44 (YES in S205), a signal (stall instruction signal) instructing pipeline installation is transmitted from the parity check unit 44 to the processor 1 (S206).
Then, the data from the check bit array 46 and the data array 43 is corrected once correctly by the error correction unit 47, and the parity bit generation unit 45 generates correct parity bits from the corrected data, and the writing unit 432 The corrected data and parity bits are written back to the data array 43 (S207).
The data (merging target data) is read again from the data array 43, and the parity check unit 44 performs a parity check (S204).
At this time, since a parity error is not detected (NO in S205), a stall release signal instructing release of the pipeline installation is transmitted from the parity check unit 44 to the processor 1, and the pipeline installation is released (S209).
Next, the corrected data in the data array 43 (merge target data) and the data from the processor to be written (write target data) are merged, and the parity bit for the merged data (merge data) is a parity bit generator. The data and parity bits generated at 45 and merged by the writing unit 432 are written back to the data array 43 (S210).
Further, the ECC bit generation unit 48 generates an ECC check bit corresponding to the merged data (merge data), and the writing unit 462 writes it back to the check bit array 46 (S211).

FIGS. 7 to 10 show the above operation applied to the pipeline operation.
The pipeline is assumed to have a four-stage structure of instruction fetch, instruction decode, execution (various functions such as data fetch are implemented according to the type of instruction), and data write.

FIG. 7 shows a case where no parity error occurred when reading from the data primary cache.
FIG. 8 shows a case where a parity error has occurred when reading from the data primary cache.
FIG. 9 shows a case where no parity error occurred when writing to the data primary cache.
FIG. 10 shows a case where a parity error has occurred when writing to the data primary cache.

In FIG. 7, the target instruction is a load instruction (LD instruction), hits the data primary cache 4, fetches data from the data primary cache 4, and stores it in the general-purpose register of the processor 1. To do.
At time = 1, the processor 1 fetches the LD instruction from the instruction primary cache 3, and at time = 2, determines that the instruction is an LD instruction.
At time = 3, the data primary cache 4 is hit, data is read from the data array 43, and the parity check unit 44 performs a parity check.
Since there is no parity error, pipeline stalls do not occur.
At time = 4, the processor 1 writes the data read from the data primary cache 4 to the general-purpose register.
In this example, since the pipeline stall does not occur, the subsequent instruction (instruction fetched at time = 2) also proceeds smoothly.

In FIG. 8, as in FIG. 7, the target instruction is a load instruction, hits the data primary cache 4, fetches data from the data primary cache 4, and To store.
However, it is assumed that there is an error (soft error) in the cache.
At time = 1, the processor 1 fetches the LD instruction from the instruction primary cache 3, and at time = 2, determines that the instruction is an LD instruction.
At time = 3, the data primary cache 4 is hit, data is read from the data array 43, and the parity check unit 44 performs a parity check.
Here, since there is an error in the cache and a parity error is detected, pipeline installation of the processor 1 occurs.
That is, this instruction stays at the data fetch stage, and the subsequent instruction (instruction fetched at time = 2) stops at the instruction decode stage.
At time = 4, the operation of the data primary cache 4 corresponding to this instruction reads the corresponding check bit from the check bit array 46, corrects the data using the check bit at time = 5, and transmits it to the processor 1. Release the stall.
At time = 6, this instruction writes data to the general-purpose register, and subsequent instructions execute the instruction execution stage.
Thus, in the case where there is an error in the cache, a pipeline stall occurs, and the performance of the processor decreases.
However, since the frequency of such errors is generally low enough, it does not affect system performance.
Rather, since there is no dedicated pipeline stage for ECC read or ECC correction, there is a great merit that the increase in the mounting cost and complexity of the processor can be suppressed.

In FIG. 9, the target instruction is a store instruction (ST instruction), hits the data primary cache 4 and stores the data of the general-purpose register in this cache.
At time = 1, the processor fetches the ST instruction from the instruction primary cache 3, and at time = 2, determines that the instruction is an ST instruction.
At time = 3, the data primary cache 4 is hit, data (merging target data) is read from the data array 43, and the parity check unit 44 performs a parity check.
Since there is no parity error, pipeline stalls do not occur.
At the same time, the general register data is read to generate a parity bit.
For example, if 8-bit data requires 1-bit parity, 2-bit parity bits may be generated when 16-bit data is written back to the cache.
Since the parity bit can be generated by XOR of 8 inputs and can be generated easily and at high speed, it can be generated at this stage.
On the other hand, for generation of ECC check bits, data is read from the data array, merged with data to be written (in this case, 16 bits of the general-purpose register), ECC check bits are generated and written back to the check bit array. Since many processes are required, a next stage (data write) and a next stage (ECC write) are provided so that these processes can be performed without stalling.
At time = 4, an ECC check bit is generated at the data write stage, and in parallel, the corresponding data and parity bit are written back to the primary cache.
At time = 5, the generated ECC check bits are written back to the check bit array 46 at a special stage of writing ECC check bits.
In this example, since the pipeline stall does not occur, the subsequent instruction (instruction fetched at time = 2) also proceeds smoothly.
Since the process of writing back the contents of the general-purpose register to the data primary cache is an event that frequently occurs in a normal program, smooth processing of subsequent instructions is essential for improving the performance of the information processing apparatus.
Therefore, it is reasonable to set a special stage at a high cost.

In FIG. 10, the target instruction is a store instruction, hits the data primary cache 4, and stores data in the general-purpose register in the data primary cache 4.
However, it is assumed that there is an error (soft error) in the cache.
In this case, the operation shown in FIG. 8 is combined with the operation shown in FIG.
At time = 1, the processor 1 fetches the ST instruction from the instruction primary cache 3, and at time = 2, determines that the instruction is an ST instruction.
At time = 3, the data primary cache 4 is hit, data (merging target data) is read from the data array 43, and the parity check unit 44 performs a parity check.
Here, since there is an error in the cache and a parity error is detected, pipeline installation of the processor 1 occurs.
At time = 4, the corresponding ECC check bit is read from the ECC check bit array.
At time = 5, the ECC check bits are used to correct the data, and the data is stored in the data array 43 together with the correct parity.
At time = 6, data is read from the data array 43 again, and the parity check unit 44 performs the parity check. This time, since the parity check does not result in a parity error, cancel the pipeline installation.
At time = 7, an ECC check bit is generated at the data write stage, and the corresponding data and parity bit are written back to the data primary cache 4 in parallel therewith.
At time = 8, the generated check bits are written back to the check bit array in a special ECC write stage.
Thus, as in FIG. 8, in the case where there is an error in the cache, a pipeline stall occurs and the performance of the processor decreases, but the frequency of occurrence of such an error is generally low enough, Does not affect system performance.
Rather, by making the processing equivalent to the read processing, the structure becomes simple, and it is possible to provide a low-cost and high-quality information processing apparatus.

Embodiment 2. FIG.
FIG. 11 shows an information processing apparatus 100 having another configuration.
The information processing apparatus 100 in FIG. 11 is configured not to have a secondary cache.
In FIG. 11, 1 is a processor, 2 is a memory, 3 is a primary cache for instructions, and 4 is a primary cache for data.
The memory 2 has an ECC check bit added as a countermeasure against soft errors.
The instruction primary cache 3 adds only parity bits.
The data primary cache 4 has both the parity bit and the ECC check bit added, and has the function described in the first embodiment.

Embodiment 3 FIG.
FIG. 12 shows an information processing apparatus 100 having another configuration.
The information processing apparatus 100 in FIG. 12 is configured to share the primary cache for instructions and data.
In FIG. 12, 1 is a processor, 2 is a memory, and 4 is an instruction / data shared primary cache.
The memory 2 has an ECC check bit added as a countermeasure against soft errors.
The instruction / data shared primary cache 4 has both the parity bit and the ECC check bit, and has the function described in the first embodiment.

Embodiment 4 FIG.
FIG. 13 shows an information processing apparatus 100 having another configuration.
The information processing apparatus 100 in FIG. 13 is an example of a multiprocessor.
In FIG. 13, 1 and 101 are processors, 2 is a memory, 3 and 103 are primary caches for instructions, 4 and 104 are primary caches for data, and 5 and 105 are secondary caches for sharing instructions and data. .
The memory 2 and the secondary caches 5 and 105 have an ECC check bit added as a countermeasure against soft errors.
Only the parity bit is added to the primary caches 3 and 103 for instructions.
The data primary caches 4 and 104 have both the parity bit and the ECC check bit added, and have the functions described in the first embodiment.

In the above first to fourth embodiments,
In a cache device that transmits and receives data to and from a processor,
(A) Data cache where data rewrite occurs (b) Has a bit to check data parity (c) Has a bit to check data ECC (d) Checks parity when data is read (E) having a means for stopping the processor pipeline when a parity error is detected;
(F) having means for reading out the ECC and restoring correct data from the ECC and the data read out in (d);
(G) having means for supplying the restored data to the processor;
(H) The information processing apparatus having means for releasing the suspension of the pipeline when the restored data is supplied to the processor has been described.

In the first to fourth embodiments,
(A) When the processor writes data back to the cache device, it has a function of generating parity of the data and writing back parity bits to the data,
(B) having a pipeline stage for sequentially reading all data from the processor cache line;
(C) having means for replacing the data to be written back as part of the data in the cache line;
(D) having means for recalculating the ECC;
(E) having means for writing back ECC;
(F) The information processing apparatus in which the above (c) to (e) are assigned to the pipeline stage has been described.

  1 processor, 2 memory, 3 instruction primary cache, 4 data primary cache, 5 secondary cache, 41 tag array, 42 hit determination unit, 43 data array, 44 parity check unit, 45 parity bit generation unit, 46 check Bit array, 47 error correction unit, 48 ECC bit generation unit, 100 information processing device, 431 reading unit, 432 writing unit, 461 reading unit, 462 writing unit.

Claims (8)

A cache device that transmits and receives data to and from a processor that performs pipeline processing,
A data array for storing data along with parity bits;
A check bit array for storing ECC (Error Check and Correction) bits of data stored in the data array;
When there is a read request from the processor, a parity check is performed on the read target data that is the target of the read request using the parity bit of the read target data, and when a data error in the read target data is detected, A parity check unit that outputs a stall instruction signal for instructing the processor to install a pipeline;
When a data error in the read target data is detected by the parity check unit, error correction of the read target data is performed using the ECC bit of the read target data, and the read target data after the error correction and release of the pipeline installation are performed. A cache device, comprising: an error correction unit that outputs a stall release signal instructing to the processor. The error correction unit is
The cache device according to claim 1, wherein during pipeline installation, error correction is performed on read target data, and the read target data after error correction is transmitted to the processor. A cache device that transmits and receives data to and from a processor that performs pipeline processing,
A data array for storing data along with parity bits;
A check bit array for storing ECC bits of data stored in the data array;
When there is a write request from the processor, the parity bit of the merge target data with respect to the merge target data merged with the write target data that is already stored in the data array and is the target of the write request A parity check unit that outputs a stall instruction signal for instructing the pipeline installation to the processor when a data error in the data to be merged is detected.
An error correction unit that performs error correction of the merge target data using an ECC bit of the merge target data when a data error of the merge target data is detected by the parity check unit;
A parity bit generation unit that generates parity bits of merge target data after error correction,
The parity check unit
A cache device characterized by confirming that there is no data error in the data to be merged using the parity bit generated by the parity bit generation unit, and outputting a stall release signal instructing release of pipeline installation to the processor . The error correction unit is
During the pipeline installation, using the ECC bit of the merge target data, error correction of the merge target data is performed,
The parity bit generator is
During the pipeline installation, the parity bit of the data to be merged after error correction is generated,
The parity check unit
4. The cache device according to claim 3, wherein during the pipeline installation, it is confirmed that there is no data error in the data to be merged using the parity bit generated by the parity bit generation unit. The cache device further includes:
When the parity check unit confirms that there is no data error in the merge target data, the write target data and the merge target data are merged and written to the data array, and the write target data and the merge target data are merged. 5. The cache device according to claim 3, further comprising a writing unit that writes a parity bit of data to the data array. The cache device further includes:
An ECC bit generation unit that generates an ECC bit of merge data between the write target data and the merge target data when the parity check unit confirms that there is no data error in the merge target data;
The writing unit
The cache device according to claim 5, wherein ECC bits of merge data generated by the ECC bit generation unit are written in the check bit array. The writing unit
In a pipeline stage provided for writing ECC bits of merge data to the check bit array, the ECC bits of merge data generated by the ECC bit generation unit are written to the check bit array. The cache device according to claim 6.   An information processing apparatus comprising the cache device according to claim 1.

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