JP2011244200A - Delta/sigma modulation apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct an offset voltage while suppressing current consumption and noise in a well balanced manner.SOLUTION: The present invention relates to a delta/sigma modulation apparatus including: sampling circuits (111a and 111b) for alternately repeating charging sampling capacitors (C1 P and C1 N9) in accordance with input voltages (vin1 and vin2) thereto and discharging charges accumulated in the sampling capacitors; offset correction voltage generating circuits (102a and 102b) for alternately repeating variable capacitors (C3 P and C3 N) in accordance with a reference voltage thereto and discharging charges accumulated in the variable capacitors; an integration circuit 113 for accumulating the charges accumulated in the sampling capacitors and the charges accumulated in the variable capacitors into integration capacitors (C2 P and C2 N); a quantizer for quantizing an output voltage of the integration circuit; digital/analog converters (105a and 105b) for performing digital/analog conversion on a quantized signal outputted from the quantizer and feeding it back to an input of the integration circuit; and a control circuit.

Description

  The present invention relates to a delta-sigma modulation device.

  The delta-sigma modulation apparatus obtains a difference (delta) between a signal (analog signal) obtained by digital-analog conversion of an analog input signal and a digital output signal, quantizes a signal obtained by integrating (sigma) the difference, and converts the digital output signal to Configured to generate. The delta-sigma modulator is a technology that achieves high accuracy by oversampling and noise shaping based on the above configuration, and is also effective in terms of low power consumption and miniaturization. A switching amplifier, an analog-digital converter, Alternatively, it is widely applied to the field of analog / digital mixed circuits such as digital / analog converters.

  By the way, the offset voltage (DC component) is superimposed on the analog input signal of the delta-sigma modulator due to various factors, and unexpected phenomena such as noise occurring in the low frequency band of the digital output signal or its demodulated signal. Will occur. Therefore, in order to correct the offset voltage in the delta-sigma modulation device, for example, a technique disclosed in Patent Document 1 has been proposed. Hereinafter, the configuration for correcting the offset voltage in the digital switching amplifier disclosed in Patent Document 1 using FIG. 8 corresponding to FIG. 1 of Patent Document 1 and FIG. 9 corresponding to FIG. 2 of Patent Document 1 will be described. The operation will be described.

  FIG. 8 corresponds to FIG. 1 of Patent Document 1, and is a block diagram showing a configuration of a digital switching amplifier including a conventional delta-sigma modulation device.

  The digital switching amplifier 10 shown in FIG. 8 includes an offset voltage addition adjustment unit 9 to correct an offset voltage generated between the output terminals 8P and 8M. Specifically, at the time of inspection immediately after manufacturing, the analog acoustic signal S5P and the analog acoustic signal S5M are in a state where the input terminal 4 is in a no-signal state (a state where the level of the input signal S1 is 0) or the input terminal 4 is grounded. The level difference (offset voltage) is detected. When the offset voltage is detected, the contact position of the semi-fixed resistor VR (see FIG. 9) of the offset voltage addition adjustment unit 9 is adjusted in the direction in which the offset voltage is canceled. As a result, an offset correction voltage for canceling the offset voltage is added to the differential input voltage composed of the pair of the input signal S1P and the input signal S1M having opposite polarities, and the differential input voltage is applied to the subtracters 5P and 5M. By inputting, an offset voltage generated between the output terminals 8P and 8M can be corrected.

  FIG. 9 corresponds to FIG. 2 of Patent Document 1, and is a circuit diagram showing a configuration of a circuit for correcting an offset voltage in the digital sigma modulation device shown in FIG.

When the input signal S1 is input to the inverting input terminals of the operational amplifiers 9a and 9b, the offset voltage addition adjusting unit 9 receives an input signal S1P and an input signal S1M having opposite polarities from the output terminals of the operational amplifiers 9a and 9b. Output toward the subtracters 5P and 5M. Note that voltages VB1 and VB2 across the semi-fixed resistor VR are supplied to the non-inverting input terminals of the operational amplifiers 9a and 9b, respectively. As a result, the operational amplifier 9a adds the voltage VB2 to the signal obtained by inverting and amplifying the input signal S1 supplied to the inverting input terminal via the resistor, and outputs it to the subtractor 5P. Further, the operational amplifier 9b adds the voltage VB1 to the inverted signal of the output signal of the operational amplifier 9a supplied to the inverting input terminal via the resistor, and outputs it to the subtracter 5M. Note that both ends of the semi-fixed resistor VR are connected to the analog voltage VDA via the fixed resistor R1 and to the reference voltage or the ground terminal via the fixed resistor R2. Since the voltages VB1 and VB2 change based on the contact position of the semi-fixed resistor VR when the resistance values of the fixed resistors R1 and R2 are constant, the output terminal 8P is changed by changing the contact position of the semi-fixed resistor VR. , The offset voltage generated during 8M is corrected.
Japanese Patent No. 3779196

  In the offset voltage addition adjusting unit 9 shown in FIG. 9, the non-inverting input terminals of the operational amplifiers 9a and 9b are provided for correcting the offset voltage from a resistance voltage dividing circuit including fixed resistors R1 and R2 and a semi-fixed resistor VR. Voltages VB1 and VB2 are supplied. According to this configuration, thermal noise is generated in each of the resistors constituting the resistor voltage dividing circuit, and as a result, noise superimposed on the output signals 8P and 8M output from the output terminals 8P and 8M is increased. There is. In order to suppress this noise, the resistance value of each resistor constituting the resistance voltage dividing circuit may be reduced. On the other hand, if the resistance value is reduced, the entire delta-sigma modulation device including the offset voltage addition adjusting unit 9 is reduced. There arises a new problem that current consumption (power consumption) increases. That is, by providing a resistor, a trade-off relationship is established between noise and current consumption.

  Furthermore, the offset voltage addition adjusting unit 9 shown in FIG. 9 is also problematic in that it is premised on a configuration including two operational amplifiers 9a and 9b with large current consumption. Note that the consumption current of the operational amplifier may be provided in the first stage of the apparatus, and is about several tens to a hundred μA, and therefore occupies a large proportion of the consumption current of the entire delta-sigma modulation apparatus.

  As described above, the conventional delta-sigma modulation device having the function of correcting the offset voltage includes a resistor that contributes to noise in the configuration for correcting the offset voltage, so that noise and current consumption are balanced. There was a problem that it was difficult to suppress. In addition, since it is premised on a configuration including two operational amplifiers for correcting the offset voltage, there is a limit to suppressing the current consumption of the entire delta-sigma modulation device.

  The present invention solves the above-described conventional problems, and an object thereof is to provide a delta-sigma modulation device capable of correcting an offset voltage while suppressing noise and current consumption in a well-balanced manner.

  In order to achieve the above object, a delta-sigma modulation device according to the present invention includes a sampling capacitor and a sampling switch. When an input voltage is input, the sampling switch switches the sampling capacitor to the sampling capacitor. A sampling circuit configured to alternately repeat charge charging according to the input voltage and discharging of the charge accumulated in the sampling capacitor, a variable capacitor, and an offset correction switch. When the reference voltage for generation is input, the charge of the variable capacitor according to the reference voltage and the discharge of the charge accumulated in the variable capacitor are alternately repeated by switching the offset correction switch. An offset correction voltage generation circuit configured as An operational amplifier and an integration capacitor provided between an input side and an output side of the operational amplifier, and the charge accumulated in the sampling capacitor and the charge accumulated in the variable capacitor are stored in the integration capacitor. An integration circuit that accumulates and generates an output voltage as a voltage between both electrodes of the integration capacitor, a quantizer that generates a quantized signal obtained by quantizing the output voltage of the integration circuit, and the quantizer A digital-to-analog converter that converts the output quantized signal from digital to analog and feeds it back to an input side of the operational amplifier of the integration circuit; and a control circuit that controls switching of the sampling switch and the offset correction switch; .

  According to this configuration, in a so-called discrete delta-sigma modulation device including a sampling circuit configured by a switched capacitor and an integration circuit, the same as the sampling circuit is used to correct the offset voltage generated in the input voltage. Is provided with an offset correction voltage generation circuit constituted by a switched capacitor. The offset correction voltage generation circuit has a simple and small-scale configuration with a variable capacitor and a switch, and it is not necessary to provide a resistor that contributes to noise, and it is necessary to consider the trade-off relationship between noise and current consumption. Disappear. Further, the offset correction voltage generation circuit does not assume the configuration of an operational amplifier that consumes a current of several tens to hundreds of μA, but generally assumes the configuration of a switched capacitor of 1 μA or less. The current is greatly improved. In the case of a discrete delta-sigma modulation device using a switched capacitor, since the entire transfer function is based on the capacitance ratio, it becomes a relative variation rather than an absolute variation, so that noise is greatly improved.

  In the delta-sigma modulation device, the input voltage includes a first input voltage and a second input voltage, and the sampling circuit includes a first sampling capacitor and a first sampling switch, When the first input voltage is input, the charge of the first sampling capacitor according to the first input voltage and the first sampling are switched by the switching of the first sampling switch. A first sampling circuit configured to alternately repeat the discharge of the charge accumulated in the capacitor for sampling, a second sampling capacitor, and a second sampling switch, wherein the second input voltage is When input, the switching to the second sampling capacitor causes the switching to the second sampling capacitor. A second sampling circuit configured to alternately repeat charge charging according to the input voltage of 2 and discharging of the charge accumulated in the second sampling capacitor, and generating the offset correction voltage The circuit includes a first variable capacitor and a first offset correction switch. When a reference voltage for generating an offset correction voltage is input, the first offset correction switch is switched to switch the first offset capacitor. A first offset correction voltage generating circuit configured to alternately repeat charging of the variable capacitor according to the reference voltage and discharging of the charge accumulated in the first variable capacitor; When a reference voltage for generating an offset correction voltage is input, a variable capacitor and a second offset correction switch are provided. The second switch is configured to alternately repeat charging of the charge according to the reference voltage to the second variable capacitor and discharging of the charge accumulated in the second variable capacitor by switching of the correction switch. An offset correction voltage generation circuit, and the integration circuit includes a differential operational amplifier having an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal, and the non-inverting output terminal. A first integrating capacitor provided between the inverting input terminal and a second integrating capacitor provided between the inverting output terminal and the non-inverting input terminal; The electric charge accumulated in the sampling capacitor and the electric charge accumulated in the first variable capacitor are accumulated in the first integrating capacitor, and between the electrodes of the first integrating capacitor. A first output voltage is generated as a voltage, and the charge accumulated in the second sampling capacitor and the charge accumulated in the second variable capacitor are accumulated in the second integration capacitor, The second output voltage may be generated as a voltage between both electrodes of the second integrating capacitor.

  According to this configuration, it is possible to correct the offset voltage generated between the first input voltage and the second input voltage while suppressing current consumption and noise in a well-balanced manner.

  In the delta-sigma modulation device, the first input voltage and the second input voltage may be differential input voltages having different polarities.

  According to this configuration, since the input level (dynamic range) is doubled and the noise is √2 times by using the differential input voltage, the S / N ratio is increased (the variation is small and stabilized). can do.

  The delta-sigma modulation device may include a filter that performs a predetermined filtering process on the first input voltage, and the second input voltage may be an output voltage of the filter.

  According to this configuration, desired filter characteristics (such as a low-pass characteristic, a high-pass characteristic, or a band-pass characteristic) can be realized, and an offset voltage caused by the filter can be corrected.

  In the delta-sigma modulation device, the input voltage is a single-ended voltage, and when the single-ended voltage is input to the sampling circuit, the sampling capacitor is charged with electric charge according to the single-ended voltage. The offset correction voltage generation circuit includes a first variable capacitor and a first offset correction switch, and is configured to alternately and repeatedly discharge the charge accumulated in the sampling capacitor. When the reference voltage for input is input, the charge of the first variable capacitor according to the reference voltage is charged and stored in the first variable capacitor by the switching of the first offset correction switch. First offset correction voltage generation configured to alternately repeat discharge of charge Path, a second variable capacitor, and a second offset correction switch. When a reference voltage for generating an offset correction voltage is input, the second offset correction switch is switched to switch the second offset correction switch. A second offset correction voltage generation circuit configured to alternately repeat charging of the charge according to the reference voltage to the variable capacitor and discharging of the charge accumulated in the second variable capacitor; The integrating circuit includes a single-ended operational amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal, and an integrating capacitor provided between the non-inverting output terminal and the inverting input terminal. The charge accumulated in the sampling capacitor, the charge accumulated in the first variable capacitor, and the charge accumulated in the second variable capacitor. Load is accumulated in the integration capacitor, the output voltage as a voltage between both electrodes of the integrating capacitor is produced may be.

  According to this configuration, when the input voltage is a single-ended voltage, the offset voltage generated in the single-ended voltage can be corrected while suppressing current consumption and noise in a well-balanced manner.

  The delta-sigma modulation device may include a filter that performs a predetermined filter process on the input voltage, and the input voltage input to the sampling circuit may be an output voltage of the filter.

  According to this configuration, desired filter characteristics (such as a low-pass characteristic, a high-pass characteristic, or a band-pass characteristic) can be realized, and an offset voltage caused by the filter can be corrected.

  ADVANTAGE OF THE INVENTION According to this invention, the delta-sigma modulation apparatus which can correct | amend the offset voltage which generate | occur | produces in an input voltage can be provided, suppressing consumption current and noise with sufficient balance.

FIG. 1 is a block diagram showing the configuration of the delta-sigma modulation apparatus according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a switched capacitor type adder and integrator and an offset correction voltage generation circuit of the delta sigma modulation apparatus of FIG. FIG. 3A is a circuit diagram showing the configuration of the variable capacitor of one of the offset correction voltage generation circuits shown in FIG. FIG. 3B is a circuit diagram showing the configuration of the variable capacitor of the other offset correction voltage generation circuit shown in FIG. FIG. 4 is a block diagram showing a configuration of a delta-sigma modulation apparatus according to the second embodiment of the present invention. FIG. 5 is a block diagram showing a configuration of a delta-sigma modulation apparatus according to the third embodiment of the present invention. FIG. 6 is a circuit diagram showing a configuration of a switched capacitor type adder and integrator and an offset correction voltage generation circuit of a delta-sigma modulation apparatus according to the third embodiment of the present invention. FIG. 7 is a block diagram showing a configuration of a delta-sigma modulation apparatus according to the fourth embodiment of the present invention. FIG. 8 is a block diagram showing a configuration of a digital switching amplifier including a conventional delta-sigma modulation device. FIG. 9 is a circuit diagram showing a configuration of a circuit for correcting an offset voltage in the digital sigma modulation apparatus shown in FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference symbols throughout the drawings, and redundant description thereof is omitted.
(First embodiment)
[Configuration of Delta-Sigma Modulator]
FIG. 1 is a block diagram showing the configuration of the delta-sigma modulation apparatus according to the first embodiment of the present invention.

  A delta-sigma modulation apparatus 100 shown in FIG. 1 is realized as an analog / digital mixed circuit including an input terminal 120a, an input terminal 120b, an output terminal 122, and voltage input terminals 125a and 125b, or an integrated circuit thereof. It is mounted on an analog-digital converter or a digital-analog converter.

  A differential input voltage composed of input voltages vin1 and vin2 having opposite polarities is input to the input terminals 120a and 120b. When the system input is a single-ended voltage, a single differential converter (not shown) is connected in front of the input terminals 120a and 120b, and input voltages vin1 and vin2 are generated in the single differential converter. The

  From the output terminal 122, one or a plurality of bits of a quantized signal Dout obtained by delta-sigma modulation of the input voltages vin1 and vin2 by the delta-sigma modulation circuit 101 is output. The quantized signal Dout is input to a subsequent circuit such as a digital filter circuit (not shown) connected to the output terminal 122 to perform a predetermined process.

  An offset correction reference voltage Vref for generating an offset correction voltage is input to the voltage input terminals 125a and 125b, respectively. The offset correction reference voltage Vref is supplied to the offset correction voltage generation circuits 102a and 102b.

  The delta sigma modulation device 100 includes a delta sigma modulation circuit 101, offset correction voltage generation circuits 102a and 102b, and a control circuit 110.

  The delta-sigma modulation circuit 101 employs a time-discrete architecture using a switched capacitor sampling circuit, and includes a switched capacitor adder / integrator 103, a quantizer 104, and a D / A converter. 105a and a D / A converter 105b.

  The switched capacitor type adder and integrator 103 is an adder constituted by a sampling capacitor, a switched capacitor comprising a sampling switch for charging / discharging the sampling capacitor, and an operational amplifier. And an integrator. The switched capacitor type adder / integrator 103 adds an analog signal (inverse characteristics of the input voltage vin1) output from the D / A converter 105a to the input voltage vin1 input to the input terminal 120a. The offset correction voltage generated by the offset correction voltage generation circuit 102a is added, and the output voltage vout1 obtained by integrating the result is generated. A similar calculation is performed on the input voltage vin2 input to the input terminal 120b, and an output voltage vout2 corresponding to the input voltage vin2 is generated.

  The quantizer 104 receives the output voltages vout1 and vout2 of the switched capacitor adder and integrator 103, and outputs a quantized signal Dout obtained by quantizing them. For example, in the case of 1-bit output, “1” is output when the voltage between the output voltage vout1 and the output voltage vout2 exceeds a predetermined threshold, and “0” is output when the voltage is lower than the predetermined threshold.

  The D / A converters 105 a and 105 b convert the quantized signal Dout output from the quantizer 104 from digital to analog, and feeds back the result to the switched capacitor adder and integrator 103.

  The offset correction voltage generation circuits 102a and 102b generate an offset correction voltage based on the offset correction reference voltage Vref input to the voltage input terminals 125a and 125b, and use the offset correction voltage as a switched capacitor adder of the delta-sigma modulation circuit 101. And to the integrator 103.

The control circuit 110 controls the entire delta-sigma modulation device 100. In particular, the control circuit 110 generates a clock signal that defines the operation timing of the offset correction voltage generation circuits 102 a and 102 b and the delta sigma modulation circuit 101, and supplies the clock signal to the offset correction voltage generation circuits 102 a and 102 b and the delta sigma modulation circuit 101. To do.
[Configuration of Switched Capacitor Type Adder, Integrator and Offset Correction Voltage Generation Circuit]
FIG. 2 is a circuit diagram showing the configuration of the switched capacitor adder / integrator 103 and the offset correction voltage generation circuits 102a and 102b shown in FIG.

  The switched capacitor adder / integrator 103 includes a sampling circuit 111a, a sampling circuit 111b, and an integration circuit 113.

  The sampling circuit 111a is configured by a switched capacitor including a sampling capacitor C1P and sampling switches SW1a to SW4a for charging / discharging the sampling capacitor C1P. The sampling switch SW1a is a switch that controls application of a power supply voltage to one electrode of the sampling capacitor C1P. The sampling switch SW2a is a switch that controls electrical connection between one electrode of the sampling capacitor C1P and the inverting input terminal of the differential operational amplifier 114. The sampling switch SW3a is a switch that controls application of the power supply voltage to the other electrode of the sampling capacitor C1P. The sampling switch SW4a is a switch that controls application of the input voltage vin1 to the other electrode of the sampling capacitor C1P. The pair of sampling switches SW1a and SW4a and the pair of sampling switches SW2a and SW3a are complementarily turned on / off (switched) based on a clock signal having a predetermined frequency (sampling frequency) supplied from the control circuit 110. The By this switching operation, the charge according to the input voltage vin1 to the sampling capacitor C1P and the discharge of the charge accumulated in the sampling capacitor C1P are alternately repeated.

  The sampling circuit 111b includes a switched capacitor including sampling switches SW1a to SW4a and a sampling capacitor C1N. The sampling switch SW1a is a switch that controls application of a power supply voltage to one electrode of the sampling capacitor C1N. The sampling switch SW2a is a switch that controls the electrical connection between one electrode of the capacitor C1N and the non-inverting input terminal of the differential operational amplifier 114. The sampling switch SW3a is a switch that controls application of the power supply voltage to the other electrode of the sampling capacitor C1N. The sampling switch SW4a is a switch that controls application of the input voltage vin2 to the other electrode of the sampling capacitor C1N. The sampling switches SW1a to SW4a of the sampling circuit 111b are turned on and off in synchronization with the sampling switches SW1a to SW4a having the same sign of the sampling circuit 111a. By this switching operation, the charge according to the input voltage vin2 to the sampling capacitor C1N and the discharge of the charge accumulated in the sampling capacitor C1N are alternately repeated.

  The integrating circuit 113 includes a differential operational amplifier 114 having an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal, an integrating capacitor C2P, and an integrating capacitor C2N. Yes. The integration capacitor C2P has one electrode electrically connected to the non-inverting output terminal of the differential operational amplifier 114 and the other electrode electrically connected to the inverting input terminal of the differential operational amplifier 114. ing. The integration capacitor C2N has one electrode electrically connected to the inverting output terminal of the differential operational amplifier 114, and the other electrode electrically connected to the non-inverting input terminal of the differential operational amplifier 114. ing.

  The offset correction voltage generation circuit 102a includes a switched capacitor including a variable capacitor C3P and offset correction switches SW1b to SW4b for charging / discharging the variable capacitor C3P. The offset correction switch SW1b is a switch that controls application of a power supply voltage to one electrode of the variable capacitor C3P. The offset correction switch SW2b is a switch that controls electrical connection between one electrode of the variable capacitor C3P and the inverting input terminal of the differential operational amplifier 114. The offset correction switch SW3b is a switch that controls application of the power supply voltage to the other electrode of the variable capacitor C3P. The offset correction switch SW4b is a switch that controls application of the offset correction reference voltage Vref to the other electrode of the variable capacitor C3P. The offset correction switches SW1b to SW4b of the offset correction voltage generation circuit 102b are turned on and off in synchronization with the sampling switches SW1a to SW4a having the same sign of the sampling circuit 111a. By this switching operation, charge according to the offset correction reference voltage Vref to the variable capacitor C3P and discharge of the charge accumulated in the variable capacitor C3P are alternately repeated.

  The variable capacitor C3P is realized by the configuration shown in FIG. That is, the capacitor C3Pk and the capacitance selection switch SWPk (k = 1 to N) are connected in parallel between the switches SW2 and SW4, and at least one of the capacitance selection switches SWPk is connected according to the offset correction voltage to be generated. Configured to turn on.

  The offset correction voltage generation circuit 102b includes a switched capacitor including a variable capacitor C3N and offset correction switches SW1b to SW4b for charging / discharging the variable capacitor C3N. The offset correction switch SW1b is a switch that controls application of a power supply voltage to one electrode of the variable capacitor C3N. The offset correction switch SW2b is a switch that controls electrical connection between one electrode of the variable capacitor C3N and the inverting input terminal of the differential operational amplifier 114. The offset correction switch SW3b is a switch that controls application of the power supply voltage to the other electrode of the variable capacitor C3N. The offset correction switch SW4b is a switch that controls application of the offset correction reference voltage Vref to the other electrode of the variable capacitor C3N. The offset correction switches SW1b to SW4b of the offset correction voltage generation circuit 102b are turned on and off in synchronization with the sampling switches SW1a to SW4a having the same sign of the sampling circuit 111a. By this switching operation, charging of the charge according to the offset correction reference voltage Vref to the variable capacitor C3N and discharging of the charge accumulated in the variable capacitor C3N are alternately repeated.

The variable capacitor C3N has the same configuration as the variable capacitor C3P shown in FIG.
[Operation of Switched Capacitor Type Adder and Integrator and Offset Correction Voltage Generation Circuit]
Hereinafter, the operations of the switched capacitor adder / integrator 103 and the offset correction voltage generation circuits 102a and 102b illustrated in FIG. 2 will be described using mathematical expressions.

  In the following description, it is assumed that the capacitances of the sampling capacitors C1P and C1N, the integration capacitors C2P and C2N, and the variable capacitors C3P and C3N are represented by respective symbols.

  In addition, the power supply voltage connected to the sampling switches SW1a and SW3a of the sampling circuits 111a and 111b is not considered for simplification of description.

  Further, assuming that “n” represents the current state, “n−1 / 2”, which will be described later, represents a state before the ½ sampling period, and “n−1”, which will be described later, represents one sampling period. It shall represent the previous state. For example, taking sampling switches SW1a and SW2a that are complementarily turned on and off as an example, if sampling switch SW1a is currently on and sampling switch SW2a is off, sampling switch SW1a is off and sampled immediately before that. The state in which the sampling switch SW2a is on is “n−1 / 2”, and the state in which the sampling switch SW1a is on and the sampling switch SW2a is off just before is “n−1”.

  First, when the sampling switches SW1a and SW4a and the offset correction SW1b and SW4b) are on and the sampling switches SW2a and SW3a and the offset correction SW2b and 3b are off, the charge Q1P accumulated in the sampling capacitors C1P and C1N , Q1N, the capacitors Q2P and Q2N accumulated in the integrating capacitors C2P and C2N, and the charges Q3P and Q3N accumulated in the variable capacitors C3P and C3N are expressed by the following equations.

Q1P = C1P · vin1 (n−1 / 2) (Formula 1)
Q1N = C1N · vin2 (n−1 / 2) (Formula 2)
Q2P = C2P · vout1 (n−1) (Formula 3)
Q2N = C2N · vout2 (n−1) (Formula 4)
Q3P = C3P · Vref (Formula 5)
Q3N = C3N · Vref (Formula 6)
Next, when the sampling switches SW1a and SW4a and the offset correction switches SW1b and SW4b are turned off and the sampling switches SW2a and SW3a and the offset correction switches SW2b and SW3b are turned on, the integration is performed according to the law of charge conservation. The charge Q2P (n) accumulated in the capacitor C2P is obtained by adding the charge Q1P accumulated in the sampling capacitor C1P and the charge Q3P accumulated in the variable capacitor C3P, and is expressed by the following equation.

Q2P (n) = Q1P + Q3P
= C1P · vin1 (n−1 / 2) + C3P · Vref (Expression 7)
Similarly, the charge Q2N (n) accumulated in the integrating capacitor C2N at this time is the sum of the charge Q1N accumulated in the sampling capacitor C1N and the charge Q3N accumulated in the variable capacitor C3N. expressed.

Q2N (n) = Q1N + Q3N
= C1N · vin2 (n−1 / 2) + C3N · Vref (Equation 8)
Further, when the output voltages vout1 and vout2 at this time are expressed as vout1 (n) and vout2 (n), respectively, (Expression 7) and Expression (8) are respectively expressed by the following expressions.

Q2P (n) = C2P · vout1 (n) (Formula 9)
Q2N (n) = C2N · vout2 (n) (Equation 10)
Therefore, based on (Equation 7) and (Equation 9), the output voltage vout1 (n) can be derived as the following equation.

Q2P (n) = C2P.vout1 (n) = C1P.vin1 (n-1 / 2) + C3P.Vref (Formula 11)
vout1 (n) = (C1P · vin1 (n−1 / 2) + C3P · Vref) / C2P (Equation 12)
Similarly, the output voltage vout2 (n) can be derived from the following equation based on (Equation 8) and (Equation 10).

Q2N (n) = C2N.vout2 (n) = C1N.vin2 (n-1 / 2) + C3N.Vref (Equation 13)
vout2 (n) = (C1N · vin2 (n−1 / 2) + C3N · Vref) / C2N (Expression 14)
As described above, while the sampling switches SW1a and SW4a and the offset correction switches SW1b and SW4b are on and the sampling switches SW2a and SW3a and the offset correction switches SW2b and 3b are off, the input voltage is applied to the sampling capacitor C1P. A charge Q1P corresponding to the difference between vin1 and the power supply voltage is accumulated, and a charge Q1N corresponding to the difference between the power supply voltage and the input voltage vin2 is accumulated in the sampling capacitor C1N.

  When the sampling switches SW1a and SW4a and the offset correction switches SW1b and SW4b are turned off and the sampling switches SW2a and SW3a and the offset correction switches SW2b and SW3b are turned on, the charge Q1P accumulated in the sampling capacitor C1P is The charge Q1N stored in the sampling capacitor C1N is transferred to the integration capacitor C2P and stored therein.

  By repeatedly performing such sampling processing and integration processing, the output voltage Vout1 becomes a voltage obtained by integrating the input voltage vin1 according to the accumulation of charge in the integration capacitor C2P, and the output voltage vout2 is integrated. The input voltage vin2 becomes an integrated voltage in accordance with the accumulation of electric charges in the capacitor C2N.

  Here, suppose that the offset voltage of the DC component is between the input voltage vin1 (n−1 / 2) input to the input terminal 120a and the input voltage vin2 (n−1 / 2) input to the input terminal 120b. Assume that Voff has occurred. The input voltage vin2 (Voff) in this case is expressed by the following equation.

vin2 (Voff) = vin2 (n−1 / 2) −Voff (Equation 15)
Here, (Equation 15) is applied to “vin2 (n−1 / 2)” in (Equation 8) regarding the charge Q2N (n) accumulated in the integrating capacitor C2N, and the following equation is considered.

C1N · (vin2 (n−1 / 2) −Voff) + C3N · Vref = C1N · vin2 (n−1 / 2) (Expression 16)
If the equation of (Expression 16) is established, the offset voltage Voff generated between the input voltage vin1 (n−1 / 2) and the input voltage vin2 (n−1 / 2) can be removed. It can be seen that the capacitance of the variable capacitor C3N should be selected so that the equation (16) is established. Note that the capacitance of the variable capacitor C3N is expressed by the following equation when (Equation 16) is modified.

C3N = C1N · Voff / Vref (Expression 17)
The method for selecting the capacitance of the variable capacitor C3N is to measure the DC offset voltage when the delta-sigma modulation device 100 is in the no-input state and to cancel the measured offset voltage as shown in FIG. At least one of the selection switches SWNk (k = 1 to N) is turned on. When the offset voltage is known, at least one of the capacitance selection switches SWNk (k = 1 to N) may be turned on in advance based on the offset voltage.

  As described above, according to the present embodiment, even when an offset voltage is generated between the input voltages vin1 and vin2 of the delta-sigma modulation apparatus 100, the offset correction voltage generation circuit 102 configured by a switched capacitor is a small scale. The offset voltage can be corrected by adding a simple circuit. Then, by correcting the offset voltage, it is possible to suppress the decrease in the dynamic range of the input bandwidth and the deterioration of the distortion characteristics caused by the offset voltage.

  In addition, according to the present embodiment, the offset correction voltage generation circuits 102a and 102b have a simple and small-scale configuration using a variable capacitor and a switch, and it is not necessary to provide a resistor that contributes to noise, and noise and current consumption. There is no need to consider the trade-off relationship between The offset correction voltage generation circuits 102a and 102b do not assume the configuration of an operational amplifier that consumes a current of several tens to hundreds of μA, but generally assume the configuration of a switched capacitor of 1 μA or less. Therefore, the entire delta-sigma modulation apparatus 100 The current consumption is greatly improved.

  In addition, according to the present embodiment, in the case of the discrete delta-sigma modulation device 100 using a switched capacitor, the transfer function of the entire system is based on the capacitance ratio of the switched capacitor, so that relative variation is not absolute variation. Therefore, the noise is greatly improved.

  In addition, according to the present embodiment, the offset correction voltage generation circuits 102a and 102b are configured by a simple and small-scale switched capacitor including a variable capacitor and an offset correction switch, so that the discrete delta-sigma modulation device 100 is configured. The switched capacitor type adder and integrator 103 used in the present invention have good affinity, and current consumption and noise can be suppressed in a better balance than in the past.

Further, according to the present embodiment, it is possible to correct an offset voltage even for a delta-sigma modulation device that is not equipped with a digital filter having an offset voltage correction function.
(Second Embodiment)
FIG. 4 is a block diagram showing a configuration of a delta-sigma modulation apparatus according to the second embodiment of the present invention. The delta sigma modulation device shown in the figure is intended for a single-ended voltage vin as compared to the delta sigma modulation device according to the first embodiment of the invention shown in FIG. The difference is that the single-ended voltage vin and the voltage filtered by the filter 106 are input thereto. In this configuration, when a desired filter characteristic (such as a low-pass characteristic, a high-pass characteristic, or a band-pass characteristic) is obtained for the output voltages vout1 and vout2 of the switched capacitor type adder and integrator 103, an offset correction voltage is generated. The circuits 102a and 102b can correct the offset voltage caused by the filter 106.
(Third embodiment)
[Configuration of Delta-Sigma Modulator]
FIG. 5 is a block diagram showing a configuration of a delta-sigma modulation apparatus according to the third embodiment of the present invention. The delta sigma modulation device 100 shown in the figure is intended for a single-ended voltage vin as compared with the delta sigma modulation device according to the first embodiment of the invention shown in FIG. Is different in that only this input voltage vin is input. Another difference is that only one D / A converter 105 is provided.
[Configuration of Switched Capacitor Type Adder, Integrator and Offset Correction Voltage Generation Circuit]
FIG. 6 is a circuit diagram showing a configuration of the switched capacitor type adder, integrator and offset correction voltage generation circuit shown in FIG.

  The switched capacitor adder / integrator 103 includes a sampling circuit 111 and an integration circuit 113. The configuration of the sampling circuit 111 is configured by a switched capacitor similar to the sampling circuit 111a shown in FIG. The integrating circuit 113 includes a single-ended operational amplifier 115 and an integrating capacitor C2P. The integration capacitor C2P has one electrode electrically connected to the output terminal of the operational amplifier 115 and the other electrode electrically connected to the inverting input terminal of the operational amplifier 115.

The configuration of the offset correction voltage generation circuit 102a is configured by a switched capacitor similar to the offset correction voltage generation circuit 102a shown in FIG. The offset correction voltage generation circuit 102c is also configured by a switched capacitor similar to the offset correction voltage generation circuit 102a shown in FIG. 2, but the positions of the offset correction switches SW3b and SW4b are switched with respect to the variable capacitor C4P. ing. That is, in the offset correction voltage generation circuit 102c, the offset correction switch SW3b is a switch that controls the application of the offset correction reference voltage Vref to the other electrode of the variable capacitor C4P, and the offset correction switch SW4b is the switch of the variable capacitor C4P. The switch controls the application of the power supply voltage to the other electrode.
[Operation of Switched Capacitor Type Adder and Integrator and Offset Correction Voltage Generation Circuit]
Hereinafter, the operations of the switched capacitor adder / integrator 103 and the offset correction voltage generation circuits 102a and 102c shown in FIG. 5 will be described using mathematical expressions.

  First, the charge accumulated in the sampling capacitor C1P when the sampling switches SW1a and SW4a and the offset correction switches SW1b and SW4b are on and the sampling switches SW2a and SW3a and the offset correction switches SW2b and SW3b are off. Q1P, the charge Q2P stored in the integrating capacitor C2P, and the charges Q3P and Q4P stored in the variable capacitors C3P and C4P are respectively expressed by the following equations.

Q1P = C1P · vin1 (n−1 / 2) (Equation 18)
Q2P = C2P · vout1 (n−1) (Equation 19)
Q3P = C3P · Vref (Equation 20)
Q4P = 0 (Formula 21)
Next, when the sampling switches SW1a and SW4a and the offset correction switches SW1b and SW4b are off and the sampling switches SW2a and SW3a and the offset correction switches SW2b and SW3b are on, based on the law of charge conservation, The charge Q4P stored in the variable capacitor C4P and the charge Q2P (n) stored in the integrating capacitor C2P are expressed by the following equations.

Q4P = −C4P · Vref (Equation 22)
Q2P (n) = Q1P + Q3P + Q4P
= C1P.vin1 (n-1 / 2) + C3P.Vref-C4P.Vref (Equation 23)
When the output voltage vout at this time is expressed as vout (n), the charge Q2P (n) accumulated in the capacitor C2P is expressed by the following equation.

Q2P (n) = C2P · vout (n) (Equation 24)
Based on (Equation 23) and (Equation 24), the output voltage vout (n) can be derived as follows.

Q2P (n) = C2P.vout (n) = C1P.vin1 (n-1 / 2) + C3P.Vref-C4P.Vref (Equation 25)
vout (n) = (C1P · vin1 (n−1 / 2) + C3P · Vref−C4P · Vref) / C2P (Equation 26)
Here, it is assumed that the DC offset voltage Voff is superimposed on the input voltage vin (n−1 / 2) input to the input terminal 120. Then, the input voltage vin (Voff) at this time is expressed by the following equation.

vin (Voff) = vin (n−1 / 2) + Voff (Equation 27)
Here, (Equation 27) is applied to “vin1 (n−1 / 2)” of (Equation 23) regarding the charge Q2P (n) accumulated in the capacitor C2P, and the following equation is considered.

C1P * (vin1 (n-1 / 2) + Voff) + C3P * Vref-C4P * Vref = C1P * vin1 (n-1 / 2) (Equation 28)
That is, if the equation of (Equation 28) is established, the offset voltage Voff generated in the input voltage vin1 (n−1 / 2) can be removed, so that the equation of (Equation 28) is variable. It can be seen that the capacitances of the capacitors C3P and C4P may be selected.

  Note that the capacitances of the variable capacitors C3P and C4P are expressed by the following equation when (Equation 28) is modified.

C3P−C4P = C1P · Voff / Vref (Equation 29)
That is, the offset voltage Voff can be corrected regardless of the polarity (positive or negative) of the offset voltage Voff by appropriately selecting the capacitances of the variable capacitors C3P and C4P that satisfy the equation (Equation 29).
(Fourth embodiment)
FIG. 7 is a block diagram showing a configuration of a delta-sigma modulation apparatus according to the fourth embodiment of the present invention. Compared with the delta sigma modulation apparatus according to the third embodiment of the present invention shown in FIG. 5, the delta sigma modulation apparatus shown in FIG. The difference is that the voltage subjected to the filtering process is input. In this configuration, when a desired filter characteristic (such as a low-pass characteristic, a high-pass characteristic, or a band-pass characteristic) is obtained for the output voltages vout1 and vout2 of the switched capacitor adder and integrator 103, an offset correction voltage is generated. The circuits 102a and 102c can correct the offset voltage caused by the filter 106.

  INDUSTRIAL APPLICABILITY The present invention is useful for a discrete delta-sigma modulation device that requires low power consumption and high accuracy.

SW1a to SW4a Sampling switches SW1b to SW4b Offset correction switch 100... Delta sigma modulator,
101: Delta-sigma modulation circuit,
102: Offset correction voltage generation circuit,
102a ... Offset correction voltage generation circuit (first offset correction voltage generation circuit)
102b ... Offset correction voltage generation circuit (second offset correction voltage generation circuit)
102c ... Offset correction voltage generation circuit (second offset correction voltage generation circuit)
DESCRIPTION OF SYMBOLS 103 ... Switched capacitor type adder and integrator 104 ... Quantizer 105, 105a, 105b ... D / A converter 106 ... Filter 110 ... Control circuit 111 ... Sampling circuit 111a ... Sampling circuit (1st sampling circuit)
111b ... Sampling circuit (second sampling circuit)
113 ... Integral circuit 114 ... Differential operational amplifier 115 ... Single-end operational amplifier 120, 120a, 120b ... Input terminal 122 ... Output terminals 125, 125a, 125b, 125c ... Voltage input terminal C1P ... Sampling capacitor (first Sampling capacitor)
C1N: Capacitor for sampling (second sampling capacitor)
C2P ... capacitor for integration (first capacitor for integration)
C2N: Integration capacitor (second integration capacitor)
C3P: Variable capacitor (first variable capacitor)
C3N: Variable capacitor (second variable capacitor)
C4P ... Variable capacitor (second variable capacitor)

Claims (6)

A sampling capacitor and a sampling switch are provided. When an input voltage is input, the sampling switch is switched and charged according to the input voltage to the sampling capacitor and stored in the sampling capacitor. A sampling circuit configured to alternately repeat the discharge of the charged charge,
When a reference voltage for generating an offset correction voltage is input, charge of the variable capacitor according to the reference voltage is charged and the variable capacitor is charged by the switching of the offset correction switch. An offset correction voltage generation circuit configured to alternately repeat the discharge of the charge accumulated in the variable capacitor;
An operational amplifier and an integration capacitor provided between an input side and an output side of the operational amplifier, and the charge accumulated in the sampling capacitor and the charge accumulated in the variable capacitor are stored in the integration capacitor. An integrating circuit that accumulates and generates an output voltage as a voltage between both electrodes of the integrating capacitor;
A quantizer for generating a quantized signal obtained by quantizing the output voltage of the integrating circuit;
A digital-to-analog converter that converts the quantized signal output from the quantizer to digital-to-analog and feeds back to the input side of the operational amplifier of the integration circuit;
A control circuit for controlling switching of the sampling switch and the offset correction switch;
A delta-sigma modulator. The input voltage includes a first input voltage and a second input voltage,
The sampling circuit is
A first sampling capacitor and a first sampling switch, and when the first input voltage is input, the switching of the first sampling switch causes the first sampling capacitor to switch to the first sampling capacitor; A first sampling circuit configured to alternately repeat charging of electric charge according to a first input voltage and discharging of electric charge accumulated in the first sampling capacitor;
A second sampling capacitor and a second sampling switch; when the second input voltage is input, the second sampling switch is switched to switch the second sampling capacitor to the second sampling capacitor; A second sampling circuit configured to alternately repeat charging of electric charge according to a second input voltage and discharging of electric charge accumulated in the second sampling capacitor;
The offset correction voltage generation circuit includes:
When a reference voltage for generating an offset correction voltage is input, the first variable capacitor is switched to the first variable capacitor by switching the first offset correction switch. A first offset correction voltage generation circuit configured to alternately repeat charge charging according to the reference voltage and discharge of charge accumulated in the first variable capacitor;
When a reference voltage for generating an offset correction voltage is input, the second variable capacitor and the second offset correction switch are input to the second variable capacitor by switching of the second offset correction switch. A second offset correction voltage generation circuit configured to alternately repeat charging of the electric charge according to the reference voltage and discharging of the electric charge accumulated in the second variable capacitor,
The integration circuit includes:
A differential operational amplifier having an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal, and a first integration provided between the non-inverting output terminal and the inverting input terminal A capacitor, and a second integrating capacitor provided between the inverting output terminal and the non-inverting input terminal,
The charge accumulated in the first sampling capacitor and the charge accumulated in the first variable capacitor are accumulated in the first integration capacitor, and are used as a voltage between both electrodes of the first integration capacitor. A first output voltage is generated;
In addition, the charge accumulated in the second sampling capacitor and the charge accumulated in the second variable capacitor are accumulated in the second integration capacitor, and between the electrodes of the second integration capacitor. A second output voltage is generated as a voltage;
The delta-sigma modulation device according to claim 1.   The delta-sigma modulation device according to claim 2, wherein the first input voltage and the second input voltage are differential input voltages having different polarities. A filter that performs a predetermined filtering process on the first input voltage;
The delta-sigma modulation device according to claim 2, wherein the second input voltage is an output voltage of the filter. The input voltage is a single-ended voltage;
The sampling circuit is
When the single-ended voltage is input, the charging according to the single-ended voltage to the sampling capacitor and the discharging of the charge accumulated in the sampling capacitor are alternately repeated,
The offset correction voltage generation circuit includes:
When a reference voltage for generating an offset correction voltage is input, the first variable capacitor is switched to the first variable capacitor by switching the first offset correction switch. A first offset correction voltage generation circuit configured to alternately repeat charge charging according to the reference voltage and discharge of charge accumulated in the first variable capacitor;
When a reference voltage for generating an offset correction voltage is input, the second variable capacitor and the second offset correction switch are input to the second variable capacitor by switching of the second offset correction switch. A second offset correction voltage generation circuit configured to alternately repeat charging of the electric charge according to the reference voltage and discharging of the electric charge accumulated in the second variable capacitor,
The integration circuit includes:
A single-ended operational amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal, and an integrating capacitor provided between the non-inverting output terminal and the inverting input terminal,
The charge accumulated in the sampling capacitor, the charge accumulated in the first variable capacitor, and the charge accumulated in the second variable capacitor are accumulated in the integration capacitor, and between the electrodes of the integration capacitor. Output voltage is generated as
The delta-sigma modulation device according to claim 1. A filter that performs a predetermined filtering process on the input voltage;
The delta-sigma modulation device according to claim 5, wherein the input voltage input to the sampling circuit is an output voltage of the filter.

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