JP2011244191A - Drive unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent shoot-through (through state) between an upper side transistor and a lower side transistor, even when there are variations in a driving circuit and the transistors, and the drive duty component of a PWM drive signal is small.SOLUTION: This drive unit includes a sink circuit to sinkingly output a driving current to the control terminal of a switching device in accordance with the second level or the first level signal of an input terminal, a current sinking transistor to sink a capacitive current through the control terminal during OFF period of the switching device, an I/F circuit to generate the input driving signal of a source circuit and an input driving signal to the sink circuit or the sink transistor in accordance with the signal of the input terminal, a selector for selecting either of the sink circuit or the sink transistor to which the input driving signal to the sink circuit or the sink transistor is output as the input driving signal, and the input terminal to receive a selecting signal to the selector for controlling the selecting operation.

Description

  The present invention relates to a driving device for a switching device mounted on a semiconductor integrated circuit device, and more particularly to a driving device for driving a switching device in which a capacitive current flows in a control terminal during an off period of the switching device. It is.

  FIG. 4 shows a high-voltage half-bridge circuit using a conventional switching device drive circuit. Such a conventional driving apparatus is described in Patent Document 1.

  This half-bridge circuit has a lower drive circuit DL for driving the lower transistor T2 of the high-voltage half-bridge circuit, and an upper drive circuit DU for driving the upper transistor T1. The driving circuits DL and DU turn on / off the transistors T1 and T2 and sink the capacitive current from the transistor control terminal and the second stage sink transistor. Has M1. The sink transistor M1 prevents one of the transistors T1 and T2 from being turned on undesirably by the capacitive current, and the output voltage fluctuation of the half-bridge circuit. Do not raise the value to a high level that could cause serious electromagnetic interference. This has the effect of preventing shoot-through and minimizing the electromagnetic interference level.

  Before that, the shoot-through of the half-bridge circuit will be described with reference to FIGS. 5A, 5B, 6A, and 6B. Shoot-through is between the upper power supply (VM) connected to T1 and the lower power supply (GND) connected to T2 when the upper transistor T1 and the lower transistor T2 of the half-bridge circuit are simultaneously turned on. In this description, a through current state is also shown as another name because a large current flows through. In this description, a large current flowing between the VM and the GND through the T1 and T2 is referred to as a through current.

First, the cause of the shoot-through when the load current is output from the OUT terminal output of the half-bridge circuit will be described with reference to FIGS. 5A and 5B.
FIGS. 5A and 5B are diagrams for explaining the operation when the load current is output from the OUT terminal which is the output of the half-bridge circuit. In FIGS. 5A and 5B, each block is shown to explain the operation state. And a block diagram showing a connection state of the load connected to the OUT terminal, an input / output signal of each block, and a load current flow, and a timing waveform diagram of each input signal, output signal, and load current. .

  The block diagram of FIG. 5A is almost the same as the half-bridge circuit using the drive circuit of the conventional invention of FIG. 4. However, in the block diagram of FIG. 5A, blocks unnecessary for explanation of shoot-through are omitted. ing.

  Further, in drawing the timing waveform diagram of FIG. 5B, the upper drive circuit DU and the lower drive circuit DL have sufficient current capability and can control the slew rate of the output voltage at the OUT terminal. The timing waveform diagram is drawn on the assumption that there is an ability to control. This is an assumption set to facilitate the explanation of the movement of the gate currents IGU and IGL at the gate terminals which are the control terminals of the upper transistor T1 and the lower transistor T2 which are switching devices. In reality, such an assumption cannot be made, and for this purpose, a conventional driving circuit as described in Patent Document 1 has been devised.

  The series of periodic operations of the half-bridge circuit from when the half-bridge circuit receives the drive signal of the periodic input signal to the source output of the load current from the OUT terminal output is the block diagram of FIG. 5A and the timing waveform of FIG. 5B. It is illustrated in the figure. As a result, it can be understood how the output voltage OUT and the load current of the OUT terminal are acted on and output from the drive signal having the periodicity, and the description on this point is omitted.

  In order to explain the cause of the shoot-through (penetration state) between the transistors T1 and T2, the gate currents IGU and IGL need to be explained in a series of periodic operations of the half-bridge circuit. This point will be described below.

First, the gate current IGU of the upper transistor T1 in the block diagram of FIG. 5A will be described.
The gate current IGU shown in FIG. 5B in the timing waveform diagram of FIG. 5B is generated by the upper drive circuit DU by the upper transistor T1 due to the rising edge of the signal GUD delayed by the delay time DT from the rising edge of the driving signal of the half-bridge circuit. The current output to the gate terminal of the transistor T1 in order to set the gate voltage GU of the transistor to H level. When the half-bridge circuit sources the load current from the OUT terminal output, the transistor T1 drives the OUT output, so that the gate current value and the capacitance value of the capacitance CT1 between the gate and drain of the transistor T1 The rising slew rate of the terminal output voltage is determined.

  Similarly, the gate current IGU shown in (f) of the timing waveform diagram is generated by the upper drive circuit DU by the upper transistor T1 due to the falling edge of the signal GUD delayed by the delay time DT from the falling edge of the driving signal of the half-bridge circuit. Current to be sucked from the gate terminal of the transistor T1 in order to set the gate voltage GU of the transistor T1 to L level. When the half-bridge circuit sources the load current from the OUT terminal output, the transistor T1 drives the OUT output. Therefore, the gate current value and the capacitance value of the capacitor CT1 between the gate and drain of the transistor T1 The falling slew rate of the OUT terminal output voltage is determined.

Next, the gate current IGL of the lower transistor T2 shown in the block diagram of FIG. 5A will be described.
The gate current IGL shown in FIG. 5A in the timing waveform diagram of FIG. 5B is driven by the lower drive circuit DL on the lower side by the signal GLD falling from the H level to the L level in response to the rising edge of the drive signal of the half bridge circuit. This current is drawn from the gate terminal of the transistor T2 in order to set the gate voltage GL of the transistor T2 to L level.

  Similarly, the gate current IGL in (b) of the timing waveform diagram is a current that flows from the gate terminal of the transistor T2 into the lower drive circuit DL when the output voltage OUT of the OUT terminal rises during the off period of the transistor T2. It is. This current is a capacitive current whose current value is determined by the rising slew rate of the output voltage OUT and the capacitance value of the capacitance CT2 between the gate and drain of the transistor T2. If the sink current capability of the lower drive circuit DL is low with respect to this current value, the gate voltage GL of the transistor T2 is swung to the H level side, and a shoot-through in which a through current flows between the transistors T1 and T2 occurs. There is a fear.

  Similarly, in the timing waveform diagram, the gate current IGL of (c) flows from the lower drive circuit DL to the gate terminal of the transistor T2 when the output voltage OUT of the OUT terminal falls during the OFF period of the transistor T2. Current. This current is a capacitive current whose current value is determined by the output voltage OUT falling slew rate and the capacitance value of the capacitance CT2 between the gate and drain of the transistor T2. If the source current capability of the lower drive circuit DL is low with respect to this current value, the gate voltage GL of the transistor T2 will fall below the GND level, but for this reason, no through current will flow between the transistors T1 and T2. .

  Similarly, in the timing waveform diagram, the gate current IGL of (d) is driven by the lower side by the rising edge of the signal GLD which is delayed from the falling edge of the driving signal of the half-bridge circuit by the time twice the delay time DT. This is a current output by the circuit DL so as to set the gate voltage GL of the transistor T2 to the H level.

Next, the cause of the shoot-through when the load current is sinked to the OUT terminal output of the half-bridge circuit will be described with reference to FIGS. 6A and 6B.
6A and 6B are diagrams for explaining the operation when the load current is sinked to the OUT terminal which is the output of the half-bridge circuit. In FIGS. 6A and 6B, the same as in FIGS. 5A and 5B. In order to explain the operation state, each block, the input / output signal of each block, the connection state of the load connected to the OUT terminal, and the flow of the load current, and each of the input / output signal and load Current timing waveform diagram.

  In FIG. 6A, for the same purpose as in FIG. 5A, it is assumed that the half-bridge circuit using the driving circuit of the conventional invention of FIG. 4 is omitted. The contents of the explanation are omitted because they are explained in FIG. 5A.

  Similar to the case where the load current is output from the OUT terminal, which is the output of the half-bridge circuit of FIG. 5A, the cause of the shoot-through (through state) of the transistors T1 and T2 is described in the half-bridge circuit. In a series of periodic operations, the gate currents IGU and IGL need to be explained. This point will be described below.

  First, the gate current IGL of the lower transistor T2 in the block diagram of FIG. 6A will be described. The gate current IGL shown in (g) in the timing waveform diagram of FIG. 6B is driven by the lower drive circuit DL on the lower side by the signal GLD falling from the H level to the L level in response to the rising edge of the drive signal of the half bridge circuit. This current is drawn from the gate terminal of the transistor T2 in order to set the gate voltage GL of the transistor T2 to L level. When the half-bridge circuit sinks the load current to the OUT terminal output, the T2 drives the OUT output, so the output of the OUT terminal is determined by this gate current value and the capacitance value of the capacitance CT2 between the gate / drain of T2. The rising slew rate of the voltage is determined.

  Similarly, in the timing waveform diagram, the gate current IGL in (h) is driven by the lower side by the rising edge of the signal GLD delayed by a time twice the delay time DT from the falling edge of the driving signal of the half bridge circuit. This is a current output by the circuit DL so as to set the gate voltage GL of the transistor T2 to the H level. When the half-bridge circuit sinks the load current to the OUT terminal output, the T2 drives the OUT output, so that the gate current value and the capacitance value of the capacitance CT2 between the gate and the drain of T2 The falling slew rate of the terminal output voltage is determined.

Next, the gate current IGU of the upper transistor T1 shown in the block diagram of FIG. 6A will be described.
The gate current IGU shown in (i) in the timing waveform diagram of FIG. 6B is generated when the output voltage OUT of the OUT terminal rises during the off-period of the transistor T1, thereby causing the gate terminal of the transistor T1 from the upper drive circuit DU. Current flowing into the This gate current is a capacitive current whose current value is determined by the output voltage OUT rising slew rate and the capacitance value of the gate-drain capacitance CT1 of the transistor T1. If the source current capability of the upper drive circuit DU is low with respect to this current value, the differential voltage GU-OUT between the gate voltage GU and the OUT output voltage of the transistor T1 will fall below 0V. Therefore, between the transistors T1 and T2 Through current does not flow.

  Similarly, the gate current IGU shown in (j) in the timing waveform diagram is generated when the upper drive circuit DU gates the upper transistor T1 by the rising edge of the signal GUD delayed by the delay time DT from the rising edge of the driving signal of the half-bridge circuit. This is a current output from the source to the gate terminal of the transistor T1 in order to set the voltage GU to the H level.

  Similarly, the gate current IGU indicated by (k) in the timing waveform diagram is generated by the upper drive circuit DU by the upper transistor T1 due to the falling edge of the signal GUD delayed by the delay time DT from the falling edge of the driving signal of the half-bridge circuit. Current to be drawn from the gate terminal of the transistor T1 in order to set the gate voltage GU of the transistor T1 to L level.

  Similarly, the gate current IGU shown in (1) in the timing waveform diagram is generated when the output voltage OUT of the OUT terminal falls during the OFF period of the transistor T1, so that the lower drive circuit DU from the gate terminal of the transistor T1. Current flowing into the This current is a capacitive current whose current value is determined by the rising slew rate of the output voltage OUT and the capacitance value of the gate-drain capacitance CT1 of the transistor T1. If the sink current capability of the upper drive circuit DU is low with respect to this current value, the differential voltage GU-OUT between the gate voltage GU and the OUT output voltage of the transistor T1 is swung to the H level side, and between the transistors T1 and T2. There is a possibility that a shoot-through through current will occur.

  As can be seen from the above description, when the load current is output from the output of the OUT terminal of the half-bridge circuit, the output voltage OUT of the OUT terminal rises during the OFF period of the transistor T2, so that the gate of the transistor T2 is output. The gate current IGL in FIG. 5B flowing from the terminal to the lower drive circuit DL becomes a problem. If the sink current capability of the lower drive circuit DL is low due to this current, the gate voltage GL of the transistor T2 is swung to the H level side, and a shoot-through in which a through current flows between the transistors T1 and T2 may occur. Because there is.

  When sinking the load current to the OUT terminal output of the half-bridge circuit, the output voltage OUT at the OUT terminal falls during the OFF period of the transistor T1, so that the upper drive circuit DU is supplied from the gate terminal of the transistor T1. The gate current IGU of (l) in FIG. If the sink current capability of the upper drive circuit DU is low due to this current, the gate voltage GU of the transistor T1 is swung to the H level side, which may cause a shoot-through in which a through current flows between the transistors T1 and T2. Because.

  The cause of the shoot-through of the half-bridge circuit has been described above. Next, with respect to this problem, a half-bridge circuit using the drive circuit of the conventional invention is loaded from the output terminal OUT of FIGS. 5A and 5B. This is considered when current is output as a source.

  According to the operation mechanism of the drive circuit of the conventional invention, when the logical product (and) of the following two conditions is satisfied, the sink transistor M1 having a high sink current capability of the drive circuit operates.

(1) For the drive circuit DL, the input signal GLD is at L level.
(2) (For the drive circuit DU, the input signal GUD is at the L level.)
(3) The gate terminal voltage GL of the lower transistor T2 is lower than the threshold voltage VthL set lower than the operating voltage VGson of the transistor T2. (For the drive circuit DU, the gate terminal voltage GU-OUT of the upper transistor T1 is lower than the threshold voltage VthL set lower than the operating voltage VGson of the transistor T1.)
Therefore, the capacitive gate current IGL of the transistor T2 in the case of FIG. 5B (b) is sunk by the sink transistor M1 of the lower drive circuit DL, and the gate terminal voltage GL of the transistor T2 is set to a sufficiently low L level. Therefore, even in the case of FIG. 5B (b), the shoot through (through state) by the transistors T1 and T2 does not occur.

  On the other hand, the sink transistor M1 of the upper drive circuit DU does not operate because it does not satisfy all the conditions (1) and (2). Thanks to this, the gate current IGU of the upper drive circuit DU that determines the slew rate of the output terminal voltage OUT of the half-bridge circuit shown in FIG. 5A is the upper drive while the output terminal voltage OUT transitions between VM and 0V. Setting according to a desired slew rate value is possible without being affected by the sink transistor M1 of the circuit DU.

  Next, a half-bridge circuit using the drive circuit of the conventional invention will be considered when the load current is sink-inputted to the output terminal OUT of FIGS. 6A and 6B.

  Also in this case, the capacitive gate current IGU of the transistor T1 in the case of (l) in FIG. 6B is the sink of the upper drive circuit DU, as in the above description when the load current is source-outputted from the output terminal OUT. Since the differential voltage GU-OUT between the gate terminal voltage GU of the transistor T1 and the output voltage OUT is maintained at a sufficiently low L level by being sunk by the transistor M1, the transistors T1 and T2 also in the case of (l) in FIG. 6B. No shoot-through due to (through state) occurs.

  On the other hand, the sink transistor M1 of the lower drive circuit DL does not operate because it does not satisfy all the conditions (1) and (2). Thanks to this, the gate current IGL of the lower drive circuit DL that determines the slew rate of the output terminal voltage OUT of the half-bridge circuit shown in FIG. 6A is lower during the transition of the output terminal voltage OUT between VM and 0V. The setting can be made in accordance with a desired slew rate value without being influenced by the sink transistor M1 of the side drive circuit DL.

  As described above, in the half-bridge circuit using the conventional driving circuit, it is possible to set the slew rate of the output voltage to a desired value, thereby preventing the occurrence of a serious electromagnetic interference. In addition, there is an effect that the upper transistor T1 and the lower transistor T2 can be prevented from being shot through (through state).

JP-A-3-3415

  However, in the half-bridge circuit using the conventional drive circuit, when the drive signal that is the PWM input signal of the half-bridge circuit is small (that is, the drive duty component of the PWM drive signal is small), the upper transistor T1 and the lower transistor There arises a problem that a shoot-through (through state) with the transistor T2 may occur. This problem will be described below.

7A, 7B, and 7C and FIGS. 8A, 8B, and 8C are diagrams for explaining this problem.
FIGS. 7A, 7B, and 7C correspond to those related to the possibility of shoot-through due to the gate current IGL of the lower transistor T2 in FIG. 5A and FIG. 5B, and show only that portion. It is. In particular, FIG. 7A shows a case where a load current is discharged from the OUT terminal. FIG. 7B shows a state where the load current is large and the VGSon of T2 is large, and the current sink stage transistor M2 operates and sinks IGL, so that T2 does not turn on and does not enter the through mode (shoot-through). . FIG. 7C shows a state in which the load current is small and the VGSon of T2 is small, and since IGL flows before M2 is turned on, T2 starts to turn on and a through mode (shoot-through) occurs.

  Similarly, FIG. 8A, FIG. 8B, and FIG. 8C correspond to those related to the possibility of shoot-through due to the gate current IGU of the upper transistor T1 in FIG. 6A and FIG. Is. In particular, FIG. 8A shows a case where a load current is sucked from the OUT terminal. FIG. 8B shows a state where the load current is large and the VGSon of T1 is large, and the current sink stage transistor M1 operates to sink IGU, so that T1 does not turn on and does not enter the through mode (shoot-through). . FIG. 8C shows a state where the load current is small and the VGSon of T1 is small, and since IGU flows before M1 is turned on, T1 starts to turn on and a through mode (shoot-through) occurs.

  Although not shown in FIGS. 7A to 8C, it is assumed that the driving duty component of the driving signal of the half-bridge circuit is small, that is, the H level pulse width of the driving signal is small in FIGS. 5B and 6B. ing. Therefore, it is assumed that the delay time DT is small.

  Problems of the conventional driving circuit will be described with reference to FIGS. 7A, 7B, and 7C regarding the possibility of shoot-through due to the gate current IGL of the lower transistor T2 of FIG. 5B (b).

  The effect of the prior art is that when the OUT terminal discharges a load current as shown in FIG. 7A, the transistor T2 is in the off state, the transistor T1 is changed from the off state to the on state, and the output of the OUT terminal is This is when the voltage rises.

  Even in this case, as shown in FIG. 7B, if VthL, delay time DT, etc. of the drive circuit of the conventional invention are appropriately set with respect to the characteristics of the transistors T1 and T2, the sink transistor M1 operates properly. The shoot through (through state) in which the transistors T1 and T2 are simultaneously turned on does not occur, and the output voltage slew rate of the OUT terminal becomes an appropriate value, so that the electromagnetic interference level can be minimized.

As described above, the transistor M1 is turned on in FIG. 7B when GLD = L and GL <VthL.
However, in this conventional driving circuit, when the load current of the load driven by the transistors T1 and T2 changes, and the VG Son voltage for switching the on / off operation of the transistors T1 and T2 changes, the sink as shown in FIG. Before the transistor M1 operates, the transistor T1 starts to turn on, and the output voltage of the OUT terminal rises. Therefore, the capacitive current IGL flows from CT2 to the gate terminal of the transistor T2, and the transistor T2 turns off and on. Enter operation and shoot-through (through state).

  In the driving circuit of the conventional invention, when the delay time DT between the signals GLD and GUD varies, or the capacitance values between the parasitic gates and sources of the transistors T1 and T2 and between the gate and drain vary. Even in such a case, there is a possibility that a shoot-through (through state) similar to FIG. 7C may occur.

  Similarly, in the case where the OUT terminal absorbs the load current as shown in FIG. 8A, the effect of the invention of the prior art is that the transistor T1 is in the off state, the transistor T2 is transitioned from the off state to the on state, and OUT OUT This is when the output voltage of the terminal falls.

  Even in this case, as shown in FIG. 8B, if VthL, delay time DT, etc. of the drive circuit of the conventional invention are appropriately set with respect to the characteristics of the transistors T1 and T2, the sink transistor M1 operates properly. The shoot through (through state) in which the transistors T1 and T2 are simultaneously turned on does not occur, and the output voltage slew rate of the OUT terminal becomes an appropriate value, so that the electromagnetic interference level can be minimized.

As described above, the transistor M1 is turned on in FIG. 8B when GUD = L and GU <VthL.
However, in the drive circuit of the conventional invention, when the load current of the load driven by the transistors T1 and T2 changes and the VG Son voltage for switching the on / off operation of the transistors T1 and T2 changes, as shown in FIG. Before the sink transistor M1 operates, the transistor T2 starts to turn on, the output voltage of the OUT terminal falls, the capacitive current IGU flows from CT1 to the gate terminal of the transistor T1, and the transistor T1 operates from off to on. And enter shoot-through.

  In the driving circuit of the conventional invention, when the delay time DT between the signals GLD and GUD varies, or the capacitance values between the parasitic gates and sources of the transistors T1 and T2 and between the gate and drain vary. Even in such a case, there is a possibility that a shoot-through (through state) similar to FIG. 8C may occur.

  From the above description, in the half-bridge circuit using the conventional drive circuit, when the drive signal which is the PWM input signal of this half-bridge circuit is small (when the drive duty component of the PWM drive signal is small), the input of the upper drive circuit It is also necessary to reduce the delay time DT between the signal GUD and the input signal GLD of the lower side drive circuit. In addition, when the capacitance value between the gate and the drain varies, there is a problem that the shoot through (penetration state) of the upper transistor T1 and the lower transistor T2 may occur.

  The present invention solves the problem of the half-bridge circuit using the above-described conventional drive circuit, and the object of the present invention is to reduce the drive signal that is the PWM input signal of the half-bridge circuit (the PWM drive signal Even if the load current of the drive circuit, the VG Son voltage, the delay time DT, the parasitic gate-source capacitance of the transistors T1 and T2, and the capacitance value between the gate and drain vary, even when the drive duty component is small) A drive circuit that constitutes a half-bridge circuit in which the shoot-through (through state) of the transistor T1 and the lower transistor T2 does not occur, the slew rate of the output voltage can be adjusted to a desired value, and the electromagnetic interference level can be optimized. Is to provide.

  The second object of the present invention is not only a half-bridge circuit using the drive circuit of the present invention and the drive direction discriminating circuit for controlling the drive circuit of the second and third inventions. Provided is a method for driving an output circuit that can adjust a slew rate of an output voltage to a desired value in an application such as an H bridge circuit, a three-phase inverter circuit, etc., can optimize an electromagnetic interference level, and does not cause a shoot-through. There is a thing.

  According to a first aspect of the present invention, there is provided a drive circuit for driving a switching device in which a capacitive current flows through the control terminal during an off period of the switching device having a control terminal. An input terminal for receiving a control signal to be turned on or off, a source circuit that outputs a drive current to the control terminal of the device according to an H level or L level signal of the input terminal, and an L level of the input terminal Or a sink circuit that sinks and outputs a drive current to the control terminal of the switching device in response to an H level signal; a current sink transistor M1 that sinks a capacitive current through the control terminal during the switching device off period; The input drive signal of the source circuit according to the signal of the input terminal and the sink circuit Or, an I / F circuit that generates an input drive signal to the sink transistor M1, and an input drive signal to the sink circuit or the transistor M1 is output as an input drive signal to either the sink circuit or the M1 transistor. A drive circuit comprising: a selector that selects whether to select; and an input terminal that receives a selection signal to the selector that controls the selection operation.

  In the present invention, the selector outputs a signal for turning off the sink transistor M1 when the input drive signal is output to the sink circuit to drive the sink circuit, and the input drive signal is sent to the sink transistor. When driving the transistor by outputting to the control terminal of M1, a signal for turning off the sink circuit is sent, or a signal for turning on the sink circuit continuously is sent. .

  Further, in the present invention, the source current of the source circuit and the sink current of the sink circuit give an appropriate drive current to the control terminal of the switching device, and a half bridge configured by a plurality of the switching devices and the drive circuit The drive circuit described above is characterized in that the slew rate of the output voltage of a circuit, an H-bridge circuit, a three-phase inverter circuit, or the like is set to an appropriate value.

  With this source circuit and sink circuit, the slew rate of the output voltage of the half-bridge circuit, H-bridge circuit, and three-phase inverter circuit configured by the drive circuit of the present invention can be set to a desired value, and the electromagnetic interference level can be set. Can be optimized.

  In the present invention, the drive circuit is characterized in that the current sink transistor M1 has a sufficient current capability and can sufficiently absorb the capacitive current flowing in the control terminal of the switching device.

  The sink transistor M1 causes a capacitive current to flow into the control terminal of the switching device during the OFF period of the switching device of the half-bridge circuit, H-bridge output circuit, and three-phase inverter circuit configured by the drive circuit of the present invention. However, there is no shoot-through (penetration state) between these switching devices.

  The drive direction discriminating circuit according to the second invention for controlling the selector of the drive circuit according to the first invention is: two switching devices T1 and T2 in which a capacitive current flows in the control terminal during an off period; Two driving circuits DU and DL for driving the switching devices T1 and T2, and an upper driving signal GUD inputted to the upper driving circuit DU for driving the upper switching device T1 by processing the driving signal of the input signal; A drive control circuit that generates and outputs a lower drive signal GLD that is input to the lower drive circuit DL that drives the lower switching device T2, and a level shift that transmits a GUD signal to the upper drive circuit DU; and an upper drive circuit An inverter that inverts the polarity of the input signal to the selector of the DU and the input signal to the selector of the lower drive circuit DL. An output voltage of the half-bridge circuit; the drive signal which is an input signal of the drive control circuit of the half-bridge circuit; an upper drive signal GUD input to the upper drive circuit DU; and an input to the lower drive circuit DL A driving direction discriminating circuit that generates a direction signal as a selection signal to the selectors of the upper driving circuit DU and the lower driving circuit DL.

  According to a second aspect of the present invention, there is provided a driving direction discriminating circuit comprising: detecting a direction generated by a signal for detecting that the output voltage of the half-bridge circuit exceeds a threshold voltage, the driving signal and the upper driving signal GUD. A signal for detecting that the output voltage of the half-bridge circuit exceeds a threshold voltage, and a direction detection signal generated by the drive signal and the lower drive signal GLD; A direction detection circuit that outputs either H level or L level according to the direction polarity indicated by the signal; and outputs a pulse having a pulse width at the time of transition from the H level to the L level of the output signal of the direction detection circuit A differential pulse circuit having a falling output terminal that outputs and a rising output terminal that outputs a pulse having a certain pulse width when the output signal of the direction detection circuit transitions from L level to H level; When there are a plurality of differential pulse circuits in response to a plurality of direction detection circuit outputs or a plurality of direction signal outputs similar to the direction detection circuit, a plurality of differential pulse circuit falling output terminals and a plurality of differential pulse circuits A pulse adding circuit that combines the rising output terminals of the differential pulse circuit into one falling output terminal and a rising output terminal, respectively; and setting each pulse output from the rising output terminal and the falling output terminal of the pulse adding circuit to a set pulse / The driving direction discriminating circuit is constituted by an SR_ flip-flop which receives a reset pulse or a reset pulse / set pulse and outputs an H level or L level signal.

  The direction detection circuit includes: a hysteresis comparator; the output voltage of the half-bridge circuit is set to the H level of the hysteresis comparator in accordance with the polarity of either the H level or the L level of the drive signal. When the threshold voltage is exceeded, an output terminal that outputs a signal of either H level or L level according to the polarity of H level or L level of the lower drive signal GLD, and the other polarity of the drive signal Accordingly, when the output voltage of the half-bridge circuit falls below the L level threshold voltage of the hysteresis comparator, either the H level or the L level polarity according to the H level or L level polarity of the upper drive signal GUD. A driving direction discrimination circuit having a direction detection circuit having one or both of the output terminal and the output terminal for outputting the signal

  When the drive direction discriminating circuit according to the second aspect of the present invention is used, the load current of the load connected to the output terminal of the half-bridge circuit is discharged when the output voltage of the half-bridge circuit rises or falls. The direction signal, which is the current direction discrimination result (drive direction discrimination result), can be sent as an appropriate selection signal to the selector of the drive circuit according to the first aspect of the invention. . The two drive circuits that constitute the half-bridge circuit use this direction signal to appropriately control the operation of the sink transistor that can sufficiently absorb the capacitive current flowing to the control terminal of the switching device, and shoot through (through state). And the slew rate of the output voltage of the half-bridge circuit can be adjusted to an appropriate value.

  The driving direction discriminating circuit according to the third aspect of the invention for controlling the driving circuit of the first aspect of the invention is: two switching devices T1 and T2 in which a capacitive current flows through the control terminal during the off period; The two driving circuits DU and DL that drive T1 and T2, and the upper driving signal GUD and the lower side that are input to the upper driving circuit DU that processes the driving signal of the input signal and drives the upper switching device T1 A drive control circuit that generates and outputs a lower drive signal GLD that is input to the lower drive circuit DL that drives the switching device T2, and a level shift that transmits a GUD signal to the upper drive circuit DU; A half-bridge composed of an inverter that inverts the polarity of the input signal to the selector and the input signal to the selector of the lower drive circuit DL. A control terminal voltage of the switching device T1 or T2 of the circuit (that is, an output voltage of the upper drive circuit DU or the lower drive circuit DL); and an input drive signal input to the upper drive circuit DU or the lower drive circuit DL A driving direction determination circuit characterized by generating a direction signal as a selection signal to the selector of the upper driving circuit DU and the lower driving circuit DL of the half-bridge circuit.

  According to a third aspect of the present invention, there is provided a driving direction discriminating circuit comprising: a signal for detecting whether the control terminal voltage of the switching device (that is, the output voltage of the driving circuit) exceeds a certain threshold voltage and the input driving signal for a certain period of time. A direction detection signal generated by a delayed rising edge signal of the delayed input drive signal; a signal for detecting whether the control terminal voltage of the switching device exceeds a threshold voltage and the input drive signal are delayed by a certain time A direction detection circuit that outputs either one or both of the direction detection signals generated by the falling edge signal of the delayed input drive signal according to the direction polarity indicated by the signal; A falling output terminal for outputting a pulse having a pulse width at the time of transition from an H level to an L level of an output signal of the direction detection circuit; A differential pulse circuit having a rising output terminal for outputting a pulse having a pulse width at the time of transition of the output signal of the direction detection circuit from L level to H level; and whether there are a plurality of outputs of the direction detection circuit or the direction detection When there are a plurality of differential pulse circuits in response to a plurality of directional signal outputs similar to those of the circuit, each of the plurality of differential pulse circuits has a falling output terminal and a plurality of the differential pulse circuits has a rising output terminal. A pulse addition circuit that combines the two falling output terminals and the rising output terminal; receiving each pulse from the rising output terminal and the falling output terminal of the pulse adding circuit as a set pulse / reset pulse or a reset pulse / set pulse; It is composed of SR_ flip-flop that outputs H level or L level signal. And the direction determining circuit.

  The direction detection circuit also includes: a hysteresis comparator; the switching device T1 or T2 when either the rising edge or the falling edge of the delayed input drive signal obtained by delaying the input drive signal by a certain time An output terminal for outputting a signal having a polarity of either H level or L level depending on whether the control terminal voltage exceeds an H level threshold voltage of the hysteresis comparator; and delaying the input drive signal by a certain time Depending on whether the control terminal voltage of the switching device T1 or T2 falls below the L level threshold voltage of the hysteresis comparator at either the falling edge or the rising edge of the delayed input drive signal, With an output terminal that outputs a signal of either polarity of level or L level; Or was the drive direction detection circuit, characterized in that it has a direction detection circuit with both.

  When the driving direction discriminating circuit according to the third aspect of the present invention is used, as in the driving direction discriminating circuit according to the second aspect, the rising edge of the input driving signal of the driving circuit constituting the half-bridge circuit or At the time of falling, it can be determined whether the load current of the load connected to the output terminal of the half-bridge circuit is being discharged or sucked, and the direction signal that is the determination result of the current direction (drive direction determination result) It can be sent as an appropriate selection signal to the selector of the drive circuit according to the first invention. The two drive circuits that constitute the half-bridge circuit use this direction signal to appropriately control the operation of the sink transistor that can sufficiently absorb the capacitive current flowing to the control terminal of the switching device, and shoot through (through state). And the slew rate of the output voltage of the half-bridge circuit can be adjusted to an appropriate value.

  The drive circuit of the present invention is a drive circuit used in a half-bridge circuit configured using a switching device in which a capacitive current flows into the control terminal during an off period. When applied to a bridge circuit, the slew rate of the output voltage of the half-bridge circuit can be adjusted to a desired value, and the electromagnetic interference level can be optimized.

  Further, when the drive circuit of the present invention is applied to the half-bridge circuit, even when the drive signal that is the PWM input signal of the half-bridge circuit is small (when the drive duty component of the PWM drive signal is small), the load on the drive circuit is reduced. Even if the current, the VGson voltage, the delay time DT, the parasitic gate-source capacitance of the transistors T1 and T2 and the capacitance value between the gate and drain vary, the shoot-through (through state) of the upper transistor T1 and the lower transistor T2 ) Does not occur, a half-bridge circuit can be configured.

  Further, not only the half-bridge circuit but also the H-bridge circuit using the drive circuit of the present invention and the drive-direction determining circuit that sends a signal for determining the drive direction of the half-bridge circuit to the selection signal input terminal of the selector of the drive circuit. In applications such as three-phase inverter circuits and the like, the output voltage slew rate can be adjusted to a desired value, the electromagnetic interference level can be optimized, and a drive method for an output circuit that does not cause shoot-through can be provided.

1 is a circuit diagram of a first embodiment of a driving device using a driving circuit. FIG. 1 is a circuit diagram showing an operating state of the drive circuit of FIG. Waveform diagram of the drive circuit of FIG. 2A FIG. 1 is a circuit diagram showing an operating state of the drive circuit of FIG. Waveform diagram of the drive circuit of FIG. 3A Circuit diagram showing a high-voltage half-bridge circuit using a conventional drive circuit Circuit diagram illustrating shoot-through of a conventional half-bridge circuit Waveform diagram explaining shoot-through of a conventional half-bridge circuit Circuit diagram illustrating shoot-through of a conventional half-bridge circuit Waveform diagram explaining shoot-through of a conventional half-bridge circuit Circuit diagram of a high-voltage half-bridge circuit using a conventional drive circuit Waveform diagram of a high-voltage half-bridge circuit using a conventional drive circuit Waveform diagram of a high-voltage half-bridge circuit using a conventional drive circuit Circuit diagram of a high-voltage half-bridge circuit using a conventional drive circuit Waveform diagram of a high-voltage half-bridge circuit using a conventional drive circuit Waveform diagram of a high-voltage half-bridge circuit using a conventional drive circuit Circuit diagram of a second embodiment of a drive device using a drive circuit and a drive direction discrimination circuit 100 A circuit diagram of the second embodiment showing the drive direction discrimination circuit 100 in detail. Waveform diagram of the circuit of the second embodiment The circuit diagram of 3rd Embodiment of the drive device using the drive circuit and the drive direction discrimination circuit 200 Circuit diagram of a fourth embodiment of a driving apparatus using a driving circuit and a driving direction discrimination circuit 300 The circuit diagram of the fourth embodiment showing the drive direction discrimination circuit 300 in detail. Waveform diagram of the circuit of the fourth embodiment Circuit diagram of a fifth embodiment of a driving apparatus using a driving circuit and a driving direction discriminating circuit 400 Circuit diagram of sixth embodiment using drive circuit, drive direction discriminating circuit 300 and drive direction discriminating circuit 300H A circuit diagram of the sixth embodiment showing in detail the driving direction discriminating circuit 300 and the driving direction discriminating circuit 300H. Waveform diagram of the circuit of the sixth embodiment 7 is a circuit diagram of a seventh embodiment of a drive device in which an H-bridge circuit is configured using the drive circuit. Circuit diagram of the input signal direction discrimination circuit shown in FIG. Waveform diagram of the input signal direction discrimination circuit shown in FIG. Waveform diagram of the input signal direction discrimination circuit shown in FIG. Circuit diagram of a modification of the input signal direction discrimination circuit shown in FIG. Waveform diagram of a modification of the input signal direction discrimination circuit shown in FIG. Waveform diagram of a modification of the input signal direction discrimination circuit shown in FIG. Circuit diagram of input signal direction discrimination circuit for three-phase inverter Waveform diagram of the input signal direction discrimination circuit of the three-phase inverter Circuit diagram of modified example of input signal direction discrimination circuit of three-phase inverter 8 is a circuit diagram of an eighth embodiment of a driving apparatus in which an H-bridge circuit is configured using a driving circuit and a driving direction determination circuit 100. The circuit diagram of the modification of 8th Embodiment of the drive device which comprised the H bridge circuit using the drive circuit and the drive direction discrimination circuit 100 9 is a circuit diagram of a ninth embodiment of a driving apparatus in which an H bridge circuit is configured by using a driving circuit and a driving direction determination circuit 200. 10 is a circuit diagram of a tenth embodiment of a driving apparatus in which an H bridge circuit is configured by using a driving circuit and a driving direction determination circuit 300. The circuit diagram of the modification of 10th Embodiment of the drive device which comprised the H bridge circuit using the drive circuit and the drive direction discrimination circuit 300 11 is a circuit diagram of an eleventh embodiment of a driving apparatus in which an H bridge circuit is configured by using a driving circuit and a driving direction determination circuit 400. A circuit diagram of a twelfth embodiment of a drive device in which an H bridge circuit is configured by using a drive circuit, a drive direction discrimination circuit 300, and a drive direction discrimination circuit 300H. Circuit diagram of drive device applying seventh embodiment to three-phase inverter circuit Circuit diagram of another drive device in which the seventh embodiment is applied to a three-phase inverter circuit Circuit diagram of drive device applying eighth embodiment to three-phase inverter circuit Circuit diagram of another drive device in which the eighth embodiment is applied to a three-phase inverter circuit Circuit diagram of drive device applying ninth embodiment to three-phase inverter circuit Circuit diagram of another drive device in which the ninth embodiment is applied to a three-phase inverter circuit Circuit diagram of drive device applying tenth embodiment to three-phase inverter circuit Circuit diagram of another drive device in which the tenth embodiment is applied to a three-phase inverter circuit Circuit diagram of drive device applying 11th embodiment to three-phase inverter circuit Circuit diagram of another drive device in which the eleventh embodiment is applied to a three-phase inverter circuit Circuit diagram of drive device applying twelfth embodiment to three-phase inverter circuit Circuit diagram of another drive device in which the twelfth embodiment is applied to a three-phase inverter circuit

(First embodiment)
FIG. 1 is a configuration diagram of a specific embodiment of the driving apparatus of the present invention. Hereinafter, a first embodiment of a half-bridge circuit which is a driving device of the present invention will be described with reference to FIG.

  FIG. 1 shows a half-bridge circuit using a drive circuit according to the first embodiment.

  The half-bridge circuit: switching device T1 and switching device T2, such as two power MOSFET transistors, in which capacitive current flows through its control terminal, ie the gate terminal, during the off period; the upper side driving transistors T1 and T2, respectively. Drive circuit DU and lower drive circuit DL; drive signal for driving this half bridge circuit and drive upper drive signal GUD and lower transistor T2 input to upper drive circuit DU for driving upper transistor T1 Connected to the output terminal OUT of the half-bridge circuit; a drive control circuit 5 that generates a lower drive signal GLD that is input to the lower drive circuit DL; a level shift 6 that transmits a GUD signal to the upper drive circuit DU; A load switch for connecting the other end of the load 11 to the power source VM or switching the connection to the GND. 7; switching means 8 for controlling the switching of the load switch 7; and an inverter 10 for inverting the polarities of the input signal of the selector 34 of the upper drive circuit DU and the input signal of the selector 44 of the lower drive circuit DL. The

  The drive circuit DU includes an interface 31, a source circuit 32, a sink circuit 33, a selector 34, and a sink transistor M1. From the interface 31, a signal for the source circuit and a signal for the sink circuit are output, and the signal for the sink circuit is supplied to either the sink circuit 33 or the sink transistor M1 depending on the selection of the selector 34. The sink transistor M1 is a transistor that sinks a capacitive current through the control terminal during the switching device OFF period.

  The drive circuit DL includes an interface 41, a source circuit 42, a sink circuit 43, a selector 44, and a sink transistor M2. The interface 41 outputs a signal for the source circuit and a signal for the sink circuit, and the signal for the sink circuit is supplied to either the sink circuit 43 or the sink transistor M2 according to the selection of the selector 44. The sink transistor M2 is a transistor that sinks a capacitive current through the control terminal during the switching device OFF period.

  The control signal output from the switching means 8 switches the load switch 7 to connect the other end of the load connected to the output terminal OUT of the half-bridge circuit to the power source VM or connect the other end of the load to GND. At the same time, it is also used as a direction signal DIR that serves as a selection signal for the selectors 34 and 44 of the upper drive circuit DU and the lower drive circuit DL. With the first control signal output from the switching means 8, the load switch 7 is connected in the direction indicated by the dotted line, and the selectors 34 and 44 are also connected in the direction indicated by the dotted line. Thus, the other end of the load 11 is connected to the VM, the sink transistor M1 is selected in the upper drive circuit DU, and the sink circuit 43 is selected in the lower drive circuit DL. Further, the load switch 7 is connected in the direction indicated by the solid line by the second control signal output from the switching means 8, and the selectors 34 and 44 are also connected in the direction indicated by the solid line. As a result, the other end of the load 11 is connected to GND, the sink circuit 33 is selected in the upper drive circuit DU, and the sink transistor M2 is selected in the lower drive circuit DL. The first control signal and the second control signal from the switching unit 8 are switched at a predetermined frequency F1. This frequency F1 is independent of the frequency F2 at which the upper drive signal GUD and the lower drive signal GLD are switched, and the frequency F1 is a frequency several orders of magnitude lower than the frequency F2. Therefore, the switching device T1 or the switching device T2 is turned on / off in the order of several hundred to several thousand while the positive current flows through the load 11 by the first control signal from the switching means 8. It is repeating.

  The switching means 8 outputs a first control signal and a second control signal alternately and repeatedly in order to supply an alternating current having a desired frequency to the load 11. When flowing from the load 11 to the ground GND side, the load switch 7 is connected as shown by a solid line, and a load current as shown by a dotted line in FIG. 5A flows. When flowing from the load 11 to the power supply VM side, the load switch 7 is connected as indicated by a dotted line, and a load current as indicated by the dotted line in FIG. 6A flows.

  A delay circuit 9 having an appropriate delay time is installed between the output terminal of the switching means 8 and the input terminal of the inverter 10 and the input terminal of the selector 44 of the lower drive circuit DL depending on the type of the load 11. You may do it. This corresponds to the case where the load is an inductive load having an inductor component or the like, and when the load switch is switched, the switching of the direction of the load current is delayed with respect to the switching of the load switch. The time can be set to an appropriate delay time value from the inductor and resistance components of the load.

  In the half-bridge circuit using the drive circuit of the present invention shown in FIG. 1, even when the duty ratio of the drive signal which is a PWM input signal is small, the shoot through of the upper transistor T1 and the lower transistor T2 is taken. The possibility of occurrence of a (penetration state) is greatly improved, and the output circuit slew rate can be set to an appropriate value, so that the electromagnetic interference level can be minimized. This point will be described with reference to FIGS. 2A and 2B and FIGS. 3A and 3B.

  FIGS. 2A and 2B are diagrams for explaining the operation when the load current is output from the OUT terminal which is the output of the half-bridge circuit. FIG. 2A shows a case where the other end of the load is grounded to the terminal GND, that is, a case where a load current is discharged from the OUT terminal. FIG. 2B shows that when the lower side drive signal GLD is changed from H to L and the current sink transistor M2 works to sink the gate current IGL, the transistor T2 is not turned on and the through mode (shoot-through) is not achieved. Indicates the state.

  2A illustrates drive signals GUD and GLD of the upper drive circuit DU and the lower drive circuit DL, a direction signal DIR input to each drive circuit, and a load connected to the OUT terminal in order to explain the operation state. It is a block diagram which shows a connection state.

  When the load current is output from the OUT terminal, the other end of the load connected to the OUT terminal by the switching means 8 is connected to GND, the direction signal DIR input to the lower drive circuit DL becomes H level, and the upper side The direction signal input to the drive circuit DU becomes L level by the inverter 10 illustrated in FIG. Note that the polarities of the direction signals input to the two drive circuits may be opposite to those described above. In this situation, the selector 34 of the upper drive circuit DU operates the sync circuit 33 to perform sync. Although the transistor M1 may be turned off and the selector 44 of the lower drive circuit DL may be operated or turned off, the direction signal DIR is transmitted to each of the drive circuits DU and DL so that the sink transistor M1 is operated. It is important to control This is explained below.

  From the explanation of the behavior of the gate current IGU of the upper transistor T1 and the gate current IGL of the lower transistor T2 when the load current is output from the OUT terminal output of the half-bridge circuit using FIG. When sourcing load current from the output, you can see two things.

  1. The rising and falling slew rates of the output voltage at the OUT terminal are determined by the gate current IGU output from the upper drive circuit DU to the gate terminal of the upper transistor T1 and the gate current IGU input by sinking to the gate terminal. .

  2. The reason why the upper transistor T1 and the lower transistor T2 become shoot through (through state) due to the capacitive current flowing into the gate terminal of the lower transistor T2 is that the current sink capability of the lower drive circuit DL is low.

  Therefore, when the load current is output from the OUT terminal, which is the output of the half-bridge circuit, the upper drive circuit DU has the sink transistor M1 always off, and the source circuit and the sink circuit output the gate current IGU at a desired value. Or input, so that the rising and falling slew rates of the OUT terminal output voltage can be determined. On the other hand, since the rising and falling slew rates of the OUT terminal output voltage do not depend on the gate current of the lower transistor T2, the lower drive circuit DL always operates the sink transistor M2 when turning off the transistor T2. It can be seen that it is sufficient to prevent shoot-through due to capacitive current.

  The drive circuit of the present invention has been devised in accordance with this idea. Since the direction of the load current is generally determined from the connection status of the other end of the load, the other end of the load is connected to the power source VM or connected to the GND. When the other end of the load 11 is connected to GND using the control signal output from the switching means 8 for switching control of the load switch 7 for switching the direction signal DIR, the upper drive circuit DU has a sink circuit. 33 is selected and operated, and the output signal of the switching means 8 and the load switch are set so that the sink transistor M2 is selected and operated in the lower drive circuit DL. With this setting, the slew rate of the output voltage of the half-bridge circuit can be set to a desired value, and shoot-through can be prevented.

  As described above, the delay circuit 9 having an appropriate delay time may be installed between the output terminal of the switching unit 8 and the input terminal of the inverter 10 and the input terminal of the selector 44 of the lower drive circuit DL. good. This corresponds to the case where the load 11 is an inductive load having an inductor component and the like, and when the load switch 7 is switched, the switching of the direction in which the load current flows is delayed with respect to the switching of the load switch. For the delay time 9, an appropriate delay time value may be set from the inductor component and the resistance component of the load.

  However, since only the delay circuit 9 does not know that the direction of the load current is switched from the source output to the sink input at an accurate timing, the direction of the load current is determined using a direction determination circuit that determines the switching of the direction of the load current. And the direction signal DIR may be sent to the drive circuits DU and DL based on the detected signal. This detection method will be described later as another invention.

  FIG. 2B is an operation waveform diagram in the drive circuit of the present invention corresponding to FIG. 7C in which the problem has been pointed out in the conventional drive circuit. Even when the delay time DT is small, the lower transistor T2 is obtained by the high sink capability of the sink transistor M1. Since the transition from the H level to the L level of the gate terminal voltage GL is steep, it can be seen that no shoot-through occurs even if the VGson voltage of the upper transistor T1 is low.

  3A and 3B are diagrams for explaining the operation when the OUT terminal, which is the output of the half-bridge circuit, sinks (sucks) the load current. FIG. 3A shows a case where the other end of the load is connected to the terminal VM, that is, a case where a load current is sucked from the OUT terminal. FIG. 3B shows a state where the current sink transistor M1 operates in response to the change of the upper drive signal GUD from H to L and the gate current IGU is sunk, the transistor T1 does not turn on and does not enter the through mode (shoot through). Indicates.

  FIG. 3A shows the driving signals GUD and GLD of the upper driving circuit DU and the lower driving circuit DL, the direction signal DIR input to each driving circuit, and the load connected to the OUT terminal in order to explain the operation state. It is a block diagram which shows a connection state.

  When the OUT terminal absorbs the load current, the switching means 8 shown in FIG. 1 connects the other end of the load 11 connected to the OUT terminal to the power supply VM, and the direction signal input to the lower drive circuit DL. DIR becomes L level, and the direction signal inputted to the upper drive circuit DU becomes H level by the inverter shown in FIG. Note that the polarities of the direction signals input to the two drive circuits may be opposite to those described above. In this situation, the selector 44 of the lower drive circuit DL operates the sink circuit 43. Although the sink transistor M2 may be turned off and the selector 34 of the upper drive circuit DU may be operated or turned off, the direction signal DIR is transmitted to each of the drive circuits DU and DL so that the sink transistor M1 is operated. It is important to control This point will be explained below.

  From the description of the behavior of the gate current IGU of the upper transistor T1 and the gate current IGL of the lower transistor T2 when the OUT terminal output of the half bridge circuit using FIGS. 6A and 6B absorbs the load current, When the terminal output sinks the load current, the following two things can be understood.

  3. The rising and falling slew rates of the output voltage at the OUT terminal are determined by the gate current IGL output from the lower drive circuit DL to the gate terminal of the lower transistor T2 and the gate current IGL input by sinking to the gate terminal. It is.

  4). The reason why the upper transistor T1 and the lower transistor T2 become shoot through (through state) due to the capacitive current flowing into the gate terminal of the upper transistor T1 is that the current sink capability of the upper drive circuit DU is low.

Therefore, when sinking load current to the OUT terminal, which is the output of the half-bridge circuit,
In the lower drive circuit DL, the sink transistor M1 is always off, and the sink circuit and the source circuit output the gate current IGL at a desired value so that the rising and falling slew rates of the OUT terminal output voltage can be determined. . On the other hand, since the rising and falling slew rates of the OUT terminal output voltage do not depend on the gate current of the upper transistor T1, the upper drive circuit DL always operates the sink transistor M1 to turn off the capacitor when turning off the transistor T1. It can be seen that the shoot-through due to the sexual current should not be generated.

The drive circuit of the present invention was devised based on this idea,
In general, the direction of the load current is determined by the connection status of the other end of the load, and is therefore output from the switching means 8 for controlling the switching of the load switch for connecting the other end of the load to the power source VM or switching the connection to GND. When the other end of the load is connected to the power source VM, the sink circuit is selected and operated in the lower drive circuit DL, and the sink transistor M1 is selected and operated in the upper drive circuit DU. Thus, the output signal of the switching means 8 and the load switch are set.
With this setting, the slew rate of the output voltage of the half-bridge circuit can be set to a desired value, and shoot-through can be prevented.

  FIG. 3B is an operation waveform diagram in the drive circuit of the present invention corresponding to FIG. 8C in which the problem has been pointed out in the conventional drive circuit. Even when the delay time DT is small, the high sink capability of the sink transistor M1 allows the upper transistor T1 to Since the transition from the H level to the L level of the gate terminal voltage GU is steep, it can be seen that no shoot-through occurs even when the VGson voltage of the lower transistor T2 is low.

  Therefore, in the half bridge circuit using the drive circuit of the present invention shown in FIG. 1, the drive signal which is the PWM input signal of the half bridge circuit is small (when the drive duty component of the PWM drive signal is small) or the drive When the load current of the circuit, the VG Son voltage, the delay time DT, the capacitance values between the parasitic gates and sources of the transistors T1 and T2 and between the gate and drain vary, the shoot-through of the upper transistor T1 and the lower transistor T2 ( The possibility of occurrence of a (penetration state) is greatly improved, and the output circuit slew rate can be set to an appropriate value to minimize the electromagnetic interference level.

(Second Embodiment)
FIG. 9 is a configuration diagram of the second embodiment using the drive circuit and the drive direction determination circuit 100 of the first embodiment. The operation of the second embodiment will be described below.
FIG. 9 shows a half-bridge circuit using the drive circuit and the drive direction discriminating circuit 100 of the first embodiment.

  The half-bridge circuit is: switching devices T1 and T2, such as two power MOSFET transistors, in which capacitive current flows through its control terminal, that is, the gate terminal during the off period; upper drive circuits that drive the transistors T1 and T2, respectively. DU and a lower drive circuit DL; a signal for processing a drive signal for driving the half-bridge circuit and an upper drive signal GUD input to the upper drive circuit DU for driving the upper transistor T1 and a lower drive for driving the lower transistor T2 A drive control circuit 5 for generating a lower drive signal GLD input to the side drive circuit DL; a level shift 6 for transmitting a GUD signal to the upper drive circuit DU; and an output terminal OUT of the half-bridge output circuit A load switch 7 for connecting the other end of the load 11 to the power source VM or switching the connection to GND; Switching means for controlling the switching of the H; inverter 10 for inverting the polarities of the input signal of the selector 34 of the upper drive circuit DU and the input signal of the selector 44 of the lower drive circuit DL; and a drive direction discriminating circuit 100 Is done.

  The half-bridge circuit of the second embodiment has substantially the same configuration as that described in the first embodiment, but the difference from the first embodiment is that a drive direction discriminating circuit 100 is provided. .

  In general, the direction of the current flowing through the load 11 is determined by the connection state of the other end of the load 11, but when the load 11 is an inductive load having an inductor component or the like, the direction of the load current when the load switch 7 is switched. Is delayed with respect to the switching of the load switch 7. In order to accurately detect the switching of the load current, the driving direction discriminating circuit 100 is used.

  The drive direction discriminating circuit 100 loads the load 11 connected to the output terminal OUT of the half bridge circuit from the output voltage of the output terminal OUT of the half bridge circuit, the drive signal, the upper drive signal GUD, and the lower drive signal GLD. The direction of the current is detected, and a direction signal DIR that takes a value of H level or L level according to the direction polarity is output. The lower drive circuit DL directly detects the direction signal DIR through the inverter 10 and the level shift 6 and the upper drive circuit DU detects the direction signal DIR. The drive circuits of the lower drive circuit DL and the upper drive circuit DU are the selectors 34 and 44, respectively. Thus, the sync circuit 33, 43 or the sync transistor M1, M2 is selected. By applying the driving direction discriminating circuit 100 to the half-bridge circuit, even if the load of the half-bridge circuit is an inductive load having an inductor component, the slew rate of the output voltage of the half-bridge circuit is set to an appropriate value. In addition, it is possible to prevent shoot-through (through state). The drive direction determination circuit 100 receives a signal from the output terminal OUT of the half-bridge circuit that is downstream of the switching device T1 or T2, but is upstream of the switching device T1 or T2, for example, the switching device T1 or T2. You may receive the signal from the gate terminal. Here, “downstream” and “upstream” refer to directions in which signals are transmitted in the system.

  Next, the operation of the drive direction determination circuit 100 in the second embodiment will be described with reference to FIGS. 10 and 11. FIG. 10 is a block diagram showing in detail the drive direction discriminating circuit 100 from the diagram of the second embodiment of FIG. 9, and FIG. 11 is a timing waveform diagram of each signal shown in FIG.

  The driving direction discriminating circuit 100 in the second embodiment includes: a withstand voltage protection circuit 102 that receives the output voltage OUT of the half-bridge circuit; and a hysteresis comparator that compares the output voltage VO from the withstand voltage protection circuit 102 with the threshold voltages VthH and VthL. 104; when the output voltage VO exceeds the threshold voltage VthH, the direction detection signal LD generated based on the output signal CO, the drive signal, and the upper drive signal GUD of the comparator 104 is output, while the output voltage VO is the threshold voltage. A direction detection signal HD that outputs a direction detection signal HD generated based on the output signal CO, the drive signal, and the lower drive signal GLD of the comparator 104 when the output signal LD falls below VthL; and the output signal LD of the direction detection circuit 108 is H When a transition from the level to the L level occurs, a pulse having a predetermined pulse width is output. A differential pulse circuit 110 having a falling output terminal R_LD and a rising output terminal S_LD that outputs a pulse having a predetermined pulse width when the output signal LD of the direction detection circuit 108 changes from L level to H level; When the output signal HD of the direction detection circuit 108 changes from the H level to the L level, the falling output terminal R_HD that outputs a pulse having a predetermined pulse width and the output signal HD of the direction detection circuit 108 changes from the L level to the H level. A differential pulse circuit 112 having a rising output terminal S_HD that outputs a pulse having a predetermined pulse width at the time of transition to a level; and one of the falling output terminals R_LD and R_HD of the differential pulse circuits 110 and 112 as a logical sum. Together with the falling output terminals RR, the rising output terminals S of the differential pulse circuits 110 and 112 A pulse addition circuit 114 that combines LD and S_HD into one rising output terminal SS by a logical OR; and sets each pulse output from the falling output terminal RR and the rising output terminal SS of the pulse addition circuit to a set pulse / reset pulse or reset pulse / SR_flip-flop 116 that receives a set pulse and outputs an H level or L level signal.

  Note that the pulse addition circuit 114 has a plurality of differential pulse circuits when there are a plurality of output signals from the direction detection circuit 108 or a plurality of direction signal outputs similar to the direction detection circuit. The pulse adder circuit combines the falling output terminal and the rising output terminals of the plurality of direction detection circuits into one falling output terminal and one rising output terminal, respectively.

  The direction detection circuit 108 receives the output voltage OUT of the half bridge circuit as the voltage VO via the withstand voltage protection circuit 102. The withstand voltage protection circuit 102 is a withstand voltage protection clamp circuit provided on the assumption that the power supply voltage of the power supply VM for power supply of the half-bridge circuit is higher than the power supply of the drive direction discrimination circuit 100. The output voltage VO is approximately equal to the output voltage VO if the output voltage OUT is lower than a certain clamp voltage (VLIM−VGS), and if the output voltage OUT is equal to or higher than the clamp voltage, the output voltage VO is VLIM−. VGS.

  The direction detection circuit 108 is a direction detection signal LD that is a polarity signal obtained by inverting the upper drive signal GUD from the time when the output voltage VO exceeds the threshold voltage VthH of the hysteresis comparator 104 when the drive signal is at the H level. Is output.

The direction detection circuit 108 is a direction detection signal HD that is a polarity signal of the lower drive signal GLD when the drive signal is at the L level and the output voltage VO is lower than the threshold voltage VthL of the hysteresis comparator 104. Is output.
When the direction detection circuit outputs the direction detection signals HD and LD as described above, it can be determined whether the output terminal OUT of the half-bridge circuit outputs the load current as a source or a sink.

  The timing waveform diagram of FIG. 11 explains this. The left half of FIG. 11 shows the case where the load current is sinked into the OUT terminal, and the right half of FIG. 11 shows the case where the load current is sourced from the OUT terminal. The load signal (1) shown in FIG. 10 (indicated by a circle 1 in the drawing, the same applies hereinafter), the drive signal, the upper drive signal GUD, and the lower drive signal in each of the cases (2), (3), and (4) The GLD, the gate voltage GU-OUT of the transistor T1, the gate voltage GL of the transistor T2, and the output voltage OUT (VO) are shown in FIG.

  From the timing chart of these waveforms and the explanation of the operation of the direction detection circuit 108 described above, when the direction signals LD and HD transition from L level to H level, the load current is sinked to the output terminal OUT of the half-bridge circuit, and the direction signal If LD and HD transition from the H level to the L level, it can be determined that the load current is input to the output terminal OUT of the half-bridge circuit.

  The direction signal LD is a direction detection signal when the output OUT of the half-bridge circuit rises, and the direction signal HD is a direction detection signal when the output OUT of the half-bridge circuit falls. This means that the direction detection circuit 108 has two direction detection circuits. The two direction detection circuits detect the direction of the load current at different times in time series.

  The drive direction discriminating circuit 100 of the second embodiment needs to process timely and output the direction signal DIR when the polarities of the two detection circuit signals LD and HD change.

  The differential pulse circuit, the pulse addition circuit, and the SR_ flip-flop are configured as shown in FIG. 10, so that the direction signal is processed in a timely manner when the polarities of the two detection circuit signals LD and HD change. DIR can be output.

  As a result, in the half bridge circuit using the drive circuit of the first embodiment and the drive direction discriminating circuit 100, the load of the half bridge circuit is an inductive load having an inductor component or the like, and this inductive load is at any timing. Even if the direction of the load current is switched, the direction of the load current can be detected in a timely manner, the slew rate of the output voltage of the half-bridge circuit is set to an appropriate value, and the shoot through (through state) Can be prevented.

(Third embodiment)
FIG. 12 is a configuration diagram of the third embodiment using a driving direction discriminating circuit 200 in which the driving circuit of the first embodiment and the driving direction discriminating circuit 100 of the second embodiment are partially modified. The operation of the third embodiment will be described below.
The third embodiment in FIG. 12 is a combination of the first embodiment and the second embodiment.

  The difference from the second embodiment is in the driving direction discrimination circuit 200 in the third embodiment. The drive direction discriminating circuit 200 further includes a differential pulse circuit 202 that receives an output signal from the switching means 8 that controls the load switch 7 or the delay circuit 9 installed according to the load condition, and outputs a direction signal DIR. .

  The differential pulse circuit 202 outputs a set pulse S_EX and a reset pulse R_EX having a certain pulse width according to the rising edge and falling edge of the output signal of the switching means 8 or the delay circuit 9.

  In addition to the set pulse signal group and the reset pulse signal group from the differential pulse circuits 110 and 112, the pulse signals S_EX and R_EX from the differential pulse circuit 202 are supplied to the pulse addition circuit 114 and the SR_ flip-flop 116, and waveform shaping is performed. A direction signal DIR is generated.

  As a result, the drive direction is discriminated by adding the control signal of the switching means 8 in addition to the output voltage of the output terminal OUT of the half-bridge circuit, the drive signal, the upper drive signal GUD, and the lower drive signal GLD. The circuit 200 can output the direction signal DIR with higher accuracy than the driving direction determination circuit 100.

(Fourth embodiment)
FIG. 13 is a configuration diagram of the fourth embodiment using the drive circuit of the first embodiment and the drive direction discrimination circuit 300 of the third embodiment. The operation of the fourth embodiment will be described below.
FIG. 13 shows a half-bridge circuit using the drive circuit of the first embodiment and the drive direction discrimination circuit 300 of the third embodiment.

The configuration of the half-bridge circuit is almost the same as the half-bridge circuit of the second embodiment shown in FIG. 9, and the difference is that the drive direction discriminating circuit 100 is replaced with the drive direction discriminating circuit 300 of the third embodiment. It is.
Since this half-bridge circuit is almost the same as that described in the second embodiment, only the operation of the drive direction discrimination circuit 300 will be described.

  The drive direction determination circuit 300 detects the direction of the load current of the load connected to the output terminal OUT of the half bridge circuit from the gate terminal voltage GL of the lower transistor T2 of the half bridge circuit and the lower drive signal GLD. Then, a direction signal DIR that takes a value of H level or L level according to the direction polarity is output.

  The lower drive circuit DL detects the direction signal DIR directly and the upper drive circuit DU detects the direction signal DIR through an inverter and a level shift, and the drive circuits DL and DU select the sync circuit or the sync transistor by each selector. By applying the driving direction discriminating circuit 300 to the half-bridge circuit, even if the load of the half-bridge circuit is an inductive load having an inductor component or the like, the slew rate of the output voltage of the half-bridge circuit is set to an appropriate value. In addition, it is possible to prevent shoot-through (through state).

  Next, the operation of the drive direction determination circuit 300 according to the third embodiment will be described with reference to FIGS. 14 and 15. FIG. 14 is a block diagram showing in detail the drive direction discriminating circuit 300 of the fourth embodiment of FIG. 13, and FIG. 15 is a timing waveform diagram of each signal shown in FIG.

  The driving direction discriminating circuit 300 of the third embodiment is similar to the driving direction discriminating circuit 100 shown in FIG. 10, and includes a direction detecting circuit 108 ′, two differential pulse circuits 110 and 112, a pulse adding circuit 114, and an SR_ flip-flop. 116. The only difference from the drive direction discriminating circuit 100 is that the direction detecting circuit 108 is changed to the direction detecting circuit 108 '. As can be seen from this, the method of outputting the direction signal DIR of the drive direction discriminating circuit 300 is the same as that of the drive direction discriminating circuit 100.

  The direction detection circuit 108 'includes a hysteresis comparator 104, an LD output terminal, an HD output terminal, and a delay circuit 107 that delays the lower drive signal GLD for a certain time.

  The LD output terminal of the direction detection circuit 108 ′ detects the falling edge of the delay signal GLD 2 obtained by delaying the lower drive signal GLD for a certain time, so that the gate terminal voltage GL of the lower transistor T 2 becomes the hysteresis comparator 104. When the voltage is higher than the threshold voltage VthL, the H level is output. When the gate terminal voltage GL of the lower transistor T2 is lower than the threshold voltage VthL, the L level is output.

  Further, the HD output terminal of the direction detection circuit 108 ′ detects that the rising edge of the delay signal GLD 2 obtained by delaying the lower drive signal GLD by a certain time, the gate terminal voltage GL of the lower transistor T 2 becomes the threshold value of the hysteresis comparator 104. When the voltage is higher than the voltage VthH, the L level is output. When the gate terminal voltage GL of the lower transistor T2 is lower than the threshold voltage VthH, the H level is output.

  The direction detection circuit 108 ′ operates to output the direction detection signals HD and LD as described above, so that it can be determined whether the output terminal OUT of the half bridge circuit outputs the load current as a source or a sink.

  This is illustrated in the timing waveform diagram of FIG. The left half of FIG. 15 shows the case where the load current is sinked into the OUT terminal, and the right half of FIG. 15 shows the case where the load current is sourced from the OUT terminal. The drive signal, the upper drive signal GUD, the lower drive signal GLD, the gate voltage GU-OUT of the transistor T1, in each of the load currents (1), (2), (3), and (4) shown in FIG. The gate voltage GL and the output voltage OUT (VO) of the transistor T2 are divided and illustrated in FIG.

  From the timing charts of these waveforms and the operation description of the direction detection circuit 108 ′ described above, if the direction signals LD and HD transition from L level to H level, the load current is sinked to the output terminal OUT of the half-bridge circuit, and the direction If the signals LD and HD transition from the H level to the L level, it can be determined that the load current is input to the output terminal OUT of the half-bridge circuit.

  The direction signal LD is a direction detection signal when the output OUT of the half-bridge circuit rises, and the direction signal HD is a direction detection signal when the output OUT of the half-bridge circuit falls. This means that the direction detection circuit 108 'has two direction detection circuits. The two direction detection circuits detect the direction of the load current at different times in time series.

  The purpose and operation of the differential pulse circuit, the pulse addition circuit, and the SR_ flip-flop have been described in the second embodiment, and will not be described here.

As a result, in the half-bridge circuit using the drive circuit of the first embodiment and the drive direction determination circuit 300,
The load of the half-bridge circuit is an inductive load having an inductor component, etc., and the direction of the load current can be detected in a timely manner regardless of the load current direction of the inductive load at any timing.
It is possible to set the slew rate of the output voltage of the half-bridge circuit to an appropriate value and prevent shoot-through (through state).

(Fifth embodiment)
FIG. 16 is a configuration diagram of the fifth embodiment using a driving direction discriminating circuit 400 in which the driving circuit of the first embodiment and the driving direction discriminating circuit 300 of the third embodiment are partially modified. The operation of the fifth embodiment will be described below.
The fifth embodiment in FIG. 16 is a combination of the first embodiment and the fourth embodiment.

  The difference from the fourth embodiment resides in the drive direction discriminating circuit 400 in the fifth embodiment. The drive direction discriminating circuit 400 further includes a differential pulse circuit 202 that receives an output signal from a switching unit that controls the load switch or a delay circuit that is installed according to the load condition, and outputs a direction signal DIR.

  The differential pulse circuit 202 outputs a set pulse S_EX and a reset pulse R_EX having a certain pulse width according to the rising edge and falling edge of the output signal of the switching means 8 or the delay circuit 9.

  In addition to the set pulse signal group and the reset pulse signal group from the differential pulse circuits 110 and 112, the pulse signals S_EX and R_EX from the differential pulse circuit 202 are supplied to the pulse addition circuit 114 and the SR_ flip-flop 116, and waveform shaping is performed. A direction signal DIR is generated.

  As a result, the drive direction discriminating circuit 400 discriminates the drive direction by adding the control signal of the switching means 8 in addition to the gate terminal voltage GL and the lower side drive signal GLD of the lower transistor T2 of the half bridge circuit. The direction signal DIR can be output with higher accuracy than the circuit 300.

(Sixth embodiment)
FIG. 17 shows a sixth example using a driving direction discriminating circuit 300H in which the driving circuit of the first embodiment, the driving direction discriminating circuit 300 of the third embodiment, and the driving direction discriminating circuit 300 of the third embodiment are slightly modified. It is a block diagram of embodiment. The operation of the sixth embodiment will be described below.
FIG. 17 shows a half-bridge circuit using the driving circuit of the first embodiment of the present invention and the driving direction discrimination circuit 300 and the driving direction discrimination circuit 300H of the third embodiment.

  The half-bridge circuit: switching devices T1 and T2 such as two power MOSFET transistors in which capacitive current flows through its control terminal during the off period; two drive circuits DU and DL that drive the transistors T1 and T2 A signal for processing the drive signal for driving the half-bridge circuit is input to the upper drive circuit DU for driving the upper transistor T1 and the lower drive circuit DL for driving the lower transistor T2. A drive control circuit 5 for generating the lower drive signal GLD; a level shift 6 for transmitting the GUD signal to the upper drive circuit DU; and the other end of the load 11 connected to the output terminal OUT of the half-bridge output circuit as a power source VM. A load switch 7 for switching the connection to GND or a switch for controlling the switching of the load switch 7; A moving direction detection circuit 300; composed of a drive direction detection circuit 300H.

  The half-bridge circuit of the sixth embodiment has almost the same configuration as that described in the fourth embodiment, but the difference from the fourth embodiment is that a drive direction discriminating circuit 300H is provided. .

The drive direction discriminating circuit 300H is a drive direction discriminating circuit dedicated to the upper drive circuit DU of the half-bridge circuit, and the direction signal DIR_H output from the drive direction discriminating circuit 300H does not go through the level shift 6 but directly to the upper drive circuit DU. The selector 34 can be controlled.
With this configuration, the load on the circuit configuration of the level shift 6 can be reduced.

  Next, the operation of the drive direction determination circuit 300H will be described with reference to FIGS. FIG. 18 is a block diagram showing in detail the driving direction discriminating circuit 300H and the driving direction discriminating circuit 300 from the diagram of the sixth embodiment of FIG. 17, and FIG. 19 is a timing waveform diagram of each signal shown in FIG. It is.

Since the description of the drive direction determination circuit 300 in the third embodiment has been described in the fourth embodiment,
I will omit the explanation on this point.

  The driving direction discriminating circuit 300H is different from the driving direction discriminating circuit 300 in the following two points.

(1) As shown in FIGS. 17 and 18, the potential on the low power supply side of the drive direction determination circuit 300H is not the ground potential GND of the half-bridge circuit but the output terminal voltage OUT of the half-bridge circuit.
(2) As shown in FIG. 18, each signal polarity of the direction detection circuit is different from that of the direction detection circuit of the drive direction determination circuit 300.

  With the configuration (1), the direction signal DIR of the drive direction determination circuit 300H can be directly transmitted to the upper drive circuit DU without passing through the level shift 6. For this reason, it is necessary to change the polarity of each signal of the direction detection circuit as described in (2) above.

As shown in FIG. 18, the circuit configuration of the direction detection circuit 2H of the drive direction determination circuit 300H is almost the same as that of the direction detection circuit 2 of the drive direction determination circuit 300, but the polarities of the signals are slightly different.
Therefore, the direction detection operation of the direction detection circuit 108′H is different from that of the direction detection circuit 108.

As shown in FIGS. 18 and 19, the LD_H output terminal of the direction detection circuit 108′H is
When the rising edge of the delayed signal GUD2H is detected by delaying the signal GUH after passing the level shift 6 of the upper drive signal GUD for a certain time,
When the gate terminal voltage GU-OUT of the upper transistor T1 is higher than the threshold voltage VthH of the hysteresis comparator 104 included in the direction detection circuit 108'H, an L level is output, and the gate terminal voltage GU-OUT of the upper transistor T1 is When it is lower than the threshold voltage VthH, the H level is output.

The HD_H output terminal of the direction detection circuit 108 ′ is
When the falling edge of the delayed signal GUD2H obtained by delaying the signal GUH after passing the level shift of the upper drive signal GLD by a certain time is detected,
When the gate terminal voltage GU-OUT of the upper transistor T1 is lower than the threshold voltage VthL of the hysteresis comparator, the L level is output, and when the gate terminal voltage GU-OUT of the upper transistor T1 is higher than the threshold voltage VthL, the H level is output. Is output.

  As the direction detection circuit 108′H operates to output the direction detection signals HD_H and LD_H as described above, it can be determined whether the output terminal OUT of the half-bridge circuit is outputting the load current as a source or sinking. .

  This is illustrated in the timing waveform diagram of FIG. The left half of FIG. 19 shows the case where the load current is sinked into the OUT terminal, and the right half of FIG. 19 shows the case where the load current is sourced from the OUT terminal. The drive signal, the upper drive signal GUD, the lower drive signal GLD, the gate voltage GU-OUT of the transistor T1, in each of the load currents (1), (2), (3), and (4) shown in FIG. The gate voltage GL and the output voltage OUT (VO) of the transistor T2 are illustrated in FIG.

From the timing diagrams of these waveforms and the operation description of the direction detection circuit 108′H described above, if the direction signals LD_H and HD_H transition from the H level to the L level, the load current is sunk input to the output terminal OUT of the half-bridge circuit, If the direction signals LD_H and HD_H transition from the L level to the H level, it can be determined that the load current is input to the output terminal OUT of the half-bridge circuit.
The direction signal LD_H is a direction detection signal when the output OUT of the half-bridge circuit rises, and the direction signal HD_H is a direction detection signal when the output OUT of the half-bridge circuit falls.

  This direction detection circuit 108'H can detect the direction of the load current in two transition states, rising and falling, of the output OUT of the half-bridge circuit.

(Seventh embodiment)
The seventh embodiment shown in FIG. 20 is an example in which an H-bridge circuit is configured using the drive circuit of the first embodiment. The operation of the seventh embodiment will be described below.
FIG. 20 shows an H-bridge circuit using the drive circuit of the first embodiment.

There are two H bridge circuits, and the load 11 is driven as a pair. These two circuits are called a forward side circuit 50 and a reverse side circuit 60.
The load 11 driven by the H bridge circuit is inserted between the output terminal FOUT of the forward side circuit 50 and the output terminal ROUT of the reverse side circuit 60.
The forward side circuit 50 and the reverse side circuit 60 are the same, and each circuit is constituted by a half-bridge circuit. The configuration of the half-bridge circuit will be described below. Since the forward side and the reverse side are the same, the forward-side half bridge circuit will be described for convenience.

  This forward-side half-bridge circuit 50 includes: switching devices T1 and T2 such as two power MOSFET transistors in which capacitive current flows through the control terminal during the off period; and a drive circuit FDU that drives the transistors T1 and T2, respectively. FDL; an input to the upper drive signal FGUD that is input to the upper drive circuit FDU that drives the upper transistor T1 by signal processing the drive signal that drives the half-bridge circuit, and an input to the lower drive circuit FDL that drives the lower transistor T2 A drive control circuit 5 for generating a lower drive signal FGLD to be transmitted; a level shift 6 for transmitting the FGUD signal to the upper drive circuit FDU; an input signal of the selector of the upper drive circuit FDU and the selector of the lower drive circuit FDL And an inverter 10 for inverting the polarity of the input signal.

  The H-bridge circuit includes: two half-bridge circuits 50 and 60 configured as described above; and an input signal direction determination circuit 70 for determining the drive direction of the load 11 between the output terminals FOUT and ROUT. Composed.

  The input signal direction discriminating circuit 70 detects two input signals of the H bridge circuit, that is, the drive signal FD of the forward side circuit 50 and the drive signal RD of the reverse side circuit 60, and the load of the H bridge circuit causes the forward side circuit 50 to be detected. At the source output, it is determined whether the reverse side circuit 60 is driven in a sink input manner or in the opposite direction, and the direction signals FDIR and RDIR are sent to the forward side circuit 50 and the reverse side circuit 60. Output with appropriate direction signal polarity.

  It should be noted that there is a delay having an appropriate delay time depending on the type of load between the output terminal of the input signal direction discrimination circuit 70 and the input terminal of the inverter of each half-bridge circuit and the input terminal of the selector of the lower drive circuit. A circuit 80 may be installed. This corresponds to the case where the load 11 is an inductive load having an inductor component or the like, and when the load driving direction is switched, the switching of the direction in which the load current flows is delayed with respect to the switching of the load driving direction. The delay time of the delay circuit 80 can be set to an appropriate delay time value from the inductor component and resistance component of the load.

  However, since only the delay circuit 80 does not know that the direction of the load current is switched from the source output to the sink input at an accurate timing, the direction of the load current is determined using a direction determination circuit that determines the switching of the direction of the load current. And the direction signal DIR may be sent to the drive circuits DU and DL based on the detected signal. This embodiment will be described later separately.

  21A, 21B, and 21C are circuit diagrams and timing diagrams for explaining the operation of the input signal direction discriminating circuit shown in FIG. The timing diagram of FIG. 21B shows a case where the time difference between the drive signal FD of the forward side circuit 50 and the drive signal RD of the reverse side circuit 60 is larger than the delay time DS of the delay circuit of the input signal direction discrimination circuit 70 (FIG. 21A). . Usually, the value of DS is set to a smaller time value than the minimum setting value of the time difference between the drive signals FD and RD for the H bridge circuit to drive the load.

  The operation of the input signal direction discrimination circuit 70 will be described with reference to the timing charts of FIGS. 21B and 21C. In particular, FIG. 21B shows a case where the FD and RD time difference is larger than DS, and FIG. 21C shows a case where there is no FD and RD time difference.

  Although not shown in FIG. 21B due to the rising edge of the drive signal FD of the forward side circuit 50, the output voltage of the FOUT terminal of the H bridge circuit has a certain delay time as shown in FIG. 11, FIG. 15, and FIG. Stand up later. This delay time varies depending on the direction of the load current, the load current value, and variations in characteristics of the transistors T1, T2, etc. Further, the output voltage of the ROUT terminal of the H bridge circuit rises after a certain delay time in the same manner as the output voltage of the FOUT terminal by the rising edge of the drive signal RD of the reverse side circuit 60.

  When the drive signal FD rises ahead of the drive signal RD as shown in FIG. 21B, the load current is inductive because the FOUT terminal voltage rises ahead of the ROUT terminal voltage. In a general case where the load is not a load, the current flows from the FOUT terminal to the ROOT terminal via the load.

  At this time, the input signal direction discrimination circuit 70 outputs the direction signal FDIR to the forward side circuit 50 at the L level, and outputs the direction signal RDIR to the reverse side circuit 60 at the H level. As a result, the selector 34 of the upper drive circuit FDU of the forward side circuit 50 operates by selecting the sink circuit 33, and the selector 44 of the lower drive circuit FDL operates by selecting the sink transistor M2. Similarly, the selector of the upper drive circuit RDU of the reverse side circuit 60 operates by selecting the sink transistor M1, and the selector of the lower drive circuit RDL operates by selecting the sink circuit.

  The circuit operation of the upper side drive circuit FDU and the lower side drive circuit FDL of the forward side circuit 50 and the circuit operation of the upper side drive circuit RDU and the lower side drive circuit RDL of the reverse side circuit 60 are operations appropriate to the direction of the load current. It is. Therefore, the input signal direction discriminating circuit 70 outputs appropriate direction signals FDIR and RDIR, so that the slew rate of the output voltage of the output terminal FOUT and the slew rate of the output voltage of the output terminal ROUT are set to appropriate values. It can be set to minimize the electromagnetic interference level, and shoot-through between the transistors T1 and T2 (through state) and shoot-through between the transistors T3 and T4 can be prevented.

  In addition, due to the falling edge of the drive signal FD of the forward side circuit 50, the output voltage of the FOUT terminal of the H bridge circuit falls after a certain delay time as in the case of the rising edge described above. This delay time varies depending on the direction of the load current, the load current value, and variations in characteristics of the transistors T1, T2, and the like. Further, the output voltage of the ROUT terminal of the H-bridge circuit also falls after a certain delay time like the FOUT terminal output voltage due to the falling edge of the drive signal RD of the reverse side circuit 60.

  As shown in FIG. 21B, when the drive signal FD falls before the drive signal RD, the FOUT terminal voltage falls before the ROUT terminal voltage. In a general case where the load is not an inductive load, the current flows from the ROUT terminal to the FOUT terminal via the load.

  At this time, the input signal direction discrimination circuit 70 outputs the direction signal FDIR to the forward side circuit 50 at the H level, and outputs the direction signal RDIR to the reverse side circuit 60 at the L level. As a result, the selector of the upper drive circuit FDU of the forward side circuit 50 operates by selecting the sink transistor M1, and the selector of the lower drive circuit FDL operates by selecting the sink circuit. Similarly, the selector of the upper drive circuit RDU of the reverse side circuit 60 operates with the sink circuit selected, and the selector of the lower drive circuit RDL operates with the sink transistor M2 selected.

  The circuit operation of the upper side drive circuit FDU and the lower side drive circuit FDL of the forward side circuit 50 and the circuit operation of the upper side drive circuit RDU and the lower side drive circuit RDL of the reverse side circuit 60 are operations appropriate to the direction of the load current. It is. Therefore, the input signal direction discriminating circuit 70 outputs appropriate direction signals FDIR and RDIR, so that the slew rate of the output voltage of the output terminal FOUT and the slew rate of the output voltage of the output terminal ROUT are set to appropriate values. It can be set to minimize the electromagnetic interference level, and shoot-through between the transistors T1 and T2 (through state) and shoot-through between the transistors T3 and T4 can be prevented.

  The timing chart of FIG. 21C shows a case where there is no time difference between the drive signal FD of the forward circuit 50 and the drive signal RD of the reverse circuit 60. In this case, the direction signals FDIR and RDIR both become L level at the rising edges of the drive signal FD of the forward side circuit 50 and the drive signal RD of the reverse side circuit 60. Thereby, the selectors of the upper drive circuits of the forward side circuit 50 and the reverse side circuit 60 of the H bridge circuit select the sink circuit, and the selectors of the lower side drive circuit select the sink transistor M2. Further, the direction signals FDIR and RDIR both become H level at the falling edges of the drive signal FD of the forward side circuit 50 and the drive signal RD of the reverse side circuit 60. Thereby, the selectors of the upper drive circuits of the forward side circuit 50 and the reverse side circuit 60 of the H bridge circuit select the sink transistor M1, and the selectors of the lower side drive circuit select the sink circuit.

  With these operations, the input signal direction discrimination circuit 70 slews the output voltage of the output terminal FOUT of the H bridge circuit even when there is no time difference between the drive signal FD of the forward side circuit 50 and the drive signal RD of the reverse side circuit 60. The rate and the slew rate of the output voltage at the output terminal ROUT can be set to appropriate values, the electromagnetic interference level can be minimized, and the shoot through (through state) between the transistors T1 and T2 and between the transistors T3 and T4 Can be prevented from being shot through.

  The input signal direction discrimination circuit 70 of the H bridge circuit shown in FIG. 20 may be replaced with the input signal direction discrimination circuit 70 ′ having the circuit configuration shown in FIGS. 22A, 22B, and 22C. In particular, FIG. 22B shows a case where the FD and RD time difference is larger than DS, and FIG. 22C shows a case where there is no FD and RD time difference.

  Even when this input signal direction discriminating circuit 70 'is used, the effects and operations when the time difference between the drive signal FD of the forward side circuit 50 and the drive signal RD of the reverse side circuit 60 is larger than the delay time DS are shown in FIGS. This is the same as that of the input signal direction discrimination circuit 70 shown in FIG. 21C. However, when there is no time difference between the drive signal FD and the drive signal RD, the polarities of the direction signals FDIR and RDIR are different from those of FIGS. 21A, 21B, and 21C.

  In the seventh embodiment, the drive circuit of the first embodiment is applied to the H-bridge circuit. However, the drive circuit is applied to the three-phase inverter circuit or the multi-phase inverter circuit shown in FIGS. 32 and 33. It may be applied. The application to these inverters can be easily imagined and understood from the configuration diagram of the H-bridge circuit in FIG. 20, and the description thereof will be omitted. Here, a configuration diagram example of an input signal direction determination circuit in the case of a three-phase inverter is shown. Only those shown in FIGS. 23A, 23B and 24 are shown. FIG. 23A and FIG. 23B show an example of a configuration diagram and a timing diagram of an input signal direction discrimination circuit of a three-phase inverter. In this timing diagram, how the direction signals UDIR, VDIR, and WDIR of each phase are output from the U-phase drive signal UD, the V-phase drive signal VD, and the W-phase drive signal WD of the three-phase inverter circuit. This is illustrated and described.

  From the relationship between the drive signals UD, VD, and WD in this timing diagram, at the rising edge of each signal, the direction signal UDIR, VDIR, and WDIR of each phase is such that the U phase sources the load current, and the V phase and W phase. Makes the drive circuit of the half-bridge circuit of each phase set the state of sinking the load current.

  At the falling edge of each signal, the direction signals UDIR, VDIR, and WDIR of each phase indicate that the V phase is the source output of the load current, and the U phase and the W phase are sinking the load current. The drive circuit of the half-bridge circuit of the phase is set. FIG. 24 shows an example of the configuration of an input signal direction discrimination circuit of another three-phase inverter. This is an application of the H-bridge circuit of FIG. 22A for three phases.

  The direction setting of these direction signals is correct when the load is a resistive load having no inductor component. However, in the case of an inductive load with an inductor component or a motor load that generates an induced voltage, the flow of the load current of each phase does not match the output voltage of each phase, and the direction setting of these direction signals is The setting is not correct for the load current.

  Even when the inverter load is an inductive load with an inductor component or a motor load that generates an induced voltage, the direction of the load current of each phase is properly detected, and the direction signal is sent to the selector of the half-bridge circuit drive circuit. An embodiment of an H-bridge circuit using a drive direction discrimination circuit that is sent to the circuit will be described later. The idea of the embodiment of the H-bridge circuit can be applied to a three-phase inverter or a multi-phase inverter as it is.

(Eighth embodiment)
In the eighth embodiment shown in FIG. 25, an H bridge circuit is configured by using two sets of half bridge circuits using the drive circuit of the first embodiment and the drive direction discriminating circuit 100 of the second embodiment. This is an example.
Since the operation principle of this H-bridge circuit is the same as that of the half-bridge circuit using the drive circuit of the second embodiment and the drive direction discriminating circuit 100 of the second embodiment, the description of the operation of this embodiment is omitted. .

  The eighth embodiment is an H bridge circuit using the drive circuit of the first embodiment and the drive direction discrimination circuit 100 of the second embodiment. However, the eighth embodiment is an H bridge circuit. Alternatively, the three-phase inverter circuit or the multi-phase inverter circuit shown in FIGS. 34 and 35 may be used.

  Similarly to FIG. 26, an example in which an H-bridge circuit using the drive circuit of the first embodiment and the drive direction discrimination circuit 100 of the second embodiment is configured is illustrated. This is obtained by deleting the drive direction discriminating circuit 100 of the half bridge circuit of the reverse side circuit from the H bridge circuit of FIG. In the case of an H bridge circuit, if there are only two phases of the half bridge circuit and the load drive current direction of the half bridge circuit output of the forward side circuit for one phase can be determined, the load drive current of the half bridge circuit output of the other reverse side circuit Since the direction is determined, the drive direction discrimination circuit 100 of the reverse side circuit can be deleted. In the three-phase inverter circuit or the multi-phase inverter circuit, the drive direction discrimination circuit 100 is required for each half-bridge circuit of each phase.

(Ninth embodiment)
The ninth embodiment shown in FIG. 27 uses two sets of half-bridge circuits using the drive circuit of the first embodiment and the drive direction discrimination circuit 200 described in the third embodiment, and the seventh embodiment. This is an embodiment in the case where an H-bridge circuit is configured using the input signal direction discrimination circuit described in the above.
Since the operation principle of this H-bridge circuit overlaps with the description of the half-bridge circuit of the third embodiment and the description of the H-bridge circuit of the seventh embodiment, the description of the operation of this example is omitted.
The ninth embodiment is an H bridge circuit using the drive circuit of the first embodiment and the drive direction determination circuit 200 described in the third embodiment. However, the ninth embodiment is an H bridge circuit. Instead, the three-phase inverter circuit or the multi-phase inverter circuit shown in FIGS. 36 and 37 may be used.

(Tenth embodiment)
In the tenth embodiment shown in FIG. 28, an H-bridge circuit is configured by using two sets of half-bridge circuits using the drive circuit of the first embodiment and the drive direction discriminating circuit 300 of the third embodiment. It is an example.
Since the operating principle of this H-bridge circuit is the same as that of the half-bridge circuit using the driving circuit in the fourth embodiment and the driving direction discriminating circuit 300 in the third embodiment, description of the operation of this embodiment is omitted. .
Although the tenth embodiment is an H bridge circuit using the drive circuit of the first embodiment and the drive direction discrimination circuit 300 of the third embodiment, the tenth embodiment is not an H bridge circuit. The three-phase inverter circuit or the multi-phase inverter circuit shown in FIGS. 38 and 39 may be used.

  Similarly to FIG. 29, an example in which an H-bridge circuit using the drive circuit of the first embodiment and the drive direction determination circuit 300 of the third embodiment is configured is illustrated. This is obtained by deleting the drive direction discrimination circuit 300 of the half-bridge circuit of the reverse side circuit from the H-bridge circuit of FIG. In the case of an H bridge circuit, if there are only two phases of the half bridge circuit and the load drive current direction of the half bridge circuit output of the forward side circuit for one phase can be determined, the load drive current of the half bridge circuit output of the other reverse side circuit Since the direction is determined, the drive direction discrimination circuit 100 of the reverse side circuit can be deleted. In the three-phase inverter circuit or the multi-phase inverter circuit, the driving direction determination circuit 300 is required for each half-bridge circuit of each phase.

(Eleventh embodiment)
The eleventh embodiment shown in FIG. 30 uses two sets of half-bridge circuits using the drive circuit of the first embodiment and the drive direction discrimination circuit 400 described in the fifth embodiment, and the seventh embodiment. This is an embodiment in the case where an H-bridge circuit is configured using the input signal direction discrimination circuit described in the above.

  Since the operation principle of this H-bridge circuit overlaps with the description of the half-bridge circuit of the fifth embodiment and the description of the H-bridge circuit of the seventh embodiment, the description of the operation of this example is omitted.

  Although the eleventh embodiment is an H bridge circuit using the drive circuit of the first embodiment and the drive direction discrimination circuit 400 described in the fifth embodiment, the eleventh embodiment is an H bridge circuit. Instead, the three-phase inverter circuit or the multi-phase inverter circuit shown in FIGS. 40 and 41 may be used.

(Twelfth embodiment)
The second embodiment shown in FIG. 31 uses two sets of half-bridge circuits using the drive circuit of the first embodiment, the drive direction discrimination circuit 300 of the third embodiment, and the drive direction discrimination circuit 300H. It is an Example at the time of comprising a circuit.

  The operating principle of this H-bridge circuit is that of a half-bridge circuit using the driving circuit of the first embodiment of the sixth embodiment, the driving direction discrimination circuit 300 of the third embodiment, and the driving direction discrimination circuit 300H. Since it is the same, the description regarding the operation of this embodiment is omitted.

  The twelfth embodiment is an H bridge circuit using the driving circuit of the first embodiment, the driving direction discrimination circuit 300 and the driving direction discrimination circuit 300H of the third embodiment, but the twelfth embodiment May be the three-phase inverter circuit or the multi-phase inverter circuit shown in FIGS. 42 and 43 instead of the H-bridge circuit.

As described above, the present invention provides a driving device mounted on a semiconductor integrated circuit device.
It has a drive circuit for driving a switching device in which a capacitive current flows in the control terminal during the OFF period of the switching device, and a drive direction discrimination circuit for discriminating the direction of the load current driven by this drive circuit. With this configuration, a half-bridge circuit that uses a combination of two sets of switching devices and a drive circuit and a drive direction discriminating circuit can optimally adjust the electromagnetic interference level due to the change of the output voltage, and the penetration mode ( This makes it possible to prevent a shoot-through or a false spot), and it is an optimum half-bridge circuit for driving a load with a switching device.

1 Upper transistor 2 Lower transistor
DESCRIPTION OF SYMBOLS 3 Upper side drive circuit 4 Lower side drive circuit 5 Drive control circuit 6 Level shift 7 Load switch 8 Switching means 9 Delay circuit 10 Inverter 11 Load

Claims (16)

A drive circuit for driving a switching device in which a capacitive current flows through the control terminal during an off period of the switching device having a control terminal,
An input terminal for receiving a control signal for turning on or off the switching device;
A source circuit that sources a drive current to the control terminal of the device in response to a first level or second level signal of the input terminal;
A sink circuit that sinks and outputs a drive current to the control terminal of the switching device in response to a second level or first level signal of the input terminal;
A current sink transistor that sinks capacitive current through the control terminal during the off period of the switching device;
An I / F circuit that generates an input drive signal of the source circuit and an input drive signal to the sink circuit or the sink transistor in accordance with a signal of the input terminal;
A selector that selects whether an input drive signal to the sink circuit or the sink transistor is output as an input drive signal to the sink circuit or the sink transistor;
A drive circuit comprising: an input terminal that receives a selection signal to the selector that controls the selection operation.   When the selector outputs the input drive signal to the sink circuit and drives the sink circuit, the selector sends a signal for turning off the sink transistor, and outputs the input drive signal to the control terminal of the sink transistor. 2. The driving circuit according to claim 1, wherein when the transistor is driven, a signal for turning off the sink circuit is sent or a signal for continuously turning on the sink circuit is sent.   The source current of the source circuit and the sink current of the sink circuit provide an appropriate drive current to the control terminal of the switching device, and a half bridge circuit, an H bridge circuit configured by a plurality of the switching devices and the drive circuit, The drive circuit according to claim 1, wherein a slew rate of an output voltage of a three-phase inverter circuit or the like is set to an appropriate value.   The drive circuit according to claim 1, wherein the current sink transistor has a sufficient current capability, and can sufficiently absorb a capacitive current flowing in a control terminal of the switching device. An upper switching device (T1) and a lower switching device (T2) for controlling current supply to the load;
An upper drive circuit (DU) and a lower drive circuit (DL) for driving the upper switching device (T1) and the lower switching device (T2), respectively;
In order to drive the upper switching device (T1), an upper drive signal (GUD) to be input to the upper drive circuit (DU) is generated, and a lower drive circuit (DL) is used to drive the lower switching device (T2). A drive control circuit for generating a lower drive signal (GLD) to be input to
A level shift for transmitting the upper drive signal (GUD) to the upper drive circuit (DU);
Switching means for switching the current direction to the load;
An inverter for inverting the polarity of the direction signal from the switching means,
The upper drive circuit (DU)
An input terminal for receiving a control signal for turning on or off the upper switching device (T1);
An upper source circuit that outputs a drive current to the control terminal of the upper switching device (T1) in response to a first level or second level signal of the input terminal;
An upper sink circuit that sinks and outputs a drive current to the control terminal of the upper switching device (T1) in response to a second level or first level signal of the input terminal;
An upper sink transistor (M1) that sinks a capacitive current through a control terminal during an off period of the upper switching device (T1);
A first input drive signal to the upper source circuit is generated in accordance with a signal at the input terminal, and an upper I / O to generate a second input drive signal to the upper sink circuit or the upper sink transistor (M1). F circuit,
A selector that selectively supplies the second input drive signal to either the upper sink circuit or the upper sink transistor based on a signal from the inverter;
The lower drive circuit (DL)
An input terminal for receiving a control signal for turning on or off the lower switching device (T2);
A lower source circuit that sources a drive current to the control terminal of the lower switching device (T2) in response to a first level or second level signal of the input terminal;
A lower sink circuit that sinks and outputs a drive current to the control terminal of the lower switching device (T2) according to a second level or first level signal of the input terminal;
A lower sink transistor (M2) that sinks a capacitive current through a control terminal during an off period of the lower switching device (T2);
A first input drive signal to the lower source circuit is generated according to a signal of the input terminal, and a second input drive signal to the lower sink circuit or the lower sink transistor (M2) is generated. A lower I / F circuit;
And a selector that selectively supplies the second input drive signal to either the lower sink circuit or the lower sink transistor based on a signal from the switching unit.   6. The driving apparatus according to claim 5, further comprising a delay circuit that delays a direction signal from the switching means for a predetermined time. Furthermore, it has a drive direction discrimination circuit,
The drive direction discrimination circuit
A hysteresis comparator that detects whether the output voltage to the load exceeds a predetermined threshold voltage;
The output to the comparator and at least one of the upper drive signal (GUD) and the lower drive signal (GLD) are used to detect whether the current flowing through the load is forward or reverse, and A direction detection circuit for outputting a direction detection signal (LD) or a second direction detection signal (HD);
Detecting one edge of the first direction detection signal (LD) and outputting a first pulse, detecting the other edge of the first direction detection signal (LD) and outputting a second pulse; Differential pulse circuit;
Detecting one edge of the second direction detection signal (HD) and outputting a third pulse, while detecting the other edge of the second direction detection signal (HD) and outputting a fourth pulse; Differential pulse circuit;
A pulse addition circuit that combines the second pulse and the fourth pulse into one output with a first logical sum, and combines the first pulse and the third pulse into one output with a second logical sum;
6. The driving device according to claim 5, further comprising a flip-flop that receives or sets an output of the pulse addition circuit.   The hysteresis comparator has a high threshold voltage and a low threshold voltage, and outputs a first level when the output voltage to the load rises above the high threshold voltage, while the output voltage to the load falls below the low threshold voltage. The driving device according to claim 7, wherein the second level is output.   The drive device according to claim 7, wherein the output voltage to the load is detected downstream of the upper switching device T1 and the lower switching device T2.   8. The driving apparatus according to claim 7, wherein the output voltage to the load is detected upstream of the upper switching device T1 and the lower switching device T2.   The driving apparatus according to claim 7, further comprising a delay circuit that delays an output from the hysteresis comparator for a predetermined time. In addition, there is a third differential pulse circuit that detects an edge in one of the direction signals from the switching means and outputs a fifth pulse, while detecting the other edge of the direction signal and outputs a sixth pulse. And
The driving device according to claim 7, wherein a fifth pulse is added to the second logical sum while a sixth pulse is added to the first logical sum.   8. The driving apparatus according to claim 7, wherein the driving direction discrimination circuit is provided in common for the upper driving circuit (DU) and the lower driving circuit (DL).   8. The driving apparatus according to claim 7, wherein one driving direction discriminating circuit is provided for each of the upper driving circuit (DU) and the lower driving circuit (DL).   6. The driving apparatus according to claim 5, wherein when the current supply to the load is two-phase, the current supply is individually controlled for each phase.   6. The driving apparatus according to claim 5, wherein when the current supply to the load has three phases, the current supply is individually controlled for each phase.

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