JP2011138604A - Thin film magnetic storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a chip area of an MRAM device formed by a magnetic body memory cell having a magnetic tunnel junction part. <P>SOLUTION: A read word line RWL and a write word line WWL are arranged corresponding to a row of an MTJ memory cell, and a bit line BL and a reference voltage wiring SL are arranged corresponding to a column of the MTJ memory cell. The MTJ memory cells that adjoin each other in the column direction share at least one of the read word line RWL and the write word line WWL. Consequently, the pitch of signal wiring laid out over a memory array 10 is relaxed, and the MTJ memory cells can be arranged efficiently, thereby achieving high integration of the memory array 10. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a thin film magnetic memory device, and more particularly to a random access memory including a memory cell having a magnetic tunnel junction (MTJ).

  An MRAM (Magnetic Random Access Memory) device has attracted attention as a storage device that can store nonvolatile data with low power consumption. An MRAM device is a storage device that performs non-volatile data storage using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit and allows random access to each of the thin film magnetic bodies.

  In particular, in recent years, it has been announced that the performance of an MRAM device is dramatically improved by using a thin film magnetic material using a magnetic tunnel junction (MTJ) as a memory cell. For MRAM devices with memory cells with magnetic tunnel junctions, see “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, Feb 2000. and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, Feb. 2000.

  FIG. 88 is a schematic diagram showing a configuration of a memory cell having a magnetic tunnel junction (hereinafter also simply referred to as “MTJ memory cell”).

  Referring to FIG. 88, the MTJ memory cell includes a magnetic tunnel junction MTJ whose resistance value changes according to the data level of stored data, and an access transistor ATR. Access transistor ATR is formed of a field effect transistor, and is coupled between magnetic tunnel junction MTJ and ground voltage Vss.

  For MTJ memory cells, write word line WWL for instructing data writing, read word line RWL for instructing data reading, and the level of stored data at the time of data reading and data writing A bit line BL which is a data line for transmitting the electrical signal is disposed.

FIG. 89 is a conceptual diagram illustrating a data read operation from the MTJ memory cell.
Referring to FIG. 89, magnetic tunnel junction MTJ includes a magnetic layer (hereinafter simply referred to as “fixed magnetic layer”) FL having a fixed magnetic field in a certain direction, and a magnetic layer (hereinafter simply referred to as “fixed magnetic layer”) having a free magnetic field. VL) (also referred to as “free magnetic layer”). A tunnel barrier TB formed of an insulator film is disposed between the fixed magnetic layer FL and the free magnetic layer VL. In the free magnetic layer VL, either one of the magnetic field in the same direction as that of the fixed magnetic layer FL and the magnetic field in a direction different from that of the fixed magnetic layer FL is written in a nonvolatile manner according to the level of stored data.

  At the time of data reading, access transistor ATR is turned on in response to activation of read word line RWL. As a result, a sense current Is supplied as a constant current from a control circuit (not shown) flows through a current path from the bit line BL to the magnetic tunnel junction MTJ to the access transistor ATR to the ground voltage Vss.

  The resistance value of the magnetic tunnel junction MTJ changes according to the relative relationship in the magnetic field direction between the fixed magnetic layer FL and the free magnetic layer VL. Specifically, when the magnetic field direction of the pinned magnetic layer FL and the magnetic field direction written in the free magnetic layer VL are the same, the resistance of the magnetic tunnel junction MTJ is greater than when both magnetic field directions are different. The value becomes smaller.

  Therefore, at the time of data reading, the voltage change caused at the magnetic tunnel junction MTJ by the sense current Is differs according to the magnetic field direction stored in the free magnetic layer VL. Thus, if the supply of the sense current Is is started after the bit line BL is once precharged to a predetermined voltage, the level of the data stored in the MTJ memory cell is read by monitoring the voltage level change of the bit line BL. Can do.

FIG. 90 is a conceptual diagram illustrating a data write operation for the MTJ memory cell.
Referring to FIG. 90, at the time of data writing, read word line RWL is inactivated and access transistor ATR is turned off. In this state, a data write current for writing a magnetic field in free magnetic layer VL is supplied to write word line WWL and bit line BL. The magnetic field direction of free magnetic layer VL is determined by a combination of directions of data write currents flowing through write word line WWL and bit line BL, respectively.

  FIG. 91 is a conceptual diagram illustrating the relationship between the direction of data write current and the direction of magnetic field during data writing.

  Referring to FIG. 91, magnetic field Hx indicated on the horizontal axis indicates the direction of magnetic field H (WWL) generated by the data write current flowing through write word line WWL. On the other hand, the magnetic field Hy indicated on the vertical axis indicates the direction of the magnetic field H (BL) generated by the data write current flowing through the bit line BL.

  The magnetic field direction stored in the free magnetic layer VL is newly written only when the sum of the magnetic fields H (WWL) and H (BL) reaches the region outside the asteroid characteristic line shown in the figure. . That is, when a magnetic field corresponding to the region inside the asteroid characteristic line is applied, the magnetic field direction stored in the free magnetic layer VL is not updated.

  Therefore, in order to update the data stored in the magnetic tunnel junction MTJ by the write operation, it is necessary to pass a current through both the write word line WWL and the bit line BL. The magnetic field direction once stored in the magnetic tunnel junction MTJ, that is, the stored data is held in a nonvolatile manner until new data writing is executed.

  Even during data reading, sense current Is flows through bit line BL. However, since the sense current Is is generally set to be about 1 to 2 digits smaller than the data write current described above, the stored data in the MTJ memory cell is erroneously read at the time of data reading due to the influence of the sense current Is. The possibility of rewriting is small.

  The above-described technical literature discloses a technique for constructing an MRAM device that is a random access memory by integrating such MTJ memory cells on a semiconductor substrate.

Roy Scheuerline and 6 others, “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Using FET Switches and Magnetic Tunnel Junctions in Each Cell Tunnel Junction and FET Switch in each Cell), (USA), 2000 Annual Meeting of the Institute of Electrical and Electronics Engineers International Solid State Circuits TA7.2 (2000 IEEE ISSCC Digest of Technical Papers, TA7.2), p. 128-129.

FIG. 92 is a conceptual diagram showing MTJ memory cells integrated and arranged in a matrix.
Referring to FIG. 92, a highly integrated MRAM device can be realized by arranging MTJ memory cells in a matrix on a semiconductor substrate. FIG. 92 shows a case where MTJ memory cells are arranged in n rows × m columns (n, m: natural numbers).

  As already described, it is necessary to arrange the bit line BL, the write word line WWL, and the read word line RWL for each MTJ memory cell. Therefore, n write word lines WWL1 to WWLn and read word lines RWL1 to RWLn and m bit lines BL1 to BLm are arranged for n × m MTJ memory cells arranged in a matrix. There is a need. That is, a configuration in which independent word lines are provided corresponding to each of the read operation and the write operation is required.

FIG. 93 is a structural diagram of an MTJ memory cell arranged on a semiconductor substrate.
Referring to FIG. 93, access transistor ATR is formed in p type region PAR on semiconductor main substrate SUB. Access transistor ATR has source / drain regions 110 and 120 which are n-type regions, and a gate 130. Source / drain region 110 is coupled to ground voltage Vss through a metal wiring formed in first metal wiring layer M1. For the write word line WWL, a metal wiring formed in the second metal wiring layer M2 is used. The bit line BL is provided in the third metal wiring layer M3.

  The magnetic tunnel junction MTJ is disposed between the second metal wiring layer M2 provided with the write word line WWL and the third metal wiring layer M3 provided with the bit line BL. Source / drain region 120 of access transistor ATR is connected to magnetic tunnel junction MTJ through metal film 150 formed in the contact hole, first and second metal wiring layers M1 and M2, and barrier metal 140. Electrically coupled. The barrier metal 140 is a cushioning material provided to electrically couple the magnetic tunnel junction MTJ and the metal wiring.

  As already described, in the MTJ memory cell, the read word line RWL is provided as a wiring independent of the write word line WWL. The write word line WWL and the bit line BL need to pass a data write current for generating a magnetic field having a magnitude greater than a predetermined value at the time of data writing. Therefore, the bit line BL and the write word line WWL are formed using metal wiring.

  On the other hand, the read word line RWL is provided to control the gate voltage of the access transistor ATR, and it is not necessary to actively flow a current. Therefore, from the viewpoint of increasing the degree of integration, the read word line RWL is formed using a polysilicon layer or a polycide structure in the same wiring layer as the gate 130 without newly providing an independent metal wiring layer. .

  As described above, since there are many wirings necessary for data reading and data writing, when the MTJ memory cells are integrated and arranged on the semiconductor substrate, the cell size increases due to the arrangement space of these wirings. There was a problem.

  Further, in order to integrate the MTJ memory cells, it is necessary to reduce the wiring pitch or increase the number of wiring layers, resulting in an increase in manufacturing cost due to complicated process steps.

  Further, since the number of wirings and the number of wiring layers are large, so-called cross-point arrangement in which MTJ memory cells are arranged at each intersection of a word line and a bit line has to be adopted, so that data read and data write It was difficult to ensure a sufficient operating margin.

  Further, at the time of data writing, it is necessary to pass a relatively large data write current through the bit line BL, and it is necessary to control the direction of this data write current according to the level of the write data. For this reason, there is a problem that a circuit for controlling the data write current becomes complicated.

  The present invention has been made to solve such problems, and an object of the present invention is to reduce the number of wirings arranged in the entire memory array in an MRAM device having MTJ memory cells. This is to achieve high integration of the MRAM device.

  Another object of the present invention is to improve the stability of data read and write operations of an MRAM device by applying a so-called folded bit line configuration.

  Still another object of the present invention is to simplify the configuration of a control circuit for supplying a data write current and reduce the chip area of the MRAM device.

  A thin film magnetic memory device according to the present invention includes a memory array having a plurality of magnetic memory cells arranged in a matrix, and each of the plurality of magnetic memory cells is driven by first and second data write currents. A memory unit having a resistance value that changes according to the level of stored data to be written, and a memory cell selection gate for allowing a data read current to pass through the memory unit during data reading, and corresponding to a row of magnetic memory cells. Provided in correspondence with a plurality of read word lines and magnetic memory cell columns for operating corresponding memory cell selection gates in response to a row selection result during data reading. In addition, a plurality of data lines for supplying a first data write current and a data read current at the time of data reading and a row are provided corresponding to the rows. And a plurality of write word lines that are selectively activated according to a row selection result for flowing the second data write current, and corresponding to either the row or the column, and at the time of data reading A plurality of reference voltage lines for supplying a reference voltage to be used, and adjacent magnetic memory cells include a plurality of write word lines, a plurality of read word lines, a plurality of data lines, and a plurality of reference voltage lines. Share a corresponding one of at least one of them.

  A thin film magnetic memory device according to another aspect of the present invention includes a memory array having a plurality of magnetic memory cells arranged in a matrix, and each of the plurality of magnetic memory cells includes first and second data. A storage unit having a resistance value that changes in accordance with the level of stored data written by a write current; and a memory cell selection gate for allowing the data read current to pass through the storage unit during data reading. A plurality of read word lines provided corresponding to a row and for operating a corresponding memory cell selection gate according to a row selection result at the time of data reading, and provided corresponding to a column of magnetic memory cells, and data A plurality of data lines for flowing a first data write current and a data read current at the time of writing and at the time of reading data are provided corresponding to the rows, Combining a plurality of write word lines selectively activated in accordance with a row selection result in order to pass a second data write current at the time of writing, a reference voltage used for data reading, and the write word line A plurality of word line current control circuits, and adjacent magnetic memory cells correspond to at least one of the plurality of write word lines, the plurality of read word lines, and the plurality of data lines. Share one.

  Preferably, adjacent magnetic memory cells share one of the corresponding write word line and data line farther from the storage unit, and one of the write word line and data line is the write word line. And has a larger cross-sectional area than the other of the signal wirings.

  Preferably, one of the write word line and the data line is formed of a material having higher electromigration resistance than the other of the write word line and the data line.

Alternatively, preferably, the magnetic memory cells adjacent in the column direction share a corresponding one of the plurality of write word lines, and two of the plurality of data lines are data lines at the time of data reading. A plurality of magnetic memory cells constituting a pair and selected by the same read word line are respectively connected to one of two data lines constituting the data line pair, and the data read current is determined by the column selection result. Are supplied to each of the two data lines constituting the data line pair corresponding to.

  Preferably, the magnetic memory cells adjacent in the column direction share a corresponding one of the plurality of read word lines, and two of the plurality of data lines are each a data line at the time of data writing. A plurality of magnetic memory cells constituting a pair and selected by the same write word line are respectively connected to one of the two data lines constituting the data line pair, and the first data write current Are supplied as currents in opposite directions to each of the two data lines constituting the data line pair corresponding to the column selection result.

Alternatively, preferably, each of two of the plurality of data lines forms a data line pair at the time of data reading and data writing, and is selected by the same read word line and the same write word line, respectively. The magnetic memory cells are respectively connected to one of the two data lines constituting the data line pair, and the data read current is applied to the two data lines constituting the data line pair corresponding to the column selection result. The first data write current is supplied to each of the two data lines and is supplied as currents in opposite directions to each of the two data lines.
More preferably, a switch circuit for electrically coupling two data lines constituting the data line pair at the time of data writing and a data line pair corresponding to the column selection result at the time of data writing are provided. A data write circuit for supplying one of the first and second voltages to each of the two data lines constituting the data line is further provided.

A thin film magnetic memory device according to still another aspect of the present invention includes a memory array having a plurality of magnetic memory cells arranged in a matrix, and each of the plurality of magnetic memory cells includes first and second memory cells. A magnetic memory cell, comprising: a storage portion whose resistance value changes according to the level of stored data written by a data write current; and a memory cell selection gate for passing the data read current through the storage portion at the time of data reading Are provided corresponding to a plurality of read word lines for operating a corresponding memory cell selection gate in accordance with a row selection result and a column of magnetic memory cells. The magnetic memory cells further including a plurality of signal wirings and adjacent in the row direction share a corresponding one of the plurality of signal wirings for data writing and data A read / write control circuit for supplying a first data write current and a data read current to the signal wiring at the time of output and a row corresponding to the row, and a second data write at the time of data write A plurality of write word lines that are selectively activated in accordance with a row selection result in order to pass a current, and a plurality of signal wirings, respectively, are provided corresponding to a reference voltage used for data reading and a plurality of signal wirings. A plurality of control switches for electrically coupling one of the corresponding ones of the plurality of control switches, and the plurality of control switches indicate a column selection result of the two signal wirings corresponding to each magnetic memory cell. One selected accordingly is combined with a reference voltage.

  Preferably, magnetic memory cells adjacent in the column direction share a corresponding one of at least one of a plurality of read word lines and a plurality of write word lines.

  Preferably, adjacent magnetic memory cells share one of the corresponding write word line and signal wiring farther from the storage unit, and one of the write word line and signal wiring is the write word It has a larger cross-sectional area than the other of the line and the signal wiring.

  Alternatively, preferably, one of the write word line and the signal wiring is formed of a material having higher electromigration resistance than the other of the corresponding write word line and the signal wiring.

A thin film magnetic memory device according to still another aspect of the present invention includes a memory array having a plurality of magnetic memory cells arranged in a matrix, and each of the plurality of magnetic memory cells includes:
A storage unit whose resistance value changes according to the level of stored data written when the data write magnetic field applied by the first and second data write currents is larger than a predetermined magnetic field, and a storage unit at the time of data reading And a memory cell selection gate for allowing a data read current to pass therethrough, provided corresponding to the row of the magnetic memory cell, and in order to pass a first data write current during data writing, A plurality of write word lines that are selectively activated in response to a plurality of read words, and a plurality of read words for operating corresponding memory cell selection gates in accordance with a row selection result at the time of data reading And a plurality of write data lines for flowing a second data write current at the time of data writing, and corresponding to the columns, And a plurality of read data lines for allowing a data read current to flow during output, and adjacent magnetic memory cells include a plurality of write word lines, a plurality of read word lines, a plurality of read data lines, and a plurality of write data lines. A corresponding one of at least one of the embedded data lines is shared.

  Preferably, adjacent magnetic memory cells share one of the corresponding write word line and write data line farther from the storage unit, and one of the write word line and write data line is The cross-sectional area is larger than the other of the write word line and the write data line.

  Preferably, one of the write word line and the write data line is formed of a material having higher electromigration resistance than the other of the write word line and the write data line.

  Alternatively, preferably, magnetic memory cells adjacent in the column direction share a corresponding one of the plurality of write word lines, and two of the plurality of read data lines are read at the time of data reading. A plurality of magnetic memory cells constituting a data line pair and selected by the same read word line are respectively connected to one of the two read data lines constituting the read data line pair, and the data read current is , Supplied to each of the two read data lines constituting the read data line pair corresponding to the column selection result.

  Preferably, the magnetic memory cells adjacent in the column direction share a corresponding one of the plurality of read word lines, and two of the plurality of write data lines are used during data writing. A plurality of magnetic memory cells constituting a write data line pair and selected by the same write word line are respectively connected to one of the two write data lines constituting the write data line pair. The second data write current is supplied as currents in opposite directions to the two write data lines constituting the write data line pair corresponding to the column selection result.

  Alternatively, preferably, two of each of the plurality of write data lines and read data lines respectively constitute a write data line pair and a read data line pair, and a plurality of magnetic data selected by the same read word line The body memory cells are connected to one of the two read data lines constituting the read data line pair, respectively, and the plurality of magnetic memory cells respectively selected by the same write word line include the write data line Each of the two write data lines constituting the pair is connected to each other, and the data read current is supplied to each of the two read data lines constituting the read data line pair corresponding to the column selection result. The second data write current is supplied as currents in opposite directions to the two write data lines constituting the write data line pair corresponding to the column selection result.

  More preferably, the thin film magnetic memory device includes a switch circuit for electrically coupling two write data lines constituting the write data line pair at the time of data writing, and at the time of data writing. And a data write circuit for supplying one of the first and second voltages to each of the two write data lines constituting the write data line pair corresponding to the column selection result.

  The thin film magnetic memory device according to claim 1 is provided in a memory array in which magnetic memory cells that perform data reading and data writing using a write word line, a read word line, a data line, and a reference voltage wiring are arranged. The number of wirings provided can be reduced. As a result, the memory array can be highly integrated and the chip area can be reduced.

  3. The thin film magnetic memory device according to claim 2, wherein the number of wirings provided in a memory array in which magnetic memory cells for performing data reading and data writing using a write word line, a read word line and a data line are arranged. Can be reduced. As a result, the memory array can be highly integrated and the chip area can be reduced.

  In the thin film magnetic memory device according to claim 3, the wiring pitch is reduced by sharing the large one of the two kinds of wirings through which the data writing current flows, and it is necessary to flow the data writing current. A cross-sectional area can be secured. As a result, in addition to the effect exhibited by the thin film magnetic memory device according to claim 1 or 2, the electromigration resistance of the wiring through which the data write current flows can be improved, and the operation reliability can be improved.

  In the thin film magnetic memory device according to the fourth aspect, one of the two types of wirings through which the data write current flows is made of a material having a high electromigration resistance. As a result, in addition to the effect exhibited by the thin film magnetic memory device according to the first or second aspect, operational reliability can be improved.

  In the thin film magnetic memory device according to the fifth aspect, by sharing the write word line, high integration can be achieved and the chip area can be reduced. Furthermore, since data reading is performed using two data lines forming a pair, in addition to the effect exhibited by the thin film magnetic memory device according to claim 1, an operation margin at the time of data reading is ensured. Can do.

  In the thin film magnetic memory device according to the sixth aspect, by sharing the read word line, high integration can be achieved and the chip area can be reduced. Furthermore, since data writing is performed using two data lines that form a pair, in addition to the effect exhibited by the thin film magnetic memory device according to claim 1, an operation margin at the time of data writing and Magnetic field noise can be reduced.

  Since the thin film magnetic memory device according to claim 7 performs data reading and data writing using two data lines forming a pair, the effect exhibited by the thin film magnetic memory device according to claim 1 or 2 is achieved. In addition, it is possible to secure an operation margin during data reading and data writing and to reduce data writing noise.

  The thin film magnetic memory device according to claim 8 has a simplified configuration of a peripheral circuit for supplying a data write current to the data line, in addition to the effect exhibited by the thin film magnetic memory device according to claim 6 or 7. Can be

  10. The thin film magnetic memory device according to claim 9, wherein the magnetic body performs data reading and data writing by using a common word line having functions of a write word line, a read word line, a data line and a reference voltage line. Memory cells can be arranged in the memory array with a reduced number of common wires. As a result, the memory array can be highly integrated and the chip area can be reduced.

  In the thin film magnetic memory device according to the tenth aspect, the number of wirings of at least one of the write word line and the read word line can be further reduced. As a result, in addition to the effects exhibited by the thin film magnetic memory device according to the ninth aspect, the memory area can be further integrated and the chip area can be reduced.

  The thin film magnetic memory device according to claim 11 has a large wiring pitch by relaxing the wiring pitch by sharing one of the two types of wirings through which the data writing current flows. A cross-sectional area can be secured. As a result, in addition to the effect exhibited by the thin film magnetic memory device according to claim 9 or 10, the electromigration resistance of the wiring through which the data write current flows can be improved, and the operation reliability can be improved.

  In the thin film magnetic memory device according to the twelfth aspect, one of the two types of wirings through which the data write current flows is required to flow a larger data write current, and is formed of a material having high electromigration resistance. As a result, in addition to the effect exhibited by the thin film magnetic memory device according to the ninth aspect, operation reliability can be improved.

  14. The thin film magnetic memory device according to claim 13, wherein a memory in which a magnetic memory cell for performing data reading and data writing using a write word line, a read word line, a write data line, and a read data line is arranged. The number of wirings provided in the array can be reduced. As a result, the memory array can be highly integrated and the chip area can be reduced.

  The thin-film magnetic memory device according to claim 14 has a large wiring pitch by relaxing the wiring pitch by sharing one of the two types of wirings through which the data writing current flows. A cross-sectional area can be secured. As a result, in addition to the effect exhibited by the thin film magnetic memory device according to the thirteenth aspect, the electromigration resistance of the wiring through which the data write current flows can be improved, and the operation reliability can be improved.

  In the thin film magnetic memory device according to the fifteenth aspect, one of the two types of wirings through which the data write current flows is made of a material having a high electromigration resistance, which requires a larger data write current to flow. As a result, in addition to the effect exhibited by the thin film magnetic memory device according to the thirteenth aspect, operational reliability can be improved.

  In the thin film magnetic memory device according to the sixteenth aspect, by sharing the write word line, high integration can be achieved and the chip area can be reduced. Furthermore, since data reading is executed using two read data lines forming a pair, an operation margin at the time of data reading can be ensured in addition to the effect exhibited by the thin film magnetic memory device according to claim 13. .

  In the thin film magnetic memory device according to the seventeenth aspect, by sharing the read word line, high integration can be achieved and the chip area can be reduced. Furthermore, since data writing is performed using two pairs of write data lines, in addition to the effect exhibited by the thin film magnetic memory device according to claim 13, the operation margin is ensured and the magnetic field is written during data writing. Noise can be reduced.

  The thin-film magnetic memory device according to claim 18 executes data reading and data writing using two read data lines and write data lines that form a pair, respectively, and therefore the thin-film magnetic memory according to claim 13 In addition to the effects produced by the device, it is possible to secure an operation margin during data reading and data writing and to reduce data writing noise.

  The thin film magnetic memory device according to claim 19 has a simplified configuration of a peripheral circuit for supplying a data write current to the data line in addition to the effect exhibited by the thin film magnetic memory device according to claim 17 or 18. Can be

It is a schematic block diagram which shows the whole structure of the MRAM device 1 according to Embodiment 1 of this invention. 3 is a circuit diagram showing a connection relationship between an MTJ memory cell and a signal line according to the first embodiment. FIG. 5 is a timing chart illustrating data writing and data reading with respect to a memory cell according to the first embodiment. FIG. 4 is a structural diagram illustrating an arrangement of memory cells according to the first embodiment. 1 is a block diagram showing a configuration of a memory array 10 according to a first embodiment. 11 is a block diagram showing a configuration of a memory array 10 according to a first modification of the first embodiment. FIG. FIG. 11 is a block diagram showing a configuration of a memory array 10 according to a second modification of the first embodiment. It is a structural diagram explaining the arrangement of the write word line WWL. FIG. 11 is a block diagram showing a configuration of a memory array 10 according to a third modification of the first embodiment. FIG. 11 is a block diagram showing a configuration of a memory array 10 according to a fourth modification of the first embodiment. FIG. 10 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a fifth modification of the first embodiment. 6 is a timing chart showing an operation of a common line SBL corresponding to ON / OFF of a common line control transistor CCT. FIG. 11 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to the second embodiment. FIG. 5 is a circuit diagram showing a configuration of a data write circuit 50w and a data read circuit 50r. FIG. 11 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a first modification of the second embodiment. FIG. 11 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a second modification of the second embodiment. It is a circuit diagram showing a configuration of a data read circuit 51r. FIG. 11 is a circuit diagram showing a connection relationship between a memory cell and a signal line according to the third embodiment. FIG. 11 is a structural diagram illustrating an arrangement of memory cells according to a third embodiment. FIG. 7 is a block diagram showing a configuration of a memory array 10 according to a third embodiment. FIG. 11 is a block diagram showing a configuration of a memory array 10 according to a first modification of the third embodiment. FIG. 11 is a block diagram showing a configuration of a memory array 10 according to a second modification of the third embodiment. FIG. 11 is a block diagram showing a configuration of a memory array 10 according to a third modification of the third embodiment. FIG. 11 is a block diagram showing a configuration of a memory array 10 according to a fourth modification of the third embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a fifth modification of the third embodiment. FIG. 16 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a sixth modification of the third embodiment. FIG. 20 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a seventh modification of the third embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a modification 8 of the third embodiment. FIG. 14 is a circuit diagram showing a connection relationship between a memory cell and a signal line according to the fourth embodiment. FIG. 10 is a structural diagram illustrating an arrangement of memory cells according to a fourth embodiment. FIG. 10 is a block diagram showing a configuration of a memory array 10 according to a fourth embodiment. FIG. 11 is a block diagram showing a configuration of a memory array 10 according to a first modification of the fourth embodiment. FIG. 16 is a block diagram showing a configuration of a memory array 10 according to a second modification of the fourth embodiment. FIG. 16 is a block diagram showing a configuration of a memory array 10 according to a third modification of the fourth embodiment. FIG. 16 is a block diagram showing a configuration of a memory array 10 according to a fourth modification of the fourth embodiment. FIG. 16 is a block diagram showing a configuration of a memory array 10 according to a fifth modification of the fourth embodiment. FIG. 20 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a sixth modification of the fourth embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a seventh modification of the fourth embodiment. FIG. 16 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a modification 8 of the fourth embodiment. FIG. 10 is a circuit diagram showing a connection relationship between a memory cell and a signal line according to the fifth embodiment. FIG. 10 is a structure diagram illustrating an arrangement of memory cells according to a fifth embodiment. FIG. 10 is a block diagram showing a configuration of a memory array 10 according to a fifth embodiment. FIG. 16 is a block diagram showing a configuration of a memory array 10 according to a first modification of the fifth embodiment. FIG. 16 is a block diagram showing a configuration of a memory array 10 according to a second modification of the fifth embodiment. FIG. 16 is a block diagram showing a configuration of a memory array 10 according to a third modification of the fifth embodiment. FIG. 16 is a block diagram showing a configuration of a memory array 10 according to a fourth modification of the fifth embodiment. FIG. 16 is a block diagram showing a configuration of a memory array 10 according to a fifth modification of the fifth embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a sixth modification of the fifth embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a seventh modification of the fifth embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a modification 8 of the fifth embodiment. FIG. 17 is a circuit diagram showing a connection relationship between MTJ memory cells and signal lines according to the sixth embodiment. FIG. 17 is a structural diagram illustrating an arrangement of MTJ memory cells according to a sixth embodiment. FIG. 10 is a block diagram showing a configuration of a memory array 10 according to a sixth embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 according to a first modification of the sixth embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 according to a second modification of the sixth embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 according to a third modification of the sixth embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a fourth modification of the sixth embodiment. FIG. 20 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a fifth modification of the sixth embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a sixth modification of the sixth embodiment. FIG. 16 is a circuit diagram showing a connection relationship between a memory cell and a signal wiring according to a seventh embodiment. FIG. 17 is a structural diagram showing an arrangement of memory cells according to a seventh embodiment. FIG. 20 is a block diagram showing a configuration of a memory array 10 according to a seventh embodiment. FIG. 20 is a block diagram showing a configuration of a memory array 10 according to a first modification of the seventh embodiment. FIG. 25 is a block diagram showing a configuration of a memory array 10 according to a second modification of the seventh embodiment. FIG. 25 is a block diagram showing a configuration of a memory array 10 according to a third modification of the seventh embodiment. FIG. 20 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a fourth modification of the seventh embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a fifth modification of the seventh embodiment. FIG. 32 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a sixth modification of the seventh embodiment. FIG. 29 is a circuit diagram showing a connection relationship between a memory cell and a signal line according to the eighth embodiment. 19 is a timing chart illustrating data writing and data reading with respect to an MTJ memory cell according to the eighth embodiment. FIG. 22 is a structural diagram showing an arrangement of MTJ memory cells according to an eighth embodiment. FIG. 20 is a block diagram showing a configuration of a memory array 10 according to an eighth embodiment. FIG. 22 is a block diagram showing a configuration of a memory array 10 according to a first modification of the eighth embodiment. FIG. 25 is a block diagram showing a configuration of a memory array 10 according to a second modification of the eighth embodiment. FIG. 25 is a block diagram showing a configuration of a memory array 10 according to a third modification of the eighth embodiment. FIG. 20 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a fourth modification of the eighth embodiment. FIG. 25 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a fifth modification of the eighth embodiment. FIG. 25 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a sixth modification of the eighth embodiment. FIG. 25 is a circuit diagram showing a connection relationship between a memory cell and a signal line according to the ninth embodiment. FIG. 30 is a structural diagram illustrating an arrangement of MTJ memory cells according to a ninth embodiment. FIG. 20 is a block diagram showing a configuration of a memory array 10 according to a ninth embodiment. FIG. 25 is a block diagram showing a configuration of a memory array 10 according to a first modification of the ninth embodiment. FIG. 25 is a block diagram showing a configuration of a memory array 10 according to a second modification of the ninth embodiment. FIG. 25 is a block diagram showing a configuration of a memory array 10 according to a third modification of the ninth embodiment. FIG. 29 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a fourth modification of the ninth embodiment. FIG. 38 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a fifth modification of the ninth embodiment. FIG. 38 is a block diagram showing a configuration of a memory array 10 and peripheral circuits according to a sixth modification of the ninth embodiment. It is the schematic which shows the structure of the memory cell which has a magnetic tunnel junction part. It is a conceptual diagram explaining the data read-out operation | movement from an MTJ memory cell. It is a conceptual diagram explaining the data write-in operation | movement with respect to an MTJ memory cell. It is a conceptual diagram explaining the relationship between the direction of a data write current at the time of data writing, and a magnetic field direction. It is a conceptual diagram which shows the MTJ memory cell integratedly arranged by the matrix form. 2 is a structural diagram of an MTJ memory cell disposed on a semiconductor substrate. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Embodiment 1]
FIG. 1 is a schematic block diagram showing an overall configuration of an MRAM device 1 according to the first embodiment of the present invention.

  Referring to FIG. 1, MRAM device 1 performs random access in response to external control signal CMD and address signal ADD, and executes input of write data DIN and output of read data DOUT.

  The MRAM device 1 has a control circuit 5 that controls the overall operation of the MRAM device 1 in response to a control signal CMD, and a plurality of MTJ memory cells (hereinafter also simply referred to as “memory cells”) arranged in a matrix. And a memory array 10. The configuration of the memory array 10 will be described in detail later. A plurality of write word lines WWL and read word lines RWL are arranged corresponding to a row of MTJ memory cells (hereinafter also simply referred to as “memory cell row”). A plurality of bit lines BL and reference voltage lines SL are arranged corresponding to memory cell columns (hereinafter also simply referred to as “memory cell columns”).

  The MRAM device 1 further includes a row decoder 20 that performs row selection in the memory array 10 according to the decoding result of the row address RA indicated by the address signal ADD, and a decoding result of the column address CA indicated by the address signal ADD. In response, column decoder 25 that performs column selection in memory array 10, and word line driver 30 for selectively activating read word line RWL and write word line WWL based on the row selection result of row decoder 20; Word line current control circuit 40 for flowing a data write current to write word line WWL at the time of data writing, and read / write for flowing a data write current and a sense current at the time of data reading and data writing, respectively Write control circuits 50 and 60 are provided.

  Read / write control circuits 50 and 60 control the voltage level of bit line BL at both ends of memory array 10, and bit data write current and sense current for executing data write and data read, respectively. Flow on line BL.

[Configuration and operation of memory cell]
FIG. 2 is a circuit diagram showing a connection relationship between the MTJ memory cell and the signal wiring according to the first embodiment.

  Referring to FIG. 2, a read word line RWL, a write word line WWL, a bit line BL, and a reference voltage line SL are provided for the memory cell.

  Memory cell includes a magnetic tunnel junction MTJ and an access transistor ATR coupled in series. As already described, a MOS transistor which is a field effect transistor formed on a semiconductor substrate is typically applied to the access transistor ATR.

  Access transistor ATR has its gate coupled to read word line RWL. Access transistor ATR is turned on when read word line RWL is activated to a selected state (H level, power supply voltage Vcc), and electrically couples magnetic tunnel junction MTJ and reference voltage line SL. The reference voltage line SL supplies the ground voltage Vss. Magnetic tunnel junction MTJ is electrically coupled between bit line BL and access transistor ATR.

  Therefore, in response to the turn-on of access transistor ATR, a current path from bit line BL to magnetic tunnel junction MTJ to access transistor ATR to reference voltage line SL is formed. By causing the sense current Is to flow through this current path, a voltage change corresponding to the level of data stored in the magnetic tunnel junction MTJ occurs in the bit line BL.

  On the other hand, when read word line RWL is deactivated to a non-selected state (L level, ground voltage Vss), access transistor ATR is turned off, and between magnetic tunnel junction MTJ and reference voltage line SL is turned off. Electrically shut off.

  The write word line WWL is provided in parallel with the read word line RWL and in proximity to the magnetic tunnel junction MTJ. At the time of data writing, a data write current is supplied to write word line WWL and bit line BL, and the level of data stored in the memory cell is rewritten by the sum of magnetic fields generated by these data write currents.

  FIG. 3 is a timing chart illustrating data writing and data reading for the memory cell according to the first embodiment.

First, the operation at the time of data writing will be described.
The word line driver 30 drives the voltage of the write word line WWL corresponding to the selected row to the selected state (H level) according to the row selection result of the row decoder 20. In the non-selected row, the voltage level of the write word line WWL remains in the non-selected state (L level).

  Read word line RWL is not activated and maintained in a non-selected state (L level) during data writing. Since each write word line WWL is coupled to the ground voltage Vss by the word line current control circuit 40, the data write current Ip flows through the write word line WWL of the selected row. On the other hand, no current flows through the write word line WWL in the non-selected row.

  Read / write control circuits 50 and 60 generate a data write current in a direction corresponding to the data level of the write data by controlling the voltage of bit line BL at both ends of memory array 10. For example, when the stored data of “1” is written, the bit line voltage on the read / write control circuit 60 side is set to a high voltage state (power supply voltage Vcc) and the read / write control circuit 50 side on the opposite side is set. Is set to a low voltage state (ground voltage Vss). Thereby, data write current + Iw flows through bit line BL in the direction from read / write control circuit 60 toward 50. On the other hand, when the stored data of “0” is written, the bit line voltages on the read / write control circuit 50 side and 60 side are set to the high voltage state (power supply voltage Vcc) and the low voltage state (ground voltage Vss), respectively. Data write current -Iw flows through bit line BL in the direction from read / write control circuit 50 to 60.

  At this time, it is not necessary to pass the data write current ± Iw to each bit line, and the read / write control circuits 50 and 60 can select a part corresponding to the selected column according to the column selection result of the column decoder 25. The voltage of the bit line BL described above may be controlled so that the data write current ± Iw is selectively supplied to the bit line.

  By setting the direction of the data write currents Ip and ± Iw in this way, the data write current in the reverse direction according to the level “1”, “0” of the stored data to be written at the time of data writing By selecting either + Iw or -Iw and fixing the data write current Ip of the write word line WWL in a fixed direction regardless of the data level, the direction of the data write current Ip flowing through the write word line WWL is changed. Can always be constant. As a result, the configuration of the word line current control circuit 40 can be simplified as described below.

Next, the data read operation will be described.
At the time of data reading, word line driver 30 drives read word line RWL corresponding to the selected row to a selected state (H level) according to the row selection result of row decoder 20. The voltage level of read word line RWL corresponding to the non-selected row is maintained in the non-selected state (L level). At the time of data reading, write word line WWL is maintained in a non-selected state (L level) without being activated.

  Before the data read operation, bit line BL is precharged to a high voltage state (power supply voltage Vcc), for example. When data reading is started from this state and read word line RWL is activated to H level in the selected row, corresponding access transistor ATR is turned on.

  Accordingly, in the memory cell, a current path of the sense current Is is formed between the reference voltage line SL that supplies the ground voltage Vss and the bit line BL via the access transistor ATR. The sense current Is causes a different voltage drop in the bit line BL depending on the data level of data stored in the memory cell. In FIG. 3, when the data level stored as an example is “1” and the magnetic field directions in the fixed magnetic layer FL and the free magnetic layer VL are the same, the stored data is “1”. The voltage drop ΔV1 of the bit line BL is small, and the voltage drop ΔV2 of the bit line BL when the stored data is “0” is larger than ΔV1. By detecting the difference between these voltage drops ΔV1 and ΔV2, the level of data stored in the memory cell can be read.

  The voltage level of reference voltage line SL needs to be set to ground voltage Vss in order to flow a sense current during data reading. On the other hand, since the access transistor ATR is turned off at the time of data writing, the reference voltage line SL does not particularly affect the magnetic tunnel junction MTJ. Therefore, the voltage level of the reference voltage line SL can be set to the ground voltage Vss as in the data reading. Therefore, the reference voltage line SL may be coupled to a node that supplies the ground voltage Vss.

FIG. 4 is a structural diagram illustrating the arrangement of the memory cells according to the first embodiment.
Referring to FIG. 4, access transistor ATR is formed in p type region PAR on semiconductor main substrate SUB. Reference voltage line SL is arranged in first metal interconnection layer M1 and is electrically coupled to one source / drain region 110 of access transistor ATR. Reference voltage line SL is coupled to a node supplying ground voltage Vss at any node on the semiconductor substrate.

  The other source / drain region 120 is magnetically connected via the metal wiring provided in the first metal wiring layer M1 and the second metal wiring layer M2, the metal film 150 formed in the contact hole, and the barrier metal 140. Coupled with the tunnel junction MTJ. The write word line WWL is provided in the second metal wiring layer M2 in the vicinity of the magnetic tunnel junction. Read word line RWL is arranged in the same layer as gate 130 of access transistor ATR.

  Bit line BL is arranged in third metal wiring layer M3 so as to be electrically coupled to magnetic tunnel junction MTJ.

[Sharing signal lines in memory arrays]
FIG. 5 is a block diagram showing a configuration of memory array 10 according to the first embodiment.

  Referring to FIG. 5, memory array 10 has a plurality of memory cells MC arranged in a matrix. In the configuration according to the first embodiment, read word line RWL and write word line WWL are provided corresponding to each memory cell row, and bit line BL and reference voltage line SL are arranged corresponding to each memory cell column. . Read word line RWL and write word line WWL are arranged along the row direction. Bit line BL and reference voltage line SL are arranged along the column direction.

  Memory cells adjacent in the row direction share the same reference voltage line SL. For example, the memory cell groups belonging to the first and second memory cell columns share one reference voltage line SL1. Reference voltage lines SL are similarly arranged for the other memory cell columns. Since the reference voltage wiring SL basically supplies a constant voltage (in this embodiment, the ground voltage Vss), it can be shared in this way without performing special voltage control or the like.

  Word line current control circuit 40 couples each write word line WWL to ground voltage Vss. Thereby, when write word line WWL is activated to a selected state (H level, power supply voltage Vcc), data write current Ip can be supplied to each write word line.

  In the following, when the write word line, the read word line, the bit line, and the reference voltage wiring are collectively expressed, they are represented using the symbols WWL, RWL, BL, and SL, respectively, and a specific write When a word line, a read word line, and a bit line are shown, a subscript is added to these symbols and expressed as RWL1, WWL1.

  By sharing the reference voltage wiring SL between memory cells adjacent in the row direction, the number of wirings arranged in the entire memory array 10 can be reduced. As a result, the memory array 10 can be highly integrated and the chip area of the MRAM device can be reduced.

[Variation 1 of Embodiment 1]
FIG. 6 is a block diagram showing a configuration of memory array 10 according to the first modification of the first embodiment.

  Referring to FIG. 6, in memory array 10 according to the first modification of the first embodiment, memory cells adjacent in the row direction share the same bit line BL. For example, the memory cell groups belonging to the first and second memory cell columns share one bit line BL. Bit lines BL are similarly arranged for other memory cell columns.

  However, if a plurality of memory cells MC are subjected to data reading or data writing corresponding to the same bit line BL, a data collision occurs and the MRAM device malfunctions. Therefore, in memory array 10 according to the first modification of the first embodiment, memory cells MC are arranged in every other row and every other column for each of the memory cell rows and the memory cell columns. Hereinafter, such an arrangement of the memory cells in the memory array 10 is also referred to as “alternate arrangement”. On the other hand, the reference voltage line SL is arranged for each memory cell column.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the first embodiment, detailed description will not be repeated.

  With such a configuration, the wiring pitch of the bit lines BL in the memory array 10 can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 2 of Embodiment 1]
FIG. 7 is a block diagram showing a configuration of the memory array 10 according to the second modification of the first embodiment.

  Referring to FIG. 7, in memory array 10 according to the second modification of the first embodiment, memory cells adjacent in the column direction share the same write word line WWL. For example, the memory cell groups belonging to the first and second memory cell rows share one write word line WWL1. The write word line WWL is similarly arranged for the other memory cell rows.

  Here, in order to perform data writing normally, it is necessary that there are not a plurality of memory cells MC arranged at the intersections of the same write word line WWL and the same bit line BL. Therefore, the memory cells MC are alternately arranged as in the first modification of the first embodiment.

  FIG. 7 shows a configuration in which the reference voltage wiring SL is arranged for each memory cell column. Similar to the configuration of FIG. 5, the memory cell column formed by two adjacent memory cell columns is shown. The reference voltage wiring SL may be shared for each set.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the first embodiment, detailed description will not be repeated.

  With such a configuration, the wiring pitch of the write word lines WWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

  Further, by reducing the wiring pitch of the write word line WWL, it is possible to secure a wider wiring width of the write word line WWL. Thereby, the effect described below further occurs.

FIG. 8 is a structural diagram for explaining the arrangement of the write word lines WWL.
FIG. 8A shows the structure of the memory cell MC corresponding to the configuration of FIGS. In the structure of FIG. 8A, since the write word line WWL is not shared between adjacent memory cell columns, it is difficult to secure the wiring width of each write word line WWL.

  As already described, at the time of data writing, it is necessary to pass a data write current through both bit line BL and write word line WWL. Since the write word line WWL is arranged between the magnetic tunnel junction MTJ via a wiring interlayer insulating film, the distance between the write word line WWL and the magnetic tunnel junction MTJ in the height direction is the bit line. It becomes larger than the distance between BL and the magnetic tunnel junction MTJ. Therefore, at the time of data writing, in order to generate a magnetic field of the same strength at the magnetic tunnel junction MTJ, a larger current is applied to the write word line WWL having a large distance from the magnetic tunnel junction MTJ. Need to flow.

  On the other hand, in the metal wiring on which the write word line WWL or the like is formed, if the current density is excessive, there is a possibility that a disconnection or a short circuit between the wirings may occur due to a phenomenon called electromigration. Therefore, it is desirable to reduce the current density of the write word line WWL.

  FIG. 8B shows the structure of the memory cell MC corresponding to the configuration of FIG. In the structure of FIG. 8B, since the write word line WWL is shared between adjacent memory cell columns, the write word line WWL can be arranged using the arrangement space for two memory cell rows. . Therefore, by increasing the wiring width of each write word line WWL, it is possible to secure a wiring width wider than at least the bit line BL, that is, a large cross-sectional area. As a result, the current density in the write word line WWL can be suppressed and the reliability of the MRAM device can be improved.

  It is also possible to improve reliability by forming a metal wiring (in FIG. 8A and FIG. 8B, the write word line WWL) having a large distance from the magnetic tunnel junction MTJ with a material having high electromigration resistance. Is effective. For example, when other metal wiring is formed of an aluminum alloy (Al alloy), the metal wiring that needs to be considered for electromigration resistance may be formed of copper (Cu).

[Modification 3 of Embodiment 1]
FIG. 9 is a block diagram showing a configuration of memory array 10 according to the third modification of the first embodiment.

  Referring to FIG. 9, in memory array 10 according to the third modification of the first embodiment, memory cells adjacent in the column direction share the same read word line RWL. For example, the memory cell groups belonging to the first and second memory cell rows share one read word line RWL1. Read word lines RWL are similarly arranged for the other memory cell rows.

  Here, in order to perform data reading normally, it is necessary that a plurality of memory cells MC selected by the same read word line RWL are not simultaneously coupled to the same bit line BL. Therefore, the memory cells MC are alternately arranged as in the first modification of the first embodiment.

  The reference voltage wiring SL has a configuration arranged for each memory cell column, but, similar to the configuration of FIG. 5, for each set of memory cell columns formed by two adjacent memory cell columns. The reference voltage line SL may be shared.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the first embodiment, detailed description will not be repeated.

  With such a configuration, the wiring pitch of the read word lines RWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 4 of Embodiment 1]
FIG. 10 is a block diagram showing a configuration of memory array 10 according to the fourth modification of the first embodiment.

  Referring to FIG. 10, in memory array 10 according to the fourth modification of the first embodiment, similarly to the second modification of the first embodiment, the memory cells adjacent in the column direction have the same write word line WWL. Share. For example, the memory cell groups belonging to the first and second memory cell rows share one write word line WWL1. The write word line WWL is similarly arranged for the other memory cell rows.

  Further, the read word line RWL is shared between memory cells adjacent in the column direction. For example, the memory cell groups belonging to the second and third memory cell rows share the read word line RWL2. The read word line RWL is similarly arranged for the subsequent memory cell rows.

  As described above, in order to perform data reading and data writing normally, a plurality of memory cells MC selected by one read word line RWL are not coupled simultaneously with the same bit line BL, and It is necessary that a plurality of memory cells MC simultaneously selected by one write word line WWL cannot be simultaneously applied with a data write magnetic field from the same bit line BL. Therefore, also in the fourth modification of the first embodiment, the memory cells MC are alternately arranged.

  The reference voltage wiring SL has a configuration arranged for each memory cell column, but, similar to the configuration of FIG. 5, for each set of memory cell columns formed by two adjacent memory cell columns. The reference voltage line SL may be shared.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the first embodiment, detailed description will not be repeated.

  With such a configuration, the wiring pitch of the write word line WWL and the read word line RWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be arranged more efficiently, and the memory array 10 can be further highly integrated and the chip area of the MRAM device can be reduced as compared with the second and third modifications of the first embodiment. it can.

  Further, similarly to the second modification of the first embodiment, the electromigration resistance of the write word line WWL can be improved and the reliability of the MRAM device can be improved.

[Modification 5 of Embodiment 1]
FIG. 11 is a block diagram showing a configuration of the memory array 10 and peripheral circuits according to the fifth modification of the first embodiment.

  Referring to FIG. 11, in memory array 10 according to the fifth modification of the first embodiment, reference voltage line SL and bit line BL are integrated into common line SBL. The common wiring SBL is arranged corresponding to each memory cell column. FIG. 11 representatively shows common lines SBL1 to SBL5 corresponding to the first to fifth memory cell columns, respectively.

  Read / write control circuit 50 includes a current supply circuit 51 for supplying a data write current and a sense current, and column selection gates arranged corresponding to the memory cell columns. FIG. 11 representatively shows column select gates CSG1 to CSG5 corresponding to common lines SBL1 to SBL5, respectively. Hereinafter, the plurality of column selection gates are collectively referred to as a column selection gate CSG.

  The column decoder 25 activates one of a plurality of column selection lines provided corresponding to the memory cell columns to a selected state according to the column selection result. FIG. 11 representatively shows column select lines CSL1 to CSL5 corresponding to common lines SBL1 to SBL5, respectively. Hereinafter, the plurality of column selection lines are collectively referred to as a column selection line CSL.

  Each column selection gate CSG is turned on according to the voltage level of the corresponding column selection line CSL.

  Read / write control circuit 60 includes a current supply circuit 61 for supplying a data write current and a write column selection gate arranged corresponding to each memory cell column. Further, a plurality of common wiring control transistors are provided corresponding to the memory cell columns, respectively. FIG. 11 representatively shows write column selection gates WCG1 to WCG5 and common line control transistors CCT1 to CCT5 corresponding to common lines SBL1 to SBL5, respectively. In the following, when the plurality of write column selection gates and common wiring control transistors are collectively referred to, the symbols WCG and CCT are used, respectively.

  Column decoder 25 further activates one of a plurality of write column selection lines provided corresponding to the memory cell columns to a selected state in accordance with the decoding result of column address CA. The write column selection line is activated only during data writing. FIG. 11 representatively shows write column select lines WCSL1 to WCSL5 corresponding to common lines SBL1 to SBL5, respectively. Hereinafter, the plurality of write column selection lines are collectively referred to simply as a write column selection line WCSL.

  Each write column selection gate WCG is turned on according to the voltage level of the corresponding write column selection line WCSL.

  The common line control transistor CCT is provided to share the functions of the reference voltage line SL and the bit line BL with respect to the common line SBL.

  Since the common line SBL also functions as the bit line BL, the memory cells MC are arranged corresponding to the same common line SBL so that the plurality of memory cells MC are not subjected to data reading or data writing. There is a need. Therefore, also in memory array 10 according to the fifth modification of the first embodiment, memory cells MC are alternately arranged.

  FIG. 12 is a timing chart showing the operation of the common line SBL corresponding to ON / OFF of the common line control transistor CCT.

  Referring to FIG. 12, operations at the time of data writing and data reading of write word line WWL and read word line RWL are the same as described with reference to FIG.

  When the common wiring control transistor CCT is turned on, the corresponding common wiring SBL is combined with the ground voltage Vss and functions as the reference voltage wiring SL.

  On the other hand, when corresponding common line control transistor CCT is turned off, common line SBL is coupled between current supply circuits 51 and 61 via column selection gate CSG and write column selection gate WCG.

  At the time of data writing, column selection gate CSG and write column selection gate WCG are turned on according to the column selection result, and the same data write current as in FIG.

  At the time of data reading, column selection gate CSG is turned on according to the column selection result, and a sense current flows through common line SBL. In the configuration using the common line SBL, the common line SBL can share the bit line BL and the reference voltage line SL smoothly by setting the precharge voltage before data reading to the ground voltage Vss. Therefore, the level of stored data held in the memory cell that is the target of data reading is detected according to the amount of voltage increase from ground voltage Vss.

  Further, it is necessary to determine whether each common line SBL is operated as the reference voltage line SL or the bit line BL in correspondence with the row decoding result at the time of data reading. That is, in the memory cell MC in the selected row, the common wiring SBL on the side coupled to the access transistor ATR is caused to function as the reference voltage wiring SL, and the common wiring SBL on the side coupled to the magnetic tunnel junction MTJ is used as the bit line BL. Need to work.

  A control signal RA1 is input to the gates of the common wiring control transistors CCT1, CCT3,... Provided corresponding to the odd-numbered memory cell columns. Control signal RA1 is activated to H level when an odd-numbered memory cell row is selected during data reading.

  A control signal / RA1 is input to the gates of common wiring control transistors CCT2, CCT4,... Provided corresponding to the even-numbered memory cell columns. Control signal / RA1 is activated to H level when an even-numbered memory cell row is selected during data reading.

  At the time of data writing, both control signals RA1 and / RA1 are inactivated to L level. As a result, each common line control transistor CCT is turned off, so that the data write current ± Iw can be supplied to the common line SBL according to the column selection result.

  With such a configuration, data reading and data writing similar to those of the first embodiment can be performed using the common wiring SBL in which the functions of the reference voltage wiring SL and the bit line BL are integrated.

  As a result, the memory array 10 can be highly integrated by relaxing the signal line pitch in the column direction and efficiently arranging the memory cells MC.

  In FIG. 11, further, memory cells adjacent in the column direction share the same write word line WWL, as in the second modification of the first embodiment.

  Therefore, the wiring pitch of the write word line WWL in the memory array 10 can be relaxed. As a result, the memory array 10 can be further highly integrated and the chip area of the MRAM device can be reduced. Further, the electromigration resistance of the write word line WWL can be improved, and the reliability of the MRAM device can be improved.

  In addition, the integration of the reference voltage wiring SL and the bit line BL by the common wiring SBL shown in this modification example is the read operation between adjacent memory cell rows described in the modification examples 3 and 4 of the first embodiment, respectively. It is also possible to apply in combination with sharing of the word line RWL and sharing of both the read word line RWL and the write word line WWL between adjacent memory cell rows.

[Embodiment 2]
In the second embodiment, application of the folded bit line configuration will be described.

  FIG. 13 is a block diagram showing structures of memory array 10 and peripheral circuits according to the second embodiment.

  Referring to FIG. 13, memory array 10 has a plurality of memory cells MC arranged in a matrix. The read word line RWL and the write word line WWL are arranged along the row direction corresponding to each memory cell row, and the bit line BL is arranged along the column direction corresponding to each memory cell column. The reference voltage line SL is arranged for each pair of memory cell columns formed by two adjacent memory cell columns, and is shared between the memory cell columns belonging to the same group. Word line current control circuit 40 couples each write word line WWL to ground voltage Vss. Thereby, when write word line WWL is activated to a selected state (H level, power supply voltage Vcc), data write current Ip can be supplied to each write word line.

  Since the memory cells MC are alternately arranged for each row and column of the memory cell rows and memory cell columns, the memory cells MC are connected to every other bit line BL. Therefore, for each set of memory cell columns formed by two adjacent memory cell columns, a bit line pair can be configured using two corresponding bit lines. For example, the bit line pair BLP1 can be configured by the bit lines BL1 and BL2 corresponding to the first and second memory cell columns, respectively. In this case, since the bit line BL2 transmits data complementary to the bit line BL1, it is also expressed as a bit line / BL1. Similarly for the subsequent memory cell columns, each bit line is arranged so as to form a bit line pair for each set of memory cell columns.

  In the following, of the bit lines constituting each bit line pair, one corresponding to the odd-numbered memory cell column and the other corresponding to the even-numbered memory cell column are also collectively referred to as bit lines BL and / BL. . Thus, data reading and data writing can be executed based on a so-called folded bit line configuration.

  Read / write control circuit 60 includes an equalize transistor that is turned on / off in response to bit line equalize signal BLEQ, and a precharge transistor that is turned on / off in response to bit line precharge signal BLPR.

  An equalize transistor is provided for each pair of memory cell columns for each bit line pair. FIG. 13 representatively shows equalize transistors 62-1 corresponding to bit lines BL1 and BL2 (/ BL1) and equalize transistors 62-2 corresponding to bit lines BL3 and BL4 (/ BL3). For example, equalize transistor 62-1 electrically couples bit lines BL1 and BL2 (/ BL1) in response to activation (H level) of bit line equalize signal BLEQ. Hereinafter, the plurality of equalize transistors are collectively referred to simply as an equalize transistor 62.

  Similarly, equalize transistors 62 provided corresponding to each of the other bit line pairs are similarly connected between bit lines BL and / BL constituting the corresponding bit line pair in response to activation of bit line equalize signal BLEQ. Connect electrically.

  Bit line equalize signal BLEQ is generated by control circuit 5. The bit line equalize signal BLEQ configures each bit line pair when the memory array 10 is in a non-selected state during the standby period of the MRAM device 1 and during the active period of the MRAM device 1 and during the data write operation within the active period. In order to short-circuit the bit lines to be activated, they are activated to H level.

  On the other hand, in the data read operation during the active period of the MRAM device, bit line equalize signal BLEQ is inactivated to L level. In response to this, the bit lines BL and / BL constituting each bit line pair are blocked.

  A precharge transistor is provided for each bit line. FIG. 13 representatively shows precharge transistors 64-1 to 64-4 corresponding to bit lines BL1 to BL4, respectively. Hereinafter, the plurality of precharge transistors are collectively referred to as a precharge transistor 64. The precharge transistors 64 are similarly arranged corresponding to the other bit lines.

  The bit line precharge signal BLPR is generated by the control circuit 5. Bit line precharge signal BLPR is activated to the H level prior to the start of the data read operation in the active period of MRAM device 1. In response to this, each precharge transistor 64 is turned on, whereby each bit line is precharged to a predetermined precharge voltage. FIG. 13 illustrates a configuration when the precharge voltage is the power supply voltage Vcc.

  A column selection line is provided for each bit line pair, that is, for each set of memory cell columns. FIG. 13 representatively shows column select line CSL1 corresponding to the first and second memory cell columns and column select line CSL2 corresponding to the third and fourth memory cell columns. Hereinafter, the plurality of column selection lines are collectively referred to as a column selection line CSL.

  The column decoder 25 activates one of the plurality of column selection lines CSL to a selected state (H level) according to the column selection result.

  Data I / O line pair DI / OP includes data lines IO and / IO, and transmits data write current ± Iw at the time of data writing and sense current Is at the time of data reading. That is, data I / O line pair DI / OP is shared during data reading and data writing.

  Next, the configuration of the column selection gate, data write circuit 50w, data read circuit 50r, and current switching circuit 53a included in read / write control circuit 50 will be described.

  Column selection gates are arranged corresponding to the memory cell columns, respectively. In FIG. 13, column select gates CSG1 to CSG4 corresponding to the first to fourth memory cell columns are representatively shown.

  Two column selection gates CSG corresponding to the same bit line pair are turned on according to a common column selection line CSL. For example, column selection gates CSG1 and CSG2 corresponding to bit line pair BLP1 are turned on / off according to the voltage level of common column selection line CSL1.

  One bit line pair is selected according to the decoding result of the column address CA, that is, the column selection result. In response to the column selection line CSL activated in accordance with the column selection result, the corresponding column selection gate CSG is turned on. As a result, bit lines BL and / BL constituting the selected bit line pair are electrically coupled to data lines IO and / IO constituting data I / O line pair DI / OP, respectively.

  FIG. 14 is a circuit diagram showing configurations of data write circuit 50w and data read circuit 50r.

  Referring to FIG. 14, data write circuit 50w operates in response to control signal WE activated at the time of data writing. Data write circuit 50w includes a P-type MOS transistor 151 for supplying a constant current to node Nw0, a P-type MOS transistor 152 and a current source circuit 153 constituting a current mirror circuit for controlling a passing current of transistor 151. Including.

  Data write circuit 50w further includes inverters 154, 155 and 156 which operate by receiving an operation current from node Nw0. Inverter 154 inverts the voltage level of write data DIN and transmits it to node Nw1. Inverter 155 inverts the voltage level of write data DIN and transmits it to the input node of inverter 156. Inverter 156 inverts the output of inverter 154 and transmits the inverted signal to node Nw2. Therefore, data write circuit 50w sets voltage levels of nodes Nw1 and Nw2 to one of power supply voltage Vcc and ground voltage Vss according to the voltage level of write data DIN.

  Data read circuit 50r operates in response to control signal RE activated at the time of data read, and outputs read data DOUT.

  Data read circuit 50r receives power supply voltage Vcc and is electrically coupled between current source circuits 161 and 162 for supplying a constant current to nodes Ns1 and Ns2, respectively, and node Ns1 and node Nr1. MOS transistor 163, N-type MOS transistor 164 electrically coupled between nodes Ns2 and Nr2, and amplifier 165 for amplifying the voltage difference between nodes Ns1 and Ns2 and outputting read data DOUT Have.

  A reference voltage Vref is applied to the gates of the transistors 163 and 164. The supply current amount of the current source circuits 161 and 162 and the reference voltage Vref are set according to the current amount of the sense current Is. Resistors 166 and 167 are provided to pull down nodes Ns1 and Ns2 to ground voltage Vss. With this configuration, data read circuit 50r can supply sense current Is from each of nodes Nr1 and Nr2.

  Data read circuit 50r further amplifies the difference in voltage change occurring at nodes Nr1 and Nr2 in accordance with the level of stored data of the memory cells connected via the column select gate and the bit line pair, and reads data DOUT is output.

  Current switching circuit 53a includes a switch SW1a for selectively coupling one of node Nw1 of data write circuit 50w and one of node Nr1 of data read circuit 50r to data line IO, and node Nw2 of data write circuit 50w. A switch SW1b that selectively couples one of nodes Nr2 of data read circuit 50r to data line / IO is provided.

  Switches SW1a and SW1b operate in response to control signals RWS having different signal levels during data reading and data writing, respectively.

  In data reading, switches SW1a and SW1b couple output nodes Nr1 and Nr2 of data reading circuit 50r to data lines IO and / IO, respectively. On the other hand, at the time of data writing, switches SW1a and SW1b couple nodes Nw1 and Nw2 of data write circuit 50w to data lines IO and / IO, respectively.

  Referring to FIG. 13 again, operations at the time of data reading and data writing will be described. In the following, a case where the third memory cell column is selected will be described as an example.

  First, an operation during data writing will be described. In response to the column selection result, column selection line CSL2 is activated to a selected state (H level), and column selection gates CSG3 and CSG4 are turned on. Thus, data lines IO and / IO are electrically coupled to bit lines BL3 and BL4 (/ BL3) constituting bit line pair BLP2, respectively. At the time of data writing, each equalizing transistor 62 is turned on, so that the bit lines BL3 and BL4 (/ BL3) are short-circuited.

  Data write circuit 50w sets the voltage level of data lines IO and / IO connected through current switching circuit 53a to one of power supply voltage Vcc and ground voltage Vss. For example, when the data level of write data DIN is L level, the outputs of inverters 154 and 156 shown in FIG. 14 are respectively supplied to power supply voltage Vcc (high voltage state) and ground voltage Vss (low voltage state). Therefore, data write current -Iw for writing L level data is applied to data line IO.

  The data write current -Iw is supplied to the bit line BL3 via the column selection gate CSG3. Data write current -Iw transmitted to bit line BL3 is turned back by equalize transistor 62-2 and transmitted as data write current + Iw in the opposite direction on the other bit line BL4 (/ BL3). Data write current + Iw flowing through bit line BL4 (/ BL3) is transmitted to data line / IO through column select gate CSG4. Therefore, it is not necessary to provide means for current sink in the read / write control circuit 60, and the configuration can be simplified.

  At the time of data writing, any one of write word lines WWL is activated to a selected state (H level), and data write current Ip is supplied. Therefore, in the memory cell column corresponding to bit line BL3, data writing of L level data is executed for the memory cell in which data write current Ip is passed through corresponding write word line WWL.

  On the other hand, when the data level of write data DIN is H level, the setting of voltage levels of nodes Nw1 and Nw2 is opposite to the above case, and bit lines BL3 and / BL3 (BL4) A reverse data write current flows and a data level opposite to the above is written. In this manner, the data write current ± Iw having a direction corresponding to the data level of the write data DIN is turned back by the equalize transistor 62 and supplied to the bit lines BL and / BL.

  In the above, the data writing when the odd-numbered memory cell column is selected has been described. In this case, the data level of write data DIN is written as it is into memory cell MC coupled to bit line BL.

  Since a data write current in the direction opposite to that of bit line BL flows through bit line / BL, when an even-numbered memory cell column is selected, a data level opposite to the data level of write data DIN is Data is written in memory cell MC coupled to bit line / BL. However, as will be apparent from the following description, in this case as well, the data level of the write data DIN can be read correctly.

Next, data reading will be described.
Memory cell MC is coupled to one of bit lines BL and / BL for each row. For example, the memory cells belonging to the first memory cell row are coupled to bit lines BL1, BL3,..., BL, and the memory cells in the second row are bit lines BL2, BL4,. Combined. Similarly, each of the memory cells is connected to one BL of each bit line pair in the odd-numbered row and is connected to / BL of the other bit line pair in the even-numbered row.

  As a result, when read word line RWL is selectively activated according to the row selection result, one of bit lines BL and / BL is coupled to memory cell MC in each bit line pair.

  Memory array 10 further includes a plurality of dummy memory cells DMC provided corresponding to the memory cell columns. Dummy memory cell DMC is coupled to one of dummy read word lines DRWL1 and DRWL2, and arranged in 2 rows × multiple columns. The dummy memory cells coupled to dummy read word line DRWL1 are coupled to bit lines BL1, BL3,... (That is, one bit line BL in each bit line pair). On the other hand, the remaining dummy memory cells coupled to dummy read word line DRWL2 are coupled to bit lines BL2, BL4,... (That is, the other bit line / BL in each bit line pair).

  Dummy read word lines DRWL1 and DRWL2 are configured such that one of BL and the other / BL of each bit line pair corresponds to a selected memory cell row, and one which is not connected to memory cell MC is connected to dummy memory cell DMC. Each is selectively activated to bind. For example, when an odd-numbered memory cell row is selected according to the row selection result, dummy read word line DRWL2 is connected to bit line / BL and dummy memory cell DMC in each bit line pair. Activated to the selected state. On the contrary, when the even-numbered memory cell row is selected, the dummy read word line DRWL1 is activated to the selected state.

  As a result, bit lines BL and / BL constituting each bit line pair are respectively coupled to one of the memory cells and dummy memory cells DMC corresponding to the selected memory cell row.

  A case where the third memory cell column is selected as an example also at the time of data reading will be described.

  Prior to the data read operation, the bit line precharge signal BLPR is activated to H level for a certain period, and each bit line is precharged to the power supply voltage Vcc.

  After precharging, column selection line CSL2 is activated to a selected state (H level) in response to a column selection result. In response to this, column select gates CSG3 and 4 are turned on. As a result, data lines IO and / IO constituting data I / O line pair DI / OP are coupled to bit lines BL3 and BL4 (/ BL3), respectively, in the same manner as during data writing.

  Data read circuit 50r supplies sense current Is in the same direction to data lines IO and / IO via current switching circuit 53a. At the time of data reading, equalizing transistor 62-2 is turned off, so that sense current Is supplied from data reading circuit 50r flows in the same direction on bit lines BL3 and BL4 (/ BL3).

  Read word line RWL is activated to a selected state (H level) according to the row selection result, and the corresponding memory cell is coupled to one of bit lines BL3 and BL4 (/ BL3). One of dummy read word lines DRWL1 and DRWL2 is activated, and the other of bit lines BL3 and BL4 (/ BL3), which is not connected to the memory cell, is coupled to dummy memory cell DMC.

  As already described, the resistance value of the memory cell MC varies depending on the level of stored data. Here, when the resistance value of the memory cell MC when storing the H level data is Rh and the resistance value of the memory cell MC when storing the L level data is R1, the resistance value Rm of the dummy memory cell DMC is: It is set to an intermediate value between Rl and Rh.

  Therefore, the data read circuit 50r compares the voltage change generated on one of the bit lines coupled to the dummy memory cell with the voltage change generated on the other of the bit line coupled to the memory cell MC by the sense current Is. The level of stored data that is the target of data reading can be detected.

  The voltage difference generated between bit lines BL3 and BL4 (/ BL3) is transmitted to nodes Ns1 and Ns2 in data read circuit 50r through data I / O line pair DI / OP. Amplifier 165 amplifies the voltage difference between nodes Ns1 and Ns2, and outputs read data DOUT.

  Therefore, when L level data is stored in the memory cell coupled to bit line BL3 (BL), and when H level data is stored in memory cell MC coupled to bit line BL4 (/ BL). , L level is output to read data DOUT. Conversely, when the H level data is stored in the memory cell coupled to the bit line BL3 (BL), and the L level data is stored in the memory cell MC coupled to the bit line BL4 (/ BL). In some cases, H level is output to read data DOUT.

  Thus, data reading and data writing can be executed based on the folded bit line configuration. As a result, it is possible to ensure an operation margin for data reading and data writing.

  Further, since the data write current is turned back by the equalizing transistor 62 and flows to the bit lines BL and / BL constituting the bit line pair, data writing can be performed without using a voltage (negative voltage) having a different polarity. Further, the direction of the data write current can be switched only by setting the voltage of data lines IO and / IO to either power supply voltage Vcc or ground voltage Vss. Therefore, the circuit configuration of data write circuit 50w can be simplified. Similarly, the read / write control circuit 60 can be simply formed with only the equalizing transistors 62-1 to 62-m without providing means for sinking current.

  Further, since magnetic field noise generated due to each of the complementary data write currents supplied in a folded manner is generated in a direction in which they cancel each other, data write noise can be reduced.

[Modification 1 of Embodiment 2]
In the first modification of the second embodiment, in addition to the folded bit line configuration shown in the second embodiment, the write word line WWL is shared between adjacent memory cells.

  FIG. 15 is a block diagram showing configurations of memory array 10 and peripheral circuits according to the first modification of the second embodiment.

  Referring to FIG. 15, in memory array 10 according to the first modification of the second embodiment, memory cells adjacent in the column direction share the same write word line WWL.

  At the time of data reading in which read word line RWL is activated, every other memory cell column is connected to each bit line, so that the memory cell column formed by two adjacent memory cell columns A bit line pair is formed for each group, and data reading similar to that in the second embodiment based on the folded bit line configuration can be executed.

  On the other hand, at the time of data writing in which write word line WWL shared between memory cells belonging to different rows is activated, data writing based on the folded bit line configuration cannot be performed. Therefore, it is necessary to perform column selection independently during data reading and data writing.

  In the first modification of the second embodiment, the column selection gate is divided into a read column selection gate RCG and a write column selection gate WCG. Similarly, the column selection line is divided into a read column selection line RCSL and a write column selection line WCSL.

  Read column select line RCSL and read column select gate RCG are arranged similarly to column select line CSL and column select gate CSG in FIG. 13, and are controlled for each set of memory cell columns corresponding to each bit line pair. Therefore, similarly to the configuration according to the second embodiment, an operation margin for data reading can be ensured.

  On the other hand, the write column selection line WCSL and the write column selection gate WCG are arranged corresponding to the memory cell columns, and are independently controlled corresponding to the memory cell columns.

  Write column selection gates WCG1, WCG3,... Provided corresponding to odd-numbered memory cell columns electrically couple corresponding bit lines BL1, BL3,... And data line IO according to the column selection result. Arranged for. On the other hand, write column selection gates WCG2, WCG4,... Provided corresponding to the even-numbered memory cell columns electrically connect corresponding bit lines BL2, BL4,. Arranged to bond to.

  Read / write control circuit 60 includes a write current control transistor arranged corresponding to each memory cell column. The write current control transistor is turned on in response to activation of the corresponding write column selection line. FIG. 11 representatively shows write current control transistors 63-1 to 63-4 provided corresponding to first to fourth memory cell columns, that is, bit lines BL1 to BL4, respectively. In the following, reference numeral 63 is used when referring to these plurality of write current control transistors. On the other hand, the arrangement of the precharge transistors 64 is the same as in the case of FIG.

  The write current control transistors 63-1, 63-3,... Provided corresponding to the odd-numbered memory cell columns correspond to the corresponding bit lines BL1, BL3,. Are arranged for electrical coupling. On the other hand, the write current control transistors 63-2, 63-4,... Provided corresponding to the even-numbered memory cell columns correspond to the corresponding bit lines BL2, BL4,. Are arranged to electrically couple.

  Therefore, in the selected memory cell column, the data write current flows in the path from data line IO (/ IO) to write column select gate WCSG to bit line BL to write current control transistor 63 to data line / IO (IO). ± Iw can flow. Note that the direction of the data write current ± Iw can be controlled by setting the voltages of the data lines IO and / IO as in the second embodiment. Therefore, as in the second embodiment, the configuration of peripheral circuits related to data writing, that is, data write circuit 50w and read / write control circuit 60 can be simplified.

  Further, although data writing based on the folded bit line configuration cannot be executed, the wiring pitch of the write word lines WWL in the memory array 10 can be relaxed. As a result, as in the case of the second modification of the first embodiment, the chip area of the MRAM device is reduced by increasing the integration of the memory array 10 and the reliability of the MRAM device is improved by improving the electromigration resistance of the write word line WWL. Can be planned.

[Modification 2 of Embodiment 2]
In the second modification of the second embodiment, in addition to the folded bit line configuration shown in the second embodiment, the read word line RWL is shared between adjacent memory cells.

  FIG. 16 is a block diagram showing configurations of the memory array 10 and peripheral circuits according to the second modification of the second embodiment.

  Referring to FIG. 16, in memory array 10 according to the second modification of the second embodiment, memory cells adjacent in the column direction share the same read word line RWL.

  Read / write control circuit 60 has equalize transistor 62 and precharge transistor 64 arranged in the same manner as in the second embodiment.

  At the time of data writing in which write word line WWL is activated, every other memory cell column is connected to each bit line, so that a memory cell column formed by two adjacent memory cell columns A bit line pair can be formed for each set. As a result, data writing similar to that in the second embodiment can be executed based on the folded bit line configuration. Therefore, an operation margin for data writing can be ensured as in the second embodiment. In addition, the configuration of peripheral circuits related to data writing, that is, data write circuit 50w and read / write control circuit 60 can be simplified, and noise during data write can be reduced.

  On the other hand, at the time of data reading in which read word line RWL shared between a plurality of memory cell rows is activated, data reading based on the folded bit line configuration cannot be performed. However, at the time of data reading, it is necessary to apply a sense current to one of data lines IO and / IO corresponding to the selected memory cell column. For the other of data lines IO and / IO, Even in the floating state, the data read operation is not adversely affected. Therefore, the arrangement of the column selection lines and the column selection gates can be the same as in the case of FIG.

  That is, at the time of data reading, each of data lines IO and / IO operates as independent data lines IO1 and IO2, and a sense current is supplied to either one according to the column selection result.

  On the other hand, at the time of data writing, data lines IO and / IO form data I / O line pair DI / OP as in the case of FIG. 13 and function as complementary data write current supply lines.

  As in the case of the first modification of the second embodiment shown in FIG. 15, the column selection gate and the column selection line may be arranged independently by read / write. In this case, in the configuration of FIG. 15, the arrangement of the read column selection gate RCG and the write column selection gate WCG and the arrangement of the read column selection line RCSL and the write column selection line WCSL may be switched.

  In the configuration according to the second modification of the second embodiment, a current switching circuit 53b and a data reading circuit 51r are arranged instead of current switching circuit 53a and data reading circuit 50r, respectively.

FIG. 17 is a circuit diagram showing a configuration of data read circuit 51r.
Referring to FIG. 17, data read circuit 51r is different from data read circuit 50r shown in FIG. 14 in that sense current Is is supplied only to node Nr1. Correspondingly, the transistor 164 shown in FIG. 14 is omitted, and the reference voltage Vref is input only to the gate of the transistor 163.

  The data read circuit 51r detects the data level of the read data DOUT by comparing the voltage drop caused by the sense current Is with a reference voltage drop ΔVr. ΔVr is set to be an intermediate value between ΔVh and ΔVl, where ΔVh is the voltage drop of the data line when H level data is read and ΔVl is the voltage drop of the data line when L level data is read. Is done.

  Therefore, in data read circuit 51r, the resistance value of resistor 167 is set so that the voltage level of node Ns2 becomes (Vcc−ΔVr).

  Referring to FIG. 16 again, current switching circuit 53b controls connection between output node Nr1 of data read circuit 50r and data lines IO1 (IO) and IO2 (/ IO) according to control signal RRS. To do. At the time of data reading, output node Nr1 of data reading circuit 50r is connected to one of data lines IO1 (IO) and IO2 (/ IO) according to the column selection result.

  Specifically, when an odd-numbered memory cell column is selected, the current switching circuit 53b supplies the node Nr1 and the data line IO1 (IO) to supply the sense current Is to the data line IO1 (IO). And connect. Data line IO2 (/ IO) is left floating with the precharge voltage maintained.

  On the other hand, when the even-numbered memory cell column is selected, the current switching circuit 53b supplies the sense current Is to the data line IO2 (/ IO), so that the node Nr1 and the data line IO2 (/ IO) And connect. On the other hand, the data line IO1 (IO) is in a floating state with the precharge voltage.

  On the other hand, at the time of data writing in which data write current is supplied to data lines IO and / IO by data write circuit 50w, current switching circuit 53b does not connect output node Nr1 to either data line IO or / IO. .

  With such a configuration, at the time of data reading, the operation margin cannot be ensured by the folded bit line configuration, but the data pitch can be normally read by relaxing the wiring pitch of the read word lines RWL in the memory array 10. Can be executed. Further, data writing based on the folded bit line configuration is executed, and the chip area of the MRAM device can be reduced by the high integration of the memory array 10 as in the case of the third modification of the first embodiment. .

[Embodiment 3]
In the third and subsequent embodiments, signal line sharing in the arrangement of memory cells having other configurations will be described.

  FIG. 18 is a circuit diagram showing a connection relationship between the memory cell and the signal wiring according to the third embodiment.

  Referring to FIG. 18, the memory cell according to the third embodiment includes a magnetic tunnel junction MTJ and an access transistor ATR coupled in series. Access transistor ATR is electrically coupled between magnetic tunnel junction MTJ and bit line BL. Access transistor ATR has its gate coupled to read word line RWL.

  Magnetic tunnel junction MTJ is electrically coupled between reference voltage line SL for supplying ground voltage Vss and access transistor ATR. Therefore, the bit line BL is not directly coupled to the magnetic tunnel junction MTJ but is connected via the access transistor ATR.

  The memory cell according to the third embodiment corresponds to a memory cell in which reference voltage line SL and bit line BL are interchanged as compared with the memory cell according to the first embodiment. Therefore, the types of signal lines to be arranged are the same as those in the first embodiment, and the voltage and current waveforms of each signal line at the time of data reading and data writing are the same as those in the first embodiment. The explanation will not be repeated.

FIG. 19 is a structural diagram illustrating the arrangement of memory cells according to the third embodiment.
Referring to FIG. 19, access transistor ATR is formed in p type region PAR on semiconductor main substrate SUB. Bit line BL is formed in first metal interconnection layer M1, and is electrically coupled to one source / drain region 110 of access transistor ATR.

  The other source / drain region 120 is magnetically connected via the metal wiring provided in the first metal wiring layer M1 and the second metal wiring layer M2, the metal film 150 formed in the contact hole, and the barrier metal 140. Coupled with the tunnel junction MTJ. The write word line WWL is provided in the second metal wiring layer M2 in the vicinity of the magnetic tunnel junction. Read word line RWL is arranged in the same layer as gate 130 of access transistor ATR.

  The reference voltage wiring SL is arranged in the third metal wiring layer M3 which is an independent metal wiring layer. Reference voltage line SL is coupled to a node supplying ground voltage Vss at any node on the semiconductor substrate.

Thus, in the memory cell according to the third embodiment, magnetic tunnel junction MTJ and bit line BL are not directly coupled but are coupled via access transistor ATR. As a result, each bit line BL is not directly coupled to a large number of magnetic tunnel junctions MTJ belonging to the corresponding memory cell column, and the corresponding read word line RWL is selected (H level). Are electrically coupled only to memory cells belonging to the memory cell row activated in the current state. Therefore, the capacity of the bit line BL can be suppressed, and the operation at the time of data reading can be speeded up.

FIG. 20 is a block diagram showing a configuration of memory array 10 according to the third embodiment.

  Referring to FIG. 20, in memory array 10, memory cells MC having the configuration shown in FIG. 18 are arranged in a matrix. Furthermore, similarly to the configuration according to the first embodiment shown in FIG. 5, memory cells adjacent in the row direction share the same reference voltage line SL.

  The arrangement of read word line RWL, write word line WWL, and bit line BL and the configuration of word line current control circuit 40 are the same as those in FIG.

  Thus, also in the arrangement of the memory cells according to the third embodiment, reference voltage line SL can be shared among a plurality of memory cell columns. Thereby, the number of wirings arranged in the entire memory array 10 can be reduced. As a result, the memory array 10 can be highly integrated and the chip area of the MRAM device can be reduced.

[Modification 1 of Embodiment 3]
FIG. 21 is a block diagram showing a configuration of memory array 10 according to the first modification of the third embodiment.

  Referring to FIG. 21, in memory array 10 according to the first modification of the third embodiment, adjacent memory cells in the row direction share the same bit line BL as in the case of FIG. On the other hand, the reference voltage line SL is arranged for each memory cell column.

  Since the structure of other parts and the operation of each memory cell at the time of data reading and data writing are the same as those in the third embodiment, detailed description will not be repeated.

  With such a configuration, the wiring pitch of the bit lines BL in the memory array 10 can be relaxed even when the memory cells according to the third embodiment capable of speeding up data reading are arranged. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

  In the configuration of the memory cell according to the third embodiment, the distance between the bit line BL and the magnetic tunnel junction MTJ is larger than the distance between the write word line WWL and the magnetic tunnel junction MTJ. Therefore, a large data write current needs to flow through the bit line BL. Therefore, considering the electromigration resistance of the bit line BL is effective for improving the reliability of the MRAM device.

  That is, in the arrangement of the memory cells according to the third embodiment, the bit line BL is secured by making the wiring width (cross-sectional area) of the bit line BL larger than the write word line WWL having a small distance from the magnetic tunnel junction. Therefore, the reliability of the MRAM device can be improved. Also, in terms of material, it is desirable to form the bit line BL with a material having high electromigration resistance.

[Modification 2 of Embodiment 3]
FIG. 22 is a block diagram showing a configuration of the memory array 10 according to the second modification of the third embodiment.

  Referring to FIG. 22, in memory array 10 according to the second modification of the third embodiment, memory cells adjacent in the column direction share the same write word line WWL as in the case of FIG. The memory cells MC are arranged alternately for the same reason as in FIG. FIG. 22 shows a configuration in which the reference voltage wiring SL is arranged for each memory cell column. Similar to the configuration of FIG. 20, the reference voltage wiring SL is connected between memory cells adjacent in the row direction. It is good also as a structure shared.

  Since the structure of other parts and the operation of each memory cell at the time of data reading and data writing are the same as those in the third embodiment, detailed description will not be repeated.

  With such a configuration, even in the arrangement of the memory cells according to the third embodiment, the wiring pitch of the write word lines WWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 3 of Embodiment 3]
FIG. 23 is a block diagram showing a configuration of the memory array 10 according to the third modification of the third embodiment.

  Referring to FIG. 23, in memory array 10 according to the third modification of the third embodiment, memory cells adjacent in the column direction share the same read word line RWL as in the case of FIG. The memory cells MC are alternately arranged for the same reason as in FIG. FIG. 23 shows a configuration in which the reference voltage wiring SL is arranged for each memory cell column. However, similarly to the configuration of FIG. 20, the memory cell column formed by two adjacent memory cell columns is shown. The reference voltage wiring SL may be shared for each set.

  Since the structure of other parts and the operation of each memory cell at the time of data reading and data writing are the same as those in the third embodiment, detailed description will not be repeated.

  With such a configuration, the wiring pitch of the read word lines RWL in the memory array 10 can be relaxed even in the arrangement of the memory cells according to the third embodiment. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 4 of Embodiment 3]
FIG. 24 is a block diagram showing a configuration of the memory array 10 according to the fourth modification of the third embodiment.

  Referring to FIG. 24, in memory array 10 according to the fourth modification of the third embodiment, memory cells adjacent in the column direction have the same write word line WWL as in the second modification of the third embodiment. Share. Further, the read word line RWL is also shared between memory cells adjacent in the column direction. For example, memory cell groups belonging to the second and third memory cell rows share the same read word line RWL2. For the subsequent memory cell rows, read word line RWL and write word line WWL are similarly arranged.

  The memory cells MC are arranged alternately for the same reason as in FIG. FIG. 24 shows a configuration in which the reference voltage wiring SL is arranged for each memory cell column. However, similarly to the configuration of FIG. 20, one reference voltage is provided by memory cells adjacent in the column direction. The wiring SL may be shared.

  Since the structure of other parts and the operation of each memory cell at the time of data reading and data writing are the same as those in the third embodiment, detailed description will not be repeated.

  With such a configuration, even in the arrangement of the memory cells according to the third embodiment, the wiring pitch of both the write word line WWL and the read word line RWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be arranged more efficiently, and the memory array 10 can be more highly integrated and the chip area of the MRAM device can be reduced than in the second and third modifications of the third embodiment. it can.

[Modification 5 of Embodiment 3]
FIG. 25 is a block diagram showing configurations of memory array 10 and peripheral circuits according to the fifth modification of the third embodiment.

  Referring to FIG. 25, the configuration of memory array 10 and the peripheral circuit according to the fifth modification of the third embodiment is similar to the configuration according to the fifth modification of the first embodiment shown in FIG.

  In the memory cell according to the third embodiment, at the time of data reading, common line SBL coupled to access transistor ATR is caused to function as bit line BL, and common line SBL coupled to magnetic tunnel junction MTJ is used as reference voltage line SL. It is necessary to function as. This is opposite to the setting of the function of the common wiring SBL in the fifth modification of the first embodiment.

  That is, it is necessary to switch on / off of the common wiring control transistor CCT corresponding to the row selection result as compared with the case of the fifth modification of the first embodiment. Therefore, in Modification 5 of Embodiment 3, control signal / RA1 is input to the gates of common wiring control transistors CCT1, CCT3,... Provided corresponding to odd-numbered memory cell columns. A control signal RA1 is input to the gates of the common wiring control transistors CCT2, CCT4,... Provided corresponding to the even-numbered memory cell columns. Settings of control signals RA1 and / RA1 are the same as in Modification 5 of Embodiment 1.

  Except for the control of the common wiring control transistor CCT, it is the same as that of the fifth modification of the first embodiment, and thus detailed description will not be repeated.

  By adopting such a configuration, even in the arrangement of the memory cells according to the third embodiment, data reading similar to that in the first embodiment is performed using the common wiring SBL in which the functions of the reference voltage wiring SL and the bit line BL are integrated. Data writing can be performed.

  As a result, the memory array 10 can be highly integrated by relaxing the wiring pitch in the column direction and efficiently arranging the memory cells MC. Further, it is possible to secure the wiring width, that is, the cross-sectional area of the common wiring SBL through which a large data writing current flows during data writing, improve the electromigration resistance of the common wiring SBL, and improve the reliability of the MRAM device. it can.

  In FIG. 25, memory cells adjacent in the column direction share one write word line WWL as in the second modification of the third embodiment.

  Therefore, the wiring pitch of the write word line WWL in the memory array 10 can be relaxed. As a result, the memory array 10 can be further highly integrated and the chip area of the MRAM device can be reduced.

  In addition, the integration of the reference voltage wiring SL and the bit line BL by the common wiring SBL shown in this modification example is the read operation between adjacent memory cell rows described in the modification examples 3 and 4 of the third embodiment, respectively. It is also possible to apply in combination with sharing of the word line RWL and sharing of both the read word line RWL and the write word line WWL between adjacent memory cell rows.

[Modification 6 of Embodiment 3]
FIG. 26 is a block diagram showing configurations of the memory array 10 and peripheral circuits according to the sixth modification of the third embodiment.

  Referring to FIG. 26, for each memory cell according to the third embodiment arranged in a matrix, each set of memory cell columns formed by two adjacent memory cell columns as in the second embodiment. In addition, a folded bit line configuration is realized using two corresponding bit lines.

  26 differs from the configuration of FIG. 13 in that in each memory cell MC, an access transistor ATR and a bit line are connected, and a magnetic tunnel junction MTJ and a reference voltage line SL are connected.

  Since the configuration of the other parts and the operation at the time of data reading and data writing are the same as those in FIG. 13, detailed description will not be repeated.

  Therefore, even in the arrangement of the memory cells according to the third embodiment, it is possible to secure an operation margin for data reading and data writing using the folded bit line configuration. Further, as in the second embodiment, it is possible to simplify the peripheral circuit and reduce data write noise.

[Modification 7 of Embodiment 3]
In the seventh modification of the third embodiment, in addition to the folded bit line configuration shown in the sixth modification of the third embodiment, the write word line WWL is shared between adjacent memory cell rows.

  FIG. 27 is a block diagram showing configurations of the memory array 10 and peripheral circuits according to the seventh modification of the third embodiment.

  27 differs from the configuration of FIG. 15 in that in each memory cell MC, the access transistor ATR and the bit line are connected, and the magnetic tunnel junction MTJ and the reference voltage line SL are connected.

  Since the structure of the other parts and the operation at the time of data reading and data writing are the same as those in FIG. 15, detailed description will not be repeated.

  Therefore, in the memory cell arrangement according to the third embodiment, it is possible to achieve both an operation margin secured by data reading based on the folded bit line configuration and high integration of the memory array 10 based on sharing the write word line. can do.

[Modification 8 of Embodiment 3]
In modification 8 of the third embodiment, in addition to the folded bit line configuration shown in modification 6 of the third embodiment, read word line RWL is shared between adjacent memory cell rows.

  FIG. 28 is a block diagram showing configurations of the memory array 10 and peripheral circuits according to the eighth modification of the third embodiment.

  28 is different from the configuration of FIG. 16 in that in each memory cell MC, the access transistor ATR and the bit line are connected, and the magnetic tunnel junction MTJ and the reference voltage line SL are connected.

  Since the configuration of the other parts and the operation at the time of data reading and data writing are the same as those of FIG. 16, detailed description will not be repeated.

  Therefore, even in the memory cell arrangement according to the third embodiment, the operation margin is secured, the peripheral circuit is simplified and the data write noise is reduced, and the read word line is shared by data writing based on the folded bit line configuration. The high integration of the memory array 10 based on the above can be realized at the same time.

[Embodiment 4]
FIG. 29 is a circuit diagram showing a connection relationship between a memory cell and a signal line according to the fourth embodiment.

  Referring to FIG. 29, for the memory cell according to the fourth embodiment, read word line RWL, write word line WWL, bit line BL and reference voltage line SL are provided for the memory cell.

  Access transistor ATR is electrically coupled between magnetic tunnel junction MTJ and reference voltage line SL supplying ground voltage Vss. Access transistor ATR has its gate coupled to read word line RWL. Magnetic tunnel junction MTJ is coupled to bit line BL.

  Read word line RWL is arranged along the row direction of the memory cells. The write word line WWL is provided in parallel with the read word line RWL and in proximity to the magnetic tunnel junction MTJ. Reference voltage line SL is arranged in parallel with write word line WWL and read word line RWL.

  Compared with the memory cell according to the first embodiment, the memory cell according to the fourth embodiment is only in that reference voltage line SL is arranged along the row direction, that is, parallel to read word line RWL and write word line WWL. Different. Therefore, the types of signal lines to be arranged are the same as those in the first embodiment, and the voltage and current waveforms of each signal line at the time of data reading and data writing are the same as those in the first embodiment. The explanation will not be repeated.

FIG. 30 is a structural diagram illustrating an arrangement of memory cells according to the fourth embodiment.
Referring to FIG. 30, access transistor ATR is formed in p type region PAR on semiconductor main substrate SUB. Reference voltage line SL is formed in first metal wiring layer M1, and is electrically coupled to one source / drain region 110 of access transistor ATR. Reference voltage line SL is coupled to a node supplying ground voltage Vss at any node on the semiconductor substrate.

  The other source / drain region 120 is magnetically connected via the metal wiring provided in the first metal wiring layer M1 and the second metal wiring layer M2, the metal film 150 formed in the contact hole, and the barrier metal 140. Coupled with the tunnel junction MTJ. The write word line WWL is provided in the second metal wiring layer M2 in the vicinity of the magnetic tunnel junction. Read word line RWL is arranged in the same layer as gate 130 of access transistor ATR.

  Bit line BL is arranged in third metal wiring layer M3, which is an independent metal wiring layer, and is electrically coupled to magnetic tunnel junction MTJ.

FIG. 31 is a block diagram showing a configuration of memory array 10 according to the fourth embodiment.
Referring to FIG. 31, in memory array 10, memory cells MC having the configuration shown in FIG. 29 are arranged in a matrix. Memory cells adjacent in the column direction share the same reference voltage line SL. For example, the memory cell groups belonging to the first and second memory cell rows share one reference voltage line SL1. Reference voltage lines SL are similarly arranged for the other memory cell columns. Since the reference voltage wiring SL basically supplies a constant voltage (in this embodiment, the ground voltage Vss), it can be shared in this way without performing special voltage control or the like.

  The arrangement of read word line RWL, write word line WWL, and bit line BL and the configuration of word line current control circuit 40 are the same as those in FIG.

  Thus, also in the memory cell arrangement according to the fourth embodiment in which reference voltage line SL is arranged along the row direction, reference voltage line SL can be shared between adjacent memory cells. Thereby, the number of wirings arranged in the entire memory array 10 can be reduced, the memory array 10 can be highly integrated, and the chip area of the MRAM device can be reduced.

[Modification 1 of Embodiment 4]
FIG. 32 is a block diagram showing a configuration of the memory array 10 according to the first modification of the fourth embodiment.

  Referring to FIG. 32, in memory array 10 according to the first modification of the fourth embodiment, memory cells adjacent in the row direction share the same bit line BL. For example, the memory cell groups belonging to the first and second memory cell columns share the same bit line BL1. On the other hand, the reference voltage line SL is arranged for each memory cell column.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the fourth embodiment, detailed description will not be repeated.

  With such a configuration, even when the memory cells according to the fourth embodiment are arranged, the wiring pitch of the bit lines BL in the memory array 10 can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 2 of Embodiment 4]
FIG. 33 is a block diagram showing a configuration of the memory array 10 according to the second modification of the fourth embodiment.

  Referring to FIG. 33, in memory array 10 according to the second modification of the fourth embodiment, both reference voltage line SL and bit line BL are shared. Similarly to FIG. 31, the reference voltage line SL is shared by memory cells adjacent in the column direction, and the bit line BL is shared by memory cells adjacent in the row direction as in FIG.

  By adopting such a configuration, it is possible to reduce both the wirings arranged along the row direction and the column direction, thereby further integrating the memory array 10 and reducing the chip area of the MRAM device.

[Modification 3 of Embodiment 4]
FIG. 34 is a block diagram showing a configuration of the memory array 10 according to the third modification of the fourth embodiment.

  Referring to FIG. 34, in memory array 10 according to the third modification of the fourth embodiment, in addition to the configuration of FIG. 31 in which reference voltage line SL is shared, the same write is performed by memory cells adjacent in the column direction. The word line WWL is further shared. The memory cells MC are arranged alternately for the same reason as in FIG.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the fourth embodiment, detailed description will not be repeated.

  With such a configuration, the wiring pitch of the write word lines WWL in the memory array 10 can be relaxed even in the memory cell arrangement according to the fourth embodiment. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

  In the configuration of the memory cell according to the fourth embodiment, since the distance between write word line WWL and magnetic tunnel junction MTJ is larger, the write word is the same as in the case of the memory cell according to the first embodiment. A large data write current needs to flow through the line WWL.

  Therefore, if the current density of the write word line WWL is reduced by securing the cross-sectional area by relaxing the wiring pitch of the write word line WWL, the electromigration resistance can be improved and the reliability of the MRAM device can be improved. In terms of material, it is desirable to form the write word line WWL with a material having higher electromigration resistance than the bit line BL.

[Modification 4 of Embodiment 4]
FIG. 35 is a block diagram showing a configuration of memory array 10 according to the fourth modification of the fourth embodiment.

  Referring to FIG. 35, in memory array 10 according to the fourth modification of the fourth embodiment, in addition to the configuration of FIG. 33 in which reference voltage line SL and bit line BL are shared, memory cells adjacent in the column direction are used. , The same read word line RWL is shared. For example, the same read word line RWL1 is shared by the memory cell groups belonging to the first and second memory cell rows. The memory cells MC are alternately arranged for the same reason as in FIG.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the fourth embodiment, detailed description will not be repeated.

  By adopting such a configuration, the wiring pitch of the read word lines RWL in the memory array 10 can be relaxed even in the memory cell arrangement according to the fourth embodiment. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 5 of Embodiment 4]
FIG. 36 is a block diagram showing a configuration of the memory array 10 according to the fifth modification of the fourth embodiment.

  Referring to FIG. 36, in memory array 10 according to the fifth modification of the fourth embodiment, similarly to the third modification of the fourth embodiment, memory cells adjacent in the column direction have the same write word line WWL and The reference voltage wiring SL is shared.

  In Modification 5 of Embodiment 4, read word line RWL is further shared between memory cells adjacent in the column direction. For example, memory cell groups belonging to the second and third memory cell rows share the same read word line RWL2. The write word line WWL and the read word line RWL are similarly arranged for the subsequent memory cell rows.

  The memory cells MC are arranged alternately for the same reason as in FIG. The reference voltage line SL is shared by memory cells adjacent in the column direction, like the write word line WWL.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the fourth embodiment, detailed description will not be repeated.

  With such a configuration, even in the memory cell arrangement according to the fourth embodiment, the wiring pitch of both the write word line WWL and the read word line RWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be arranged more efficiently, the memory array 10 can be further highly integrated, and the chip area of the MRAM device can be reduced as compared with the third and fourth modifications of the fourth embodiment. it can.

[Modification 6 of Embodiment 4]
FIG. 37 is a block diagram showing structures of the memory array 10 and peripheral circuits according to the sixth modification of the fourth embodiment.

  Referring to FIG. 37, for the memory cells according to the fourth embodiment arranged in a matrix, each set of memory cell columns formed by two adjacent memory cell columns as in the second embodiment. In addition, a folded bit line configuration is realized using two corresponding bit lines.

  37 is different from the configuration of FIG. 13 in that the reference voltage wiring SL is arranged in the row direction.

  Since the configuration of the other parts and the operation at the time of data reading and data writing are the same as those in FIG. 13, detailed description will not be repeated.

  Therefore, also in the arrangement of the memory cells according to the fourth embodiment, it is possible to secure operation margins for data reading and data writing using the folded bit line configuration. Similarly to the second embodiment, the configuration of peripheral circuits of data write circuit 50w and read / write control circuit 60 can be simplified and data write noise can be reduced.

[Variation 7 of Embodiment 4]
In Modification 7 of Embodiment 4, in addition to the folded bit line configuration shown in Modification 6 of Embodiment 4, sharing of write word line WWL between adjacent memory cell rows is achieved.

  FIG. 38 is a block diagram showing configurations of the memory array 10 and peripheral circuits according to the seventh modification of the fourth embodiment.

  38 differs from the configuration of FIG. 15 in that the reference voltage line SL is arranged in the row direction.

  Since the structure of the other parts and the operation at the time of data reading and data writing are the same as those in FIG. 15, detailed description will not be repeated.

  Therefore, also in the memory cell arrangement according to the fourth embodiment, it is possible to achieve both an operation margin secured by data reading based on the folded bit line configuration and a high integration of memory array 10 based on sharing the write word line. can do.

[Modification 8 of Embodiment 4]
In modification 8 of the fourth embodiment, in addition to the folded bit line configuration shown in modification 6 of the fourth embodiment, read word line RWL is shared between adjacent memory cell rows.

  FIG. 39 is a block diagram showing configurations of the memory array 10 and peripheral circuits according to the eighth modification of the fourth embodiment.

  39 differs from the configuration of FIG. 16 in that the reference voltage line SL is arranged in the row direction in each memory cell MC.

  Since the configuration of the other parts and the operation at the time of data reading and data writing are the same as those of FIG. 16, detailed description will not be repeated.

  Therefore, even in the memory cell arrangement according to the fourth embodiment, the operation margin is secured, the peripheral circuit is simplified and the data write noise is reduced, and the read word line is shared by data writing based on the folded bit line configuration. The high integration of the memory array 10 based on the above can be realized at the same time.

[Embodiment 5]
FIG. 40 is a circuit diagram showing a connection relationship between memory cells and signal lines according to the fifth embodiment.

  Referring to FIG. 40, the memory cell according to the fifth embodiment includes a magnetic tunnel junction MTJ and an access transistor ATR coupled in series. Access transistor ATR is electrically coupled between magnetic tunnel junction MTJ and bit line BL. Access transistor ATR has its gate coupled to read word line RWL. The reference voltage line SL is arranged along the row direction as in the fourth embodiment.

  Magnetic tunnel junction MTJ is electrically coupled between reference voltage line SL for supplying ground voltage Vss and access transistor ATR. Therefore, the bit line BL is not directly coupled to the magnetic tunnel junction MTJ but is connected via the access transistor ATR.

  The memory cell according to the fifth embodiment is different from the memory cell according to the fourth embodiment in that the reference voltage wiring SL and the bit line BL, the magnetic tunnel junction MTJ, and the access transistor ATR are connected to each other. Equivalent to. Therefore, the types of signal lines to be arranged are the same as those in the first embodiment, and the voltage and current waveforms of each signal line at the time of data reading and data writing are the same as those in the first embodiment. The explanation will not be repeated.

FIG. 41 is a structural diagram illustrating the arrangement of memory cells according to the fifth embodiment.
Referring to FIG. 41, access transistor ATR is formed in p type region PAR on semiconductor main substrate SUB. Bit line BL is formed in first metal interconnection layer M1, and is electrically coupled to one source / drain region 110 of access transistor ATR.

  The other source / drain region 120 is magnetically connected via the metal wiring provided in the first metal wiring layer M1 and the second metal wiring layer M2, the metal film 150 formed in the contact hole, and the barrier metal 140. Coupled with the tunnel junction MTJ. The write word line WWL is provided in the second metal wiring layer M2 in the vicinity of the magnetic tunnel junction. Read word line RWL is arranged in the same layer as gate 130 of access transistor ATR.

  The reference wiring SL is arranged in the third metal wiring layer M3 that is an independent metal wiring layer. Reference wiring SL is coupled to a node supplying ground voltage Vss at any node on the semiconductor substrate.

  Thus, in the memory cell according to the fifth embodiment, magnetic tunnel junction MTJ and bit line BL are not directly coupled but are coupled via access transistor ATR. As a result, each bit line BL is not directly coupled to a large number of magnetic tunnel junctions MTJ belonging to the corresponding memory cell column, and the corresponding read word line RWL is selected (H level). Are electrically coupled only to memory cells belonging to the memory cell row activated in the current state. Therefore, the capacity of the bit line BL can be suppressed, and the operation at the time of data reading can be speeded up.

FIG. 42 is a block diagram showing a configuration of memory array 10 according to the fifth embodiment.
Referring to FIG. 42, in memory array 10, memory cells MC having the configuration shown in FIG. 40 are arranged in a matrix. Further, similarly to the configuration according to the fourth embodiment shown in FIG. 31, memory cells adjacent in the column direction share the same reference voltage line SL.

  The arrangement of read word line RWL, write word line WWL, and bit line BL and the configuration of word line current control circuit 40 are the same as those in FIG. 31 and will not be described repeatedly.

  Thus, also in the arrangement of the memory cells according to the fifth embodiment, reference voltage line SL can be shared between memory cells adjacent in the column direction. Thereby, the number of wirings arranged in the entire memory array 10 can be reduced. As a result, the memory array 10 can be highly integrated and the chip area of the MRAM device can be reduced.

[Modification 1 of Embodiment 5]
FIG. 43 is a block diagram showing a configuration of the memory array 10 according to the first modification of the fifth embodiment.

  Referring to FIG. 43, in memory array 10 according to the first modification of the fifth embodiment, memory cells adjacent in the row direction share the same bit line BL as in FIG. On the other hand, the reference voltage line SL is arranged for each memory cell column.

  Since the structure of other parts and the operation of each memory cell at the time of data reading and data writing are the same as those in the fifth embodiment, detailed description will not be repeated.

  With such a configuration, the wiring pitch of the bit lines BL in the memory array 10 can be relaxed even when the memory cells according to the fifth embodiment capable of speeding up data reading are arranged. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

  In the configuration of the memory cell according to the fifth embodiment, as in the third embodiment, the distance between the bit line BL and the magnetic tunnel junction MTJ is such that the write word line WWL and the magnetic tunnel junction MTJ. Therefore, a large data write current needs to flow through the bit line BL. Therefore, considering the electromigration resistance of the bit line BL is effective for improving the reliability of the MRAM device.

  That is, in the arrangement of the memory cells according to the fifth embodiment, the bit line BL is secured by making the wiring width (cross-sectional area) of the bit line BL larger than the write word line WWL having a small distance from the magnetic tunnel junction. Therefore, the reliability of the MRAM device can be improved. Also, in terms of material, it is desirable to form the bit line BL with a material having high electromigration resistance.

[Modification 2 of Embodiment 5]
FIG. 44 is a block diagram showing a configuration of the memory array 10 according to the second modification of the fifth embodiment.

  Referring to FIG. 44, in memory array 10 according to the second modification of the fifth embodiment, both reference voltage line SL and bit line BL are shared as in the case of FIG. Similarly to FIG. 42, the reference voltage line SL is shared by memory cells adjacent in the column direction, and the bit line BL is shared by memory cells adjacent in the row direction as in FIG.

  Since the structure of other parts and the operation of each memory cell at the time of data reading and data writing are the same as those in the fifth embodiment, detailed description will not be repeated.

  By adopting such a configuration, it is possible to reduce both the wirings arranged along the row direction and the column direction, thereby further integrating the memory array 10 and reducing the chip area of the MRAM device.

[Modification 3 of Embodiment 5]
FIG. 45 is a block diagram showing a configuration of memory array 10 according to the third modification of the fifth embodiment.

  Referring to FIG. 45, in memory array 10 according to the third modification of the fifth embodiment, in addition to the configuration of FIG. 42 in which reference voltage line SL is shared, the same write is performed by memory cells adjacent in the column direction. The word line WWL is further shared. The memory cells MC are arranged alternately for the same reason as in FIG.

  Since the structure of other parts and the operation of each memory cell at the time of data reading and data writing are the same as those in the fifth embodiment, detailed description will not be repeated.

  With such a configuration, even in the memory cell arrangement according to the fifth embodiment, the wiring pitch of the write word lines WWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 4 of Embodiment 5]
FIG. 46 is a block diagram showing a configuration of memory array 10 according to the fourth modification of the fifth embodiment.

  Referring to FIG. 46, in memory array 10 according to the fourth modification of the fifth embodiment, the memory cells adjacent in the column direction share the same read word line RWL. The memory cells MC are alternately arranged for the same reason as in FIG.

  Since the structure of other parts and the operation of each memory cell at the time of data reading and data writing are the same as those in the fifth embodiment, detailed description will not be repeated.

  With such a configuration, even in the arrangement of the memory cells according to the fifth embodiment, the wiring pitch of the read word lines RWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 5 of Embodiment 5]
FIG. 47 is a block diagram showing a configuration of memory array 10 according to the fifth modification of the fifth embodiment.

  Referring to FIG. 47, in memory array 10 according to the fifth modification of the fifth embodiment, memory cells adjacent in the column direction have the same write word line WWL as in the third modification of the fifth embodiment. Share. Further, the read word line RWL is also shared between memory cells adjacent in the column direction. For example, memory cell groups belonging to the second and third memory cell rows share the same read word line RWL2. For the subsequent memory cell rows, read word line RWL and write word line WWL are similarly arranged. The memory cells MC are arranged alternately for the same reason as in FIG. The reference voltage line SL is shared by memory cells adjacent in the column direction, like the write word line WWL.

  Since the structure of other parts and the operation of each memory cell at the time of data reading and data writing are the same as those in the fifth embodiment, detailed description will not be repeated.

  With such a configuration, even in the memory cell arrangement according to the fifth embodiment, the wiring pitch of both the write word line WWL and the read word line RWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be arranged more efficiently, and the memory array 10 can be further highly integrated and the chip area of the MRAM device can be reduced as compared with the third and fourth modifications of the fifth embodiment. it can.

[Modification 6 of Embodiment 5]
FIG. 48 is a block diagram showing structures of the memory array 10 and peripheral circuits according to the sixth modification of the fifth embodiment.

  Referring to FIG. 48, for each memory cell according to the fifth embodiment arranged in a matrix, each set of memory cell columns formed by two adjacent memory cell columns as in the second embodiment. In addition, a folded bit line configuration is realized using two corresponding bit lines.

  In FIG. 48, the access transistor ATR and the magnetic tunnel junction MTJ are connected to the bit line BL and the reference voltage line SL in each memory cell MC, and the reference voltage line SL is arranged in the row direction. , Different from the configuration of FIG.

  Since the configuration of the other parts and the operation at the time of data reading and data writing are the same as those in FIG. 13, detailed description will not be repeated.

  Therefore, also in the arrangement of the memory cells according to the fifth embodiment, it is possible to secure an operation margin for data reading and data writing using the folded bit line configuration. Similarly to the second embodiment, the configuration of the peripheral circuits of data write circuit 50w and read / write control circuit 60 can be simplified and data write noise can be reduced.

[Modification 7 of Embodiment 5]
In the seventh modification of the fifth embodiment, in addition to the folded bit line configuration shown in the sixth modification of the fifth embodiment, the write word line WWL is shared between adjacent memory cell rows.

  FIG. 49 is a block diagram showing structures of the memory array 10 and peripheral circuits according to the seventh modification of the fifth embodiment.

  In FIG. 49, the access transistor ATR and the magnetic tunnel junction MTJ are connected to the bit line BL and the reference voltage line SL, respectively, and the reference voltage line SL is arranged in the row direction in each memory cell MC. 15 is different from the configuration of FIG.

  Since the structure of the other parts and the operation at the time of data reading and data writing are the same as those in FIG. 15, detailed description will not be repeated.

  Therefore, even in the memory cell arrangement according to the fifth embodiment, it is possible to achieve both the operation margin ensuring by data reading based on the folded bit line configuration and the high integration of the memory array 10 based on sharing the write word line. can do.

[Modification 8 of Embodiment 5]
In modification 8 of the fifth embodiment, in addition to the folded bit line configuration shown in modification 6 of the fifth embodiment, read word line RWL is shared between adjacent memory cell rows.

  FIG. 50 is a block diagram showing structures of the memory array 10 and peripheral circuits according to the eighth modification of the fifth embodiment.

  50, in each memory cell MC, the access transistor ATR and the magnetic tunnel junction MTJ are connected to the bit line BL and the reference voltage line SL, respectively, and the reference voltage line SL is arranged in the row direction. This is different from the configuration of FIG.

  Since the configuration of the other parts and the operation at the time of data reading and data writing are the same as those of FIG. 16, detailed description will not be repeated.

  Therefore, even in the memory cell arrangement according to the fifth embodiment, the operation margin is secured, the peripheral circuit is simplified and the data write noise is reduced, and the read word line is shared by data writing based on the folded bit line configuration. The high integration of the memory array 10 based on the above can be realized at the same time.

[Embodiment 6]
FIG. 51 is a circuit diagram showing a connection relationship between MTJ memory cells and signal lines according to the sixth embodiment.

  Referring to FIG. 51, access transistor ATR is electrically coupled between magnetic tunnel junction MTJ and write word line WWL. Magnetic tunnel junction MTJ is coupled between access transistor ATR and bit line BL. Access transistor ATR has its gate coupled to read word line RWL.

  Write word line WWL is set to ground voltage Vss at the time of data reading. As a result, when read word line RWL is activated to a selected state (H level) during data reading, access transistor ATR is turned on, and bit line BL to magnetic tunnel junction MTJ to access transistor ATR to write word line. A sense current Is can flow through the path of WWL.

  On the other hand, at the time of data writing, the access transistor ATR is turned off and the data write current is supplied to the bit line BL and the write word line WWL to correspond to the level of the stored data written to the magnetic tunnel junction MTJ. A magnetic field can be generated.

FIG. 52 is a structural diagram illustrating the arrangement of MTJ memory cells according to the sixth embodiment.
Referring to FIG. 52, write word line WWL and bit line BL are arranged in first metal interconnection layer M1 and second metal interconnection layer M2, respectively. Read word line RWL is arranged in the same layer as gate 130 of access transistor ATR.

  By setting write word line WWL to ground voltage Vss at the time of data reading, MTJ memory cells can be arranged by two metal wiring layers M1 and M2 without providing reference wiring SL. As a result, the number of metal wiring layers can be reduced and manufacturing costs can be reduced.

  Next, data reading and data writing operations for the MTJ memory cell according to the sixth embodiment will be described.

  Referring again to FIG. 3, at the time of data reading, write word line WWL is maintained in a non-selected state (L level). Since each write word line WWL is coupled to the ground voltage Vss by the word line current control circuit 40, the voltage of the write word line WWL at the time of data reading is the same ground voltage Vss as the voltage level of the reference voltage line SL. . On the other hand, since no current flows through the reference voltage line SL during data writing, no magnetic field is generated for the MTJ memory cell.

  Therefore, even if reference voltage line SL is omitted, the voltages and currents of write word line WWL, read word line RWL and bit line BL are set in the same manner as in FIG. 3, and the MTJ memory cell according to the sixth embodiment is set. Thus, data reading and data writing operations can be executed.

FIG. 53 is a block diagram showing a configuration of memory array 10 according to the sixth embodiment.
Referring to FIG. 53, in memory array 10 according to the sixth embodiment, memory cells adjacent in the row direction share the same bit line BL. For example, the memory cell groups belonging to the first and second memory cell columns share the same bit line BL1. Since the configuration of read word line RWL, write word line WWL, and word line current control circuit 40 and the operation of each memory cell during data reading and data writing are the same as those in FIG. 5, description thereof will not be repeated.

  With such a configuration, even when the memory cell according to the sixth embodiment capable of reading and writing data with a smaller number of wires is arranged, the wiring pitch of bit lines BL in memory array 10 Can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 1 of Embodiment 6]
FIG. 54 is a block diagram showing a configuration of the memory array 10 according to the first modification of the sixth embodiment.

  Referring to FIG. 54, in memory array 10 according to the first modification of the sixth embodiment, memory cells adjacent in the column direction share the same write word line WWL. Therefore, the memory cells MC are alternately arranged for the same reason as in FIG.

  Since the structure of the other portions and the operation of each memory cell at the time of data reading and data writing are the same as in the sixth embodiment, detailed description will not be repeated.

  With such a configuration, the wiring pitch of the write word lines WWL in the memory array 10 can be relaxed even in the arrangement of the memory cells according to the sixth embodiment. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

  In the configuration of the memory cell according to the sixth embodiment, as in the first embodiment, the distance between the write word line WWL and the magnetic tunnel junction MTJ is equal to the bit line BL and the magnetic tunnel junction MTJ. Therefore, a large data write current needs to flow through the write word line WWL. Therefore, considering the electromigration resistance of the write word line WWL is effective for improving the reliability of the MRAM device.

  That is, also in the arrangement of the memory cells according to the sixth embodiment, the write word line WWL is secured by making the wiring width (cross-sectional area) of the write word line WWL larger than the bit line BL having a small distance from the magnetic tunnel junction. The reliability of the MRAM device can be improved by increasing the electromigration resistance of the WWL. In terms of material, it is desirable to form the write word line WWL with a material having high electromigration resistance.

[Modification 2 of Embodiment 6]
FIG. 55 is a block diagram showing a configuration of the memory array 10 according to the second modification of the sixth embodiment.

  Referring to FIG. 55, in memory array 10 according to the second modification of the sixth embodiment, memory cells adjacent in the column direction share the same read word line RWL. Therefore, the memory cells MC are alternately arranged for the same reason as in FIG. Since the structure of the other portions and the operation of each memory cell at the time of data reading and data writing are the same as in the sixth embodiment, detailed description will not be repeated.

  With such a configuration, even in the arrangement of the memory cells according to the sixth embodiment, the wiring pitch of the read word lines RWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 3 of Embodiment 6]
FIG. 56 is a block diagram showing a configuration of memory array 10 according to the third modification of the sixth embodiment.

  Referring to FIG. 56, in memory array 10 according to the third modification of the sixth embodiment, similarly to the first modification of the sixth embodiment, memory cells adjacent in the column direction have the same write word line WWL. Share. Further, the read word line RWL is also shared between memory cells adjacent in the column direction. For example, memory cell groups belonging to the second and third memory cell rows share the same read word line RWL2. For the subsequent memory cell rows, read word line RWL and write word line WWL are similarly arranged.

  Therefore, the memory cells MC are alternately arranged for the same reason as in FIG. Since the structure of the other portions and the operation of each memory cell at the time of data reading and data writing are the same as in the sixth embodiment, detailed description will not be repeated.

  With such a configuration, even in the memory cell arrangement according to the sixth embodiment, the wiring pitch of both the write word line WWL and the read word line RWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be arranged more efficiently, and the memory array 10 can be further highly integrated and the chip area of the MRAM device can be reduced as compared with the first and second modifications of the sixth embodiment. it can.

[Modification 4 of Embodiment 6]
FIG. 57 is a block diagram showing structures of memory array 10 and peripheral circuits according to the fourth modification of the sixth embodiment.

  Referring to FIG. 57, for each memory cell according to the sixth embodiment arranged in a matrix, each set of memory cell columns formed by two adjacent memory cell columns as in the second embodiment. In addition, a folded bit line configuration is realized using two corresponding bit lines.

  57, the arrangement of the reference voltage wiring SL is omitted and the connection relationship between the signal wiring of the read word line RWL, the write word line WWL, and the bit line BL and the memory cell MC is the configuration of FIG. And different. Since the configuration of the peripheral circuit for supplying the data write current and sense current to bit line BL and the operation at the time of data reading and data writing are the same as those in FIG. 13, detailed description will not be repeated. .

  Therefore, also in the arrangement of the memory cells according to the sixth embodiment, it is possible to secure an operation margin for data reading and data writing using the folded bit line configuration. Similarly to the second embodiment, the circuit configuration of the peripheral circuits of data write circuit 50w and read / write control circuit 60 can be simplified and data write noise can be reduced.

[Modification 5 of Embodiment 6]
In Modification 5 of Embodiment 6, in addition to the folded bit line configuration shown in Modification 4 of Embodiment 6, sharing of write word line WWL between adjacent memory cell rows is achieved.

  FIG. 58 is a block diagram showing configurations of memory array 10 and peripheral circuits according to the fifth modification of the sixth embodiment.

  58, the arrangement of the reference voltage wiring SL is omitted, and the connection relationship between the signal wiring of the read word line RWL, the write word line WWL, and the bit line BL and the memory cell MC is the configuration of FIG. And different. Since the configuration of the peripheral circuit for supplying the data write current and sense current to bit line BL and the operation at the time of data reading and data writing are the same as those in FIG. 15, detailed description will not be repeated. .

  Therefore, also in the memory cell arrangement according to the sixth embodiment, it is possible to achieve both the operation margin ensuring by data reading based on the folded bit line configuration and the high integration of the memory array 10 based on sharing the write word line. can do.

[Modification 6 of Embodiment 6]
In the sixth modification of the sixth embodiment, in addition to the folded bit line configuration shown in the fourth modification of the sixth embodiment, the read word line RWL is shared between adjacent memory cell rows.

  FIG. 59 is a block diagram showing structures of memory array 10 and peripheral circuits according to the sixth modification of the sixth embodiment.

  In FIG. 59, the arrangement of the reference voltage wiring SL is omitted, and the connection relationship between the signal wiring of the read word line RWL, the write word line WWL, and the bit line BL and the memory cell MC is shown in FIG. And different. Since the configuration of the peripheral circuit for supplying the data write current and sense current to bit line BL and the operation at the time of data reading and data writing are the same as those in FIG. 16, detailed description will not be repeated. .

  Therefore, even in the memory cell arrangement according to the sixth embodiment, the operation margin is secured, the peripheral circuit is simplified and the data write noise is reduced, and the read word line is shared by data writing based on the folded bit line configuration. The high integration of the memory array 10 based on the above can be realized at the same time.

[Embodiment 7]
FIG. 60 is a circuit diagram showing a connection relationship between memory cells and signal lines according to the seventh embodiment.

  Referring to FIG. 60, bit line BL is electrically coupled to magnetic tunnel junction MTJ through access transistor ATR. Magnetic tunnel junction MTJ is coupled between write word line WWL and access transistor ATR. Read word line RWL is coupled to the gate of access transistor ATR. The read word line RWL and the write word line WWL are arranged in parallel, and the bit line BL is arranged in a direction intersecting with these word lines.

  Compared with the memory cell according to the sixth embodiment, the memory cell according to the seventh embodiment is arranged by replacing the connection relationship between bit line BL and write word line WWL and magnetic tunnel junction MTJ and access transistor ATR. It corresponds to a thing. Therefore, the types of signal lines to be arranged are the same as those in the sixth embodiment, and the voltage and current waveforms of each signal line at the time of data reading and data writing are the same as those in the sixth embodiment, so that detailed description is given. The explanation will not be repeated.

FIG. 61 is a structural diagram showing an arrangement of memory cells according to the seventh embodiment.
Referring to FIG. 61, bit line BL and write word line WWL are arranged in first metal interconnection layer M1 and second metal interconnection layer M2, respectively. Read word line RWL is arranged in the same layer as gate 130 of access transistor ATR. Magnetic tunnel junction MTJ is directly coupled to write word line WWL.

  Thus, also in the configuration of the memory cell according to the seventh embodiment, the MTJ memory cell can be arranged using the two metal wiring layers M1 and M2 while omitting the reference wiring SL.

  Further, since the bit line BL is coupled to the magnetic tunnel junction MTJ via the access transistor ATR, each bit line BL is a target of data reading, that is, the corresponding read word line RWL is Only the MTJ memory cells belonging to the memory cell row activated in the selected state (H level) are electrically coupled. As a result, as in the third embodiment, the capacity of the bit line BL can be suppressed, and the operation at the time of data reading can be speeded up.

FIG. 62 is a block diagram showing a configuration of memory array 10 according to the seventh embodiment.
Referring to FIG. 62, in memory array 10 according to the seventh embodiment, memory cells adjacent in the row direction share the same bit line BL.

  Since the configuration of read word line RWL, write word line WWL and word line current control circuit 40 and the operation of each memory cell during data reading and data writing are the same as in the sixth embodiment, description thereof will not be repeated.

  With such a configuration, even when the memory cells according to the seventh embodiment capable of reducing the number of signal lines and increasing the speed of data reading are arranged, the wiring pitch of the bit lines BL in the memory array 10 Can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

  In the configuration of the memory cell according to the seventh embodiment, as in the third embodiment, the distance between the bit line BL and the magnetic tunnel junction MTJ is equal to the write word line WWL and the magnetic tunnel junction MTJ. Therefore, a large data write current needs to flow through the bit line BL. Therefore, considering the electromigration resistance of the bit line BL is effective for improving the reliability of the MRAM device.

  That is, also in the arrangement of the memory cells according to the seventh embodiment, the bit line BL is secured by making the wiring width (cross-sectional area) of the bit line BL larger than the write word line WWL having a small distance from the magnetic tunnel junction. Therefore, the reliability of the MRAM device can be improved. Also, in terms of material, it is desirable to form the bit line BL with a material having high electromigration resistance.

[Modification 1 of Embodiment 7]
FIG. 63 is a block diagram showing a configuration of the memory array 10 according to the first modification of the seventh embodiment.

  Referring to FIG. 63, in memory array 10 according to the first modification of the seventh embodiment, memory cells adjacent in the column direction share the same write word line WWL as in the case of FIG. Therefore, the memory cells MC are alternately arranged for the same reason as in FIG.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the seventh embodiment, detailed description will not be repeated.

  With such a configuration, even in the arrangement of the memory cells according to the seventh embodiment, the wiring pitch of the write word lines WWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 2 of Embodiment 7]
FIG. 64 is a block diagram showing a configuration of the memory array 10 according to the second modification of the seventh embodiment.

  Referring to FIG. 64, in memory array 10 according to the second modification of the seventh embodiment, memory cells adjacent in the column direction share the same read word line RWL as in the case of FIG. The memory cells MC are arranged alternately as in the case of FIG.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the seventh embodiment, detailed description will not be repeated.

  By adopting such a configuration, the wiring pitch of the read word lines RWL in the memory array 10 can be relaxed even in the memory cell arrangement according to the seventh embodiment. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 3 of Embodiment 7]
FIG. 65 is a block diagram showing a configuration of memory array 10 according to the third modification of the seventh embodiment.

  Referring to FIG. 65, in memory array 10 according to the third modification of the seventh embodiment, similarly to the first modification of the seventh embodiment, the memory cells adjacent in the column direction have the same write word line WWL. Share. Further, the read word line RWL is also shared between memory cells adjacent in the column direction. For example, memory cell groups belonging to the second and third memory cell rows share the same read word line RWL2. For the subsequent memory cell rows, read word line RWL and write word line WWL are similarly arranged. The memory cells MC are arranged alternately as in the case of FIG.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the seventh embodiment, detailed description will not be repeated.

  With such a configuration, even in the memory cell arrangement according to the seventh embodiment, the wiring pitch of both the write word line WWL and the read word line RWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be arranged more efficiently, the memory array 10 can be further highly integrated, and the chip area of the MRAM device can be reduced as compared with the first and second modifications of the seventh embodiment. it can.

[Modification 4 of Embodiment 7]
FIG. 66 is a block diagram showing structures of the memory array 10 and peripheral circuits according to the fourth modification of the seventh embodiment.

  Referring to FIG. 66, for the memory cells according to the seventh embodiment arranged in a matrix, each set of memory cell columns formed by two adjacent memory cell columns, as in the second embodiment. In addition, a folded bit line configuration is realized using two corresponding bit lines.

  66 is different from the configuration of FIG. 57 in that in each memory cell MC, access transistor ATR and bit line BL are connected, and magnetic tunnel junction MTJ and write word line WWL are connected.

  The configuration of the other parts and the operation at the time of data reading and data writing are the same as in the case of FIG. 57, and therefore detailed description will not be repeated.

  Therefore, even in the arrangement of the memory cells according to the seventh embodiment, it is possible to secure an operation margin for data reading and data writing using the folded bit line configuration. Similarly to the second embodiment, the circuit configuration of the peripheral circuits of data write circuit 50w and read / write control circuit 60 can be simplified and data write noise can be reduced.

[Modification 5 of Embodiment 7]
In the fifth modification of the seventh embodiment, in addition to the folded bit line configuration shown in the fourth modification of the seventh embodiment, the write word line WWL is shared between adjacent memory cell rows.

  FIG. 67 is a block diagram showing structures of memory array 10 and peripheral circuits according to the fifth modification of the seventh embodiment.

  67 differs from the configuration of FIG. 58 in that in each memory cell MC, access transistor ATR and bit line BL are connected, and magnetic tunnel junction MTJ and write word line WWL are connected.

  Since the configuration of the other parts and the operation at the time of data reading and data writing are the same as those in FIG. 58, detailed description will not be repeated.

  Therefore, in the memory cell arrangement according to the seventh embodiment, it is possible to achieve both the operation margin securing by data reading based on the folded bit line configuration and the high integration of the memory array 10 based on sharing the write word line. can do.

[Modification 6 of Embodiment 7]
In the sixth modification of the seventh embodiment, in addition to the folded bit line configuration shown in the fourth modification of the seventh embodiment, the read word line RWL is shared between adjacent memory cell rows.

  FIG. 68 is a block diagram showing structures of the memory array 10 and peripheral circuits according to the sixth modification of the seventh embodiment.

  68 differs from the configuration of FIG. 59 in that in each memory cell MC, access transistor ATR and bit line BL are connected, and magnetic tunnel junction MTJ and write word line WWL are connected.

  Since the structure of the other parts and the operation at the time of data reading and data writing are the same as those in FIG. 59, detailed description will not be repeated.

  Therefore, also in the memory cell arrangement according to the seventh embodiment, the operation margin is secured, the peripheral circuit is simplified and the data write noise is reduced, and the read word line is shared by data writing based on the folded bit line configuration. The high integration of the memory array 10 based on the above can be realized at the same time.

[Embodiment 8]
FIG. 69 is a circuit diagram showing a connection relationship between memory cells and signal lines according to the eighth embodiment.

  Referring to FIG. 69, in the eighth embodiment, read bit line RBL for supplying sense current Is at the time of data reading, and write bit line WBL for supplying data write current ± Iw at the time of data writing. Is provided independently.

  Access transistor ATR is electrically coupled between magnetic tunnel junction MTJ and read bit line RBL. That is, read bit line RBL is electrically coupled to magnetic tunnel junction MTJ through access transistor ATR.

  Magnetic tunnel junction MTJ is coupled to access transistor ATR and write bit line WBL. The read word line RWL and the write word line WWL are provided in a direction crossing the read bit line RBL and the write bit line WBL. Read word line RWL is coupled to the gate of access transistor ATR.

  FIG. 70 is a timing chart illustrating data writing and data reading for the MTJ memory cell according to the eighth embodiment.

First, the operation at the time of data writing will be described.
The word line driver 30 drives the voltage of the write word line WWL corresponding to the selected row to the selected state (H level) according to the row selection result of the row decoder 20. In the non-selected row, the voltage level of the write word line WWL remains in the non-selected state (L level). By coupling each write word line WWL to the ground voltage Vss by the word line current control circuit 40, the data write current Ip can be supplied to the write word line WWL in the selected row.

  Further, by controlling the voltage of the write bit line WBL in the same manner as the voltage of the bit line BL at the time of data writing described with reference to FIG. 3, the write bit line WBL is controlled in accordance with the data level of the storage data to be written. Data write current ± Iw can flow. Thereby, data writing to the MTJ memory cell can be executed.

  Read word line RWL is maintained in a non-selected state (L level) during data writing. Read bit line RBL is precharged to a high voltage state (Vcc). Since access transistor ATR maintains a turn-off state, no current flows through read bit line RBL during data writing.

  On the other hand, at the time of data reading, write word line WWL is maintained in a non-selected state (L level), and its voltage level is fixed to ground voltage Vss by word line current control circuit 40.

  The word line driver 30 drives the read word line RWL corresponding to the selected row to the selected state (H level) according to the row selection result of the row decoder 20. In the non-selected row, the voltage level of the read word line RWL remains in the non-selected state (L level). Read / write control circuits 50 and 60 supply a fixed amount of sense current Is for data reading to read bit line RBL, and set the voltage of write bit line WBL to ground voltage Vss.

  Since read bit line RBL is precharged to a high voltage state (Vcc) before data reading, the turn-on of access transistor ATR in response to activation of read word line RWL causes read bit line RBL to access transistor ATR to A current path for the sense current Is can be formed in the magnetic tunnel junction MTJ to the write bit line WBL (ground voltage Vss). As a result, a voltage drop corresponding to the stored data appears on the read bit line RBL, so that a data read operation similar to that shown in FIG. 3 can be executed.

FIG. 71 is a structural diagram showing an arrangement of MTJ memory cells according to the eighth embodiment.
Referring to FIG. 71, read bit line RBL is formed in first metal interconnection layer M1 and coupled to source / drain region 110 of access transistor ATR. The write word line WWL is arranged in the second metal wiring layer M2. The write bit line WBL is coupled to the magnetic tunnel junction MTJ and formed in the third metal wiring layer M3. The MTJ memory cell is coupled to the source / drain region 120 of the access transistor ATR via the first and second metal wiring layers M1, M2, the metal film 150, and the barrier metal 140.

  The read bit line RBL is not directly coupled to the magnetic tunnel junction MTJ, but can be connected only to the magnetic tunnel junction MTJ of the MTJ memory cell that is the target of data reading via the access transistor ATR. Thereby, the capacity of the read bit line RBL can be suppressed, and the operation at the time of data reading can be speeded up.

  For write bit line WBL, the distance from magnetic tunnel junction MTJ can be reduced, so that the magnetic coupling at the time of data writing is set large, and data writing that flows through write bit line WBL at the time of data writing is performed. The current value of the current ± Iw can be reduced. As a result, the operation reliability can be improved by reducing magnetic noise generated by the data write current and suppressing the current density of the write bit line.

  By separately arranging the read bit line RBL and the write bit line WBL, it is possible to enjoy the above effects in a balanced manner.

FIG. 72 is a block diagram showing a configuration of memory array 10 according to the eighth embodiment.
Referring to FIG. 72, in memory array 10 according to the eighth embodiment, memory cells MC having the configuration shown in FIG. 69 are arranged in a matrix. Read word line RWL and write word line WWL are arranged along the row direction, and read bit line RBL and write bit line WBL are arranged along the column direction.

  Word line current control circuit 40 couples each write word line WWL to ground voltage Vss. Thereby, the voltage and current of write word line WWL during data reading and data writing can be controlled as shown in FIG.

  Memory cells adjacent in the row direction share either the read bit line RBL or the write bit line WBL.

  For example, the memory cell groups belonging to the first and second memory cell columns share one read bit line RBL1, and the memory cell groups belonging to the second and third memory cell columns are 1 The two write bit lines WBL1 are shared. Similarly, the read bit lines RBL and the write bit lines WBL are alternately arranged for the subsequent memory cell columns.

  Corresponding to the same read bit line RBL or write bit line WBL, data collision occurs when a plurality of memory cells MC are subjected to data reading or data writing, so that the memory cells MC are alternately arranged.

  With such a configuration, the wiring pitch of the read bit line RBL and the write bit line WBL in the memory array 10 can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

  Next, the configuration of a peripheral circuit for flowing data write current ± Iw and sense current Is will be described.

  The column selection line is provided independently for data reading and data writing for each memory cell column, that is, for each bit line. FIG. 72 representatively shows read column selection lines RCSL1 to RCSL3 and write column selection lines WCSL1 to WCSL3 corresponding to the first to third memory cell columns, respectively. In the following, when these read column selection lines and write column selection lines are generically referred to, the symbols RCSL and WCSL are used, respectively.

  Column decoder 25 activates one of a plurality of read column selection lines RCSL to a selected state (H level) at the time of data reading according to the column selection result, and a plurality of write columns at the time of data writing. One of the selection lines WSL is activated to a selected state (H level).

  A column selection gate is provided independently for data reading and data writing for each memory cell column, similarly to the column selection line. 72 representatively shows read column select gates RCG1 to RCG3 and write column select gates WCG1 to WCG3. In the following, when the plurality of read column selection gates and write column gates are generically referred to, symbols RCG and WCG are used, respectively.

  Write column select gate WCG is electrically coupled between corresponding write bit line WBL and data line IO. Read column select gate RCG is electrically coupled between corresponding read bit line RBL and data line / IO.

  Data I / O line pair DI / OP formed of data lines IO and / IO transmits data write current ± Iw at the time of data writing. On the other hand, the sense current at the time of data reading is transmitted by one data line / IO.

  Nodes Nw1 and Nw2 of data write circuit 50w for supplying data write current ± Iw are connected to data lines IO and / IO, respectively. Node Nr1 of data read circuit 51r is connected to data line / IO. Since the configuration and operation of data write circuit 50w and data read circuit 51r are as described in FIGS. 14 and 17, respectively, detailed description will not be repeated.

  Each read column selection line RCSL and each read column selection gate RCG, and each write column selection line WCSL and write column selection gate WCG are associated one-to-one. For example, read column select gate RCG1 and write column select gate WCG1 corresponding to bit line BL1 are turned on / off according to the voltage levels of read column select line RCSL1 and write column select line WCSL1, respectively.

  Any one bit line is selected according to the decoding result of the column address CA, that is, the column selection result. In response to the read column selection line RCSL or write column selection line WCSL activated according to the column selection result, the corresponding read column selection gate RCG or write column selection gate WCG is turned on. As a result, the selected read bit line RBL or write bit line WBL is electrically coupled to one of data lines IO and / IO constituting data I / O line pair DI / OP.

  Read / write control circuit 60 includes a write current control transistor, a precharge transistor, and a write bit line voltage control transistor, each arranged corresponding to a memory cell column. In FIG. 72, write current control transistors 63-1 to 63-3 and write bit line voltage control transistors respectively provided corresponding to first to third memory cell columns, that is, write bit lines WBL1 to WBL3. 65-1 to 65-3 and precharge transistors 64-1 to 64-3 provided corresponding to read bit lines RBL1 to RBL3, respectively, are representatively shown. In the following, the reference numeral 65 is used to collectively refer to the plurality of write bit line voltage control transistors.

  Each of write bit line voltage control transistors 65 is turned on during data reading, and couples corresponding write bit line WBL to ground voltage Vss in order to secure a current path for sense current Is. Other than during data reading, each write bit line voltage control transistor 65 is turned off, and each write bit line WBL is disconnected from the ground voltage Vss. Since the arrangement and operation of write current control transistor 63 and precharge transistor 64 are the same as in FIG. 15, description thereof will not be repeated.

  With such a configuration, at the time of data writing, in the selected memory cell column, data line IO to write column selection gate WCG to write bit line WBL to write current control transistor 63 to data line / IO The data write current ± Iw can be made to flow through these paths. Note that the direction of the data write current ± Iw can be controlled by setting the voltages of the data lines IO and / IO as in the second embodiment. Therefore, as in the second embodiment, the configuration of peripheral circuits related to data writing, that is, data write circuit 50w and read / write control circuit 60 can be simplified.

  As described above, even in the configuration in which the read bit line RBL and the write bit line WBL are provided independently, data reading and data writing as shown in FIG. 70 are executed according to the row selection result and the column selection result. Can do.

[Modification 1 of Embodiment 8]
FIG. 73 is a block diagram showing a configuration of memory array 10 according to the first modification of the eighth embodiment.

  Referring to FIG. 73, in memory array 10, as in the eighth embodiment, adjacent memory cells in the row direction share either read bit line RBL or write bit line WBL. Furthermore, in Modification 1 of Embodiment 8, memory cells adjacent in the column direction share the same write word line WWL. For example, the memory cell groups belonging to the first and second memory cell rows share the same write word line WWL1. Further, the memory cells MC are arranged alternately.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the eighth embodiment, detailed description will not be repeated.

  With such a configuration, the wiring pitch of the write word lines WWL in the memory array 10 can be reduced even in the memory cell arrangement according to the eighth embodiment in which the read bit line RBL and the write bit line WBL are independently arranged. . As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

  In the configuration of the memory cell according to the eighth embodiment, the distance between write word line WWL and magnetic tunnel junction MTJ is larger than the distance between write bit line WBL and magnetic tunnel junction MTJ. As in the case of the memory cell according to the first embodiment, it is necessary to pass a large data write current through write word line WWL.

  Therefore, the current density of the write word line WWL can be reduced by relaxing the wiring pitch of the write word line WWL and ensuring the cross-sectional area. Thereby, it is possible to improve the electromigration resistance of the write word line WWL through which a large data write current flows, thereby improving the reliability of the MRAM device. In terms of material, it is desirable to form the write word line WWL with a material having higher electromigration resistance than the write bit line WBL.

[Modification 2 of Embodiment 8]
FIG. 74 is a block diagram showing a configuration of memory array 10 according to the second modification of the eighth embodiment.

  Referring to FIG. 74, in memory array 10, as in the eighth embodiment, memory cells adjacent in the row direction share one of read bit line RBL and write bit line WBL. Furthermore, in Modification 2 of Embodiment 8, memory cells adjacent in the column direction share the same read word line RWL. For example, the memory cell groups belonging to the first and second memory cell rows share the same read word line RWL1. Further, the memory cells MC are arranged alternately.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the eighth embodiment, detailed description will not be repeated.

  With such a configuration, the wiring pitch of read word lines RWL in memory array 10 can be relaxed even in the memory cell arrangement according to the eighth embodiment in which read bit line RBL and write bit line WBL are independently arranged. . As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 3 of Embodiment 8]
FIG. 75 is a block diagram showing a configuration of memory array 10 according to the third modification of the eighth embodiment.

  Referring to FIG. 75, in memory array 10 according to the third modification of the eighth embodiment, memory cells adjacent in the column direction have the same write word line WWL as in the first modification of the eighth embodiment. Share. Further, the read word line RWL is also shared between memory cells adjacent in the column direction. For example, memory cell groups belonging to the second and third memory cell rows share the same read word line RWL2. For the subsequent memory cell rows, read word line RWL and write word line WWL are similarly arranged.

  However, in an arrangement in which both read word line RWL and write word line WWL are shared, read bit line RBL and write bit line WBL cannot be shared between memory cells adjacent in the column direction. Therefore, in the configuration of FIG. 75, read bit line RBL and write bit line WBL are arranged for each memory cell column.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the eighth embodiment, detailed description will not be repeated. Although not shown in FIG. 75 for convenience of description, a precharge transistor 64 is arranged corresponding to each read bit line RBL, as in the case of FIGS. 72 to 74.

  With such a configuration, even in the memory cell arrangement according to the eighth embodiment, the wiring pitch of both the write word line WWL and the read word line RWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be arranged by intensively reducing the pitch of the wiring arranged in the row direction. Thereby, the memory array 10 can be highly integrated and the chip area of the MRAM device can be reduced.

[Modification 4 of Embodiment 8]
FIG. 76 is a block diagram showing configurations of memory array 10 and peripheral circuits according to the fourth modification of the eighth embodiment.

  Referring to FIG. 76, for the memory cells according to the eighth embodiment arranged in a matrix, each set of memory cell columns formed by two adjacent memory cell columns, as in the second embodiment. In addition, a folded bit line configuration is realized by using two corresponding read bit lines and write bit lines. For example, a write bit line pair can be configured by the write bit lines WBL1 and WBL2 corresponding to the first and second memory cell columns, respectively. In this case, since write bit line WBL2 transmits data complementary to write bit line WBL1, it is also expressed as bit line / WBL1. Similarly, a read bit line pair can be formed by read bit lines RBL1 and RBL2 (/ RBL1) corresponding to the first and second memory cell columns, respectively.

  Similarly for the subsequent memory cell columns, each read bit line RBL and write bit line WBL are arranged so as to form a write bit line pair and a read bit line pair for each set of memory cell columns.

  In the following, among the write bit lines constituting each write bit line pair, one corresponding to the odd-numbered memory cell column and the other corresponding to the even-numbered memory cell column are designated as write bit lines WBL and / WBL. Also collectively referred to. Thus, data writing can be executed based on a so-called folded bit line configuration.

  Similarly, of the read bit lines constituting each read bit line pair, one corresponding to the odd-numbered memory cell column and the other corresponding to the even-numbered memory cell column are designated as read bit lines RBL and / RBL, respectively. Collectively. Data reading is performed using dummy memory cells arranged in the same manner as in the second embodiment with respect to read bit line RBL. Thus, data reading can be executed based on a so-called folded bit line configuration.

  The read column selection line and the write column selection line are provided for each read bit line pair and write bit line pair, that is, for each set of memory cell columns. Therefore, the two read column selection gates RCG and write column selection gates WCG corresponding to the same set are turned on / off in response to the common read column selection line RCSL and write column selection line WCSL, respectively.

  For example, the read column selection gates RCG1 and RCG2 corresponding to the first and second memory cell columns operate according to the common read column selection line RCSL1. Similarly, write column selection gates WCG1 and WCG2 operate according to a common write column selection line WCSL1.

  Write column selection gates WCG1, WCG3,... Provided corresponding to odd-numbered write bit lines WBL are electrically coupled between corresponding write bit lines WBL and data lines IO. On the other hand, write column select gates WCG2, WCG4,... Provided corresponding to even-numbered write bit lines / WBL are electrically coupled between corresponding write bit lines / WBL and data lines / IO.

  Similarly, read column select gates RCG1, RCG3,... Provided corresponding to odd-numbered read bit lines RBL are electrically coupled between corresponding read bit lines RBL and data lines IO. On the other hand, read column select gates RCG2, RCG4,... Provided corresponding to even-numbered read bit lines / RBL are electrically coupled between corresponding read bit lines / RBL and data lines / IO.

  Data I / O line pair DI / OP formed of data lines IO and / IO transmits data write current ± Iw at the time of data writing and transmits a sense current at the time of data reading.

  Data write circuit 50w and data read circuit 50r for supplying data write current ± Iw are connected to data lines IO, / IO through current switching circuit 53a. Since the configuration and operation of data write circuit 50w, data read circuit 50r and current switching circuit 53a are as shown in FIG. 14, detailed description will not be repeated.

  In response to the decode result of the column address CA, that is, the read column selection line RCSL or write column selection line WCSL activated according to the column selection result, the corresponding two read column selection gates RCG or write column selection gates WCG Turns on. As a result, the read bit lines RBL and / RBL constituting the selected read bit line pair or the write bit lines WBL and / WBL constituting the selected write bit line pair become the data I / O line pair DI / OP. Are electrically coupled to each of data lines IO and / IO.

  Read / write control circuit 60 is provided corresponding to each write bit line pair, is provided corresponding to equalize transistor 62 which is turned on / off in response to control signal WE, and corresponding to each write bit line WBL. Includes a write bit line voltage control transistor 65 that electrically couples the corresponding write bit line and the ground voltage Vss. Further, although not shown in FIG. 76, a precharge transistor 64 that is turned on / off in response to a bit line precharge signal BLPR corresponds to each read bit line RBL, as in FIGS. Arranged.

  With such a configuration, the selected read bit line pair conducts data reading by flowing a sense current in the same manner as the bit line pair of the second embodiment at the time of data reading. Similarly, the selected write bit line pair performs data writing by passing a data write current through corresponding equalizer transistor 62 in the same manner as the bit line pair of the second embodiment at the time of data writing. .

  Therefore, also in the arrangement of the memory cells according to the eighth embodiment, it is possible to secure an operation margin for data reading and data writing using the folded bit line configuration. Similarly to the second embodiment, the circuit configuration of the peripheral circuits of data write circuit 50w and read / write control circuit 60 can be simplified and data write noise can be reduced.

[Modification 5 of Embodiment 8]
In Modification 5 of Embodiment 8, in addition to the folded bit line configuration shown in Modification 4 of Embodiment 8, sharing of write word line WWL between adjacent memory cell rows is achieved.

  FIG. 77 is a block diagram showing structures of memory array 10 and peripheral circuits according to the fifth modification of the eighth embodiment.

  Referring to FIG. 77, in memory array 10 according to the fifth modification of the eighth embodiment, the memory cells adjacent in the column direction share the same write word line WWL.

  At the time of data reading in which the read word line RWL is activated, every other memory cell column is connected to each read bit line RBL, so that the memory cell formed by two adjacent memory cell columns A read bit line pair is formed for each set of columns, and data reading similar to that of the fourth modification of the eighth embodiment based on the folded bit line configuration can be executed.

  On the other hand, at the time of data writing in which write word line WWL shared between a plurality of memory cell rows is activated, data writing based on the folded bit line configuration cannot be performed. Therefore, in the fifth modification of the eighth embodiment, activation of the column selection line at the time of data writing is controlled for each memory cell column.

Read / write control circuit 60 includes a write current control transistor 63 arranged corresponding to each memory cell column, instead of equalize transistor 62. The write current control transistor is turned on in response to activation of the corresponding write column selection line. 77 representatively shows write current control transistors 63-1 to 63-4 provided corresponding to the first to fourth memory cell columns, that is, write bit lines WBL1 to WBL4, respectively. Although not shown, the precharge transistor 64 is arranged corresponding to each read bit line RBL, as in the case of FIGS.

  The write current control transistors 63-1, 63-3,... Provided corresponding to the odd-numbered memory cell columns correspond to the corresponding write bit lines WBL1, WBL3,. Are arranged to electrically couple. On the other hand, the write current control transistors 63-2, 63-4,... Provided corresponding to the even-numbered memory cell columns correspond to the corresponding write bit lines WBL2, WBL4,. Arranged to electrically couple IO.

  Therefore, in the selected memory cell column, data write is performed on the path from data line IO (/ IO) to write column selection gate WCSG to write bit line WBL to write current control transistor 63 to data line / IO (IO). Current ± Iw can flow. The direction of data write current ± Iw can be controlled by setting the voltages of data lines IO and / IO as in the second embodiment. Therefore, as in the second embodiment, the configuration of peripheral circuits related to data writing, that is, data write circuit 50w and read / write control circuit 60 can be simplified.

  Further, although data writing based on the folded bit line configuration cannot be executed, the wiring pitch of the write word lines WWL in the memory array 10 can be relaxed. As a result, as in the first modification of the eighth embodiment, the chip area of the MRAM device is reduced by increasing the integration of the memory array 10, and the reliability of the MRAM device is improved by improving the electromigration resistance of the write word line WWL. Can be planned.

[Modification 6 of Embodiment 8]
In the sixth modification of the eighth embodiment, in addition to the folded bit line configuration shown in the fourth modification of the eighth embodiment, the read word line RWL is shared between adjacent memory cells.

  FIG. 78 is a block diagram showing structures of the memory array 10 and peripheral circuits according to the sixth modification of the eighth embodiment.

  Referring to FIG. 78, in memory array 10 according to the sixth modification of the eighth embodiment, memory cells adjacent in the column direction share the same read word line RWL.

  Read / write control circuit 60 includes an equalize transistor 62 and a write bit line voltage control transistor 65 arranged in the same manner as in the fourth modification of the eighth embodiment. The read / write control circuit 60 further includes a precharge transistor 64 arranged corresponding to each read bit line RBL, as shown in FIGS. 72 to 74, although not shown.

  At the time of data writing in which the write word line WWL is activated, every other memory cell column is connected to each write bit line WBL. Therefore, a memory formed by two adjacent memory cell columns. A write bit line pair can be formed for each set of cell columns. As a result, data writing similar to that of the fourth modification of the eighth embodiment based on the folded bit line configuration can be executed. Therefore, an operation margin for data writing can be ensured as in the second embodiment. In addition, the circuit configuration of peripheral circuits related to data writing, that is, the data write circuit 50w and the read / write control circuit 60 peripheral circuit can be simplified, and magnetic field noise generated during data writing can be reduced.

  On the other hand, at the time of data reading in which read word line RWL shared between a plurality of memory cell rows is activated, data reading based on the folded bit line configuration cannot be performed.

  In the configuration according to the sixth modification of the eighth embodiment, a current switching circuit 53b and a data reading circuit 51r are arranged in place of current switching circuit 53a and data reading circuit 50r, respectively. Since configurations and operations of current switching circuit 53b and data reading circuit 51r have already been described with reference to FIGS. 16 and 17, detailed description thereof will not be repeated.

  With such a configuration, it is not possible to secure an operation margin with the folded bit line configuration, but the data pitch can be normally executed by relaxing the wiring pitch of the read word lines RWL in the memory array 10. As a result, similarly to the third modification of the second embodiment, the chip area of the MRAM device can be reduced by highly integrating the memory array 10.

  Therefore, also in the arrangement of the memory cells according to the eighth embodiment, the operation margin is secured, the peripheral circuit is simplified and the data write noise is reduced, and the read word line RWL is shared by data writing based on the folded bit line configuration. The high integration of the memory array 10 based on the implementation can be realized at the same time.

[Embodiment 9]
FIG. 79 is a circuit diagram showing a connection relationship between memory cells and signal lines according to the ninth embodiment.

  Referring to FIG. 79, in the memory cell according to the ninth embodiment, access transistor ATR is electrically coupled between read bit line RBL and magnetic tunnel junction MTJ. Magnetic tunnel junction MTJ is coupled between access transistor ATR and write word line WWL. Access transistor ATR has its gate coupled to read word line RWL.

  As described with reference to FIG. 70, the voltage level of write word line WWL at the time of data reading is set to ground voltage Vss, so that write word line WWL is coupled to magnetic tunnel junction MTJ instead of read bit line RBL. Can do. Thus, at the time of data reading, in response to activation of read word line RWL, access transistor ATR is turned on, and between read bit line RBL-access transistor ATR-magnetic tunnel junction MTJ-write word line WWL. A current path of the sense current Is can be formed, and a voltage change corresponding to the storage data of the magnetic tunnel junction MTJ can be generated in the read bit line RBL.

  On the other hand, at the time of data writing, magnetic field perpendicular to each other can be generated at magnetic tunnel junction MTJ by the data write currents flowing through write word line WWL and write bit line WBL.

  Therefore, in the data write and data read operations for the MTJ memory cell according to the ninth embodiment, the voltages and currents of read word line RWL, write word line WWL, read bit line RBL and write bit line WBL are set similarly to FIG. Can be done by doing.

FIG. 80 is a structural diagram illustrating the arrangement of MTJ memory cells according to the ninth embodiment.
Referring to FIG. 80, in the ninth embodiment, write bit line WBL does not need to be coupled to other wiring or MTJ memory cells, so priority is given to improving magnetic coupling with magnetic tunnel junction MTJ. Can be arranged freely. Write bit line WBL is arranged immediately below magnetic tunnel junction MTJ using, for example, second metal interconnection layer M2.

  The write word line WWL is electrically coupled to the magnetic tunnel junction MTJ and disposed in the third metal wiring layer M3. Since the arrangement of read word line RWL, access transistor ATR and read bit line RBL is the same as that of FIG. 71, description thereof will not be repeated.

  With such a configuration, the read bit line RBL is coupled to the magnetic tunnel junction MTJ via the access transistor ATR. Therefore, the read bit line RBL is directly connected to a number of magnetic tunnel junctions MTJ belonging to the same memory cell column. The capacity of the read bit line RBL can be suppressed without connection. As a result, the data reading operation can be speeded up.

  Further, since the interval between the magnetic tunnel junction MTJ and the write word line WWL can be narrowed, the magnetic coupling at the time of data writing can be increased, and the amount of data write current Ip of the write word line WWL can be reduced. Can be set. As a result, the operation reliability can be improved by reducing magnetic noise generated by the data write current and suppressing the current density of the write bit line.

  Therefore, similarly to the memory cell according to the eighth embodiment, by separately arranging read bit line RBL and write bit line WBL, the above effects can be enjoyed in both data reading and data writing. it can.

FIG. 81 is a block diagram showing a configuration of memory array 10 according to the ninth embodiment.
Referring to FIG. 81, in memory array 10 according to the ninth embodiment, memory cells adjacent in the row direction share one of read bit line RBL and write bit line WBL, as in FIG. To do.

  For example, the memory cell groups belonging to the first and second memory cell columns share one read bit line RBL1, and the memory cell groups belonging to the second and third memory cell columns are 1 The two write bit lines WBL1 are shared. Similarly, the read bit lines RBL and the write bit lines WBL are alternately arranged for the subsequent memory cell columns.

  Further, the arrangement of the write bit line voltage control transistor 65 in the read / write control circuit 60 becomes unnecessary due to the configuration of the memory cell.

  Arrangement and configuration of memory cell MC, read word line RWL, write word line WWL, word line current control circuit 40, and peripheral circuit for supplying data write current and sense current according to the column selection result Since it is the same as that of form 8, description is not repeated.

  With such a configuration, even when the memory cells according to the ninth embodiment are arranged, the wiring pitch of read bit line RBL and write bit line WBL in memory array 10 can be relaxed. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

  In the configuration of the memory cell according to the ninth embodiment, the distance between write bit line WBL and magnetic tunnel junction MTJ is larger than the distance between write word line WWL and magnetic tunnel junction MTJ. Therefore, a large data write current needs to flow through the write bit line WBL. Therefore, considering the electromigration resistance of the write bit line WBL is effective in improving the reliability of the MRAM device.

  That is, also in the arrangement of the memory cell according to the ninth embodiment, the write bit line WBL has a wiring width (cross-sectional area) larger than that of the write word line WWL having a small distance from the magnetic tunnel junction portion, thereby The electromigration resistance of the line WBL can be increased and the reliability of the MRAM device can be improved. Also, in terms of material, it is desirable to form the write bit line WBL with a material having high electromigration resistance.

[Variation 1 of Embodiment 9]
FIG. 82 is a block diagram showing a configuration of memory array 10 according to the first modification of the ninth embodiment.

  Referring to FIG. 82, in memory array 10 according to the first modification of the ninth embodiment, memory cells adjacent in the column direction share the same write word line WWL as in FIG.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the ninth embodiment, detailed description will not be repeated.

  With such a configuration, the wiring pitch of the write word lines WWL in the memory array 10 can be relaxed even in the memory cell arrangement according to the ninth embodiment. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 2 of Embodiment 9]
FIG. 83 is a block diagram showing a configuration of the memory array 10 according to the second modification of the ninth embodiment.

  Referring to FIG. 83, in memory array 10 according to the second modification of the ninth embodiment, memory cells adjacent in the column direction share the same read word line RWL as in FIG.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the ninth embodiment, detailed description will not be repeated.

  By adopting such a configuration, the wiring pitch of the read word lines RWL in the memory array 10 can be relaxed even in the memory cell arrangement according to the ninth embodiment. As a result, the memory cells MC can be efficiently arranged to highly integrate the memory array 10 and the chip area of the MRAM device can be reduced.

[Modification 3 of Embodiment 9]
FIG. 84 is a block diagram showing a configuration of memory array 10 according to the third modification of the ninth embodiment.

  Referring to FIG. 84, in memory array 10 according to the third modification of the ninth embodiment, memory cells adjacent in the column direction have the same write word line WWL as in the first modification of the ninth embodiment. Share. Further, the read word line RWL is also shared between memory cells adjacent in the column direction. For example, memory cell groups belonging to the second and third memory cell rows share the same read word line RWL2. For the subsequent memory cell rows, read word line RWL and write word line WWL are similarly arranged.

  As in the case of FIG. 75, in the arrangement in which both read word line RWL and write word line WWL are shared, read bit line RBL and write bit line WBL cannot be shared between memory cells adjacent in the row direction. . Read bit line RBL and write bit line WBL are arranged for each memory cell column.

  Since the structure of other portions and the operation of each memory cell at the time of data reading and data writing are the same as those in the ninth embodiment, detailed description will not be repeated.

  With such a configuration, even in the memory cell arrangement according to the ninth embodiment, the wiring pitch of both the write word line WWL and the read word line RWL in the memory array 10 can be relaxed. As a result, the memory cells MC can be arranged by intensively reducing the pitch of the wiring arranged in the row direction. Thereby, the memory array 10 can be highly integrated and the chip area of the MRAM device can be reduced.

[Modification 4 of Embodiment 9]
FIG. 85 is a block diagram showing structures of memory array 10 and peripheral circuits according to the fourth modification of the ninth embodiment.

  Referring to FIG. 85, the memory cells according to the seventh embodiment arranged in a matrix form are memory cells formed by two adjacent memory cell columns as in the fourth modification of the eighth embodiment. A folded bit line configuration is realized by using two corresponding read bit lines and write bit lines for each set of columns.

  85, in each memory cell MC, the point that the write word line WWL is connected to the magnetic tunnel junction MTJ and the point that the write bit line WBL is not connected to the magnetic tunnel junction MTJ are the modifications of the eighth embodiment. Different from the configuration of FIG. Further, the arrangement of the write bit line voltage control transistor 65 in the read / write control circuit 60 becomes unnecessary due to the configuration of the memory cell.

  Since the structure of the other parts and the operation at the time of data reading and data writing are the same as in the case of FIG. 76, detailed description will not be repeated.

  Therefore, also in the arrangement of the memory cells according to the ninth embodiment, it is possible to secure an operation margin for data reading and data writing using the folded bit line configuration. Similarly to the second embodiment, the circuit configuration of the data write circuit 50w and the read / write control circuit 60 peripheral circuit can be simplified and the data write noise can be reduced.

[Variation 5 of Embodiment 9]
In the fifth modification of the ninth embodiment, in addition to the folded bit line configuration shown in the fourth modification of the ninth embodiment, the write word line WWL is shared between adjacent memory cell rows.

  FIG. 86 is a block diagram showing structures of memory array 10 and peripheral circuits according to the fifth modification of the ninth embodiment.

  86, in each memory cell MC, the point that the write word line WWL is connected to the magnetic tunnel junction MTJ and the point that the write bit line WBL is not connected to the magnetic tunnel junction MTJ are the modifications of the eighth embodiment. Different from the configuration of FIG. 77 according to Example 5. Further, the arrangement of the write bit line voltage control transistor 65 in the read / write control circuit 60 becomes unnecessary due to the configuration of the memory cell.

  Since the structure of the other parts and the operation at the time of data reading and data writing are the same as in the case of FIG. 77, detailed description will not be repeated.

  Therefore, even in the memory cell arrangement according to the ninth embodiment, it is possible to achieve both the operation margin ensuring by data reading based on the folded bit line configuration and the high integration of the memory array 10 based on sharing the write word line. can do.

[Modification 6 of Embodiment 9]
In the sixth modification of the ninth embodiment, in addition to the folded bit line configuration shown in the fourth modification of the ninth embodiment, the read word line RWL is shared between adjacent memory cell rows.

  FIG. 87 is a block diagram showing structures of the memory array 10 and peripheral circuits according to the sixth modification of the ninth embodiment.

  87, in each memory cell MC, the point that the write word line WWL is connected to the magnetic tunnel junction MTJ and the point that the write bit line WBL is not connected to the magnetic tunnel junction MTJ are the modifications of the eighth embodiment. It differs from the configuration of FIG. 78 according to Example 6. Further, the arrangement of the write bit line voltage control transistor 65 in the read / write control circuit 60 becomes unnecessary due to the configuration of the memory cell.

  Since the configuration of the other parts and the operation at the time of data reading and data writing are the same as those in FIG. 78, detailed description will not be repeated.

  Therefore, even in the memory cell arrangement according to the ninth embodiment, the operation margin is secured, the peripheral circuit is simplified and the data write noise is reduced, and the read word line is shared by data writing based on the folded bit line configuration. The high integration of the memory array 10 can be realized at the same time.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  10 memory array, 20 row decoder, 25 column decoder, 30 word line driver, 40 word line current control circuit, 50, 60 read / write control circuit, 50w data write circuit, 50r, 51r data read circuit, 53a, 53b Current switching circuit, 62 equalize transistor, 63 write current control transistor, 64 precharge transistor, 65 write bit line voltage control circuit, ATR access transistor, BL, / BL bit line, CCT common wiring control transistor, CSG column selection gate, FL pinned magnetic layer, MTJ magnetic tunnel junction, RBL read bit line, RCG read column selection gate, RWL read word line, SL reference voltage wiring, SBL common wiring, TB tunnel barrier, VL free magnetic layer, WCG line Column select gates, WBL, / WBL write bit line, WWL write word line.

Claims (5)

A thin film magnetic memory device,
A memory array having a plurality of magnetic memory cells arranged in a matrix;
Each of the plurality of magnetic memory cells includes:
A storage unit whose resistance value changes according to the level of stored data written by the first and second data write currents;
A memory cell selection gate for allowing a data read current to pass through the storage unit during data read,
A plurality of read word lines provided corresponding to the rows of the magnetic memory cells and for operating the corresponding memory cell selection gate according to a row selection result in the data reading;
A plurality of data lines provided corresponding to the columns of the magnetic memory cells, for flowing the first data write current and the data read current, respectively, at the time of data writing and at the time of data reading;
A plurality of write word lines provided corresponding to the rows and selectively activated in accordance with a row selection result in order to flow the second data write current during the data writing;
A plurality of reference voltage wirings provided corresponding to any one of the row and the column and for supplying a reference voltage used at the time of data reading;
The plurality of magnetic memory cells are alternately arranged at every one row and every other column at intersections of the plurality of read word lines, the plurality of write word lines, and the plurality of data lines. Provided,
The thin film magnetic memory device in which the magnetic memory cells adjacent in the column direction share a corresponding one of the plurality of write word lines. A thin film magnetic memory device,
A memory array having a plurality of magnetic memory cells arranged in a matrix;
Each of the plurality of magnetic memory cells includes:
A storage unit whose resistance value changes according to the level of stored data written by the first and second data write currents;
A memory cell selection gate for allowing a data read current to pass through the storage unit during data read,
A plurality of read word lines provided corresponding to the rows of the magnetic memory cells and for operating the corresponding memory cell selection gate according to a row selection result in the data reading;
A plurality of data lines provided corresponding to the columns of the magnetic memory cells, for flowing the first data write current and the data read current, respectively, at the time of data writing and at the time of data reading;
A plurality of write word lines provided corresponding to the rows and selectively activated in accordance with a row selection result in order to flow the second data write current during the data writing;
A plurality of reference voltage wirings provided corresponding to any one of the row and the column and for supplying a reference voltage used at the time of data reading;
The plurality of magnetic memory cells are alternately arranged at every one row and every other column at intersections of the plurality of read word lines, the plurality of write word lines, and the plurality of data lines. Provided,
The thin film magnetic memory device in which the magnetic memory cells adjacent in the column direction share a corresponding one of the plurality of read word lines. A word line driver for connecting one end of an activated write word line of the plurality of write word lines to a first voltage according to the row selection result;
The thin film magnetic memory device according to claim 1, further comprising a plurality of word line current control circuits for coupling the other ends of the plurality of write word lines to a second voltage. Two of each of the plurality of data lines constitutes a data line pair at the time of data reading,
The plurality of magnetic memory cells selected by the same read word line are respectively connected to one of two data lines constituting the data line pair,
3. The thin film magnetic memory device according to claim 1, wherein the data read current is supplied to each of two data lines constituting the data line pair corresponding to a column selection result. Two of each of the plurality of data lines constitute a data line pair at the time of data writing,
The plurality of magnetic memory cells selected by the same write word line are respectively connected to one of two data lines constituting the data line pair,
The first data write current is supplied as currents in opposite directions to each of the two data lines constituting the data line pair corresponding to a column selection result. The thin film magnetic memory device described.

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