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JP2011134750A - Semiconductor device - Google Patents

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JP2011134750A
JP2011134750A JP2009290273A JP2009290273A JP2011134750A JP 2011134750 A JP2011134750 A JP 2011134750A JP 2009290273 A JP2009290273 A JP 2009290273A JP 2009290273 A JP2009290273 A JP 2009290273A JP 2011134750 A JP2011134750 A JP 2011134750A
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semiconductor chip
semiconductor device
end surface
interposer
interface
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JP5728641B2 (en
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Takanori Konishi
孝憲 小西
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Panasonic Electric Works Co Ltd
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Panasonic Electric Works Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for preventing separation or the like in an interface by efficiently reinforcing the interface between an end face of a semiconductor chip and a fillet against thermal stress generated by the warpage at low and high temperatures. <P>SOLUTION: In the semiconductor device for sealing an area between the semiconductor chip 2 and an interposer 7 by using an underfill 9, a plurality of linear irregular sections 5 along a horizontal direction having widths W<SB>1</SB>of 30-50 μm in depth directions are provided at least at one portion of an end face 3 of the semiconductor chip 2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、フリップチップ実装型の半導体装置に関するものである。   The present invention relates to a flip chip mounting type semiconductor device.

近年、樹脂封止型半導体装置は、高密度化、高集積化、および動作の高速化の傾向にあり、従来型のパッケージよりもさらに小型化、薄型化できる半導体チップのパッケージが求められているが、このような要求に対応するものとしてフリップチップ実装が一般に用いられている(特許文献1、2参照)。   In recent years, resin-encapsulated semiconductor devices have a tendency of higher density, higher integration, and higher speed of operation, and there is a demand for semiconductor chip packages that can be made smaller and thinner than conventional packages. However, flip chip mounting is generally used to meet such a demand (see Patent Documents 1 and 2).

図3は、従来のフリップチップ実装型の半導体装置を示す断面図である。この半導体装置100は、IC、LSI等の半導体チップ2が、両面に回路が設けられた基板でありスルーホール等を介して両面の回路が導通するインターポーザ7の上面部に設けられている。なお、半導体チップ2の周囲に隣接して、チップ抵抗やチップコンデンサ等の電子部品11がインターポーザ7に実装される場合もある。   FIG. 3 is a cross-sectional view showing a conventional flip chip mounting type semiconductor device. In this semiconductor device 100, a semiconductor chip 2 such as an IC or LSI is provided on an upper surface portion of an interposer 7 where a circuit is provided on both sides and a circuit on both sides is conducted through a through hole. An electronic component 11 such as a chip resistor or a chip capacitor may be mounted on the interposer 7 adjacent to the periphery of the semiconductor chip 2.

インターポーザ7の下面部には、パッド電極にはんだボール8が接続され、半導体装置100は、このはんだボール8により回路基板12に接続される。   A solder ball 8 is connected to the pad electrode on the lower surface portion of the interposer 7, and the semiconductor device 100 is connected to the circuit board 12 by the solder ball 8.

半導体チップ2は、その表面の電極に多数のバンプ6を形成した後、このバンプ6とインターポーザ7の上面部のパッド電極とを位置合わせして接触させた状態で、フェースダウンでインターポーザ7の上面部に載置される。そしてバンプ6を加熱溶融させた後に固化することにより、半導体チップ2の電極とインターポーザ7の上面部のパッド電極とが電気的に接続される。   In the semiconductor chip 2, a large number of bumps 6 are formed on the electrode on the surface, and then the bump 6 and the pad electrode on the upper surface of the interposer 7 are aligned and contacted, and the upper surface of the interposer 7 is face-down. Placed on the part. The bumps 6 are heated and melted and then solidified, whereby the electrodes of the semiconductor chip 2 and the pad electrodes on the upper surface of the interposer 7 are electrically connected.

また、半導体チップ2とインターポーザ7との間は、液状の樹脂組成物のアンダーフィル材を充填、硬化したアンダーフィル9により封止される。アンダーフィル9によりバンプ6を保護することができ、半導体チップ2とインターポーザ7との接合強度を高め、また、大気中の水分が半導体チップ2とインターポーザ7との間に侵入するのを防止して半導体装置100のパッケージの耐湿性を向上させることができる。   Further, the gap between the semiconductor chip 2 and the interposer 7 is sealed with an underfill 9 filled and cured with an underfill material of a liquid resin composition. The underfill 9 can protect the bumps 6, increase the bonding strength between the semiconductor chip 2 and the interposer 7, and prevent moisture in the atmosphere from entering between the semiconductor chip 2 and the interposer 7. The moisture resistance of the package of the semiconductor device 100 can be improved.

このような構造のフリップチップ実装型の半導体装置100は、実装面積が小さく、さらにバンプ6の高さは通常数100μm以下と低く、ワイヤボンディング接続の場合のようにワイヤまで樹脂封止する必要がないので実装後の高さも低くすることができ、小型化、薄型化等の要求に応えることができる。   The flip chip mounting type semiconductor device 100 having such a structure has a small mounting area, and the height of the bump 6 is usually as low as several hundred μm or less, and it is necessary to encapsulate the resin up to the wire as in the case of wire bonding connection. Therefore, it is possible to reduce the height after mounting, and to meet demands such as downsizing and thinning.

アンダーフィル9は、アンダーフィル材を充填する際に、その一部が半導体チップ2とインターポーザ7との間から外方に滲み出し、半導体チップ2の端面部3から外方にはアンダーフィル9のフィレット10が形成される。このフィレット10は、その基端部が半導体チップ2の端面部3に表面張力により付着し、その外方に傾斜しながら延びる形状を有している。   When the underfill material 9 is filled with the underfill material, part of the underfill 9 oozes out from between the semiconductor chip 2 and the interposer 7, and the underfill 9 is formed outwardly from the end surface portion 3 of the semiconductor chip 2. Fillet 10 is formed. The fillet 10 has a shape in which the base end portion is attached to the end surface portion 3 of the semiconductor chip 2 by surface tension and extends while inclining outward.

一方、半導体チップ2とインターポーザ7との間をアンダーフィル9により封止した後、半導体装置100に熱が加わった場合、特に半導体チップ2とフィレット10との界面およびインターポーザ7とフィレット10との界面に応力を受ける。   On the other hand, when heat is applied to the semiconductor device 100 after sealing between the semiconductor chip 2 and the interposer 7 with the underfill 9, particularly the interface between the semiconductor chip 2 and the fillet 10 and the interface between the interposer 7 and the fillet 10. Under stress.

このように応力を受けるとこれらの界面で剥離を生じる場合もあるため、従来、アンダーフィル材に低応力化剤を配合する等の対応がなされている。しかしながら、このような対応によっても信頼性の向上は必ずしも十分ではない場合もあり、半導体装置100の信頼性をより高める技術が求められている。   When stress is applied in this way, peeling may occur at these interfaces. Conventionally, countermeasures such as blending a low stress agent with the underfill material have been made. However, even with such measures, the improvement in reliability may not always be sufficient, and a technique for further improving the reliability of the semiconductor device 100 is required.

このような技術として、図4に示すように、半導体チップ2の端面部3に、垂直方向に沿った線状の凹凸部110を水平方向に複数設け、端面部3の水平方向に全体として波状に凹凸部110を設けることが提案されている(特許文献3参照)。   As such a technique, as shown in FIG. 4, a plurality of linear concavo-convex portions 110 along the vertical direction are provided in the horizontal direction on the end surface portion 3 of the semiconductor chip 2, and the entire surface of the end surface portion 3 is wavy in the horizontal direction. It has been proposed to provide a concavo-convex portion 110 on the surface (see Patent Document 3).

このような波状の凹凸部110を設けることで、そのアンカー効果により半導体チップ2の端面部3とフィレット10との界面の密着性が向上し、応力に対する一定の補強作用が期待できる。   By providing such a wave-shaped uneven portion 110, the anchor effect improves the adhesion at the interface between the end face portion 3 of the semiconductor chip 2 and the fillet 10, and a constant reinforcing action against stress can be expected.

特開2009−155405号公報JP 2009-155405 A 特開2002−110735号公報JP 2002-110735 A 特開2004−304081号公報JP 2004-304081 A

しかしながら、図4に示すような凹凸部110を設けることで、そのアンカー効果により半導体チップ2の端面部3とフィレット10との界面の密着性がある程度向上し、応力に対する一定の補強作用が期待できるものの、低温時や高温時の熱応力によるストレス、例えばヒートサイクル時のストレスを考慮した場合、半導体チップ2の端面部3とフィレット10との界面には引き裂き応力がかかることになる。   However, by providing the concavo-convex portion 110 as shown in FIG. 4, the anchor effect improves the adhesion at the interface between the end surface portion 3 of the semiconductor chip 2 and the fillet 10 to some extent, and a certain reinforcing action against stress can be expected. However, when stress due to thermal stress at low temperature or high temperature, for example, stress at the time of heat cycle, is considered, tearing stress is applied to the interface between the end face portion 3 of the semiconductor chip 2 and the fillet 10.

すなわち、半導体チップ2とインターポーザ7との熱膨張率の差により、低温では半導体チップ2側に凸側への反りが生じ、高温では逆にインターポーザ7側に凸側への反りが生じる。   That is, due to the difference in thermal expansion coefficient between the semiconductor chip 2 and the interposer 7, the semiconductor chip 2 is warped toward the convex side at a low temperature, and conversely, the interposer 7 is warped toward the convex side at a high temperature.

このような半導体チップ2側およびインターポーザ7側への縦方向の反りは、いずれも半導体チップ2の端面部3とフィレット10との界面において、界面から引き離す方向への応力、すなわち引き裂き応力を発生させる。   Such warpage in the vertical direction toward the semiconductor chip 2 side and the interposer 7 side generates stress in a direction away from the interface, that is, tearing stress, at the interface between the end face portion 3 of the semiconductor chip 2 and the fillet 10. .

ところが、このような引き裂き応力に対して、図4に示すような凹凸部110では、凹凸の方向が垂直方向であるため引き裂き方向への補強にならず、低温時や高温時の熱応力による半導体チップ2の端面部3とフィレット10との界面での剥離を十分に抑制することができず、そして半導体チップ2やフィレット10自身の亀裂を誘発するおそれもあるという問題点があった。   However, with respect to such a tearing stress, the uneven portion 110 as shown in FIG. 4 is not reinforced in the tearing direction because the direction of the unevenness is vertical, and the semiconductor is caused by thermal stress at low or high temperatures. There is a problem that peeling at the interface between the end face portion 3 of the chip 2 and the fillet 10 cannot be sufficiently suppressed, and there is a possibility that the semiconductor chip 2 or the fillet 10 itself may be cracked.

本発明は、以上の通りの事情に鑑みてなされたものであり、低温時や高温時の反りによる熱応力に対して半導体チップの端面部とフィレットとの界面を効率的に補強し、この界面での剥離等を防止することが可能な半導体装置を提供することを課題としている。   The present invention has been made in view of the circumstances as described above, and effectively reinforces the interface between the end surface portion of the semiconductor chip and the fillet against thermal stress caused by warping at low temperature or high temperature. It is an object of the present invention to provide a semiconductor device capable of preventing peeling and the like.

本発明は、上記の課題を解決するために、以下のことを特徴としている。   The present invention is characterized by the following in order to solve the above problems.

第1に、本発明の半導体装置は、半導体チップとインターポーザとの間をアンダーフィルで封止した半導体装置であって、半導体チップの端面部の少なくとも一部に、深さ方向の幅が30〜50μmの水平方向に沿った線状の凹凸部を垂直方向に複数設けたことを特徴とする。   1stly, the semiconductor device of this invention is a semiconductor device which sealed between the semiconductor chip and the interposer by the underfill, Comprising: The width | variety of the depth direction is 30- in at least one part of the end surface part of a semiconductor chip. A plurality of linear concavo-convex portions along the horizontal direction of 50 μm are provided in the vertical direction.

第2に、上記第1の半導体装置において、凹凸部は、端面部のエッチング、研磨、および研削から選ばれるいずれかの方法により形成されたものであることを特徴とする。   Second, in the first semiconductor device, the concavo-convex portion is formed by any method selected from etching, polishing, and grinding of the end surface portion.

上記第1および第2の発明によれば、半導体チップの端面部の少なくとも一部に、深さ方向の幅が30〜50μmの水平方向に沿った線状の凹凸部を垂直方向に複数設けることで、低温時や高温時の反りによる熱応力に対して、これに対抗するように水平方向に沿って設けられた線状の凹凸部がアンカーとして有効に作用する。従って、半導体チップの端面部とフィレットとの界面が効率的に補強され、この界面での剥離等を有効に防止することができる。   According to the first and second inventions, a plurality of linear concavo-convex portions along the horizontal direction having a width in the depth direction of 30 to 50 μm are provided in at least a part of the end surface portion of the semiconductor chip in the vertical direction. Thus, linear irregularities provided along the horizontal direction to effectively counter thermal stress caused by warping at low temperatures or high temperatures effectively act as anchors. Therefore, the interface between the end face portion of the semiconductor chip and the fillet is efficiently reinforced, and peeling or the like at this interface can be effectively prevented.

本発明の半導体装置の実施形態におけるフィレットが形成された半導体チップの端面部の周辺を示す断面図である。It is sectional drawing which shows the periphery of the end surface part of the semiconductor chip in which the fillet was formed in embodiment of the semiconductor device of this invention. 図1の半導体装置の斜視図である。FIG. 2 is a perspective view of the semiconductor device of FIG. 1. 従来のフリップチップ実装型の半導体装置を示す断面図である。It is sectional drawing which shows the conventional flip-chip mounting type semiconductor device. 半導体チップの端面部に、垂直方向に沿った線状の凹凸部を設けたフリップチップ実装型の半導体装置を示す平面図である。It is a top view which shows the flip-chip mounting type semiconductor device which provided the linear uneven | corrugated | grooved part along the perpendicular direction in the end surface part of the semiconductor chip.

以下、図面を参照しながら本発明の実施形態について説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図1は、本発明の半導体装置の実施形態におけるフィレットが形成された半導体チップの端面部の周辺を示す断面図、図2は、図1の半導体装置の斜視図(半導体チップとインターポーザのみを示し、フィレット等のその他の構成部分は省略している。)である。   1 is a cross-sectional view showing the periphery of an end surface portion of a semiconductor chip on which a fillet is formed in an embodiment of a semiconductor device of the present invention, and FIG. 2 is a perspective view of the semiconductor device of FIG. 1 (only a semiconductor chip and an interposer are shown) , And other components such as fillets are omitted.).

本実施形態の半導体装置は、図1に示すように、半導体チップ2の端面部3に、水平方向に沿った線状の凹凸部5を垂直方向に複数設けたことを特徴としている。   As shown in FIG. 1, the semiconductor device of this embodiment is characterized in that a plurality of linear concavo-convex portions 5 along the horizontal direction are provided on the end surface portion 3 of the semiconductor chip 2 in the vertical direction.

この凹凸部5を設けることで、図3の従来技術のように端面部3を平滑面とした場合や、図4に示すように端面部3に垂直方向に沿った線状の凹凸部110を設けた場合に比べて、低温時や高温時の反りによる熱応力に対して、これに対抗するように水平方向に沿って設けられた線状の凹凸部5がアンカーとして有効に作用する。   By providing the concavo-convex portion 5, when the end surface portion 3 is a smooth surface as in the prior art of FIG. 3, or as shown in FIG. 4, the linear concavo-convex portion 110 along the direction perpendicular to the end surface portion 3 is provided. Compared with the case where it is provided, the linear concavo-convex portion 5 provided along the horizontal direction effectively acts as an anchor against thermal stress caused by warping at low temperatures or high temperatures.

すなわち、半導体チップ2とインターポーザ7との熱膨張率の差により、低温では半導体チップ2側に凸側への反りが生じ、高温では逆にインターポーザ7側に凸側への反りが生じるが、図1に示すように水平方向に沿った線状の凹凸部5を設けることで、これらの凸側への反りによる半導体チップ2の端面部3とフィレット10との界面での引き裂き応力に対して線状の凹凸部5が抵抗するように作用する。従って、この引き裂き応力に抵抗するのに適切な方向に設けた凹凸部5により、この界面が効率的に補強され、この界面での剥離等を有効に防止することができる。   That is, due to the difference in coefficient of thermal expansion between the semiconductor chip 2 and the interposer 7, the semiconductor chip 2 side warps to the convex side at low temperatures, while the interposer 7 side warps to the convex side at high temperatures. As shown in FIG. 1, by providing a linear concavo-convex portion 5 along the horizontal direction, a line is formed against tearing stress at the interface between the end surface portion 3 of the semiconductor chip 2 and the fillet 10 due to warpage to the convex side. The concavo-convex portion 5 acts to resist. Therefore, the uneven portion 5 provided in an appropriate direction to resist the tear stress effectively reinforces this interface, and can effectively prevent peeling at this interface.

凹凸部5は、図1の深さ方向の幅W1が30〜50μmである。幅W1が30μm未満であると半導体チップ2の端面部3とフィレット10との界面での引き裂き応力に対する補強作用が不十分となる場合がある。一方、幅W1が50μmを超えると凹凸部5の機械的強度が低下し、半導体チップ2の端面部3とフィレット10との界面での引き裂き応力に対する補強作用が不十分となる場合がある。 As for the uneven | corrugated | grooved part 5, the width W 1 of the depth direction of FIG. 1 is 30-50 micrometers. If the width W 1 is less than 30 μm, the reinforcing action against the tearing stress at the interface between the end face portion 3 of the semiconductor chip 2 and the fillet 10 may be insufficient. On the other hand, when the width W 1 exceeds 50 μm, the mechanical strength of the concavo-convex portion 5 decreases, and the reinforcing action against the tear stress at the interface between the end face portion 3 of the semiconductor chip 2 and the fillet 10 may be insufficient.

凹凸部5を形成する方法は、特に限定されないが、例えば、端面部3のエッチング、研磨、研削等が挙げられる。その他、半導体チップ2のダイシングにより凹凸部5を形成してもよい。   Although the method of forming the uneven | corrugated | grooved part 5 is not specifically limited, For example, the etching of the end surface part 3, grinding | polishing, grinding etc. are mentioned. In addition, the uneven portion 5 may be formed by dicing the semiconductor chip 2.

半導体チップ2の形状は、特に限定されず、正方形、長方形、円形等のいずれであってもよい。凹凸部5は、半導体チップ2の端面部3の全体に設けることもできるが、端面部3の少なくとも一部に設けることによっても熱応力による半導体チップ2の端面部3とフィレット10との界面での剥離等を抑制することができる。例えば、半導体チップ2の形状が正方形や長方形の場合には、凹凸部5は、半導体チップ2の少なくとも一辺に設けることができる。半導体チップ2の形状が円形の場合は、円周の1/4以上の範囲に凹凸部5を設けることが好ましい。   The shape of the semiconductor chip 2 is not particularly limited, and may be any of a square, a rectangle, a circle, and the like. The concavo-convex portion 5 can be provided on the entire end surface portion 3 of the semiconductor chip 2, but also by providing at least a part of the end surface portion 3 at the interface between the end surface portion 3 of the semiconductor chip 2 and the fillet 10 due to thermal stress. Can be prevented. For example, when the shape of the semiconductor chip 2 is a square or a rectangle, the uneven portion 5 can be provided on at least one side of the semiconductor chip 2. When the shape of the semiconductor chip 2 is circular, it is preferable to provide the concavo-convex portion 5 in a range of 1/4 or more of the circumference.

また、線状の凹凸部5は、半導体チップ2の端面部3の一辺において全て連続したものであってもよいが、その他、半導体チップ2の端面部3の一辺の長さに比べて短い線状の複数の凹凸部5が端面部3の一辺の各所に設けられたものであってもよい。   Further, the line-shaped uneven portion 5 may be continuous on one side of the end surface portion 3 of the semiconductor chip 2, but is a line shorter than the length of one side of the end surface portion 3 of the semiconductor chip 2. A plurality of concavo-convex portions 5 may be provided at various locations on one side of the end surface portion 3.

本実施形態の半導体装置の全体の構成は、図1に示した部分以外は、例えば図3に示すような従来と同様の構成とすることができる。そして本実施形態の半導体装置は、IC、LSI等の半導体チップ2と、回路形成されたFRグレードやセラミック基板等のインターポーザ7との間をアンダーフィル材により封止することにより製造することができる。   The entire configuration of the semiconductor device of this embodiment can be the same as the conventional configuration as shown in FIG. 3, for example, except for the portion shown in FIG. The semiconductor device according to the present embodiment can be manufactured by sealing between the semiconductor chip 2 such as an IC or LSI and the interposer 7 such as an FR grade or ceramic substrate on which a circuit is formed with an underfill material. .

例えば、インターポーザ7の上面部のパッド電極にバンプ6を介して半導体チップ2を接続し、次いでバンプ6間の隙間にアンダーフィル材をディスペンサ等を用いて塗布、充填した後、加熱硬化し、さらに半導体チップ2の全体を樹脂封止する等の工程を経て、フリップチップ実装による半導体装置を製造することができる。   For example, the semiconductor chip 2 is connected to the pad electrode on the upper surface portion of the interposer 7 via the bump 6, and then an underfill material is applied and filled in a gap between the bumps 6 using a dispenser or the like, and then heated and cured, Through a process such as resin-sealing the entire semiconductor chip 2, a semiconductor device by flip chip mounting can be manufactured.

アンダーフィル材としては、特に限定されないが、常温で液状のものを用いることができる。アンダーフィル材の粘度は、好ましくは25℃で0.1〜100Pa・s、より好ましくは0.5〜30Pa・sである。具体的には、例えば、エポキシ樹脂、硬化剤等を配合したエポキシ樹脂組成物をアンダーフィル材として用いることができる。   Although it does not specifically limit as an underfill material, A liquid thing can be used at normal temperature. The viscosity of the underfill material is preferably 0.1 to 100 Pa · s, more preferably 0.5 to 30 Pa · s at 25 ° C. Specifically, for example, an epoxy resin composition containing an epoxy resin, a curing agent, or the like can be used as the underfill material.

アンダーフィル材の加熱硬化の条件は、特に限定されるものではなくアンダーフィル材の種類に応じて適宜のものとすればよいが、例えば、エポキシ樹脂組成物の場合には120〜170℃、0.5〜5時間とすることができる。   The conditions for heat-curing the underfill material are not particularly limited, and may be set appropriately according to the type of the underfill material. For example, in the case of an epoxy resin composition, 120 to 170 ° C., 0 .5-5 hours.

本発明の半導体装置におけるパッケージ形態としては、各種のフリップチップ実装型のパッケージ、例えば、ベアーICの場合は勿論、WLCSP(Wafer Level Chip Size Package)、BGA(Ball Grid Array)、CSP(Chip Size Package)等が挙げられる。   As a package form in the semiconductor device of the present invention, various flip chip mounting type packages, for example, in the case of a bear IC, WLCSP (Wafer Level Chip Size Package), BGA (Ball Grid Array), CSP (Chip Size Package) are used. ) And the like.

以下、実施例により本発明をさらに詳しく説明するが、本発明はこれらの実施例に何ら限定されるものではない。
<実施例1〜4、比較例1〜5>
直径80μmのSn−Ag−Cuバンプが200μmピッチで配置された半導体チップ(TEGチップ、10mm×10mm×300μm)とインターポーザ(FR−4)との間にアンダーフィル材(パナソニック電工株式会社製「CV5186S」)を80℃で充填し、その後150℃で1時間硬化した。
EXAMPLES Hereinafter, although an Example demonstrates this invention in more detail, this invention is not limited to these Examples at all.
<Examples 1-4, Comparative Examples 1-5>
An underfill material (CV5186S, manufactured by Panasonic Electric Works Co., Ltd.) between a semiconductor chip (TEG chip, 10 mm × 10 mm × 300 μm) in which Sn-Ag-Cu bumps having a diameter of 80 μm are arranged at a pitch of 200 μm and an interposer (FR-4). ]) At 80 ° C. and then cured at 150 ° C. for 1 hour.

なお、インターポーザの上面部における半導体チップの端面部の位置から間隔をおいた位置にはアンダーフィル材の充填前に予め、チップ抵抗およびチップコンデンサを実装、配列した。   Note that a chip resistor and a chip capacitor were mounted and arranged in advance at a position spaced from the position of the end surface portion of the semiconductor chip on the upper surface portion of the interposer before filling with the underfill material.

実施例1〜4では、半導体チップの端面部の一辺または四辺全てに、半導体チップの端面部を研削することにより、水平方向に沿った線状の凹凸部を垂直方向に複数設けた。凹凸部の深さ方向の幅は、30μmまたは50μmとした。   In Examples 1 to 4, a plurality of linear concavo-convex portions along the horizontal direction were provided in the vertical direction by grinding the end surface portion of the semiconductor chip on one side or all four sides of the end surface portion of the semiconductor chip. The width of the concavo-convex portion in the depth direction was 30 μm or 50 μm.

一方、比較例1では、凹凸部を設けずに四辺の端面部を全て平滑面とした半導体チップを用いた。比較例2〜4では、実施例1〜4と同様にして半導体チップの端面部に凹凸部を設けたが、凹凸部の深さ方向の幅は、10μmまたは80μmとした。比較例5では、半導体チップの端面部に、研削により図4に示すような垂直方向に沿った線状の凹凸部を水平方向に複数設けた半導体チップを用いた。   On the other hand, in Comparative Example 1, a semiconductor chip was used in which all of the end surfaces of the four sides were smooth surfaces without providing uneven portions. In Comparative Examples 2 to 4, an uneven portion was provided on the end surface portion of the semiconductor chip in the same manner as in Examples 1 to 4, but the width in the depth direction of the uneven portion was 10 μm or 80 μm. In Comparative Example 5, a semiconductor chip was used in which a plurality of linear concavo-convex portions along the vertical direction as shown in FIG.

以上のようにして実施例1〜4、比較例1〜5のそれぞれについて20個の半導体装置のパッケージを作製した。このパッケージを、液槽ヒートサイクルにてCondition B(−55℃/+125℃)の条件で3000サイクル処理した。   As described above, 20 semiconductor device packages were produced for each of Examples 1 to 4 and Comparative Examples 1 to 5. This package was treated for 3000 cycles under the condition of Condition B (−55 ° C./+125° C.) in a liquid bath heat cycle.

このヒートサイクル試験後のパッケージについて、半導体チップの端面部とフィレットとの界面における剥離の有無により次の基準に従って評価した。
○:20個のパッケージの全てについて剥離無し
△:20個のパッケージ中、1〜4個のパッケージについて剥離有り
×:20個のパッケージ中、5個以上のパッケージについて剥離有り
評価結果を表1に示す。
The package after the heat cycle test was evaluated according to the following criteria depending on the presence or absence of peeling at the interface between the end face portion of the semiconductor chip and the fillet.
○: No peeling for all 20 packages Δ: Peeling for 1 to 4 packages in 20 packages ×: Peeling for 5 or more packages in 20 packages Table 1 shows the evaluation results Show.

Figure 2011134750
Figure 2011134750

表1より、半導体チップの端面部の少なくとも一部に、深さ方向の幅が30〜50μmの水平方向に沿った線状の凹凸部を垂直方向に複数設けた実施例1〜4では、凹凸部が半導体チップの端面部とフィレットとの界面を補強し、界面での剥離は見られなかった。   From Table 1, in Examples 1 to 4, in which at least part of the end surface portion of the semiconductor chip is provided with a plurality of linear concavo-convex portions along the horizontal direction having a width in the depth direction of 30 to 50 μm in the vertical direction, The portion reinforces the interface between the end face portion of the semiconductor chip and the fillet, and peeling at the interface was not observed.

これに対して半導体チップの端面部に凹凸部を設けずに四辺の端面部を全て垂直面とした比較例1では、多数のパッケージにおいて半導体チップの端面部とフィレットとの界面での剥離が見られた。   On the other hand, in Comparative Example 1 in which the end surfaces of the semiconductor chip are not provided with uneven portions and all of the end surfaces of the four sides are vertical surfaces, peeling is observed at the interface between the end surface of the semiconductor chip and the fillet in many packages. It was.

比較例2〜4では、半導体チップの端面部に深さ方向の幅が30μm未満または50μmを超える凹凸部を設けたが、半導体チップの端面部とフィレットとの界面での剥離が見られた。   In Comparative Examples 2 to 4, an uneven part having a width in the depth direction of less than 30 μm or more than 50 μm was provided on the end face part of the semiconductor chip, but peeling at the interface between the end face part of the semiconductor chip and the fillet was observed.

比較例5では、半導体チップの端面部に垂直方向に沿った線状の凹凸部を設けたが、半導体チップの端面部とフィレットとの界面での剥離が見られた。   In Comparative Example 5, linear uneven portions along the vertical direction were provided on the end surface portion of the semiconductor chip, but peeling at the interface between the end surface portion of the semiconductor chip and the fillet was observed.

2 半導体チップ
3 端面部
5 凹凸部
7 インターポーザ
9 アンダーフィル
1 深さ方向の幅
2 Semiconductor chip 3 End face part 5 Uneven part 7 Interposer 9 Underfill W 1 Width in depth direction

Claims (2)

半導体チップとインターポーザとの間をアンダーフィルで封止した半導体装置であって、半導体チップの端面部の少なくとも一部に、深さ方向の幅が30〜50μmの水平方向に沿った線状の凹凸部を垂直方向に複数設けたことを特徴とする半導体装置。   A semiconductor device in which a gap between a semiconductor chip and an interposer is sealed with an underfill, and at least part of an end surface portion of the semiconductor chip, linear irregularities along a horizontal direction with a depth of 30 to 50 μm A semiconductor device characterized in that a plurality of portions are provided in the vertical direction. 凹凸部は、端面部のエッチング、研磨、および研削から選ばれるいずれかの方法により形成されたものであることを特徴とする請求項1に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the concavo-convex portion is formed by any method selected from etching, polishing, and grinding of the end face portion.
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