JP2011199378A - Clock recovery circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock recovery circuit for maintaining a fixed loop gain without damaging the resistance of data reception even if an edge does not exist in a data signal for a long time.SOLUTION: A loop filter 40 converts a control current into a control voltage and smoothes and outputs the control voltage, a voltage controlled oscillator 50 generates a clock signal CLK having a frequency corresponding to the control voltage, a frequency comparison circuit 10 compares the frequency of the clock signal CLK with the frequency of a reference clock signal Fr, and outputs the control current corresponding to a comparison result to the loop filter 40, a phase comparator 21 and a charge pump 22 compare the phase of a data signal DATA with the phase of the clock signal CLK, and outputs the control current corresponding to a comparison result to the loop filter 40, a reception data length measuring circuit 31 measures the data length of the data signal DATA, compares the data length with an expected value, and outputs a control signal S1 when the data length is equal to or longer than an expected value, and an input voltage control circuit outputs the control current corresponding to the control signal S1 to the loop filter 40.

Description

  The present invention relates to a clock recovery circuit that generates a clock signal for extracting data from a serially transmitted data signal, and more particularly to a serial data transmission system compliant with a standard such as USB (Universal Serial Bus) 2.0. The present invention relates to a clock recovery circuit.

  FIG. 9 is a block diagram showing a clock recovery circuit 100 according to the prior art. The clock recovery circuit 100 generates and outputs a clock signal Fo for extracting data from a data signal DATA obtained by digitizing serial data from the outside.

  The phase comparator 102 is an XOR type phase comparator, and outputs an up signal UPa and a down signal DNa to the charge pump CPa according to the phase difference between the data signal DATA and the clock signal Fo. When the phase of the clock signal Fo is delayed, the pulse width of the up signal UPa is longer than the pulse width of the down signal DNa, and when the phase of the clock signal Fo is advanced, the pulse width of the down signal DNa is increased. It becomes longer than the pulse width of the signal UPa. When the phase difference is zero, the pulse widths of the up signal UPa and the down signal DNa are equal. The charge pump CPa receives the up signal UPa and the down signal DNa from the phase comparison circuit 102, and discharges current to the loop filter 104 via the selector 103 or from the loop filter 104 according to the up signal UPa and the down signal DNa. The control current CPao is output to the selector 103 by drawing the current.

  The frequency comparator 101 compares the frequencies of the reference clock signal Fr and the clock signal Fo, and outputs an up signal UPb and a down signal DNb to the charge pump CPb according to the frequency difference. The charge pump CPb receives the up signal UPb and the down signal DNb from the frequency comparator 101, and discharges current to the loop filter 104 via the selector 103 or from the loop filter 104 according to the up signal UPb and the down signal DNb. By drawing the current, the control current CPbo is output to the selector 103.

  The selector 103 selects the control current CPao or the control current CPbo according to the selection signal SEL, and outputs it to the loop filter 104 as the control current CPo. The loop filter 104 converts the control current CPo into a control voltage and smoothes it, and outputs it to the voltage controlled oscillator 105 as a control voltage for controlling the frequency of the clock signal Fo generated by the voltage controlled oscillator 105. The voltage controlled oscillator 105 generates and outputs a clock signal Fo having a frequency corresponding to the input control voltage.

  Next, the operation of the clock recovery circuit 100 will be described. When the clock recovery circuit 100 starts to operate, an L level selection signal SEL is input to the selector 103, and the path from the frequency comparator 101 to the loop filter 104 becomes active, and the frequency comparator 101, charge pump CPb, loop The loop composed of the filter 104 and the voltage controlled oscillator 105 is controlled so that the frequency of the clock signal Fo becomes a frequency within a predetermined range. When the difference between the frequency of the reference clock signal Fr and the frequency of the clock signal Fo falls within a predetermined range, the selection signal SEL switches from the L level to the H level, and the path from the phase comparator 102 to the loop filter 104 becomes active. Become. Thereby, the phase of the clock signal Fo is controlled to be synchronized with the phase of the data signal DATA by the loop constituted by the phase comparator 102, the charge pump CPa, the loop filter 104, and the voltage controlled oscillator 105.

  FIG. 10 is a timing chart when the clock recovery circuit 100 in FIG. 9 controls the phase of the clock signal Fo to be synchronized with the phase of the data signal DATA. Referring to FIG. 10, the phase of the clock signal Fo is adjusted so that the falling edge of the clock signal Fo occurs at the center (time t8) of the period from time t7 to time t9, which is the pulse width of the data signal DATA. Has been.

  As prior art relating to the clock recovery circuit, there are Patent Document 1 and Patent Document 2. Japanese Patent Application Laid-Open No. 2004-228561 has an object to stabilize the jitter tolerance of the frequency tracking loop in the clock recovery circuit, and a second integration circuit and a pattern generator are added to the configuration of the conventional clock recovery circuit. The second integration circuit generates an up / down signal, and the pattern generator generates a frequency correction control signal for following the change in the frequency of the serial data based on the up / down signal.

  The pulse width of the USB 2.0 data signal varies from 1 T to 6 T (1 T = 2.08 us) from the USB 2.0 standard, and the data signal is up to 0.6 UI (UNIT INTERVAL) (1 UI = 2.08 us). Jitter is allowed. When the pulse width of the data signal fluctuates, the loop gain of the analog PLL clock recovery circuit, which is a conventional technique, also fluctuates. Since the loop gain greatly fluctuates, it is difficult to find the optimum solution for the design of the filter coefficient of the loop filter and the gain of the voltage controlled oscillator, and the tolerance of data reception is not improved. In particular, when the clock recovery circuit receives long data having the same value for a long period (for example, 6T), there is no rising edge or falling edge (hereinafter, both are collectively referred to as an edge) in the data signal. Therefore, the phase comparator does not output the up signal and the down signal, and the output terminal of the charge pump enters a high impedance state. At this time, the control voltage input to the voltage controlled oscillator becomes unstable, the phase of the clock signal is shifted from the phase of the data signal, and the phase lock is easily released.

  FIG. 11 is a timing chart when a data signal DATA having no edge for a long time is input to the clock recovery circuit 100 of FIG. Referring to FIG. 11, from time t10 to time t11, the data signal DATA is at L level, and the phase comparator 102 generates an H level up signal UPa and an L level down signal DNa. As a result, the output terminal of the charge pump CPa becomes a high impedance state, the control current CPo input to the voltage controlled oscillator 105 via the loop filter 104 becomes unstable, and the phase of the clock signal Fo becomes the level of the data signal DATA. Proceeds relative to phase.

  The object of the present invention is to solve the above-described problem, and a clock capable of maintaining a constant loop gain without impairing the durability of data reception even when there is no edge in a data signal for a long period (for example, from 1T to 6T). It is to provide a recovery circuit.

A clock recovery circuit according to the present invention is a clock recovery circuit that generates and outputs a clock signal for extracting data from a data signal.
A smoothing circuit for smoothing and outputting an input control signal;
A voltage controlled oscillation circuit unit that generates a clock signal having a frequency corresponding to the control signal output from the smoothing circuit unit;
A frequency comparison circuit unit that compares the frequency of the clock signal with the frequency of a predetermined reference clock signal, generates a first control signal according to the comparison result, and outputs the first control signal to the smoothing circuit unit;
A phase comparison circuit unit that compares the phase of the data signal with the phase of the clock signal, generates a second control signal according to the comparison result, and outputs the second control signal to the smoothing circuit unit;
Received data length measuring means for measuring a data length of the data signal, comparing the data length with a predetermined expected value, and outputting a predetermined third control signal when the data length is equal to or greater than the expected value When,
And input voltage control means for generating a fourth control signal corresponding to the third control signal and outputting the fourth control signal to the smoothing circuit section.

  In the clock recovery circuit, the received data length measuring unit detects a rising edge and a falling edge of the data signal and measures a data length of the data signal.

  Further, in the clock recovery circuit, the reception data length measuring means counts the clock signal and measures the data length of the data signal.

  Still further, in the clock recovery circuit, the expected value is 2 or more.

  In the clock recovery circuit, the reception data length measurement unit may change and set the expected value based on at least one first setting signal.

Further, in the clock recovery circuit, the input voltage control means is
Charge / discharge control means for outputting a predetermined fifth control signal based on a rising edge and a falling edge of the clock signal in response to the third control signal;
Charge / discharge means for generating a fourth control signal corresponding to the fifth control signal by increasing or decreasing the current from the constant current source is provided.

  Still further, in the clock recovery circuit, the input voltage control means changes and sets the current from the constant current source based on at least one second setting signal.

  According to the present invention, the data length of the data signal is measured, the data length is compared with a predetermined expected value, and when the data length is greater than or equal to the expected value, the received data length that outputs the predetermined third control signal Since the measurement means and the input voltage control means for generating the fourth control signal corresponding to the third control signal and outputting the fourth control signal to the voltage controlled oscillation circuit section through the smoothing circuit section are provided, the data of the data signal When the length is longer than the expected value, it is possible to prevent the control signal to the voltage-controlled oscillation circuit unit from entering a high impedance state, and the phase shift of the clock recovery circuit is due to the phase shift between the data signal and the clock signal. Exceeding the possible range can be avoided, and the data reception tolerance of the clock recovery circuit can be improved.

  According to the present invention, the reception data length measurement means changes and sets the expected value based on at least one first setting signal, so that the reception data length measurement circuit, the input voltage control circuit, the smoothing circuit And the data length of the data signal when starting the phase control of the clock signal by the loop constituted by the voltage control oscillation circuit unit can be adjusted.

  Furthermore, according to the present invention, since the input voltage control means changes and sets the current from the constant current source based on at least one second setting signal, the received data length measurement circuit, the input voltage control circuit, The loop gain of the loop constituted by the smoothing circuit unit and the voltage control oscillation circuit unit can be adjusted, and the accuracy when the phase of the clock signal is controlled by the loop can be finely adjusted.

1 is a block diagram showing a clock recovery circuit 1 according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a reception data length measurement circuit 31 in FIG. 1. FIG. 3 is a circuit diagram showing a data edge detection circuit 312 in FIG. 2. 3 is a circuit diagram showing the counter 311 and the expected value comparison circuit 313 of FIG. 2 when the expected value is 2. FIG. FIG. 2 is a circuit diagram showing an input voltage control circuit 32 of FIG. 1. 2 is a timing chart showing an operation of the clock recovery circuit 1 of FIG. 1 when an expected value is 2. FIG. It is a circuit diagram which shows the reception data length measurement circuit 31a which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the input voltage control circuit 32a which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the clock recovery circuit 100 which concerns on a prior art. 10 is a timing chart when the clock recovery circuit 100 of FIG. 9 controls the phase of the clock signal Fo to be synchronized with the phase of the data signal DATA. 10 is a timing chart when a data signal DATA having no edge for a long period of time is input to the clock recovery circuit 100 of FIG. 9.

First embodiment.
FIG. 1 is a block diagram showing a clock recovery circuit 1 according to the first embodiment of the present invention. The clock recovery circuit 1 receives a data signal DATA and a reference clock signal Fr obtained by digitizing serial data input from an external device (not shown), and receives a clock signal CLK for extracting data from the data signal DATA. appear. Here, the number of clock pulses of the clock signal CLK corresponding to a period in which the H level or the L level continues in the data signal DATA is referred to as a data length of the data signal DATA.

  The clock recovery circuit 1 according to the first embodiment controls input control currents CPOUT1, CPOUT2, and CPOUT3 in the clock recovery circuit 1 that generates and outputs a clock signal CLK for extracting data from the data signal DATA. A loop filter 40 that converts the voltage into a voltage and outputs it after smoothing, a voltage-controlled oscillator 50 that generates a clock signal CLK having a frequency corresponding to the control voltage output from the loop filter 40, and a frequency of the clock signal CLK Compared with the frequency of the reference clock signal Fr, the frequency comparison circuit unit 10 that generates the control current CPOUT1 according to the comparison result and outputs it to the loop filter 40, and compares the phase of the data signal DATA with the phase of the clock signal CLK. Control current CPOUT2 according to the comparison result The phase comparator 21 and the charge pump 22 output to the loop filter 40 and the data length of the data signal DATA are measured, and the data length is compared with a predetermined expected value. A reception data length measurement circuit 31 that outputs a control signal S1 and an input voltage control circuit that generates a control current CPOUT3 corresponding to the control signal S1 and outputs the control current CPOUT3 to the loop filter 40 are provided.

  The clock recovery circuit 1 includes a frequency comparison circuit unit 10, a phase comparison circuit unit 20, a loop filter 40 that forms a smoothing circuit unit, and a voltage control oscillator 50 that forms a voltage control transmission circuit unit. . The frequency comparison circuit unit 10 includes a frequency divider 11, a frequency comparator 12, and a charge pump 13. The phase comparison circuit unit 20 includes a phase comparator 21, a charge pump 22, and a reception data length. A measurement circuit 31 and an input voltage control circuit 32 are provided.

  In FIG. 1, first, the frequency comparison circuit unit 10 will be described. The frequency divider 11 divides the clock signal CLK output from the voltage controlled oscillator 50 into 1 / N (N is an integer where N> 0, for example, 2) to generate the clock signal Fv. And output to the frequency comparator 12. When there is no need to divide the clock signal CLK, the divider 11 need not be provided.

  The frequency comparator 12 receives the clock signal Fv from the frequency divider 11, the reference clock signal Fr from the external device (not shown), and the control signal FLOCK1, and charge pumps the up signal UP1 and the down signal DN1. 12 is output. When the control signal FLOCK1 is at L level, the frequency comparator 12 outputs an up signal UP1 at H level and a down signal DN1 at L level to the charge pump 13. On the other hand, when the control signal FLOCK1 is at the H level, the frequency comparator 12 compares the phase and frequency of the reference clock signal Fr with the phase and frequency of the clock signal Fv, respectively. For example, the frequency comparator 12 compares the rising edge of the reference clock signal Fr with the rising edge of the clock signal Fv. When the rising edge of the reference clock signal Fr is input to the frequency comparator 12 before the rising edge of the clock signal Fv, the frequency comparator 12 does not change the L until the rising edge of the clock signal Fv is input. A level up signal UP 1 and an L level down signal DN 1 are generated and output to the charge pump 13. In addition, when the rising edge of the clock signal Fv is input to the frequency comparator 12 before the rising edge of the reference clock signal Fr, the frequency comparator 12 does not input until the rising edge of the reference clock signal Fr is input. Meanwhile, an H level up signal UP 1 and an H level down signal DN 1 are generated and output to the charge pump 13.

The charge pump 13 operates as follows according to the up signal UP1 and the down signal DN1 from the frequency comparator 12.
(1) When the up signal UP1 is at the H level and the down signal DN1 is at the L level, the charge pump 13 sets the output terminal to the high impedance state.
(2) When both the up signal UP1 and the down signal DN1 are at the H level, the charge pump 13 draws a predetermined control current CPOUT1 from the loop filter 40.
(3) When both the up signal UP1 and the down signal DN1 are at the L level, the charge pump 13 discharges the predetermined control current CPOUT1 to the loop filter 40.

  As described above, the frequency comparison circuit unit 10 sets the output terminal to the high impedance state when the control signal FLOCK1 is at the L level, and outputs the control current CPOUT1 to the loop filter 40 when the control signal FLOCK1 is at the H level. .

  Next, the phase comparison circuit unit 20 will be described. The phase comparator 21 receives the clock signal CLK from the voltage controlled oscillator 50, the data signal DATA from the external device (not shown), and the control signal FLOCK2, and receives the up signal UP2 and the down signal DN2 as the charge pump 22. Output to. When the control signal FLOCK2 is at L level, the phase comparator 21 outputs an up signal UP2 at H level and a down signal DN2 at L level to the charge pump 22. On the other hand, when the control signal FLOCK2 is at the H level, the phase comparator 21 compares the phase of the clock signal CLK with the phase of the data signal DATA. When the phase of the clock signal CLK is equal to the phase of the data signal DATA, the phase comparator 21 is a signal level obtained by inverting the signal level of the clock signal CLK and having the same pulse width in synchronization with the clock signal CLK. The down signal DN2 is generated and output to the charge pump 22. When the phase of the clock signal CLK is delayed from the phase of the data signal DATA, the phase comparator 21 generates the up signal UP2 and the down signal DN2 and outputs them to the charge pump 22. At this time, the up signal UP2 Is longer than the pulse width of the down signal DN2 and the period in which both the up signal UP2 and the down signal DN2 are at the L level is compared with the case where the phase of the clock signal CLK and the phase of the data signal DATA are equal. The time corresponding to the phase difference becomes longer. Further, when the phase of the clock signal CLK is ahead of the phase of the data signal DATA, the phase comparator 21 generates the up signal UP2 and the down signal DN2 and outputs them to the charge pump 22, and at this time, the up signal UP2 Is shorter than the pulse width of the down signal DN2, and when the up signal UP2 and the down signal DN2 are both at the H level, the phase of the clock signal CLK is equal to the phase of the data signal DATA. The time corresponding to the phase difference becomes longer. Further, when the data signal DATA has no edge and only the clock signal CLK is input, that is, when the data length of the data signal DATA is 2 or more, the phase comparator 21 outputs the H level up signal UP2 and the L level signal. The down signal DN2 is output to the charge pump 22.

The charge pump 22 operates as follows according to the up signal UP2 and the down signal DN2 from the phase comparator 21.
(1) When the up signal UP2 is at the H level and the down signal DN2 is at the L level, the charge pump 13 sets the output terminal to the high impedance state.
(2) When both the up signal UP2 and the down signal DN2 are at the H level, the charge pump 13 draws a predetermined control current CPOUT2 from the loop filter 40.
(3) When both the up signal UP2 and the down signal DN2 are at the L level, the charge pump 13 discharges the predetermined control current CPOUT2 to the loop filter 40.

  As described above, in the phase comparator 21 and the charge pump 22, when the control signal FLOCK2 is at L level, the output terminal of the charge pump 22 is in a high impedance state, the control signal FLOCK2 is at H level, and the data signal DATA. Is less than 2, the charge pump 22 outputs the control current CPOUT2 to the loop filter 40, and when the control signal FLOCK2 is at the H level and the data length of the data signal DATA is 2 or more, the charge pump 22 The output terminal becomes high impedance.

  The reception data length measurement circuit 31 receives a clock signal CLK from the voltage controlled oscillator 50 and a data signal DATA from an external device (not shown), detects an edge of the data signal DATA, and receives data of the data signal DATA. The length is measured, and when the data length of the data signal DATA is equal to or greater than a predetermined value (hereinafter referred to as an expected value), the H level control signal S1 is output to the input voltage control circuit 32, while the data length of the data signal DATA Is less than the expected value, the L level control signal S1 is output to the input voltage control circuit 32.

  The input voltage control circuit 32 sets the output terminal in a high impedance state when the control signal S1 is at the L level, and supplies current to the loop filter 40 in synchronization with the clock signal CLK when the control signal S1 is at the H level. The control current CPOUT3 is output to the loop filter 40 by drawing out the current or drawing the current from the loop filter 40.

  As described above, in the received data length measurement circuit 31 and the input voltage control circuit 32, when the data length of the data signal DATA is less than the expected value, the output terminal of the input voltage control circuit 32 is in a high impedance state, and the data signal When the DATA data length is longer than the expected value, the input voltage control circuit 32 outputs the control current CPOUT3 to the loop filter 40.

  The loop filter 40 converts the control current CPOUT1 output from the frequency comparison circuit unit 10 and the control current CPOUT2 and control current CPOUT3 output from the phase comparison circuit unit 20 into control voltages and smooths them to the voltage controlled oscillator 50. Output. The voltage controlled oscillator 50 generates and outputs a clock signal CLK having a frequency corresponding to the input control voltage.

  Hereinafter, configurations and operations of the reception data length measurement circuit 31 and the input voltage control circuit 32 will be described in detail.

  FIG. 2 is a block diagram showing the received data length measurement circuit 31 of FIG. The reception data length measurement circuit 31 includes a counter 311, a data edge detection circuit 312, and an expected value comparison circuit 313. In FIG. 2, the data edge detection circuit 312 detects the rising edge and the falling edge of the data signal DATA, and outputs an H level clear signal CLR to the counter 311 when any edge is detected. The counter 311 is an up-counter with reset, and resets the count value to 1 based on the H level clear signal CLR, and then counts the pulses of the clock signal CLK from the voltage controlled oscillator 50 to indicate the count value. CNT is output to the expected value comparison circuit 313. The expected value comparison circuit 313 compares the count signal CNT with a preset expected value, and outputs an H-level control signal S1 to the input voltage control circuit 32 when the value of the count signal CNT is equal to or higher than the expected value. On the other hand, when the value of the count signal CNT is less than the expected value, the L level control signal S 1 is output to the input voltage control circuit 32.

  FIG. 3 is a circuit diagram showing the data edge detection circuit 312 of FIG. The data edge detection circuit 312 includes a resistor R1, a capacitor C1, a buffer B1, and an exclusive OR gate XOR1. The exclusive OR gate XOR1 generates a clear signal CLR indicating an XOR operation result between the data signal DATA and the signal level at the connection point P1, and outputs the clear signal CLR to the counter 311. The resistor R1 and the capacitor C1 constitute a low pass filter. When the data signal DATA changes from the L level to the H level, the potential at the connection point P1 gradually rises according to the time constant, and for a predetermined period (C × R × α (C is the capacitor C1) until it is determined to be the H level. , R is the resistance value of the resistor R1, α is a proportional constant)), and the clear signal becomes H level. On the other hand, when the data signal DATA changes from the H level to the L level, the potential at the connection point P1 gradually decreases according to the time constant and is cleared for a predetermined period (C × R × α) until it is determined to be the L level. The signal becomes H level.

  FIG. 4 is a circuit diagram showing the counter 311 and the expected value comparison circuit 313 of FIG. The counter 311 includes a D flip-flop FF1. In the D flip-flop FF1, the power supply voltage VCC is input to the input terminal D, the clock signal CLK from the voltage controlled oscillator 50 is input to the clock terminal CK, and the clear signal CLR from the data edge detection circuit 312 is input to the reset terminal RES. The count signal CNT is output from the non-inverting output terminal to the expected value comparison circuit 313.

  Since the power supply voltage VCC is always at the H level, each time the clock signal CLK is input, the D flip-flop FF1 outputs the H level count signal CNT from the non-inverting output terminal and the H level clear signal CLR is input. Then, the count signal CNT of L level is output from the non-inverting output terminal until the next clock signal CLK is input. As described above, the clear signal CLR becomes H level when the data edge detection circuit 312 detects the edge of the data signal DATA. Therefore, the count signal CNT is H when the data length of the data signal DATA is 2 or more. Become a level.

  The expected value comparison circuit 313 includes an AND gate AND1, and the AND gate AND1 generates a control signal S1 indicating an operation result of the AND of the power supply voltage VCC and the count signal CNT from the counter 311 to generate an input voltage control circuit. 32. Here, since the power supply voltage VCC is always at the H level, the control signal S1 is at the H level when the count signal CNT is at the H level, while the control signal S1 is at the L level when the count signal CNT is at the L level. . Therefore, the control signal S1 becomes H level when the data length of the data signal DATA is 2 or more.

  FIG. 5 is a circuit diagram showing the input voltage control circuit 32 of FIG. The input voltage control circuit 32 includes a charge / discharge control unit 321 and a charge / discharge unit 322.

  The charge / discharge control unit 321 includes an AND gate AND2, a NOT gate NOT1, an SR flip-flop FF2, a NAND gate NAND1, a buffer B2, an AND gate AND3, and a buffer B3. The AND gate AND2 inputs the clock signal CLK from the voltage controlled oscillator 50 and the control signal S1 from the received data length measurement circuit 31, and outputs a signal indicating the AND operation result to the set input terminal of the SR flip-flop FF2. At the same time, the signal is output to the reset input terminal of the SR flip-flop FF2 via the NOT gate NOT1. The SR flip-flop FF2 outputs a signal from the non-inverting output terminal to the buffer B2 through the NAND gate NAND1, and outputs a signal from the inverting output terminal to the buffer B3 through the AND gate AND3. Further, the control signal S1 from the reception data length measurement circuit 31 is input to the NAND gate NAND1 and the AND gate AND3. Buffer B2 outputs up signal UP3 to charging / discharging unit 322, and buffer B3 outputs down signal DN3 to charging / discharging unit 322.

  The charging / discharging unit 322 includes a constant current source 323 that generates a current Ion, NMOSFETs Q1, Q2, Q3, and Q4, and PMOSFETs Q5, Q6, and Q7. NMOSFETs Q1 and Q2 constitute a current mirror circuit. A current Ion flows through NMOSFET Q1, and a current corresponding to the current Ion flows through NMOSFET Q2. The NMOSFETs Q1 and Q3 constitute a current mirror circuit. A current Ion flows through the NMOSFET Q1, and a current corresponding to the current Ion flows through the NMOSFET Q3. Further, the PMOSFETs Q5 and Q6 constitute a current mirror circuit. A current equal to the current flowing through the NMOSFET Q2 flows through the PMOSFET Q5, and a current corresponding to the current flowing through the PMOSFET Q5 flows through the PMOSFET Q6. Further, the PMOSFETs Q6 and Q7 and the NMOSFETs Q4 and Q3 are connected in series between the power supply voltage VCC and the ground, constitute a CMOS inverter, and receive the up signal UP3 and the down signal DN3 from the charge / discharge control unit 321. Then, the control current CPOUT3 is output to the loop filter 40 as will be described in detail later.

  First, the operation of the charge / discharge control unit 321 when the control signal S1 is at the L level will be described. When the control signal S1 is at L level, an L level signal is input to the set input terminal of the SR flip-flop FF2 and an H level signal is input to the reset input terminal regardless of the signal level of the clock signal CLK. . Therefore, the SR flip-flop FF2 outputs an L level signal from the non-inverting output terminal, and outputs an H level signal from the inverting output terminal. The up signal UP3 is at the H level because it is the negation of the logical product of the output signal of the non-inverted output terminal and the control signal S1, while the down signal DN3 is the logical product of the inverted output terminal and the control signal S1. L level. That is, when the control signal S1 is at L level, the up signal UP3 is at H level and the down signal DN3 is at L level.

  Next, the operation of the charge / discharge control unit 321 when the control signal S1 is at the H level will be described. When the control signal S1 is at the H level, a signal having the same signal level as the clock signal CLK is input to the set input terminal of the SR flip-flop FF2, and a signal having a signal level obtained by inverting the clock signal CLK is input to the reset input terminal. Is done. Therefore, the SR flip-flop FF2 outputs a signal having the same signal level as the clock signal CLK from the non-inverting output terminal, and outputs a signal having a signal level obtained by inverting the clock signal CLK from the inverting output terminal. Since the up signal UP3 is a negation of the logical product of the output signal of the non-inverted output terminal and the control signal S1, the up signal UP3 has a signal level obtained by inverting the clock signal CLK, while the down signal DN3 has the inverted output terminal and the control signal S1. Therefore, the signal level is obtained by inverting the clock signal CLK. That is, when the control signal S1 is at the H level, both the up signal UP3 and the down signal DN3 are at a signal level obtained by inverting the clock signal CLK in synchronization with the clock signal CLK.

The charging / discharging unit 322 operates as follows according to the up signal UP3 and the down signal DN3 from the charging / discharging control unit 321.
(1) When the up signal UP3 is at the H level and the down signal DN3 is at the L level, both the PMOSFET Q7 and the NMOSFET Q4 are turned off, and the output terminal is in a high impedance state.
(2) When both the up signal UP3 and the down signal DN3 are at the H level, the PMOSFET Q7 is turned off and the NMOSFET Q4 is turned on. A current corresponding to the current Ion to be drawn is drawn from the loop filter 40.
(3) When both the up signal UP3 and the down signal DN3 are at the L level, the PMOSFET Q7 is turned on and the NMOSFET Q4 is turned off. The current corresponding to the current Ion is discharged to the loop filter 40.

  Since it is configured as described above, the clock recovery circuit 1 operates as follows. First, the H level control signal FLOCK1 is input to the frequency comparison circuit unit 10, and the L level control signal FLOCK2 is input to the phase comparison circuit unit 20, and the frequency comparison circuit unit 10, the loop filter 40, and the voltage controlled oscillator 50 is controlled so that the phase of the clock signal CLK is synchronized with the phase of the reference clock signal Fr. Next, an L level control signal FLOCK 1 is input to the frequency comparison circuit unit 10, and an H level control signal FLOCK 2 is input to the phase comparison circuit unit 20. When the data length of the data signal DATA is less than 2, the phase of the clock signal CLK is changed to the phase of the data signal DATA by the loop constituted by the phase comparator 21, the charge pump 22, the loop filter 40, and the voltage controlled oscillator 50. Controlled to synchronize. On the other hand, when the data length of the data signal DATA is 2 or more, the phase of the clock signal CLK is changed by the loop composed of the reception data length measurement circuit 31, the input voltage control circuit 32, the loop filter 40, and the voltage control oscillator 50. Controlled to be maintained.

  FIG. 6 is a timing chart showing the operation of the clock recovery circuit 1 when the expected value is 2. Here, it is assumed that the L-level control signal FLOCK1 is input to the frequency comparison circuit unit 10 and the H-level control signal FLOCK2 is input to the phase comparison circuit unit 20. In the period from time t1 to time t4, the data length of the data signal DATA is less than 2. Therefore, at time t1, t2, t3, the clear signal CLR becomes H level in synchronization with the clock signal CLK, so that the control signal S1 is at L level and the up signal UP3 is in the period from time t1 to time t4. Since it is at the H level and the down signal DN3 is at the L level, the output terminal of the input voltage control circuit 32 is in a high impedance state. On the other hand, during the period from time t1 to time t4, the phase comparator 21 generates the up signal UP2 and the down signal DN2, and the charge pump 22 outputs the control current CPOUT2 to the loop filter 40. Therefore, in the period from time t1 to time t4, the phase of the clock signal CLK is synchronized with the phase of the data signal DATA by the loop constituted by the phase comparator 21, the charge pump 22, the loop filter 40, and the voltage controlled oscillator 50. To be controlled.

  At time t4, the data length of the data signal DATA becomes 2 or more, and this state continues until time t5. Therefore, during the period from time t4 to time t5, the clear signal CLR is at L level, the control signal S1 is at H level in response to the rising edge of the clock signal CLK at time t4, and the input voltage control circuit 32 is an up signal. The UP3 and the down signal DN3 are changed in synchronization with the clock signal CLK, and the control current CPOUT3 is output. On the other hand, during a period from time t4 to time t5, the phase comparator 21 generates an H level up signal UP2 and an L level down signal DN2, and the output terminal of the charge pump 22 is in a high impedance state. Therefore, during the period from time t4 to time t5, the phase of the clock signal CLK is maintained by the loop constituted by the reception data length measurement circuit 31, the input voltage control circuit 32, the loop filter 40, and the voltage controlled oscillator 50. To be controlled.

  At time t5, a rising edge occurs in the data signal DATA and the data length of the data signal DATA becomes less than 2. Therefore, in the period from time t5 to time t6, the clock recovery circuit 1 performs the above-described time t1 to time t4. It operates in the same manner as in FIG. Furthermore, since the data length of the data signal DATA becomes 2 or more at time t6, the clock recovery circuit 1 operates in the same manner as the operation from time t4 to time t5 described above in the period after time t6.

  As described above, according to the first embodiment, when the data length of the data signal DATA is 2 or more, the reception data length measurement circuit 31 outputs the H level control signal S1, and the input voltage control circuit 32 outputs the control current CPOUT3 to the loop filter 40, and inputs the control voltage to the voltage controlled oscillator 50 via the loop filter 40. Therefore, when the data length of the data signal DATA is 2 or more, The control voltage can be prevented from entering a high impedance state, and the phase shift between the data signal DATA and the clock signal CLK can be prevented from exceeding the phase adjustable range of the clock recovery circuit 1. The tolerance of data reception of the recovery circuit 1 can be improved.

  In the first embodiment, the charge pump 13, the charge pump 22, and the input voltage control circuit 32 generate control currents CPOUT1, CPOUT2, and CPOUT3, respectively, and output them to the loop filter 40, and the loop filter 40 is input. However, the present invention is not limited to this, and the charge pump 13, the charge pump 22, and the input voltage control circuit 32 are configured as follows. A control signal or a control voltage may be generated and output to the loop filter 40, and the control signal or control voltage input to the loop filter 40 may be smoothed and output to the voltage controlled oscillator 50.

  Further, in the first embodiment, the expected value is 2, but the present invention is not limited to this, and the expected value may be 2 or more.

Second embodiment.
FIG. 7 is a circuit diagram showing a received data length measurement circuit 31a according to the second embodiment of the present invention. The components other than the reception data length measurement circuit 31a are the same as those in the first embodiment, and a description thereof will be omitted. The reception data length measurement circuit 31a includes a counter 311, a data edge detection circuit 312, and an expected value comparison circuit 313a. The counter 311 and the data edge detection circuit 312 are the same as those in the first embodiment. The expected value comparison circuit 313a changes and sets the value of the expected value based on the setting signal SET1 from an external device (not shown) as compared with the expected value comparison circuit 313 of the first embodiment. Is different. The control signal SEL1 is composed of an N-bit signal indicating an expected value, is input to the expected value comparison circuit 313a, is decoded, and is set as an expected value.

  As described above, according to the second embodiment, there are the same functions and effects as those of the first embodiment. Furthermore, according to the second embodiment, the reception data length measurement circuit 31a changes and sets the expected value to an arbitrary value based on the setting signal SET1 from the external device. The data length of the data signal DATA when starting the phase control of the clock signal CLK by the loop constituted by the input voltage control circuit 32, the loop filter 40, and the voltage controlled oscillator 50 can be adjusted.

Third embodiment.
FIG. 9 is a circuit diagram showing an input voltage control circuit 32a according to the third embodiment of the present invention. The components other than the input voltage control circuit 32a are the same as those in the first embodiment, and a description thereof will be omitted. The input voltage control circuit 32a includes a charge / discharge control unit 321 and a charge / discharge unit 322a. The charge / discharge control unit 321 is the same as that of the first embodiment. Compared with the charging / discharging unit 322 of the first embodiment, the charging / discharging unit 322a is configured such that the constant current source 323a changes and sets the current Ion based on a setting signal SET2 from an external device (not shown). The point is different. The setting signal SET2 is composed of an N-bit signal indicating the current Ion, is input to the constant current source 323a, is decoded, and is set as the current Ion.

  As described above, according to the third embodiment, there are the same functions and effects as those of the first embodiment. Further, according to the third embodiment, the input voltage control circuit 32a changes and sets the current Ion from the constant current source 323 to an arbitrary value based on the setting signal SET2 from the external device. The loop gain of the loop constituted by the length measurement circuit 31, the input voltage control circuit 32, the loop filter 40, and the voltage control oscillator 50 can be adjusted, and the accuracy when the phase of the clock signal CLK is controlled by the loop is improved. Fine adjustments can be made.

  In the first embodiment, instead of the reception data length measurement circuit 31 and the input voltage control circuit 32, the reception data length measurement circuit 31a used in the second embodiment and the third embodiment are used. An input voltage control circuit 32a may be used. The clock recovery circuit in this case has the same operational effects as those of the first embodiment, the second embodiment, and the third embodiment.

  As described above in detail, according to the clock recovery circuit of the present invention, the data length of the data signal is measured, and the data length is compared with a predetermined expected value. The received data length measuring means for outputting the third control signal, and the input voltage for generating the fourth control signal corresponding to the third control signal and outputting the fourth control signal to the voltage controlled oscillation circuit unit through the smoothing circuit unit Control means, so that when the data length of the data signal is longer than the expected value, the control signal to the voltage controlled oscillation circuit unit can be prevented from entering a high impedance state, and the data signal and the clock signal Can be avoided from exceeding the phase adjustment range of the clock recovery circuit, and the data reception tolerance of the clock recovery circuit can be improved.

  Also, according to the clock recovery circuit of the present invention, the reception data length measurement means changes and sets the expected value based on at least one first setting signal, so that the reception data length measurement circuit, the input voltage It is possible to adjust the data length of the data signal when starting the phase control of the clock signal by the loop constituted by the control circuit, the smoothing circuit unit, and the voltage control oscillation circuit unit.

  Furthermore, according to the clock recovery circuit of the present invention, the input voltage control means changes and sets the current from the constant current source based on at least one second setting signal, so that the received data length measurement circuit, The loop gain of the loop composed of the input voltage control circuit, the smoothing circuit unit, and the voltage control oscillation circuit unit can be adjusted, and the accuracy when controlling the phase of the clock signal can be finely adjusted by the loop. .

1 ... Clock recovery circuit,
10: Frequency comparison circuit section,
11 ... frequency divider,
12 ... Frequency comparator,
13 ... Charge pump,
20: Phase comparison circuit unit,
21 ... Phase comparator,
22 ... Charge pump,
31, 31a ... Received data length measuring circuit,
32, 32a ... input voltage control circuit,
40 ... Loop filter,
50 ... Voltage controlled oscillator,
311 ... Counter
312 ... Data edge detection circuit,
313, 313a ... expected value comparison circuit,
321... Charge / discharge control unit,
322, 322a ... charging / discharging part,
323, 323a ... constant current source,
AND1, AND2, AND3 ... ANDGATE,
B1, B2, B3 ... buffer,
C1 ... capacitor
CLK: Clock signal,
CLR ... Clear signal,
CNT: Count signal,
CPOUT1, CPOUT2, CPOUT3 ... control current,
DATA: Data signal,
DN1, DN2, DN3 ... down signal,
FF1 ... D flip-flop,
FF2 ... SR flip-flop,
FLOCK1, FLOCK2 ... control signal,
Fr: reference clock signal,
Fv: Clock signal,
Ion ... current,
NAND1 ... NAND gate,
NOT1 ... Knot gate,
P1 ... connection point,
Q1, Q2, Q3, Q4 ... NMOSFET,
Q5, Q6, Q7 ... PMOSFET,
R1 ... resistance,
S1 ... control signal,
SET1, SET2 ... Setting signal,
UP1, UP2, UP3 ... Up signal,
XOR1 ... Exclusive OR gate.

Japanese Patent No. 3939574. JP 2008-263509 A.

Claims (7)

In a clock recovery circuit that generates and outputs a clock signal for extracting data from a data signal,
A smoothing circuit for smoothing and outputting an input control signal;
A voltage controlled oscillation circuit unit that generates a clock signal having a frequency corresponding to the control signal output from the smoothing circuit unit;
A frequency comparison circuit unit that compares the frequency of the clock signal with the frequency of a predetermined reference clock signal, generates a first control signal according to the comparison result, and outputs the first control signal to the smoothing circuit unit;
A phase comparison circuit unit that compares the phase of the data signal with the phase of the clock signal, generates a second control signal according to the comparison result, and outputs the second control signal to the smoothing circuit unit;
Received data length measuring means for measuring a data length of the data signal, comparing the data length with a predetermined expected value, and outputting a predetermined third control signal when the data length is equal to or greater than the expected value When,
A clock recovery circuit comprising: input voltage control means for generating a fourth control signal corresponding to the third control signal and outputting the fourth control signal to the smoothing circuit unit.   2. The clock recovery circuit according to claim 1, wherein the received data length measuring means detects a rising edge and a falling edge of the data signal and measures a data length of the data signal.   3. The clock recovery circuit according to claim 1, wherein the reception data length measuring means measures the data length of the data signal by counting the clock signal.   4. The clock recovery circuit according to claim 1, wherein the expected value is 2 or more.   5. The clock according to claim 1, wherein the reception data length measurement unit changes and sets the expected value based on at least one first setting signal. 6. Recovery circuit. The input voltage control means includes:
Charge / discharge control means for outputting a predetermined fifth control signal based on a rising edge and a falling edge of the clock signal in response to the third control signal;
The charging / discharging means which generate | occur | produces the 4th control signal according to the said 5th control signal by increasing / decreasing the electric current from a constant current source is provided among Claims 1-5 characterized by the above-mentioned. The clock recovery circuit according to claim 1.   7. The input voltage control unit according to claim 1, wherein the input voltage control unit changes and sets the current from the constant current source based on at least one second setting signal. The clock recovery circuit described.

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