JP2011198032A - Information processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing apparatus capable of detecting a delay of an interruption response time, in real time.SOLUTION: The information processing apparatus includes a control computation part 11 for analyzing a command to be executed; an interruption controller 12 input with an interruption signal, and for informing the control computation part 11 of generation of interruption; and an interruption response time controller 13, input with the interruption signal for finding a lapse time from the time, when the interruption signal is input for comparing the lapse time with a restriction time predetermined, in response to the interruption signal and for outputting the comparison result.

Description

  The present invention relates to an information processing apparatus.

  In an information processing apparatus having a CPU (Central Processing Unit), when an interrupt occurs, the interrupt controller notifies the CPU of the occurrence of the interrupt. The CPU that has received the notification of the interruption interrupts the process that is currently being executed, and transfers the execution of the instruction to the interrupt handler.

  Since interrupts have priority, if a low-priority interrupt occurs while the CPU is executing high-priority interrupt processing, low-priority interrupt processing is performed until high-priority interrupt processing ends. The start of is delayed.

  Conversely, if a high priority interrupt occurs while the CPU is executing a low priority interrupt process, the high priority interrupt process is executed and the low priority interrupt process is interrupted.

  An information processing device always wants to execute two processes with different priorities periodically. If the start of the process is greatly delayed, the system must fail within a specified time to prevent the system from failing or the output efficiency from being degraded. Constraints such as wanting to execute may be imposed.

  In order to develop an application for an information processing device that satisfies this restriction, it is detected that the start of interrupt processing with low priority is delayed due to the processing of interrupt with high priority, and the delay in interrupt response time is real-time. Need to know exactly.

  However, since the interrupt controller only notifies the CPU that a low-priority interrupt has occurred after the processing of a high-priority interrupt has been completed, the CPU will notify the time when the interrupt occurred and the time since the occurrence. There is a problem that time cannot be known.

  Conventionally, in a multiprocessor system, there is known an interrupt processing method in which an interrupt notification to a plurality of processors is performed when a set time has elapsed, or in response to occurrence of a predetermined number of interrupts when the set time elapses or before the set time elapses. (For example, refer to Patent Document 1).

  In this interrupt processing method, when an interrupt request generated at a plurality of interrupt generation sources is detected, interrupt request source identification information corresponding to the detected interrupt request is generated and stored. When the set time elapses, or when a predetermined number of interrupt request source identification information has been accumulated when the set time elapses or before the set time elapses, an interrupt signal is sent to a processor capable of accepting interrupts in a plurality of processors. Sending out.

However, this interrupt processing method has a problem that the system configuration is complicated and a delay in interrupt response time cannot be detected in real time.

JP-A-7-129528

  The present invention provides an information processing apparatus capable of detecting a delay in interrupt response time in real time.

  An information processing apparatus according to one embodiment of the present invention includes a control arithmetic unit that interprets and executes an instruction, an interrupt signal that is input and an interrupt controller that notifies the control arithmetic unit of occurrence of an interrupt, and the interrupt signal. An interrupt response time controller that obtains an elapsed time from when the interrupt signal is input, compares the elapsed time with a predetermined constraint time according to the interrupt signal, and outputs a comparison result. It is characterized by that.

  According to the present invention, an information processing apparatus capable of detecting a delay in interrupt response time in real time can be obtained.

The block diagram which shows the information processing apparatus which concerns on the Example of this invention. The block diagram which shows the structure of the interrupt response time controller of the information processing apparatus which concerns on the Example of this invention. The time series figure for demonstrating operation | movement of the interruption response time controller of the information processing apparatus which concerns on the Example of this invention. The state machine figure for demonstrating the state of the interrupt response time controller of the information processing apparatus which concerns on the Example of this invention. The block diagram which shows the information processing apparatus of the comparative example which concerns on the Example of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  The information processing apparatus according to the present embodiment will be described with reference to FIGS. FIG. 1 is a block diagram illustrating an information processing apparatus according to the present embodiment. As illustrated in FIG. 1, the information processing apparatus 10 according to the present exemplary embodiment includes a CPU (control operation unit) 11, an interrupt controller 12, and an interrupt response time controller 13.

  The CPU 11 interprets and executes an instruction written in a ROM (Read Only Memory) or the like. The interrupt controller 12 receives an interrupt signal when an interrupt occurs, determines which interrupt signal is transmitted to the CPU 11 at which timing based on the priority set for each interrupt generating device, and sends the interrupt signal to the CPU 11 in an appropriate order. Notice.

  When an interrupt signal is input, the interrupt response time controller 13 obtains an elapsed time from when the interrupt signal is input, compares the elapsed time with a predetermined constraint time according to the interrupt signal, and compares the comparison result. Output.

  The CPU 11 outputs IC (Interrupt Controller) setting data to the interrupt controller 12 and outputs IRC (Interrupt Response time Controller) setting data to the interrupt response time controller 13 when the information processing apparatus 10 is initialized, for example, when the power is turned on. .

  The IC setting data is data indicating the priority corresponding to a plurality of interrupts, for example. The ICP setting data is, for example, data indicating a predetermined restriction time corresponding to each interrupt.

  The interrupt response time controller 13 outputs an IRC interrupt signal (constraint time violation detection signal) to the interrupt controller 12 when the elapsed time exceeds the constraint time. When receiving the IRC interrupt signal, the interrupt controller 12 notifies the CPU 11 that there is a violation of the constraint time by an interrupt instruction.

  Furthermore, the information processing apparatus 10 can be connected to another information processing apparatus such as a debugger 14. By connecting the debugger 14, IC setting data, IRC setting data, interrupt response time, and the like can be monitored, and the operating state of the interrupt response time controller 13 can be visualized.

  Here, the interrupt response time is the time required from when an interrupt occurs until the interrupt is notified to the CPU 11. The restricted time is the time allowed from when an interrupt occurs until the interrupt is notified to the CPU 11.

  FIG. 2 is a block diagram showing the configuration of the interrupt response time controller 13. As shown in FIG. 2, the interrupt response time controller 13 includes a constraint time storage 21, an interrupt elapsed time counter 22, and an interrupt elapsed time comparator 23.

  The restricted time storage 21 stores the restricted time set by the CPU 11. The interrupt elapsed time counter 22 counts the elapsed time when an interrupt signal is input. The interrupt elapsed time comparator 23 compares the elapsed time with the constraint time, and generates an IRC interrupt signal when the elapsed time exceeds the constraint time.

  The constraint time storage 21 has a plurality of registers corresponding to the number of interrupt signals. Each register is assigned an interrupt number corresponding to each interrupt, and stores a predetermined restriction time corresponding to each interrupt.

  The interrupt elapsed time counter 22 has a plurality of counters corresponding to the number of interrupt signals. Each counter is assigned an interrupt number corresponding to each interrupt. When a corresponding interrupt signal is input, an elapsed time corresponding to each interrupt is counted.

  The interrupt elapsed time comparator 23 has a plurality of comparators corresponding to the number of interrupt signals. Each comparator is assigned an interrupt number corresponding to each interrupt, and the count value (elapsed time) of the counter of the corresponding interrupt number is compared with the constraint time stored in the register of the corresponding interrupt number, and compared. Output the result.

  That is, the comparator corresponding to each interrupt outputs an IRC interrupt signal when the elapsed time corresponding to each interrupt exceeds the constraint time corresponding to each interrupt, and outputs a time initialization signal for resetting the counter of the corresponding interrupt number. Output.

  The interrupt elapsed time counter 22 stops and resets the counter of the corresponding interrupt number in the interrupt elapsed time counter 22 when there is an interrupt instruction for the interrupt controller 12 to notify the CPU 11 of the corresponding IRC interrupt.

  Note that the CPU 11 and the interrupt controller 12 themselves are well-known and will not be described in detail.

  In the information processing apparatus 10 configured as described above, when an interrupt occurs, the elapsed time since the occurrence of the interrupt is counted, and when the elapsed time exceeds a predetermined restriction time for the interrupt, the interrupt response time is determined in real time. It is configured to detect the delay.

  FIG. 3 is a diagram for explaining the operation of the interrupt response time controller 13, and shows the state of each register of the constraint time storage 21 and each counter of the interrupt elapsed time counter 22 in time series.

  As shown in FIG. 3, the time t0 indicates when the information processing apparatus 10 is off. At this time, the constraint time of each register of the constraint time storage 21 and the count value of each counter of the interrupt elapsed time counter 22 are 0, respectively.

  Time t1 indicates when the information processing apparatus 10 is turned on and the restriction time is set in the register corresponding to each interrupt number in the restriction time storage 21. The time limits for interrupts of interrupt numbers 1 to 4 (hereinafter simply referred to as interrupts 1 to 4) are, for example, 35, 36, 100, and 45, respectively. Here, the unit of time is arbitrary.

  Time t2 indicates the time when the time 20 has elapsed since the occurrence of the interrupt 1 and the time 5 has elapsed since the occurrence of the interrupt 2. At this time, the CPU executes an interrupt process having a higher priority than interrupts 1 and 2.

  The interrupt elapsed time comparator 23 compares the elapsed time (20) in interrupt 1 with the constraint time (35), and compares the elapsed time (5) in interrupt 2 with the constraint time (36).

  At time t3, between the time t2 and the time t3, the processing of the interrupt having a higher priority than the interrupt 1 is completed, and the interrupt controller 12 generates an interrupt instruction for the interrupt 1 for which the notification to the CPU 11 has been delayed. It shows the time when interrupt 1 with higher priority is being processed. In other words, the case where the interrupt 1 is processed within the restricted time is shown.

  Since the interrupt controller 12 notifies the CPU 11 of an interrupt instruction for interrupt 1, the interrupt response time controller 13 stops counting the interrupt number 1 and resets it.

  In the meantime, the time when the elapsed time (36) in the interrupt 2 has reached the constraint time (36) is shown. The interrupt elapsed time comparator 23 compares the elapsed time at the interrupt number 2 with the constraint time (36). When the elapsed time of the interrupt with the interrupt number 2 reaches the constraint time (36), the interrupt elapsed time comparator 23 sends an IRC interrupt signal to the interrupt controller 12. The time initialization signal is output to the interrupt elapsed time counter 22.

  FIG. 4 is a state machine diagram for explaining the operation of the interrupt response time controller 13. As shown in FIG. 4, the interrupt response time controller 13 transitions between the Idle state 40 and the Interrupt state 41 in the process of performing the above-described processing. After the transition from the initial state to the idle state 40, the interrupt signal 42 is received to transit to the interrupt state 41, and the interrupt elapsed time counter 22 starts counting the corresponding interrupt number.

  When the next interrupt signal 43 is input in the Interrupt state 41, the state transits to the Interrupt state 41 and the interrupt elapsed time counter 22 starts counting the corresponding interrupt number.

  When an interrupt instruction is received in the Interrupt state 41, whether the transition to the Idle state 46 or the self-transition 48 to the Interrupt state is determined according to the number of interrupts stacked within the constraint time range. In either case, the corresponding interrupt number counter is stopped and reset.

  When the interrupt elapsed time comparator 23 transmits 47 an IRC interrupt signal in the Interrupt state 41, the counter of the corresponding interrupt number is stopped and reset, and transitions to the Idle state 40 or the Interrupt state 41 according to the number of stacked interrupts. To do.

  When the remaining number of interrupt stacks is 0, all the interrupts have been processed, so the transition to the Idle state 40 is made. When the remaining number of interrupt stacks is 1 or more, an unprocessed interrupt remains, and the state transits to the Interrupt state 41.

  FIG. 5 is a block diagram illustrating a configuration of an information processing apparatus of a comparative example according to the present embodiment. Here, the comparative example is an information processing apparatus that does not have the interrupt response time controller 13.

  As shown in FIG. 5, the information processing apparatus 50 of the comparative example includes a CPU 11 and an interrupt controller 12. In order to detect violation of the restriction time of the interrupt response in the information processing apparatus 50 of the comparative example, for example, a method of resetting the watchdog timer for each interrupt period using a watchdog timer can be considered.

  The watchdog timer is a hardware time measuring device built in the CPU 11, and usually the main program falls into an illegal state such as a hang-up and regular watchdog operations are not performed (timeout). In some cases, it is used to perform exception handling.

  However, the method using the watchdog timer generates software processing overhead that resets the timer count of the watchdog timer every period. In addition, since the timer count is reset in a time shorter than the original constraint time, detection of the constraint time violation becomes inaccurate. Furthermore, there are drawbacks such as that a code different from the original function of the software is required and that it cannot be set for each interrupt.

  Therefore, when the interrupt response time is delayed from the expected value, the constraint time violation cannot be detected in real time and without causing software processing overhead at the time when the interrupt response time becomes longer.

  On the other hand, in the information processing apparatus 10 according to the present embodiment, as described above, since all processing is performed by hardware, it is possible to detect violation of the constraint time in real time. There is no overhead when processing with software.

  Therefore, the information processing apparatus 10 is suitable for use in an application development environment using the debugger 14. Since the application software can know the violation of the constraint time in real time, there is an advantage that the corrective measures can be taken earlier than the information processing apparatus 50 of the comparative example.

  The information processing apparatus 10 can be configured as a semiconductor integrated circuit in which a CPU 11, an interrupt controller 12, and an interrupt response time controller 13 are integrated on one chip. Alternatively, the CPU 11, the interrupt controller 12, and the interrupt response time controller 13 can be combined individually.

  As described above, the information document device 10 of the present embodiment includes the interrupt response time controller 13 that obtains the elapsed time from when the interrupt occurs, compares the elapsed time with the constraint time, and outputs the comparison result. ing.

  As a result, when the elapsed time exceeds the constraint time, the CPU 11 can be notified via the interrupt controller 12 that there is a violation of the constraint time. Therefore, an information processing apparatus capable of detecting a delay in interrupt response time in real time can be obtained.

  Although the case where the information processing apparatus is a single processor type has been described here, it goes without saying that the information processing apparatus can be applied to a multiprocessor type information processing apparatus.

  The interrupt instruction generated due to the IRC interrupt signal has been described for the case of a high-priority interrupt. However, if it is desired to detect violation of the constraint time in a shorter time, it may be notified as an exception. Is possible.

10, 50 Information processing device 11 CPU
12 Interrupt controller 13 Interrupt response time controller 14 Debugger 21 Restricted time storage 22 Interrupt elapsed time counter 23 Interrupt elapsed time comparator

Claims (5)

A control operation unit that interprets and executes instructions;
An interrupt controller that receives an interrupt signal and notifies the control computation unit of the occurrence of an interrupt;
Interrupt response time when the interrupt signal is input, an elapsed time from when the interrupt signal is input is obtained, the elapsed time is compared with a predetermined constraint time according to the interrupt signal, and a comparison result is output A controller,
An information processing apparatus comprising: The interrupt response time controller outputs a constraint time violation detection signal to the interrupt controller when the elapsed time reaches the constraint time,
When the interrupt controller receives the constraint time violation detection signal, the interrupt controller notifies the control arithmetic unit that there is a violation of the constraint time by an interrupt instruction. The interrupt response time controller
A constraint time storage for storing the constraint time;
When the interrupt signal is input, an interrupt elapsed time counter that counts the elapsed time;
An interrupt elapsed time comparator that compares the elapsed time with the constraint time and generates the constraint time violation detection signal when the elapsed time reaches the constraint time;
The information processing apparatus according to claim 1, further comprising:   The interrupt elapsed time counter is stopped and reset when the interrupt controller notifies the control arithmetic unit of the occurrence of the interrupt, or when the elapsed time reaches the constraint time. The information processing apparatus according to claim 3.   The information processing apparatus according to claim 2, wherein the restricted time is an allowable time from when the interruption occurs until the interruption is notified to the control calculation unit.

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