JP2011191874A - Data signal transmission and reception method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To transmit a data signal at a high speed by automatically setting the transmission time delay of the data signal to a PLC body even when the number of expansion units is increased, and setting a data signal processing signal from the PLC body in accordance with the above automatic setting. <P>SOLUTION: Each of expansion units 21 to 24 measures time delay required for self-transmission with respect to a data signal, sets up the measured time delay information due to the self-transmission as delay information to a memory inside itself, and transmits known time delay information due to the transmission of the data signal in each of communication cables 31 to 34 and the measured time delay information due to the self-transmission to the rear stage side. The PLC body 10 causes a data signal processing signal having the same cycle as that of a clock signal to delay by the time delay included in both of the time delay information, causes the delayed data signal processing signal to rise, and then performs the capturing processing of the data signal to be transmitted from the extended unit at the rising and falling timing of the data signal processing signal and the transfer processing of the data signal to the extended unit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data signal transmission / reception method in a ring data communication system, and more specifically, transfers a data signal from a PLC main body to an extension unit, and transfers the next data signal after the transferred data signal is captured by the PLC main body. In the data signal communication method by the ring data communication system to be started, the present invention relates to enabling high-speed communication processing of the data signal by setting up the delay information of the data signal.

  The PLC is also called a programmable controller or a programmable logic controller, and is composed of a PLC main body that controls the entire PLC, and various extension units such as an I / O unit and a DA conversion unit that are controlled by the PLC main body. .

  The type and number of expansion units are determined according to user specifications. The creation of a PLC control program and various settings for each expansion unit are performed by an external computer, for example, a programming tool installed in user program creation support software (see Patent Document 1).

  The PLC shown in FIG. 6 includes a PLC main body 100 and a plurality of first to fourth extension units 210-240. These are connected by first to fourth communication cables 310-340 such as RS232C. The connection lengths of the first to fourth communication cables 310 to 340 are various. 6, tx1, tx2, tx3, and tx4 are time delays due to transmission of the data signal Sx transmitted from the PLC main body 100 to the extension unit in each communication cable 310-340, and td1, td2, td3, and td4 are the data signals. A time delay due to the transmission of Sx in each expansion unit 210-240 is shown. The total time delay (tx1 + tx2 + tx3 + tx4) + (td1 + td2 + td3 + td4) is referred to as a time delay t.

  The PLC main body 100 transmits a data signal Sx to each expansion unit 210-240 in synchronization with the internal clock signal CLKx. The communication method of these data signals Sx is a ring data communication method, and the next data signal is transmitted until the data signal Sx transmitted from the PLC main body 100 to the extension unit 210-240 is returned to the PLC main body 100 as the data signal Sxa. Not to be.

  In the data signals Sx and Sxa shown in FIG. 7, “x” is x = 1, 2, 3, 4,. The data signal Sx is a data signal transferred from the PLC main body 100 to each expansion unit 210-240. The data signal Sxa is appended with the subscript “a” to the data signal Sx, and transferred from the PLC main body 100. Data signal Sx returned to PLC main body 100 after elapse of time delay t is shown.

JP 2002-108422 A

  In the case of the conventional method, for example, as shown in FIG. 8A, the time t1 after the lapse of the delay time t is the time t1 after the data signal Sx transferred from the PLC main body 100 to each expansion unit 210-240 at the time t0. As shown in (b), it is received as a data signal Sxa and taken into the PLC main body 100. Since the time delay t in this case is within the clock width tw of the clock signal CLKx shown in FIG. 8C in the PLC main body 100, the data signal Sx can be captured. In this case, a time delay t corresponding to the clock width tw is a predetermined time.

  Here, the rising period of the clock signal CLKx is a data signal Sx capturing process period, and the falling period is a transfer process period.

  However, as shown in FIGS. 9 (a), (b), and (c) corresponding to FIGS. 8 (a), (b), and (c), data due to the passage of each communication cable 310-340 and each expansion unit 210-240. Since the time delay t of the signal Sx exceeds the clock width tw of the clock signal CLKx by the delay time Δt and is delayed from the predetermined time t by the delay time Δt, the PLC main body 100 detects the data signal Sxa. The import process cannot be performed.

  Therefore, conventionally, as shown in FIG. 9C, the data signal processing signal Px having a length corresponding to the time delay t by having a pulse width longer than the pulse width tw of the clock signal CLKx by the pulse width Δt. And the data signal is captured during the rising period of the data signal processing signal Px.

  This will be described with reference to FIG. 10A shows the clock signals CLK1, CLK2, CLK3,... Having a pulse width tw, and FIG. 10B shows the data signals S1, S2, S3 from the PLC main body 100 side and the data signals. Data signals S1a, S2a, S3a received by the PLC main body 100 with a time delay t after the transfer of S1, S2, S3 are shown. The time difference between the data signals S1 and S1a, the time difference between S2 and S2a, and the time difference between S3 and S3a are time delays t, which are relative to S1a, S2, S2a,. It is necessary to control with the data signal processing signals P10, P20,... Shown in FIG. 10C in which the time difference Δt is added to the pulse width tw of the clock signals CLK1, CLK2, CLK3,. . Here, for example, the rising period of the clock signal CLK1 is 0-180 degrees in terms of phase, and the falling period (half cycle) is 180-360 degrees.

  After all, conventionally, whenever the number of expansion units increases, the user needs to set the time delay information of the data signal in the PLC main body 100, but this setting is troublesome for the user.

  Therefore, in the present invention, the time delay information of the data signal due to the transmission in the cable and the transmission in the extension unit is automatically set up in the extension unit, and the set time delay information is given to the PLC main body, thereby It is an object to be solved to automatically set the pulse width of the processing signal to enable high-speed transmission of the data signal in the ring data communication system.

The data signal transmission / reception method according to the present invention sequentially transfers a data signal from a PLC main body to a plurality of extension units via a communication cable in synchronization with a clock signal, and transmits the data signal returned to the PLC main body after completing the transfer. In the data signal transmission / reception method by the ring data communication method that performs capture processing in the main body,
Each extension unit receives a data signal from the front side, measures a time delay required for the transmission within itself with respect to the received data signal, and transmits the time delay information due to the measured transmission within itself to the internal unit. A step of setting up as delay information in the memory, a known time delay information by transmission in the communication cable connected between the received data signal and the preceding stage side, and a time delay information by the measured transmission within itself A step of transmitting to the subsequent stage, and
The PLC main body delays the data signal processing signal having the same cycle as the clock signal to rise by at least the time delay included in the both time delay information transmitted from the extension unit, and thereafter the data signal processing. The step of taking in the data signal transmitted from the expansion unit at the rising and falling timing of the signal and the step of transferring the data signal to the expansion unit are performed.

  Preferably, the extension unit measures a time delay due to the internal transmission of the data signal by a time delay measurement timer held in the extension unit, and uses the measured information as time delay information.

  In the present invention, it takes time for the data signal to pass through the communication cable and the extension unit, and even if there is a time delay between the start of transfer from the PLC body and the return to the PLC body, the data signal having the same cycle as the clock signal Data signals can be captured by processing signals, and even if the number of expansion units increases, data signal capture processing can be performed at the same timing as the clock cycle of the clock signal, enabling high-speed transmission of data signals Become.

  According to the present invention, even if the number of expansion units increases, it is possible to automatically set the time delay of the data signal due to the transmission within the communication cable or the transmission within the expansion unit, and perform the data signal transfer and capture processing. .

FIG. 1 is a diagram showing a hardware configuration of a PLC used for implementing a data signal communication method according to an embodiment of the present invention. FIG. 2 is a diagram showing a hardware configuration inside the PLC main body in the PLC of FIG. FIG. 3 is a diagram showing a hardware configuration inside the expansion unit in the PLC of FIG. FIG. 4 is a diagram for explaining the time delay of the data signal transmitted between the PLC main body and the extension unit. FIG. 5 is a timing chart for explaining the data signal communication method of this embodiment. FIG. 6 is a diagram showing a hardware configuration of a PLC used for implementing the data signal communication method according to the conventional example. FIG. 7 is a timing chart for explaining the delay time of the data signal by the data signal communication method of FIG. FIG. 8 is a timing chart for explaining the conventional data signal communication method. FIG. 9 is a diagram showing another timing chart for explaining a conventional data signal communication method. FIG. 10 is a diagram showing still another timing chart for explaining the conventional data signal communication method.

  Hereinafter, a data signal communication method according to an embodiment of the present invention will be described with reference to the accompanying drawings.

  Referring to FIG. 1, the PLC or PLC system to which this data signal communication method is applied includes PLC main body 10 and a plurality of first to fourth extension units 21-24. These are connected by first to fourth communication cables 31-34 such as RS232C. 1, tx1, tx2, tx3, tx4... Are time delays due to the transmission of the data signal Sx transmitted from the PLC main body 10 to the respective expansion units 21-24 within the respective communication cables 31-34, as in FIG. .., Td1, td2, td3, td4,... Also indicate the time delay due to the transmission of the data signal in each extension unit 21-24, as in FIG. The total time delay (tx1 + tx2 + tx3 + tx4) + (td1 + td2 + td3 + td4) is also referred to as the time delay t as in FIG.

  Referring to FIG. 2, the PLC main body 10 includes a CPU 10a that performs various controls such as sequence control, a program memory 10b that stores various programs such as firmware, ladder programs, and communications executed by the CPU 10a, and data storage. Or a memory 10c used for work and a communication interface 10d between the expansion units 21-24.

  In the PLC main body 10, the data signal transmission control by the CPU 10 a will be described later, but the CPU 10 a has the same period as the clock signal by the delay time due to the transmission of the data signal in the extension unit 21-24 and the transmission in the communication cable 31-34. The process of delaying and starting the data signal processing signal of the data signal, the subsequent processing of capturing the data signal transmitted from the expansion unit at the rise and fall timing of the data signal processing signal, and the transfer of the data signal to the expansion unit And a step for performing processing. A program for this step execution is stored in the program memory 10b.

  Referring to FIG. 3, the first extension unit 21 includes a communication control CPU 21a, a memory 21b in which programs such as firmware and communication programs executed by the CPU 21a are stored, the PLC main body 10 and other second to fourth. A communication interface 21c between the extension units 22-24 and a time delay measurement timer 21d are included.

  In the first extension unit 21, the time delay measurement timer 21d measures the time required for data signal transmission in the extension unit 21, and the time delay is synchronized with the input of the data signal to the first extension unit 21. The measurement operation is started, and the time delay measurement operation is terminated in synchronization with the output of the data signal. The time delay information of the data signal measured by the time delay measurement timer 21d is set up in the memory 21b.

  The time delay information of the data signal transmitted through the first communication cable 31 connected between the first extension unit 21 and the front stage side (the front stage in this example is the PLC main body 10) is stored in the memory 21b. The transmission time delay information in the first communication cable 31 is fixed information and is known information in advance. The CPU 21a of the first extension unit 21 stores the time delay information in the memory 21b as one piece of information held by the first communication cable 31. For example, the first communication cable 31 to the first extension unit 21 is provided with time delay information of the data signal according to the cable length, the frequency of the data signal, and other conditions.

  The CPU 21a of the first extension unit 21 transmits the measured time delay information and known time delay information together with other information to the rear stage (the rear stage in this example is the extension unit 22).

  From the above, the first extension unit 21 receives the data signal from the PLC main body 10 which is the front stage side, measures the time delay required for the transmission within itself with respect to the received data signal, and performs the above measurement. Setting up time delay information due to transmission within itself as delay information in its own memory 21b, and known time delay information due to transmission within the communication cable 31 connected between the PLC body 10 with respect to the received data signal And the step of transmitting the measured time delay information due to the transmission within itself to the second extension unit 22 on the rear stage side. This step execution program is stored in the memory 21b.

  The other second to fourth extension units 22-24 are not shown in their internal configurations, but have the same configuration as the first extension unit 21.

  The time delay information of the data signal Sx will be described with reference to FIGS. A data signal Sx is input from the PLC main body 10 to the first extension unit 21 in the first communication cable 31 over time tx1. The first extension unit 21 receives the data signal Sx via its own communication interface 21c, and starts the time delay measurement timer 21d in response to the input of the data signal Sx under the control of the CPU 21a. The data signal Sx is processed by the CPU 21a in the first extension unit 21 and then output to the second communication cable 32 via the communication interface 21c. At this time, the CPU 21a ends the time delay measurement timer operation of the time delay measurement timer 21d. The measured value of the time delay measurement timer 21d at this time is a value from when the data signal Sx is input to the first expansion unit 21 until it is output, and the transmission time of the data signal Sx within the first expansion unit 21 It becomes delay information. Then, the time delay information when the data signal Sx is transmitted in the extension unit 21 (time delay information in the extension unit) is set up and stored in the memory 21b. The data signal Sx is transmitted to the second extension unit 22 including the processing information processed by the first extension unit 21 and the time delay information.

  In the second and subsequent expansion units 22 and later, although not described, the data signal Sx is processed and transmitted in the same manner as the first expansion unit 21 and finally transmitted to the PLC main body 10.

  The table of FIG. 4 shows time delay information and transmission information regarding the above transmission information. The table of FIG. 4 shows time delay information td1-td4 set up in the memory for each extension unit 21-24 and transmission information transmitted to the subsequent stage. Processing information is not shown. Regarding the transmission information, the time extension information td1 due to the transmission within the expansion unit and the time delay information tx1 due to the transmission within the communication cable 31 are transmitted from the first extension unit 21 to the second extension unit 22 and are transmitted to the subsequent stage. The amount of transmission information increases as shown in the table of FIG.

  From the above, the time delay information tx1-tx4, td1-td4 is transmitted to the PLC main body 10 together with the processing information in each of the expansion units 21-24. The PLC main body 10 controls the transfer and capture processing of the data signal Sx as shown in FIG. 5 based on the transmitted time delay information.

  The PLC main body 10 can determine the total time delay as the time delay t as described above from the time delay information tx1-tx4, td1-td4.

  Hereinafter, the transfer and capture processing of the data signal Sx will be described with reference to FIG. First, as shown in FIG. 5A, the PLC main body 10 controls data signal transfer by using clock signals CLK1, CLK2, CLK3,... Having a clock width tw. The rising period and the falling period of these clock signals are the same tw. As shown in FIG. 5B, the data signal S1 is first transferred from the PLC main body 10 to the first extension unit 21 via the communication cable 31 at time t0. The data signal S1 is transferred through each of the second to fourth extension units 22-24, and after being transferred to the fourth extension unit 24 at the final stage, the data signal S1 is returned to the extension unit again to be connected to the PLC. It is received by the main body 10 at time t2. The data signal S1 received at time t2 is referred to as a data signal S1a for the same reason as described above. The data signal S1 is received by the PLC body 10 after the time delay t set by the time delay information, and is taken in as the data signal S1a. The same applies to the other data signals S2, S2a, S3, S3a,. There is a time difference Δt between the time delay t and the pulse width tw of the clock signal. Here, the clock width of the clock signal is the predetermined time as described above, and the time difference Δt is a time delay from the predetermined time of the data signal S.

  In the present embodiment, as shown in FIG. 5 (c), the PLC body 10 determines that the time difference Δt has elapsed from the transfer start time t0 of the first data signal S1 among the data signals S1, S2, S3,. To rise the data signal processing signal P1 having the same pulse width as the pulse width tw of the clock signal CLK1. In this case, the half cycle of the data signal processing signal P1 is equal to that of the clock signal CLK1, and the phase for capturing the data signal of the data signal processing signal P1 is 0 degrees at the rising start and 180 degrees at the falling start. Therefore, the time difference Δt is compensated.

  Then, the PLC body 10 generates the data signal processing signals P2, P3,... Having the same pulse width tw as the data signal processing signal P1 following the data signal processing signal P1, and the data signal processing signals P1, P2 , P3,..., Data signals S1a, S2a, S3a,.

  The data signals S1a, S2a, S3a,... Are signals having the same contents as the data signals S1, S2, S3,..., Respectively, and have been transferred from the PLC body 10 to the expansion unit 21-24. Is a signal that is received and processed by the PLC body 10 with a time delay t with respect to the data signals S1, S2, S3,.

  That is, in the present embodiment, it takes time for the data signal to pass through the communication cable and the extension unit, and even if there is a time delay between the start of transfer from the PLC main body and the return to the PLC main body, it is the same as the clock signal. Since the data signal can be captured and processed by the periodic data signal processing signal, the data signal can be transmitted at high speed even when the number of expansion units is increased.

10 PLC main body 21-24 1st-4th expansion unit 31-34 1st-4th communication cable

Claims (2)

Ring data communication in which a data signal is sequentially transferred from a PLC main body to a plurality of expansion units via a communication cable in synchronization with a clock signal, and a data signal that has been transferred and returned to the PLC main body is captured by the PLC main body. In the data signal transmission / reception method by the method,
Each expansion unit
Receiving a data signal from the preceding stage; and
Measuring the time delay required for transmission within the received data signal;
Setting up the time delay information due to the measured internal transmission as delay information in its own internal memory;
Transmitting the known time delay information by transmission within the communication cable connected between the preceding stage and the received data signal to the subsequent stage, and the time delay information by the measured transmission within itself, to the subsequent stage,
Run
The PLC body is
A step of delaying and starting the data signal processing signal having the same cycle as the clock signal by a time delay included in at least both the time delay information transmitted from the extension unit;
Thereafter, a step of performing a process of taking in the data signal transmitted from the expansion unit at the rising and falling timing of the data signal processing signal, and a process of transferring the data signal to the expansion unit,
Run the
A data signal transmission / reception method.   The method according to claim 1, wherein the measurement time delay information is time delay information measured by a time delay measurement timer held in the extension unit.

Images