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JP2011175215A - Display device and method for manufacturing the display device - Google Patents

Display device and method for manufacturing the display device Download PDF

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JP2011175215A
JP2011175215A JP2010041065A JP2010041065A JP2011175215A JP 2011175215 A JP2011175215 A JP 2011175215A JP 2010041065 A JP2010041065 A JP 2010041065A JP 2010041065 A JP2010041065 A JP 2010041065A JP 2011175215 A JP2011175215 A JP 2011175215A
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chip
region
wiring
area
conductive film
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Hiroyuki Fujita
宏之 藤田
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Seiko Instruments Inc
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Seiko Instruments Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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  • Liquid Crystal (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems of absence of a means for directly measuring density of conductive particles included in an anisotropic conductive film and absence of a means for knowing particle density variations of the anisotropic conductive film. <P>SOLUTION: A wiring-inhibited region 10 is arranged in the active side of an IC chip 1, and a transparent see-through region 3 is arranged so as to cope with the wiring-inhibited region, in the transparent substrate 9 of a display element mounted with the IC chip 1. By measuring the number of conductive particles 7 placed on the wiring region through the see-through region 3, the density of conductive particles included in the anisotropic conductive film can be inspected. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、液晶表示装置を含む表示装置の配線部分の接続構造に関し、特に透明基板と電子部品との接続技術に関する。   The present invention relates to a connection structure of a wiring portion of a display device including a liquid crystal display device, and more particularly to a connection technique between a transparent substrate and an electronic component.

高画質、高精細、広視角範囲、動画などの高速な応答速度のディスプレイとして、画素単位で選択駆動するためのスイッチング素子を有する液晶表示素子を用いたTFT型液晶表示装置が知られている。   As a display having a high response speed such as high image quality, high definition, wide viewing angle range, and moving image, a TFT type liquid crystal display device using a liquid crystal display element having a switching element for selectively driving pixel by pixel is known.

TFT型液晶表示装置を構成する液晶表示素子では、ガラスから形成される基板と対向基板との間に液晶層が挟持されており、基板の液晶層側の面に、y方向に並設されるゲート線(走査信号線)と、このゲート線と絶縁されて、x方向に並設されるソース線(データ線)とが形成されている。ゲート線とソース線で囲まれた各領域がそれぞれ画素領域となり、この画素領域にスイッチング素子としてTFTと透明画素電極とが形成されている。ゲート線に走査信号が供給されることにより、TFTがオンされ、このオンされたTFTを通してソース線からの信号が画素電極に供給される。これらのゲート線とソース線には、駆動用のICチップ(半導体回路)から信号が入力される(例えば、特許文献1を参照)。   In a liquid crystal display element constituting a TFT type liquid crystal display device, a liquid crystal layer is sandwiched between a substrate made of glass and a counter substrate, and arranged in parallel in the y direction on the surface of the substrate on the liquid crystal layer side. A gate line (scanning signal line) and a source line (data line) that are insulated from the gate line and arranged in parallel in the x direction are formed. Each region surrounded by the gate line and the source line becomes a pixel region, and a TFT and a transparent pixel electrode are formed as switching elements in the pixel region. When the scanning signal is supplied to the gate line, the TFT is turned on, and a signal from the source line is supplied to the pixel electrode through the turned-on TFT. Signals are input from the driving IC chip (semiconductor circuit) to these gate lines and source lines (see, for example, Patent Document 1).

従来からICチップと配線板との接続には、異方性導電膜(ACF)が広く用いられている。異方性導電膜はバインダーとして熱硬化性樹脂を有しており、接続端子が導電性粒子を挟みこんだ状態で更に加熱加圧され続けると、熱硬化性樹脂が重合して異方性導電膜が硬化する。そして導電性粒子によって接続端子同士が電気的に接続されると共に、接続端子同士が硬化した異方性導電膜で固定される(例えば、特許文献2を参照)。図6に下基板側から異方性導電膜接続部を透視したところを示す。   Conventionally, an anisotropic conductive film (ACF) has been widely used to connect an IC chip and a wiring board. The anisotropic conductive film has a thermosetting resin as a binder, and when the connection terminal continues to be heated and pressurized with the conductive particles sandwiched between them, the thermosetting resin is polymerized and anisotropic conductive. The film is cured. The connection terminals are electrically connected by the conductive particles, and the connection terminals are fixed by a cured anisotropic conductive film (see, for example, Patent Document 2). FIG. 6 shows the anisotropic conductive film connecting portion seen through from the lower substrate side.

特開2006−339613号公報(第1図、第2図)JP-A-2006-339613 (FIGS. 1 and 2) 特開2005−200521号公報(第5図)Japanese Patent Laying-Open No. 2005-200521 (FIG. 5)

しかしながら、異方性導電膜を加熱加圧するときに、最初に軟化したバインダーと共に導電性粒子が被着体の外側に流れ出すので、接続すべき接続端子の間の導電性粒子の量が少なくなり、接続端子同士が導電性粒子によって接続されないことがあった。導電性粒子の量の不足は元の異方性導電膜に含まれる導電性粒子が少なかったり、導電性粒子密度がばらついたりすることでも発生する。従来から接続端子上の導電性粒子数を測定することは行われているが、異方性導電膜に含まれる導電性粒子密度を直接測定する手段がなかった。異方性導電膜に含まれる導電性粒子密度バラツキがあっても判らなかった。   However, when the anisotropic conductive film is heated and pressurized, the conductive particles flow out of the adherend together with the softened binder first, so the amount of conductive particles between the connection terminals to be connected is reduced, The connection terminals may not be connected by the conductive particles. The shortage of the amount of conductive particles also occurs when the number of conductive particles contained in the original anisotropic conductive film is small or the density of the conductive particles varies. Conventionally, the number of conductive particles on the connection terminal has been measured, but there has been no means for directly measuring the density of conductive particles contained in the anisotropic conductive film. Even if there were variations in the density of the conductive particles contained in the anisotropic conductive film, it was not understood.

ICチップの能動面に配線パターンが形成されない配線禁止領域を設ける。また、表示素子の基板側のICチップの配線禁止領域に対応する領域には不透明な金属電極を設けない透視領域を設ける。これにより、表示素子の基板側から透視領域を通して、ICチップの配線禁止領域に存在する導電性粒子の粒子分布や粒子数を測定できる構造とする。   A wiring prohibited area where a wiring pattern is not formed is provided on the active surface of the IC chip. In addition, a transparent region in which an opaque metal electrode is not provided is provided in a region corresponding to the wiring prohibition region of the IC chip on the substrate side of the display element. Thus, a structure in which the particle distribution and the number of particles of the conductive particles existing in the wiring prohibited area of the IC chip can be measured from the substrate side of the display element through the perspective area.

また、この透視領域は配線禁止領域よりもサイズが大きくなるように設けられる。
さらに、配線禁止領域の大きさが0.01mm四方〜0.1mm四方で、透視領域は配線禁止領域との寸法の差が0.006mm〜0.01mmになるように設けられても良い。
The see-through area is provided so as to be larger in size than the wiring prohibited area.
Furthermore, the size of the wiring prohibited area may be 0.01 mm square to 0.1 mm square, and the fluoroscopic area may be provided so that the difference in dimension from the wiring prohibited area is 0.006 mm to 0.01 mm.

導電性粒子の数にバラツキ、減少があったときに現品で確認することができるようになった。製造工程においてインラインで自動検査をすることもできるようになった。   When the number of conductive particles varies or decreases, it can be confirmed on the actual product. In-line automatic inspection can be performed in the manufacturing process.

本発明の表示装置を説明するための模式図である。It is a schematic diagram for demonstrating the display apparatus of this invention. 本発明の表示装置の断面を表す模式図である。It is a schematic diagram showing the cross section of the display apparatus of this invention. 本発明の表示装置の一部を拡大した模式図である。It is the schematic diagram which expanded a part of display apparatus of this invention. 本発明の表示装置の一部を示す模式図である。It is a schematic diagram which shows a part of display apparatus of this invention. 本発明の表示装置の一部を示す模式図である。It is a schematic diagram which shows a part of display apparatus of this invention. 従来の表示装置を説明するための模式図である。It is a schematic diagram for demonstrating the conventional display apparatus.

本発明は、表示素子の透明基板にICチップが異方性導電膜によって接続されており、ICチップの能動面には配線禁止領域が設けられる。この配線禁止領域に対応するように透明基板には透視領域が設けられる。この透視領域には、不透明な金属端子や配線は配置されていない。そのため、透視領域を通して配線禁止領域に配置される導電性粒子を見ることができる。そして、この導電性粒子を計数することにより、異方性導電膜に含まれる導電性粒子密度を測定することができる。   In the present invention, an IC chip is connected to a transparent substrate of a display element by an anisotropic conductive film, and a wiring prohibited region is provided on the active surface of the IC chip. A transparent region is provided on the transparent substrate so as to correspond to the wiring prohibited region. In this see-through region, opaque metal terminals and wirings are not arranged. Therefore, the conductive particles arranged in the wiring prohibited area can be seen through the fluoroscopic area. Then, by counting the conductive particles, the density of the conductive particles contained in the anisotropic conductive film can be measured.

また、この透視領域は配線禁止領域よりもサイズが大きくなるように設けられる。
また、本発明の表示装置の製造方法は、配線禁止領域が設けられたICチップと、配線禁止領域に対応するように透視領域が設けられた透明基板とを準備し、透明基板にICチップを異方性導電膜により接続する。そして透視領域を通して配線禁止領域に設けられた異方性導電膜に含まれる導電性粒子を計数し、異方性導電膜の導電性粒子密度を測定する。
The see-through area is provided so as to be larger in size than the wiring prohibited area.
In addition, the manufacturing method of the display device of the present invention prepares an IC chip provided with a wiring prohibited area and a transparent substrate provided with a transparent area corresponding to the wiring prohibited area. They are connected by an anisotropic conductive film. And the conductive particle contained in the anisotropic conductive film provided in the wiring prohibition area | region through the fluoroscope area | region is counted, and the conductive particle density of an anisotropic conductive film is measured.

以下、本発明の表示装置の構成を図1〜5を基に説明する。
図2は本発明の表示装置を模式的に示す断面図である。図示するように、本発明の表示装置は、上基板8と下基板9の間に液晶層(図示しない)が挟持される。ICチップ1は異方性導電膜5で液晶表示素子の下基板9上に接続される。ICチップ1の接続端子(以下、バンプと称す)6と下基板9上の電極パッド2は、異方性導電膜5に含まれる導電性粒子7により電気的に接続される。
Hereinafter, the configuration of the display device of the present invention will be described with reference to FIGS.
FIG. 2 is a cross-sectional view schematically showing the display device of the present invention. As shown in the drawing, in the display device of the present invention, a liquid crystal layer (not shown) is sandwiched between an upper substrate 8 and a lower substrate 9. The IC chip 1 is connected to the lower substrate 9 of the liquid crystal display element by an anisotropic conductive film 5. Connection terminals (hereinafter referred to as bumps) 6 of the IC chip 1 and the electrode pads 2 on the lower substrate 9 are electrically connected by conductive particles 7 included in the anisotropic conductive film 5.

図1は本発明の表示装置の接続部を、下基板側を通して観察した様子を示す。ICチップ1上のバンプ(電極パッド2に隠れて見えない)に対応する位置に電極パッド2が位置あわせされ、電極パッド2から配線4が引き出される。ICチップ1上の能動面に配線が形成されない配線禁止領域10が設けられる。   FIG. 1 shows a state in which the connection portion of the display device of the present invention is observed through the lower substrate side. The electrode pad 2 is aligned at a position corresponding to the bump on the IC chip 1 (hidden from the electrode pad 2 and cannot be seen), and the wiring 4 is drawn from the electrode pad 2. A wiring prohibited area 10 in which no wiring is formed is provided on the active surface on the IC chip 1.

ここで、図4を用いてICチップ1の構成を説明する。ICチップ1の両端部には下基板の電極パッドに接続されるためのバンプ6が配置される。さらに、中央部には、配線等が形成されない配線禁止領域10が設けられる。   Here, the configuration of the IC chip 1 will be described with reference to FIG. Bumps 6 for connecting to the electrode pads on the lower substrate are arranged at both ends of the IC chip 1. Further, a wiring prohibition region 10 where no wiring or the like is formed is provided at the center.

次に、図5を用いて下基板9の、ICチップ1との接続領域の構成を説明する。下基板9には、ICチップ1のバンプ6と接続される電極パッド2が設置され、この電極パッド2から配線4が引き出される。電極パッド2および配線4は不透明な金属薄膜から形成される。さらに、ICチップが接続された際に、配線禁止領域10と対応する位置に透視領域3が設けられる。この部分は不透明な金属電極が設けられていないため、透明である。   Next, the configuration of the connection region of the lower substrate 9 with the IC chip 1 will be described with reference to FIG. The lower substrate 9 is provided with electrode pads 2 connected to the bumps 6 of the IC chip 1, and the wiring 4 is drawn out from the electrode pads 2. The electrode pad 2 and the wiring 4 are formed from an opaque metal thin film. Further, when the IC chip is connected, the see-through region 3 is provided at a position corresponding to the wiring prohibited region 10. This portion is transparent because an opaque metal electrode is not provided.

図3は図1の一部を拡大した模式図である。ICチップ1上には異方性導電膜5の導電性粒子7が分散されている。下基板9の透視領域3を通してICチップ1上の状態を確認でき、配線禁止領域10上にある導電性粒子7を計数することができる。   FIG. 3 is an enlarged schematic view of a part of FIG. Conductive particles 7 of the anisotropic conductive film 5 are dispersed on the IC chip 1. The state on the IC chip 1 can be confirmed through the transparent region 3 of the lower substrate 9, and the conductive particles 7 on the wiring prohibited region 10 can be counted.

以下、本発明の表示装置および表示装置の製造方法について、実施例を用いて具体的に説明する。   Hereinafter, the display device and the method for manufacturing the display device of the present invention will be specifically described with reference to examples.

本実施例の表示装置の構成を、図2を用いて説明する。本実施例では、液晶表示素子の上基板8と下基板9はそれぞれ0.25mmの厚さのガラス基板から構成される。ICチップ1は20mm×0.8mm×0.28mmの大きさである。異方性導電膜5は下基板9へ貼り付ける時の位置あわせ容易性と部材コストを考慮してICチップ1の大きさより一回り大きいサイズとする。本実施例では22mm×1.2mm×0.02mmの異方性導電膜5を用いる。ICチップのバンプ6の大きさは0.015mm×0.1mmで、その高さは0.012mmである。下基板9の電極パッド2は、ICチップ1と下基板9との位置あわせの容易性を考慮してバンプ6の端部よりそれぞれ0.002mm程度大きくし、0.019mm×0.104mmとする。   The structure of the display device of this embodiment will be described with reference to FIG. In this embodiment, the upper substrate 8 and the lower substrate 9 of the liquid crystal display element are each composed of a glass substrate having a thickness of 0.25 mm. The IC chip 1 has a size of 20 mm × 0.8 mm × 0.28 mm. The anisotropic conductive film 5 is set to a size that is slightly larger than the size of the IC chip 1 in consideration of the ease of alignment when pasted to the lower substrate 9 and the member cost. In this embodiment, an anisotropic conductive film 5 of 22 mm × 1.2 mm × 0.02 mm is used. The size of the bump 6 of the IC chip is 0.015 mm × 0.1 mm, and its height is 0.012 mm. The electrode pads 2 of the lower substrate 9 are about 0.002 mm larger than the end portions of the bumps 6 in consideration of the ease of alignment between the IC chip 1 and the lower substrate 9 to be 0.019 mm × 0.104 mm. .

また、図4に示すようにICチップ1上には配線禁止領域10が設けられる。配線禁止領域10は、パシベーション膜、金属膜、または、ICチップを構成する珪素やガリウム砒素のような半導体膜で形成されてもよい。この大きさは0.01mm×0.01mm〜0.1mm×0.1mmが望ましい。更に望ましくは0.02mm×0.02mm〜0.05mm〜0.05mmがよい。配線禁止領域10が大きいとICチップ1が大きくなりコストが増大する。逆に配線禁止領域10が小さいと導電性粒子7の計数精度が低下する。本実施例では、配線禁止領域10の大きさを0.03mm×0.03mmに設定する。   Further, as shown in FIG. 4, a wiring prohibited area 10 is provided on the IC chip 1. The wiring prohibition region 10 may be formed of a passivation film, a metal film, or a semiconductor film such as silicon or gallium arsenide constituting an IC chip. This size is preferably 0.01 mm × 0.01 mm to 0.1 mm × 0.1 mm. More desirably, 0.02 mm × 0.02 mm to 0.05 mm to 0.05 mm is preferable. If the wiring prohibition area 10 is large, the IC chip 1 becomes large and the cost increases. On the contrary, when the wiring prohibited area 10 is small, the counting accuracy of the conductive particles 7 is lowered. In this embodiment, the size of the wiring prohibited area 10 is set to 0.03 mm × 0.03 mm.

また、図5に示すように液晶表示素子の下基板9上には透視領域3が設けられる。透視領域3は、透明であればよく、ガラスで構成された下基板上に透明電極が形成されてもよい。この透視領域3の大きさはICチップ1と下基板9との位置あわせにズレがおこることを考慮してICチップ上の配線禁止領域10の端部からそれぞれ0.003mm〜0.005mm、合計寸法で0.006mm〜0.01mm程度大きくする。本実施例では、透視領域3の大きさを0.038mm×0.038mmとする。また、異方性導電膜は導電性粒子の平均直径が0.0035mmであって、該導電性粒子の面積密度が1平方mm当り5万個のものを用いる。   Further, as shown in FIG. 5, a see-through region 3 is provided on the lower substrate 9 of the liquid crystal display element. The transparent region 3 may be transparent, and a transparent electrode may be formed on the lower substrate made of glass. The size of the see-through area 3 is 0.003 mm to 0.005 mm from the end of the wiring prohibited area 10 on the IC chip in consideration of the deviation in the alignment between the IC chip 1 and the lower substrate 9. The dimension is increased by about 0.006 mm to 0.01 mm. In the present embodiment, the size of the transparent region 3 is 0.038 mm × 0.038 mm. An anisotropic conductive film having an average diameter of conductive particles of 0.0035 mm and an area density of the conductive particles of 50,000 per square mm is used.

このように配線禁止領域10が設けられたICチップ1が透視領域3を設けた下基板9に異方性導電膜5により接続された構成により、透視領域3を通して配線禁止10上の導電粒子7の計数が可能となる。   As described above, the IC chip 1 provided with the wiring prohibited area 10 is connected to the lower substrate 9 provided with the transparent area 3 by the anisotropic conductive film 5, so that the conductive particles 7 on the wiring prohibited 10 pass through the transparent area 3. Can be counted.

また、本実施例の表示装置の製造方法では、上述のように配線禁止領域10を設けたICチップ1と、透視領域3を設けた下基板9を準備した後、ICチップ1を、異方性導電膜5を用いて下基板9に加熱加圧して接続する。接続後に下基板9側より配線禁止領域10を顕微鏡で観察し、配線禁止領域10内にある導電性粒子7の数を数える。この測定値を、事前に測定されたサンプルの導電粒子個数と導電粒子個数の標準偏差と比較検証することで、異方性導電膜中の導電粒子分布の異常や導電粒子の面積密度の違う異方性導電膜の誤使用を確認できる。なお、本実施例では、平均導電性粒子個数45個で標準偏差は8であった。   Further, in the display device manufacturing method of this embodiment, after preparing the IC chip 1 provided with the wiring prohibited area 10 and the lower substrate 9 provided with the fluoroscopic area 3 as described above, the IC chip 1 is anisotropically prepared. The conductive film 5 is used to connect to the lower substrate 9 by heating and pressing. After the connection, the wiring prohibited area 10 is observed with a microscope from the lower substrate 9 side, and the number of conductive particles 7 in the wiring prohibited area 10 is counted. By comparing and verifying this measured value with the number of conductive particles of the sample measured in advance and the standard deviation of the number of conductive particles, abnormal distribution of conductive particles in the anisotropic conductive film or different density of conductive particles was found. The misuse of the anisotropic conductive film can be confirmed. In this example, the average number of conductive particles was 45 and the standard deviation was 8.

本実施例では、表示装置を構成する部品の大きさが実施例1と異なる。その他の表示装置の基本的な構成は同じである。   In the present embodiment, the sizes of the parts constituting the display device are different from those in the first embodiment. The basic configuration of the other display devices is the same.

本実施例では液晶表示素子の上基板8と下基板9はそれぞれ0.3mmの厚さのガラス基板から構成される。ICチップ1は19.95mm×1.27mm×0.33mmの大きさである。異方性導電膜5は貼り付け時の位置あわせ容易性と部材コストを考慮してICチップ1の大きさより一回り大きいサイズとする。本実施例では22mm×2.0mm×0.02mmの異方性導電膜を用いる。ICチップのバンプ6は0.03mm×0.067mmの大きさでその高さは0.015mmである。下基板9の電極パッド2は、ICチップ1と下基板9との位置あわせの容易性を考慮して前記バンプ6の端部からそれぞれ0.002mm程度大きくし、0.034mm×0.071mmとする。   In this embodiment, the upper substrate 8 and the lower substrate 9 of the liquid crystal display element are each composed of a glass substrate having a thickness of 0.3 mm. The IC chip 1 has a size of 19.95 mm × 1.27 mm × 0.33 mm. The anisotropic conductive film 5 has a size that is slightly larger than the size of the IC chip 1 in consideration of ease of alignment at the time of bonding and member cost. In this embodiment, an anisotropic conductive film of 22 mm × 2.0 mm × 0.02 mm is used. The bump 6 of the IC chip has a size of 0.03 mm × 0.067 mm and a height of 0.015 mm. The electrode pads 2 of the lower substrate 9 are about 0.002 mm larger from the end portions of the bumps 6 in consideration of the ease of alignment between the IC chip 1 and the lower substrate 9, and are 0.034 mm × 0.071 mm. To do.

図4に示すようにICチップ1上には配線禁止領域10が設けられる。配線禁止領域10はパシベーション膜、金属膜、または、ICチップを構成する珪素やガリウム砒素のような半導体膜で形成されてもよい。本実施例では、配線禁止領域10の大きさを0.04mm×0.04mmに設定した。また、図5に示すように液晶表示素子の下基板9上には透視領域3が設けられる。本実施例では、透視領域3の大きさを0.05mm×0.05mmとする。また、異方性導電膜は導電性粒子の平均直径が0.004mmであって、該導電性粒子の面積密度が1平方mm当り3万個のものを用いる。   As shown in FIG. 4, a wiring prohibited area 10 is provided on the IC chip 1. The wiring prohibition region 10 may be formed of a passivation film, a metal film, or a semiconductor film such as silicon or gallium arsenide constituting an IC chip. In this embodiment, the size of the wiring prohibited area 10 is set to 0.04 mm × 0.04 mm. Further, as shown in FIG. 5, a see-through region 3 is provided on the lower substrate 9 of the liquid crystal display element. In this embodiment, the size of the fluoroscopic region 3 is 0.05 mm × 0.05 mm. As the anisotropic conductive film, one having an average diameter of conductive particles of 0.004 mm and an area density of 30,000 particles per square mm is used.

このように配線禁止領域10が設けられたICチップ1が、透視領域3が設けられた下基板9に、異方性導電膜5により接続された構成により、透視領域3を通して配線禁止領域10上の導電粒子7の計数が可能となる。   Thus, the IC chip 1 provided with the wiring prohibited area 10 is connected to the lower substrate 9 provided with the transparent area 3 by the anisotropic conductive film 5, so that the IC chip 1 on the wiring prohibited area 10 passes through the transparent area 3. The conductive particles 7 can be counted.

また、実施例1と同様の製造方法で表示装置を製造し、ICチップ1の接続後に下基板9側より配線禁止領域10を顕微鏡で観察したところ、配線禁止領域10内にある導電性粒子7は平均導電性粒子個数27個で標準偏差は6となった。   Further, when the display device was manufactured by the same manufacturing method as in Example 1 and the wiring prohibited area 10 was observed with a microscope from the lower substrate 9 side after the IC chip 1 was connected, the conductive particles 7 in the wiring prohibited area 10 were observed. The average number of conductive particles was 27 and the standard deviation was 6.

また、上述の各実施例では液晶表示素子を有する表示装置について説明したが、有機EL素子、無機EL素子やプラズマ表示素子を用いた表示装置においても同様の構成と製造方法を用いることができる。   In each of the above-described embodiments, the display device having a liquid crystal display element has been described. However, the same configuration and manufacturing method can be used for a display device using an organic EL element, an inorganic EL element, or a plasma display element.

導電性粒子の数を計数できる構成なので、製造工程での異常発見が容易になる。透明基板を備える表示装置であれば適用できるので、EL素子やプラズマ表示素子を用いた表示装置にも適用できる。画像認識技術と組み合わせることで自動検査を行うこともできる。   Since it is possible to count the number of conductive particles, it is easy to find abnormalities in the manufacturing process. Since it can be applied to any display device including a transparent substrate, it can also be applied to a display device using an EL element or a plasma display element. Automatic inspection can also be performed in combination with image recognition technology.

1 ICチップ
2 電極パッド
3 透視領域
4 配線
5 異方性導電膜(ACF)
6 バンプ
7 導電性粒子
8 上基板
9 下基板
10 配線禁止領域
1 IC chip 2 Electrode pad 3 Transparent region 4 Wiring 5 Anisotropic conductive film (ACF)
6 Bump 7 Conductive particle 8 Upper substrate 9 Lower substrate 10 Wiring prohibited area

Claims (4)

透明基板を有する表示素子と、前記透明基板に異方性導電膜により接続されたICチップとを備える表示装置において、
前記ICチップには配線禁止領域が設けられ、
前記透明基板には前記配線禁止領域に対応して透明な透視領域が設けられ、
前記透視領域を通して前記配線禁止領域の前記異方性導電膜に含まれる導電性粒子が見えることを特徴とする表示装置。
In a display device comprising a display element having a transparent substrate, and an IC chip connected to the transparent substrate by an anisotropic conductive film,
The IC chip is provided with a wiring prohibited area,
The transparent substrate is provided with a transparent see-through area corresponding to the wiring prohibited area,
The display device characterized in that the conductive particles contained in the anisotropic conductive film in the wiring prohibited region can be seen through the see-through region.
前記透視領域が前記配線禁止領域より大きいことを特徴とする請求項1に記載の表示装置。   The display device according to claim 1, wherein the see-through area is larger than the wiring prohibition area. 前記配線禁止領域の大きさが0.01mm四方〜0.1mm四方で、前記透視領域と前記配線禁止領域との寸法の差が0.006mm〜0.01mmであることを特徴とする請求項2に記載の表示装置。   The size of the wiring prohibited area is 0.01 mm square to 0.1 mm square, and a difference in dimension between the see-through area and the wiring prohibited area is 0.006 mm to 0.01 mm. The display device described in 1. 表示素子の透明基板にICチップが異方性導電膜により接続された表示装置の製造方法において、
配線禁止領域が設けられた前記ICチップと、前記配線禁止領域に対応するように透明な透視領域が設けられた前記透明基板とを準備する第一工程と、
前記透明基板に前記ICチップを前記異方性導電膜により接続する第二工程と、
前記透視領域を通して前記配線禁止領域上の前記異方性導電膜の導電性粒子密度を測定する第三工程と、を備えることを特徴とする表示装置の製造方法。
In a manufacturing method of a display device in which an IC chip is connected to a transparent substrate of a display element by an anisotropic conductive film,
A first step of preparing the IC chip provided with a wiring prohibited area and the transparent substrate provided with a transparent see-through area corresponding to the wiring prohibited area;
A second step of connecting the IC chip to the transparent substrate by the anisotropic conductive film;
And a third step of measuring the conductive particle density of the anisotropic conductive film on the wiring prohibited region through the transparent region.
JP2010041065A 2010-02-25 2010-02-25 Display device and method for manufacturing the display device Pending JP2011175215A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108375849A (en) * 2018-04-27 2018-08-07 武汉华星光电技术有限公司 Array substrate and chip bonding method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108375849A (en) * 2018-04-27 2018-08-07 武汉华星光电技术有限公司 Array substrate and chip bonding method
WO2019205487A1 (en) * 2018-04-27 2019-10-31 武汉华星光电技术有限公司 Array substrate and chip binding method
US11101230B2 (en) 2018-04-27 2021-08-24 Wuhan China Star Optoelectronics Technology Co., Ltd. Array substrate and chip bonding method

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