JP2011171642A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control fall or contact of a mask pattern which may occur due to side wall transfer. <P>SOLUTION: A first TEOS oxide film 2, a silicon nitride film 3, a first amorphous silicon film 4, and a second TEOS oxide film 5 are laminatedly formed on a silicon substrate 1. The TEOS oxide film 5 is processed to an intermediate pattern 5a of the first width D1 by patterning based on resist and a core material pattern 5b of the second width D2 is formed by slimming processing thereto. A second amorphous silicon film 6 is formed and processed by spacer processing to form a side wall film 6a, and the core material pattern 5b is removed to obtain an independent mask pattern 6b. Since the same amorphous silicon film 4 is used for foundation, the fall or contact of the mask pattern 6b can be controlled. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having a fine pattern.

  In the photolithography technique which is one of the semiconductor processing techniques, there is a sidewall transfer processing technique as a technique for miniaturizing beyond the minimum width of the optical patterning of the resist film. For example, in the one shown in Patent Document 1, the following process is adopted.

  First, a resist pattern is formed on a thin film that is a film to be processed by a normal lithography process to form a core material pattern having a predetermined pitch. Next, a silicon oxide film is formed with a predetermined film thickness along the upper surface and side surfaces of the core material pattern and the exposed upper surface of the thin film, and the silicon oxide film is processed with a spacer to expose the upper surface of the resist pattern and the upper surface of the thin film, Spacers are formed on the side surfaces of the core material pattern. Thereafter, the core material pattern is removed, and the spacer is left as a mask pattern. This is a technique that enables fine processing with a smaller pitch than the core material pattern by processing a thin film using the obtained mask pattern as a mask.

  However, when the pattern is further miniaturized and the width of the mask pattern is narrowed, the mask pattern is formed while maintaining the film thickness necessary for the etching process, and the adjacent mask patterns are brought into contact with each other. For example, the mask pattern tends to collapse. If the mask patterns are brought into contact with each other or fall to one side, it becomes difficult to realize a desired process and cause a defective etching.

Special table 2008-512002 gazette

  The present invention relates to a method of manufacturing a semiconductor device in which when a fine mask pattern is formed using a sidewall transfer technique, the mask pattern is formed so as not to easily fall down and a film to be processed can be reliably etched. The purpose is to provide.

  According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: sequentially stacking a core material base film and a core material film on a film to be processed; and processing the core material film into a line and space pattern having a first width. Forming an intermediate pattern, slimming the intermediate pattern to form a second width core material pattern that is narrower than the first width, and along the top and side surfaces of the core material pattern and the core Forming a mask film made of the same material as the core material base film and having a predetermined thickness along the upper surface of the core material base film exposed between the material patterns; and spacer processing the mask film Forming a sidewall film on the sidewall of the core material pattern; removing the core material pattern to form a mask pattern made of the sidewall film; and etching the film to be processed using the mask pattern as a mask. Characterized in place sequentially executes the steps of.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a step of sequentially stacking a stopper film, a core material base film, and a core material film on an upper surface of a film to be processed; A step of forming an intermediate pattern by processing into an and-space pattern, a step of slimming the intermediate pattern to form a core material pattern having a second width smaller than the first width, an upper surface of the core material pattern, and Forming a mask film made of the same material as the core material base film with a predetermined film thickness along the side surface and along the upper surface of the core material base film exposed between the core material patterns; Forming a sidewall film on the sidewall of the core material pattern by spacer processing until the stopper film is exposed; removing the core material pattern to form a mask pattern made of the sidewall film; and With etching the core material underlying film and the stopper film disk pattern as a mask, it has a feature wherein at sequentially executing and the step of etching the film to be processed.

  According to the present invention, when a fine mask pattern is formed using the sidewall transfer technique, the mask pattern can be formed so as not to easily collapse.

Schematic longitudinal cross-sectional view of the stage of the manufacturing process which concerns on one Embodiment of this invention (the 1) Schematic longitudinal section of each stage of the manufacturing process (Part 2) Schematic longitudinal section of each stage of the manufacturing process (Part 3) Schematic longitudinal section of each stage of the manufacturing process (Part 4) Schematic longitudinal sectional view at each stage of the manufacturing process according to the comparative example

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 4 in the case where it is applied to a process of forming a line and space pattern such as a NAND flash memory device. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the ratio of the thickness of each layer is different from the actual one.

  1 to 4 show schematic cross-sections in each process corresponding to a series of manufacturing processes throughout the partial diagrams (a) to (h). In this embodiment, a TEOS oxide film formed on a silicon substrate typified by a semiconductor substrate or the like is processed into a fine line and space pattern to form a mask pattern, and each manufacturing process when the silicon substrate 1 is finely processed. The vertical side surface in a process is shown typically.

  First, as shown in FIG. 1A, a first TEOS oxide film 2, a silicon nitride film 3, a first amorphous silicon film 4, and a second TEOS oxide film 5 are formed on a silicon substrate 1 as a base. Laminate. The first TEOS oxide film 2 is formed as a film to be processed, and is formed with a film thickness of, for example, 300 nm. The silicon nitride film 3 functions as a stopper film and is used in a sidewall processing process. The silicon nitride film 3 is formed with a thickness of 50 nm by, for example, a low pressure CVD method. The first amorphous silicon film 4 is formed as a core material base film and is formed with a predetermined film thickness. The second TEOS oxide film 5 is formed as a core material film, and is formed with a film thickness of 200 nm, for example.

  Next, as shown in FIG. 1B, the photoresist is subjected to line-and-space patterning at a pitch of the first width D1 by a normal photolithography technique, and the TEOS oxide film 5 is formed as an RIE (reactive ion) using this as a mask. Etching is performed by an etching method to form an intermediate pattern 5a. The first width D1 can correspond to the minimum width of the limit of optical patterning. Further, overetching is performed in order to reliably process the TEOS oxide film 5, and the concave portion 4a is formed by slightly digging down the first amorphous silicon film 4 as a base. That is, the amorphous silicon film 4 located between the intermediate patterns 5a is formed thinner than the amorphous silicon film 4 located below the intermediate pattern 5a. This is due to the relationship that the selection ratio cannot be infinite by the etching process by the RIE method.

  After that, as shown in FIG. 2C, the intermediate pattern 5a processed as described above is slimmed to form a core material pattern 5b. Here, in order to etch the TEOS oxide film 5 of the intermediate pattern 5a, hydrofluoric acid (HF) treatment is performed as a wet process, so that the width dimension of the intermediate pattern 5a is reduced to the second width D2 (= D1 / 2) which is about half. . Thereby, the distance D3 between the core material patterns 5b becomes the dimension which added the 2nd width D2 to the 1st width D1, in other words, becomes a dimension 3 times the 2nd width D2. Since the wet process isotropically proceeds, the upper surface is etched in addition to the side surface of the intermediate pattern 5a.

  Next, as shown in FIG. 2D, a second amorphous silicon film 6 is formed as a mask film. The second amorphous silicon film 6 is along the upper surface and the side surface of the core material pattern 5b formed by the slimming process, and is along the upper surface of the first amorphous silicon film 4 exposed between the core material patterns 5b. It is formed on the entire surface. At this time, the second amorphous silicon film 6 is formed to have the same thickness as the second width D2, which is the width of the core material pattern 5b.

  Subsequently, as shown in FIG. 3E, the second amorphous silicon film 6 formed as described above is subjected to spacer processing to form a sidewall film 6a on the sidewall of the core material pattern 5b. The spacer processing is performed until the upper surface of the silicon nitride film 3 between the core material patterns 5b is exposed by performing an etch back process by the RIE method. Thereby, sidewall films 6a are formed on both side walls of the core material pattern 5b. The side wall film 6a is formed in a rounded shape while becoming thinner from the lower part to the upper part in the side part opposite to the core material pattern 5b.

  Next, as shown in FIG. 3F, a mask pattern 6b is formed by removing the core material pattern 5b and leaving the sidewall film 6a. Here, the second TEOS oxide film 5 forming the core material pattern 5b is selectively etched and removed by hydrofluoric acid treatment. At this time, when the core material pattern 5b is etched by etching with hydrofluoric acid, the first amorphous silicon film 4 exposed on the bottom surface serves as a stopper to stop the etching. On the side where the core material pattern 5b is not formed, the silicon nitride film 3 serves as a stopper and etching does not proceed.

  When the mask pattern 6b is formed as described above, since the entire base is an amorphous silicon film made of the same material as the mask pattern 6b, the mask pattern 6b generated in the comparative example (see FIG. 5) as will be described later is used. The defect of inclination is eliminated, and the problem that the mask patterns 6b come into contact with each other at the upper end portion to close the pattern opening is eliminated.

  Subsequently, as shown in FIG. 4G, the mask pattern 6a formed by spacer processing of the second amorphous silicon film is used as a mask to expose the core material pattern 5b by RIE. The first amorphous silicon film 4 is etched. In this case, since the mask pattern 6b used as a mask is also formed of the same amorphous silicon film, the etching proceeds simultaneously, but since the film thickness is large with respect to the etching progress direction, the first amorphous silicon film is caused by the film thickness difference. 4 can be removed.

  Thereafter, as shown in FIG. 4H, the silicon nitride film 3 and the first TEOS oxide film 2 are etched by the RIE method using the mask pattern 6b as a mask. Subsequently, the mask pattern 6b and the silicon nitride film 3 are removed to obtain a desired processing pattern 2a for the first TEOS oxide film 2 which is a film to be processed. In this case, the processed pattern 2a is formed in a line-and-space pattern having the same second width D2 as the width dimension of the mask pattern 6b. As a result, it is possible to perform patterning of the second width D2, which is half of the first width D1, which is first patterned by the photolithography technique. Note that the underlying silicon substrate can be etched using the obtained processed pattern 2a as a mask.

  According to the present embodiment as described above, the first amorphous silicon film 4 is formed on the upper surface of the first TEOS oxide film 2 which is a film to be processed via the silicon nitride film 3, so that it is a mask film. Even if the core material pattern 5b is removed after the step of forming the spacer by etching back the second amorphous silicon film 6, the same kind of film is formed as the base of the formed mask pattern 6b. It is possible to prevent the mask pattern 6b from falling and causing contact.

  Further, according to the present embodiment, since the silicon nitride film 3 as the stopper film is formed, the first amorphous silicon film 4 is etched by over-etching at the time of processing the intermediate pattern 5a or the mask pattern 6b. Even when the silicon nitride film 3 disappears and the silicon nitride film 3 is exposed, the wet process for removing the core material pattern 5b may cause the silicon nitride film 3 as a stopper to adversely affect the first TEOS oxide film 2 that is a film to be processed. Absent.

Next, in order to clarify the effect of the above-described embodiment, a comparative example in which occurrence of a defect is predicted will be described with reference to FIG.
FIG. 5A shows the same processing step as in the state of FIG. 2C of the present embodiment. In this comparative example, the processing process proceeds with a configuration in which the core material base film corresponding to the first amorphous silicon film 4 in the present embodiment is not provided. As in the present embodiment, overetching is performed in the step of forming the intermediate pattern 5 a, so that the recess 3 a is formed in the silicon nitride film 3. When the intermediate pattern 5a is slimmed, the core material pattern 5b is obtained.

  Thereafter, as shown in FIG. 5B, an amorphous silicon film 6 is formed as a mask film, and a mask pattern 6a is formed when spacer processing is performed by an etch back process. At this time, a recess 3 b is formed in the silicon nitride film 3.

  Subsequently, as shown in FIG. 5C, when wet processing is performed to remove the core material pattern 5b, the formed mask pattern 6a is formed in an isolated state on the underlying silicon nitride film 3. Will be. In this state, the mask pattern 6a is formed so as to straddle the portion of the recess 3a of the silicon nitride film 3 where there is a step. For this reason, each mask pattern 6a is formed on the silicon nitride film 3 having a different thickness at the lower end, and different stress acts on the mask pattern 6a when the core material pattern 5b is removed. Will do.

  For example, since the silicon nitride film 3 generates contraction stress, the contraction stress is stronger at the thick part, while the amorphous silicon film 6 constituting the mask pattern 6a generates expansion stress. As shown by the arrows, the mask pattern 6a is subjected to different stresses on the left and right. As a result, as shown by the white arrow in the figure, the mask pattern 6a generates stress in a direction in which the portion facing toward the side where the core material pattern 5 is formed contacts, and this causes the mask pattern 6a to collapse and contact. (Indicated by a broken line in FIG. 5C).

  In the present embodiment, the reason for the above is that the same kind of stress is applied to the left and right by using amorphous silicon, which is the same material. As a result, a recess 4a that forms a step is formed in the first amorphous silicon film 4 that is the base. Even when formed in the middle of processing, the mask pattern 6b can be formed without being adversely affected. As a result, the mask pattern 6b can be prevented from falling down and causing contact failure as much as possible. Can be applied.

The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
In addition to the first TEOS oxide film 2, the film to be processed can be a silicon film such as a polycrystalline silicon film or an amorphous silicon film, another silicon oxide film, a silicon nitride film, a carbon film, or the like. A desired processing pattern can be formed by appropriately selecting different materials such as a stopper film, a core material film (core material base film), and a mask film according to the material of the film to be processed.

  The substrate used as the base can be a substrate other than the silicon substrate 1, such as another semiconductor substrate or an insulating substrate, or a conductor film, an insulating film, a semiconductor film, etc. formed on these substrates. It can also be.

  The slimming process of the intermediate pattern 5a obtained by processing the second TEOS oxide film 5 employs a process by a dry process capable of isotropic etching such as a CDE (chemical dry etching) method in addition to the wet process. be able to.

  In the drawings, 1 is a silicon substrate, 2 is a first TEOS oxide film (film to be processed), 3 is a silicon nitride film (stopper film), 4 is a first amorphous silicon film (core underlayer film), and 5 is a first film. 2 is a TEOS oxide film (core material film), 5a is an intermediate pattern, 5b is a core material pattern, 6 is a second amorphous silicon film (mask film), and 6b is a mask pattern.

Claims (5)

A step of sequentially laminating a core material base film and a core material film on the work film;
Processing the core film into a first width line and space pattern to form an intermediate pattern;
A step of slimming the intermediate pattern to form a core material pattern having a second width narrower than the first width;
A mask film made of the same material as the core material base film and having a predetermined film thickness along the upper surface and side surfaces of the core material pattern and along the upper surface of the core material base film exposed between the core material patterns. Forming, and
Forming a sidewall film on the sidewall of the core material pattern by spacer processing the mask film;
Removing the core material pattern and forming a mask pattern made of a sidewall film;
And a step of etching the film to be processed using the mask pattern as a mask. In the manufacturing method of the semiconductor device according to claim 1,
The core material base film has a smaller thickness of the core material base film positioned between the intermediate patterns than the thickness of the core material base film positioned below the intermediate pattern when the intermediate pattern is formed. A method of manufacturing a semiconductor device, characterized by comprising: A step of sequentially laminating a stopper film, a core material base film, and a core material film on the upper surface of the work film;
Processing the core film into a first width line and space pattern to form an intermediate pattern;
A step of slimming the intermediate pattern to form a core material pattern having a second width narrower than the first width;
A mask film made of the same material as the core material base film and having a predetermined film thickness along the upper surface and side surfaces of the core material pattern and along the upper surface of the core material base film exposed between the core material patterns. Forming, and
Forming a sidewall film on the sidewall of the core material pattern by processing the mask film until the stopper film is exposed; and
Removing the core material pattern and forming a mask pattern made of a sidewall film;
Etching the core material base film and the stopper film using the mask pattern as a mask, and sequentially performing a process of etching the film to be processed. In the manufacturing method of the semiconductor device in any one of Claims 1 thru | or 3,
The method of manufacturing a semiconductor device, wherein the core material film and the mask film are formed using different materials from a silicon film, a silicon oxide film, a silicon nitride film, and a carbon film. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the mask film is formed with a film thickness of the same dimension as the second width.

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