JP2011166171A - Solid-state image pickup device, method of driving the same, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup device for reducing a chip area for forming the solid-state image pickup device and reducing the cost of an individual chip, and to provide miniaturized electronic equipment by employing the solid-state image pickup device. <P>SOLUTION: The solid-state image pickup device has a structure in which a first substrate 80 having a photoelectric conversion unit PD and a second substrate 81 having a charge storage capacity unit 61 and a plurality of MOS transistors are laminated. Connection electrodes (26, 27, 56, 57) which are formed at the first substrate 80 and the second substrate 81, respectively, and electrically connect the first substrate 80 and the second substrate 81. By this, the solid-state image pickup device having a global shutter function can be formed in a smaller area. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a CMOS type solid-state imaging device having a global shutter function. The present invention also relates to a method for driving the solid-state imaging device and an electronic apparatus using the solid-state imaging device.

  In recent years, video cameras, electronic still cameras, and the like have been widely used. For these cameras, CCD (Charge Coupled Device) type and amplification type solid-state imaging devices are used. In an amplification type solid-state imaging device, signal charges generated and accumulated in a photoelectric conversion unit of a light receiving pixel are guided to an amplification unit provided in the pixel, and a signal amplified by the amplification unit is output from the pixel. In an amplification type solid-state imaging device, a plurality of such pixels are arranged in a matrix. Examples of the amplification type solid-state imaging device include a solid-state imaging device using a junction field effect transistor for an amplification unit, and a CMOS type solid-state imaging device using a CMOS (Complementary Metal Oxide Semiconductor) transistor for an amplification unit.

  Conventionally, in a general CMOS type solid-state imaging device, a method of sequentially reading out signal charges generated and accumulated in photoelectric conversion units of respective pixels arranged in a two-dimensional matrix for each row has been adopted. In this case, since the exposure timing in the photoelectric conversion unit of each pixel is determined by the start and end of reading of the signal charge, the exposure timing is different for each pixel. For this reason, when imaging a fast-moving subject using such a CMOS solid-state imaging device, there is a problem that the subject is distorted.

  In order to solve the above problems, a simultaneous imaging function (global shutter function) that realizes the same time accumulation of signal charges has been recently proposed, and a CMOS solid-state imaging device having a global shutter function The use of is also increasing.

  In a CMOS type solid-state imaging device having a global shutter function, it is usually necessary to have a storage capacitor portion having a light shielding property in order to store signal charges generated by a photoelectric conversion portion until reading (for example, Patent Document 1). In such a conventional CMOS type solid-state imaging device, after exposing all pixels simultaneously, the signal charges generated in each photoelectric conversion unit are transferred to each storage capacitor unit at the same time, and accumulated once. The signal charges are sequentially converted into pixel signals at a predetermined readout timing.

JP 2004-111590 A

  However, in a conventional CMOS solid-state imaging device having a global shutter function, the photoelectric conversion unit and the storage capacitor unit must be formed on the same plane of the substrate, and an increase in chip area is inevitable. Furthermore, in the market of solid-state imaging devices that are becoming smaller and more pixels year by year, the burden of increasing costs due to an increase in chip area is becoming serious. In addition, when the photoelectric conversion unit and the storage capacitor unit are formed on the same plane of the substrate, there is a problem that the light receiving area of the photoelectric conversion unit is reduced because the area of the substrate is adopted by the storage capacitor unit.

  In view of the above, the present invention provides a solid-state imaging device in which the chip area on which the solid-state imaging device is formed can be reduced and the cost of a single chip can be reduced. In addition, an electronic apparatus that is miniaturized by using the solid-state imaging device is provided.

  In order to solve the above problems and achieve the object of the present invention, a solid-state imaging device of the present invention is a photoelectric conversion unit formed on a first substrate, and generates and accumulates signal charges corresponding to incident light. And a charge storage capacitor unit formed on the second substrate side, the charge storage capacitor unit temporarily holding a signal charge transferred from the photoelectric conversion unit, and formed on the second substrate A plurality of MOS transistors, a plurality of MOS transistors for transferring signal charges stored in the charge storage capacitor section, and a first connection electrode formed on the first substrate And a second connection electrode formed on the second substrate that is electrically connected to the first connection electrode formed on the first substrate, and the charge storage capacitor portion is directly below the second connection electrode. Is formed. In addition, the charge storage capacitor portion includes a two-layer wiring layer including a first connection electrode and a second connection electrode connected to the first connection electrode, a wiring layer formed on the second substrate, and a gap therebetween. The dielectric layer is formed.

  In the solid-state imaging device of the present invention, the first substrate and the second substrate are integrated by electrically connecting the first substrate and the second substrate by the connection electrode. In addition, since the photoelectric conversion unit is formed on the first substrate and the plurality of MOS transistors are formed on the second substrate, a large area of the photoelectric conversion unit formed on the first substrate is ensured. Can do.

  In the solid-state imaging device of the present invention described above, the solid-state imaging device driving method of the present invention resets the signal charge accumulated in the photoelectric conversion unit at the same time for all the pixels, and starts accumulation of the signal charge. The process of ending the exposure period by transferring the signal charge accumulated in the photoelectric conversion unit to the charge storage capacitor unit at the same time for all pixels, and the signal charge accumulated in the charge storage capacitor unit for each pixel A step of sequentially transferring through the transistor.

  An electronic apparatus of the present invention includes an optical lens, the above-described solid-state imaging device of the present invention, and a signal processing circuit that processes an output signal output from the solid-state imaging device.

  According to the present invention, the chip area on which the solid-state imaging device is formed can be reduced, and the cost of a single chip can be reduced. Further, by using the solid-state imaging device of the present invention, an electronic device with a reduced size can be obtained.

1 is a schematic configuration diagram illustrating an entire solid-state imaging device according to a first embodiment of the present invention. 1 is a schematic cross-sectional configuration diagram for one pixel of a solid-state imaging device according to a first embodiment of the present invention. 1A and 1B are schematic cross-sectional configuration diagrams in the middle of manufacturing a solid-state imaging device according to a first embodiment of the present invention. A and B are manufacturing process diagrams of the first connection electrode and the second connection electrode in the first substrate, and manufacturing process diagrams of the first connection electrode and the second connection electrode in the second substrate (part 1). FIGS. 4A and 4B are manufacturing process diagrams of a first connection electrode and a second connection electrode in a first substrate, and manufacturing process diagrams of a first connection electrode and a second connection electrode in a second substrate (part 2). FIGS. FIGS. 3A and 3B are manufacturing process diagrams of a first connection electrode and a second connection electrode in a first substrate, and manufacturing process diagrams of a first connection electrode and a second connection electrode in a second substrate (part 3); FIGS. It is a figure which shows the adhesion method of the 1st connection electrode and 2nd connection electrode in a 1st board | substrate, and the 1st connection electrode and 2nd connection electrode in a 2nd board | substrate. It is a figure which shows the adhesion method of the 1st connection electrode and 2nd connection electrode in a 1st board | substrate, and the 1st connection electrode and 2nd connection electrode in a 2nd board | substrate. 2 is a circuit configuration of one pixel of the solid-state imaging device according to the first embodiment of the present invention. 2 is a circuit configuration of adjacent two rows by two columns and four pixels of the solid-state imaging device according to the first embodiment of the present invention. It is an example of the timing chart which shows the drive method of the solid-state imaging device in the 1st Embodiment of this invention. It is a schematic sectional block diagram of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. It is a schematic block diagram of the electronic device which concerns on the 3rd Embodiment of this invention.

Hereinafter, an example of a solid-state imaging device, a driving method thereof, and an electronic apparatus according to an embodiment of the present invention will be described with reference to FIGS. Embodiments of the present invention will be described in the following order. In addition, this invention is not limited to the following examples.
1. 1. First embodiment: Solid-state imaging device 1.1 Configuration of entire solid-state imaging device 1.2 Configuration of main part 1.3 Manufacturing method of solid-state imaging device 1.4 Circuit configuration of solid-state imaging device 1.5 Solid-state imaging device Driving method 2. 2. Second embodiment: solid-state imaging device Third Embodiment: Electronic Device

<1. First Embodiment: Solid-State Imaging Device>
[1.1 Configuration of the entire solid-state imaging device]
FIG. 1 is a schematic configuration diagram showing an entire solid-state imaging device 1 according to the first embodiment of the present invention.
A solid-state imaging device 1 according to the present embodiment includes a pixel unit 3 including a plurality of pixels 2 arranged on a substrate 11 made of silicon, a vertical drive circuit 4, a column signal processing circuit 5, and a horizontal drive circuit. 6, an output circuit 7, a control circuit 8, and the like.

  The pixel 2 includes a photoelectric conversion unit made of a photodiode, a charge storage capacitor unit, and a plurality of MOS transistors, and a plurality of pixels 2 are regularly arranged on the substrate 11 in a two-dimensional array. The MOS transistor constituting the pixel 2 may be four MOS transistors constituted by a transfer transistor, a reset transistor, a selection transistor, and an amplifier transistor, or may be three MOS transistors excluding the selection transistor. .

  The pixel unit 3 is composed of pixels 2 regularly arranged in a two-dimensional array. The pixel unit 3 amplifies a signal charge actually received by light and amplifies a signal charge generated by photoelectric conversion and reads it to the column signal processing circuit 5 and a black for outputting an optical black serving as a black level reference. And a reference pixel region (not shown). The black reference pixel region is normally formed on the outer periphery of the effective pixel region.

  The control circuit 8 generates a clock signal, a control signal, and the like that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. The clock signal and control signal generated by the control circuit 8 are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by, for example, a shift register, and selectively scans each pixel 2 of the pixel unit 3 in the vertical direction sequentially in units of rows. Then, a pixel signal based on the signal charge generated according to the amount of light received in the photodiode of each pixel 2 is supplied to the column signal processing circuit 5 through the vertical signal line 9.

  The column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and a signal output from the pixels 2 for one row is sent to the black reference pixel region (not shown, but around the effective pixel region) for each pixel column. Signal processing such as noise removal and signal amplification. A horizontal selection switch (not shown) is provided between the output stage of the column signal processing circuit 5 and the horizontal signal line 10.

  The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.

  The output circuit 7 performs signal processing on signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the signals.

[1.2 Structure of main parts]
Next, a schematic configuration of a main part of the solid-state imaging device 1 according to the present embodiment will be described with reference to FIGS. FIG. 2 is a schematic cross-sectional configuration diagram for one pixel of the solid-state imaging device 1 according to the present embodiment. FIGS. 3A and 3B are schematic cross-sectional configuration diagrams in the middle of manufacturing the solid-state imaging device 1 shown in FIG. .

  As shown in FIG. 2, the solid-state imaging device 1 according to the present embodiment includes a first substrate 80 on which a photoelectric conversion unit PD is formed, a second substrate on which a charge storage capacitor unit 61 and a plurality of MOS transistors are formed. And a substrate 81. The first substrate 80 and the second substrate 81 are stacked and bonded together. The first substrate 80 side on which the photoelectric conversion unit PD is formed constitutes a light incident surface on which the light L is incident. On the light incident surface of the first substrate 80, the color filter 59, and An on-chip lens 60 is formed.

  The configuration of the first substrate 80 and the second substrate 81 will be described in detail with reference to FIGS. 3A and 3B.

First, the first substrate 80 will be described.
As shown in FIG. 3A, the first substrate 80 is formed on the photoelectric conversion portion PD, the semiconductor substrate 12 in which the impurity region 16 to be the drain of the first transfer transistor Tr1 is formed, and on the semiconductor substrate 12. The multi-layer wiring layer 17 is also included.

  The semiconductor substrate 12 is formed of an N-type silicon substrate, and a P-type well layer 13 is formed on the semiconductor substrate 12. The P-type well layer 13 can be formed by ion-implanting P-type impurities into the semiconductor substrate 12.

The photoelectric conversion unit PD includes an N-type well layer 14 formed in the P-type well layer 13 and a region in contact with the N-type well layer 14 and a P + -type impurity region formed on the surface side of the P-type well layer 13. 15. The N-type well layer 14 is formed by ion-implanting N-type impurities into a desired region of the P-type well layer 13. The P + -type impurity region 15 is formed by ion-implanting a P-type impurity at a high concentration in a desired region of the P-type well layer 13. In this photoelectric conversion part PD, due to the effect of the pn junction between the P + type impurity region 15 and the N type well layer 14 and the pn junction between the N type well layer 14 and the P type well layer 13, HAD (Hole Accumulation Diode: Registered trademark) structure.
In the photoelectric conversion unit PD having such a configuration, signal charges corresponding to the amount of incident light L are generated, and photoelectric conversion is performed in a depletion layer formed between the P + type impurity region 15 and the N type well layer 14. The signal charge is accumulated.

The impurity region 16 is formed on a surface side of the P-type well layer 13 and is separated from the photoelectric conversion unit PD by a predetermined distance, and temporarily accumulates signal charges transferred from the photoelectric conversion unit PD. It is considered as an area to do. The impurity region 16 is formed by ion-implanting N-type impurities at a high concentration in a desired region of the P-type well layer 13.
In the present embodiment example, a region between the photoelectric conversion unit PD and the impurity region 16 is a channel portion of the first transfer transistor Tr1.

  The multilayer wiring layer 17 is formed on the P-type well layer 13 in which the photoelectric conversion part PD and the impurity region 16 are formed on the semiconductor substrate 12. In the multilayer wiring layer 17, the gate electrode 19 constituting the first transfer transistor Tr1, the first wiring layer M1 formed on the gate electrode 19, and the second wiring layer M2 formed on the first wiring layer M1. Are laminated via an interlayer insulating film 18.

  The gate electrode 19 is formed above the channel portion between the photoelectric conversion portion PD and the impurity region 16 formed in the P-type well layer 13 via a gate insulating film (not shown).

  In the first wiring layer M1, the first connection wiring 23 and the second connection wiring 22 are respectively configured. The first connection wiring 23 is connected to the impurity region 16 through a contact portion 21 formed in the interlayer insulating film 18. Further, the second connection wiring 22 is connected to the gate electrode 19 through a contact portion 20 formed in the interlayer insulating film 18.

  In the second wiring layer M2, the first connection electrode 27 and the second connection electrode 26 are respectively configured, and the first connection electrode 27 and the second connection electrode 26 are exposed on the surface of the multilayer wiring layer 17. ing. The first connection electrode 27 is connected to the first connection wiring 23 formed of the first wiring layer M <b> 1 through the contact portion 24 formed in the interlayer insulating film 18. The second connection electrode 26 is connected to the second connection wiring 22 formed of the first wiring layer M <b> 1 via the contact portion 25 formed in the interlayer insulating film 18.

  In the first substrate 80 having the above configuration, the side opposite to the side on which the first connection electrode 27 and the second connection electrode 26 of the semiconductor substrate 12 are formed is the light incident side. As will be described later, the semiconductor substrate 12 in the first substrate is removed to a predetermined thickness in a later step.

Next, the second substrate 81 will be described.
As shown in FIG. 3B, the second substrate 81 includes a semiconductor substrate 28 on which impurity regions 30, 31, 32, 34, and 35 used as sources and drains of a plurality of MOS transistors are formed, and an upper portion of the semiconductor substrate 28. And a multilayer wiring layer 36 formed in the above. A charge storage capacitor portion 61 is formed in the multilayer wiring layer 36. In the present embodiment, the plurality of MOS transistors formed on the second substrate 81 are the second transfer transistor Tr2, the reset transistor Tr3, the amplification transistor Tr4, and the selection transistor Tr5.

The semiconductor substrate 28 is formed of an N-type silicon substrate, and a P-type well layer 29 is formed on the semiconductor substrate 28. The P-type well layer 29 can be formed by ion-implanting P-type impurities into the semiconductor substrate 28.
The impurity regions 30, 31, 32, 34, and 35 constituting the second transfer transistor Tr2, the reset transistor Tr3, the amplification transistor Tr4, and the selection transistor Tr5 are formed in desired regions on the surface side of the P-type well layer 29, respectively. ing. These impurity regions 30, 31, 32, 34, 35 are formed by ion-implanting N-type impurities at a high concentration in desired regions of the P-type well layer 29.

  The impurity region 30 is a source of the second transfer transistor Tr2. The impurity region 31 is shared by the drain of the second transfer transistor Tr2 and the source of the reset transistor Tr3, and is used as a floating diffusion region from which signal charges are read. The impurity region 32 is shared by the drain of the reset transistor Tr3 and the source of the amplification transistor Tr4. The impurity region 34 is shared by the drain of the amplification transistor Tr4 and the source of the selection transistor Tr5. The impurity region 35 is used as the drain of the selection transistor Tr5. The P-type well layer 29 region between the impurity regions 30, 31, 32, 34, and 35 serves as a channel portion constituting each MOS transistor.

  The multilayer wiring layer 36 is formed on the P-type well layer 29 in which the impurity regions 30, 31, 32, 34, and 35 are formed on the semiconductor substrate 28. In the multilayer wiring layer 36, the gate electrodes 38, 39, 40, and 41, the first wiring layer M1 ′, the second wiring layer M2 ′, and the third wiring layer M3 ′ that constitute each MOS transistor include an interlayer insulating film. 37 are stacked.

  Each gate electrode 38, 39, 40, 41 is formed on a channel part constituting each MOS transistor via a gate insulating film (not shown). The gate electrode 38 formed on the P-type well layer 29 between the impurity region 30 and the impurity region 31 is the gate electrode 38 of the second transfer transistor Tr2. The gate electrode 39 formed on the P-type well layer 29 between the impurity region 31 and the impurity region 32 is used as the gate electrode of the reset transistor Tr3. Further, the gate electrode 40 formed on the P-type well layer 29 between the impurity region 32 and the impurity region 34 is used as the gate electrode of the amplification transistor Tr4. The gate electrode 41 formed on the P-type well layer 29 between the impurity region 34 and the impurity region 35 is a gate electrode of the selection transistor Tr5.

  The first wiring layer M1 ′ is formed on the gate electrodes 38, 39, 40, 41 via the interlayer insulating film 37. In the first wiring layer M1 ′, the first connection wiring 50 and the second connection wiring 49 are formed. The selection wiring 48 and the vertical signal line 9 are configured. The first connection wiring 50 is connected to the impurity region 30 serving as the source of the second transfer transistor Tr <b> 2 via the contact portion 42 formed in the interlayer insulating film 37. The second connection wiring 49 is connected to the impurity region 31 and the gate electrode 40 of the amplification transistor Tr4 via contact portions 43 and 44 formed in the interlayer insulating film 37, respectively. That is, the impurity region 31 that is a floating diffusion region and the gate electrode 40 of the amplification transistor Tr4 are electrically connected by the second connection wiring 49. The selection wiring 48 is connected to the gate electrode 41 of the selection transistor Tr5 through a contact portion 45 formed in the interlayer insulating film 37. A selection pulse is supplied from the selection wiring 48 to the gate electrode 41 of the selection transistor Tr5. The vertical signal line 9 is connected to the impurity region 35 which is the drain of the selection transistor Tr5 through a contact portion 46 formed in the interlayer insulating film 37.

  In the second wiring layer M <b> 2 ′, the third connection wiring 52 and the charge holding electrode 51 are configured. The third connection wiring 52 is connected to the first connection wiring 50 through a contact portion 47 formed in the interlayer insulating film 37. The charge holding electrode 51 is formed extending in a predetermined region. As will be described later, the charge holding electrode 51 is an electrode constituting the charge storage capacitor portion 61. For this reason, the charge holding electrode 51 is formed in a size that can sufficiently obtain the capacitance value of the charge storage capacitor portion 61. The charge holding electrode 51 is connected to a first transfer wiring formed in the multilayer wiring layer 36 of the second substrate 81 (not shown). The charge holding electrode 51 is connected to the charge holding electrode 51 from the first transfer wiring. A first transfer pulse is supplied.

  A dielectric layer 53 is formed on the third connection wiring 52 and the charge holding electrode 51 of the second wiring layer M2 ′, and the third wiring layer M3 ′ is connected to the second wiring via the dielectric layer 53. It is formed on the layer M2 ′. That is, the dielectric layer 53 is configured to be sandwiched between the second wiring layer M2 'and the third wiring layer M3'. As the material of the dielectric layer 53, TaO, HfO, AlO or the like, which is a high dielectric material, can be used.

  In the third wiring layer M3 ′, a first connection electrode 56 and a second connection electrode 57 are configured, and the first connection electrode 56 and the second connection electrode 57 are exposed on the surface of the multilayer wiring layer 36. Has been. The first connection electrode 56 is connected to the third connection wiring 52 including the second wiring layer M2 ′ via the contact portion 55 formed in the dielectric layer 53, and is configured by the second wiring layer M2 ′. Further, it is formed to extend above the charge holding electrode 51. The second connection electrode 57 is connected to the charge holding electrode 51 made of the second wiring layer M <b> 2 ′ via the contact portion 54 formed in the dielectric layer 53. In this embodiment, the charge storage capacitor portion 61 is formed by the charge holding electrode 51 and the first connection electrode 56 formed above the charge holding electrode 51 via the dielectric layer 53.

  Although not shown in FIG. 3B, a second transfer wiring for supplying a second transfer pulse is connected to the gate electrode 38 of the second transfer transistor Tr2. Similarly, a reset wiring for supplying a reset pulse is also connected to the gate electrode 39 of the reset transistor Tr3. These second transfer wiring and reset wiring are formed by a desired wiring layer formed in the multilayer wiring layer 36.

  The solid-state imaging device 1 according to the present embodiment includes the first connection electrodes 56 and 27 and the second connection electrodes 57 and 57 of the first substrate 80 and the second substrate 81 on the second substrate 81. The first substrate 80 is laminated so that the 26 are connected to each other. Then, the first substrate 80 and the second substrate 81 are bonded to each other, whereby the impurity region 16 that constitutes the first transfer transistor Tr1, the charge storage capacitor portion 61, and the impurity region that constitutes the second transfer transistor Tr2. 30 are electrically connected. In the solid-state imaging device 1 of the present embodiment, the photoelectric conversion unit PD and the charge storage capacitor unit 61 are three-dimensionally stacked by stacking and bonding the first substrate 80 and the second substrate 81. The

  In the solid-state imaging device 1 according to the present embodiment, the first connection electrode 56 also serves as a light shielding film, and the impurity region 30 serving as the source of the second transfer transistor Tr2 is shielded by the first connection electrode 56. . For this reason, the incidence of light on the impurity region 30 is suppressed, and the generation of unnecessary signal charges is suppressed, so that color mixing is reduced. In this case, it is preferable that all regions except the opening portion of the photoelectric conversion unit PD are shielded from light.

  Next, a manufacturing method of the solid-state imaging device 1 according to the present embodiment in which the first substrate 80 and the second substrate 81 are stacked and formed will be described.

[1.3 Manufacturing Method of Solid-State Imaging Device]
4A, 5A, and 6A are manufacturing process diagrams of the first connection electrode 27 and the second connection electrode 26 on the first substrate 80. FIGS. 4B, 5B, and 6B are diagrams on the second substrate 81. FIG. FIG. 6 is a manufacturing process diagram of a first connection electrode 56 and a second connection electrode 57. 7 and 8 are diagrams showing a method of bonding the first connection electrodes 27 and 56 and the second connection electrodes 26 and 57 together. Note that the previous step of forming the first connection electrode 27 and the second connection electrode 26 on the first substrate 80 and the first connection electrode 56 and the second connection electrode 57 on the second substrate 81 is a normal solid state. Since it is the same as the manufacturing method of an imaging device, explanation is omitted. 4 to 8, parts corresponding to those in FIGS. 2 and 3 are denoted by the same reference numerals.

As shown in FIG. 4A, after forming the interlayer insulating film 18 covering the first wiring layer M1 on the first substrate 80, the first connection electrode 27 and the second connection electrode 26 made of the second wiring layer M2 are formed. Form. The first connection electrode 27 is formed so as to be connected to the first connection wiring 23 via the contact portion 24, and the second connection electrode 26 is connected to the second connection wiring 22 via the contact portion 25. To form.
Similarly, in the second substrate 81, as shown in FIG. 4B, after the formation of the interlayer insulating film 37 covering the second wiring layer M2 ′, the first connection electrode 56 and the second connection electrode 56 made of the third wiring layer M3 ′ are formed. A connection electrode 57 is formed. The first connection electrode 56 is formed so as to be connected to the third connection wiring 52 via the contact portion 55, and the second connection electrode 57 is connected to the charge holding electrode 51 via the contact portion 54. To form.
In the present embodiment, the first connection electrodes 27 and 56 and the second connection electrodes 26 and 57 are each formed of aluminum.

Thereafter, as shown in FIG. 5A, after the first connection electrode 27 and the second connection electrode 26 made of aluminum are formed on the first substrate 80, the first connection electrode 27 and the second connection electrode 26 are covered. An adhesive agent is applied to form an adhesive layer 18a.
Similarly, as shown in FIG. 5B, after the first connection electrode 56 and the second connection electrode 57 made of aluminum are formed on the second substrate 81, the first connection electrode 56 and the second connection electrode 57 are covered. Thus, an adhesive is applied to form an adhesive layer 37a.
The adhesive layers 18 a and 37 a also serve as the interlayer insulating films 18 and 37.

  6A and 6B, the adhesive layers 18a and 37a are removed by oxygen plasma etching, and the first connection electrodes 27 and 56 and the second connection electrodes 26 of the first substrate 80 and the second substrate 81 are removed. , 57 are exposed. Thereafter, the surface of each electrode is activated by, for example, argon sputtering to form activated layers 18b and 37b.

  After that, as shown in FIG. 7, the activation layer 37 b of the second substrate 81 is pressure-bonded so that the activation layer 18 b of the first substrate 80 is bonded. Then, the activated electrode surfaces are pressure-bonded to each other so that the first substrate 80 and the second substrate 81 are integrated, and the first connection electrode 27, the first connection electrode 56, and the first substrate The two connection electrodes 26 and the second connection electrodes 57 are electrically joined to each other.

  By adhering as described above, the first substrate 80 and the second substrate 81 are integrated and electrically connected.

  After the first substrate 80 and the second substrate 81 are connected, the semiconductor substrate 12 on the light incident side of the first substrate 80 is removed by etching as shown in FIG. Therefore, the thickness is reduced to a necessary thickness (because light is absorbed by the photoelectric conversion portion PD).

  Thereafter, as shown in FIG. 2, a color filter 59, an on-chip lens 60, and the like are sequentially formed on the light incident surface side of the upper portion of the first substrate 80, and the solid-state imaging device 1 of this embodiment is completed. To do. The color filter 59, the on-chip lens 60, and the like are also formed in the same manner as in a normal solid-state imaging device manufacturing method.

[1.4 Circuit configuration of solid-state imaging device]
Next, a driving method of the solid-state imaging device 1 according to the present embodiment will be described with reference to FIG. FIG. 9 shows a circuit configuration for one pixel of the solid-state imaging device 1 of the present embodiment, and FIG. 10 shows a circuit configuration for two adjacent rows and two columns and four pixels.

  The line a in FIG. 9 represents the first connection electrode 27 and the second connection electrode 26 formed on the first substrate 80, and the first connection electrode 56 and the second connection electrode 57 formed on the second substrate 81. This is an electrode connection surface.

  The anode side of the photodiode which is the photoelectric conversion unit PD is grounded, and the cathode side is connected to the source of the first transfer transistor Tr1. Although not shown in FIG. 2, as shown in FIGS. 9 and 10, a photoelectric conversion unit reset transistor Tr6 is formed on the first substrate 80, and the cathode side of the photoelectric conversion unit PD is formed. Is connected to the drain of the photoelectric conversion unit reset transistor Tr6. A power supply voltage wiring 85 for applying a power supply voltage VDD is connected to the source of the photoelectric conversion unit reset transistor Tr6. In addition, a reset wiring 75 for supplying a reset pulse φPDRST is connected to the gate electrode 62 of the photoelectric conversion unit reset transistor Tr6.

  The drain of the first transfer transistor Tr <b> 1 is connected to the source of the second transfer transistor Tr <b> 2 via the first connection electrode 56 that forms the charge storage capacitor portion 61. A first transfer wiring 84 to which a first transfer pulse φTRG1 is supplied is connected to the gate electrode 19 of the first transfer transistor Tr1. The first transfer wiring 84 is connected to the charge holding electrode 51 constituting the charge storage capacitor portion 61.

  The drain of the second transfer transistor Tr2 is connected to the source of the reset transistor Tr3 and to the gate electrode 40 of the amplification transistor Tr4. A second transfer wiring 63 for supplying a second transfer pulse φTRG2 is connected to the gate electrode 38 of the second transfer transistor Tr2.

  A power supply voltage wiring 88 for applying a power supply voltage VDD is connected to the drain of the reset transistor Tr3, and a reset wiring 64 for supplying a reset pulse φRST is connected to the gate electrode 39 of the reset transistor Tr3. .

  A power supply voltage wiring 88 for applying a power supply voltage VDD is connected to the source of the amplification transistor Tr4, and the drain of the amplification transistor Tr4 is connected to the source of the selection transistor Tr5.

  A selection wiring 48 for supplying a selection pulse φSEL is connected to the gate electrode 41 of the selection transistor Tr5, and a drain of the selection transistor Tr5 is connected to the vertical signal line 9.

  As shown in FIG. 10, in the solid-state imaging device 1 in which the pixels 2 are arranged in a two-dimensional matrix, the second transfer wiring 63 and the reset wiring 64 that are common to the gate electrodes 38, 39, and 41 for each row. The selection wiring 48 is connected. The second transfer pulse φTRG2, the reset pulse φRST, and the selection pulse φSEL input to the gate electrodes 38, 39, and 41 are supplied from the vertical drive circuit 4. Although not shown, the vertical drive circuit 4 also supplies a reset pulse φPDRST supplied to the gate electrode 62 of the photoelectric conversion unit reset transistor Tr6 and a first transfer pulse φTRG1 supplied to the gate electrode 19 of the first transfer transistor Tr1. The

A common vertical signal line 9 is connected to the drain of the selection transistor Tr5 for each column.
A column signal processing circuit 5 provided for each column is connected to the subsequent stage of the vertical signal line 9. A horizontal transistor Tr 7 to which a horizontal selection pulse from the horizontal drive circuit 6 is input is connected to the subsequent stage of the column signal processing circuit 5.

[1.5 Driving Method of Solid-State Imaging Device]
Next, a driving method in the solid-state imaging device 1 having the above circuit configuration will be described using the timing chart shown in FIG. 11 and the circuit configuration of FIG.

  First, the reset pulse φPDRST is set to high to simultaneously turn on the photoelectric conversion unit reset transistors Tr6 of all the pixels, thereby resetting the photoelectric conversion units PD of all the pixels to have the same potential as the power supply voltage VDD. That is, by this operation, unnecessary charges stored in the photoelectric conversion units PD of all the pixels are discharged, and the potential of the photoelectric conversion unit PD is reset to a constant value (VDD).

  Next, the reset pulse φPDRST is set to low to simultaneously turn off the photoelectric conversion unit reset transistors Tr6 of all the pixels, and generation and accumulation of signal charges are started in the photoelectric conversion units PD of all the pixels. The signal charge is generated according to the amount of light incident on the photoelectric conversion unit PD, and the generated signal charge is accumulated in a potential well formed by the effect of the pn junction in the photoelectric conversion unit PD. At this time, it is assumed that the signal charges stored in the charge storage capacitor unit 61 are sequentially read at the time of the previous reading and the charge storage capacitor unit 61 is empty, but the charge storage capacitor unit 61 is reset separately. You may provide the timing to do.

  Next, before the predetermined accumulation time elapses after the reset pulse φPDRST is set to low, the first transfer pulse φTRG1 is set to high to turn on the first transfer transistors Tr1 of all the pixels at the same time and accumulate in the photoelectric conversion unit PD. The signal charge is transferred to the impurity region 16. Then, since the impurity region 16, the impurity region 30, and the charge storage capacitor portion 61 are electrically connected, the signal charge is the impurity region 16, the impurity region 30, and the charge storage capacitor formed in the first substrate 80. It is temporarily stored in the unit 61. In addition, while the first transfer pulse φTRG1 is high as described above, the signal charge is mainly stored in the charge storage capacitor portion 61.

  Thereafter, the first transfer pulse φTRG1 is set to low to turn off the first transfer transistors Tr1 of all the pixels, so that the signal charges mainly accumulated in the charge storage capacitor portion 61 are depleted in the impurity regions 16 and 30. Transferred to the layer. As shown in FIG. 11, the time from when the reset pulse φPDRST is set to low until the first transfer pulse φTRG1 is set to low again is the accumulated exposure time (electronic shutter time). Note that when the signal charge is transferred from the photoelectric conversion unit PD to the charge storage capacitor unit 61 by setting the first transfer pulse φTRG1 to high, the potential of the first transfer pulse φTRG1 is the signal charge from the photoelectric conversion unit PD. Use a potential that allows complete transfer.

  Next, the reset pulse φPDRST is set to high to turn on the photoelectric conversion unit reset transistors Tr6 of all the pixels to reset the photoelectric conversion unit PD. As a result, while reading out the signal charge stored in the charge storage capacitor unit 61, the signal charge accumulated in the photoelectric conversion unit PD and exceeding the maximum stored charge amount of the photoelectric conversion unit PD becomes the charge storage capacitor unit 61. Prevent overflowing. Alternatively, the photoelectric conversion unit PD is reset to the same potential as the power supply voltage VDD in preparation for the next signal charge accumulation. While the signal charge is being accumulated in the charge storage capacitor portion 61 and the impurity regions 16 and 30, a potential that forms an inversion layer on the surface of the charge storage capacitor portion 61 is added as the potential of the first transfer pulse φTRG1. May be. Thereby, generation | occurrence | production of a dark current can be suppressed during accumulation | storage of a signal charge.

  Thereafter, the selection pulse φSEL (1) is set to high, the first row selection transistor Tr5 is turned on, and the first row pixel 2 is selected. In a state where the selection pulse φSEL (1) in the first row is set high, the reset pulse φRST (1) is set high, and the reset transistor Tr3 in the first row is turned on. As a result, the potential of the impurity region 31 serving as the floating diffusion region connected to the gate electrode 40 of the amplification transistor Tr4 is reset to the same potential as the power supply voltage VDD. At this time, the reset output of the amplification transistor Tr4 is stored in the column signal processing circuit 5 via the vertical signal line 9.

  Next, the second transfer pulse φTRG2 (1) is set to high to turn on the second transfer transistor Tr2 of the pixel 2 in the first row, and the signal charges in the impurity region 30 and the impurity region 16 of the pixel 2 in the first row. Is transferred to the impurity region 31 which is a floating diffusion region. At this time, the potential of the second transfer pulse φTRG2 (1) is set to a potential at which the signal charge can be completely transferred from the impurity region 30 and the impurity region 16 to the impurity region 31. When the signal charge is read out to the impurity region 31, the potential of the impurity region 31 that is the floating diffusion region changes, and a signal voltage corresponding to the potential change is applied to the gate electrode 40 of the amplification transistor Tr4. Then, the signal voltage amplified by the amplification transistor Tr4 is output to the vertical signal line 9.

  The signal voltage output to the vertical signal line 9 is sent to the column signal processing circuit 5. The column signal processing circuit 5 outputs the difference between the reset output stored earlier and the amplified signal voltage as the pixel signal of the pixel 2 in the first row. The pixel signals of the pixels 2 in the first row are serially output from the output terminal Vout via the output circuit 7 by sequentially turning on the horizontal transistors Tr7 by the horizontal drive circuit 6.

  Thereafter, after the selection pulse φSEL (1) is set to low, the selection pulse φSEL (2) is set to high to turn on the selection transistor Tr5 in the second row and select the pixel 2 in the second row. In the state where the selection pulse φSEL (2) of the selection transistor Tr5 in the second row is set high, the state of the second transfer pulse φTRG2 (2) and the reset pulse φRST (2) is changed to the second transfer pulse φTRG2 ( 1) It is driven in the same manner as the reset pulse φRST (1). As a result, the readout operation similar to that of the first row surface described above is performed for the pixels 2 in the second row.

  As can be seen from the above description, in the solid-state imaging device 1 of this embodiment, the accumulation exposure time for generating and accumulating signal charges in the photoelectric conversion unit PD is performed at the same time for all pixels. The signal charges accumulated at the same time for all the pixels are accumulated and held in the respective charge accumulation capacitors 61, read out to the impurity region 31 in line order, and amplified according to the potential of the signal charges. Is output via the vertical signal line 9.

  According to the solid-state imaging device 1 of the present embodiment example, the conventional solid-state imaging device having a global shutter function and the circuit configuration itself are not significantly changed, but the photoelectric conversion unit PD and the circuit portion are formed on different substrates. Thereby, the opening area of photoelectric conversion part PD can be enlarged. That is, in the present embodiment example, since the entire effective area of the light receiving surface of the first substrate 80 can be used as the photoelectric conversion unit PD, the area of the photoelectric conversion unit PD itself can be secured, The opening area can also be increased. Thereby, the light receiving sensitivity is improved.

In addition, the photoelectric conversion unit PD formed on the first substrate 80 and the plurality of MOS transistors formed on the second substrate 81 are also independent processes in the manufacturing method of the conventional solid-state imaging device 1. Is formed. For this reason, the number of processes obtained by adding the process of forming the first substrate 80 and the process of forming the second substrate 81 of the present embodiment, except for the processes that can be shared by forming all of them on one substrate. Is close to the number of steps in manufacturing a conventional solid-state imaging device. That is, the conventional solid-state imaging device that forms all the elements on one substrate and the solid-state imaging device 1 of the present embodiment that forms necessary elements on the first substrate 80 and the second substrate 81, respectively, The number of manufacturing processes does not change much. On the other hand, in the solid-state imaging device 1 of the present embodiment, the first substrate 80 that forms the photoelectric conversion unit PD and the second substrate 81 that forms the charge storage capacitor unit 61 and a plurality of MOS transistors are separately formed. Therefore, the area of one substrate can be reduced. For this reason, the chip area on which the solid-state imaging device 1 is formed can be reduced, and the number of chips taken from one wafer can be increased.
As described above, in this embodiment, the number of steps is not changed, and the number of chips that can be taken from one wafer can be increased, so that the cost of a single chip can be reduced theoretically.

  Further, in the solid-state imaging device 1 of the present embodiment example, the first substrate 80 and the second substrate 81 are electrically connected, so that the circuit configuration for driving the plurality of MOS transistors is all the second substrate. It is sufficient to form 81, and the circuit is not complicated.

  As described above, according to the solid-state imaging device 1 of the present embodiment, each pixel 2 has the charge storage capacitor portion 61 so that an electronic shutter operation (global shutter operation) can be performed simultaneously for all pixels. it can. In addition, by stacking the charge storage capacitor unit 61 and the photoelectric conversion unit PD in a three-dimensional manner, the maximum light reception sensitivity can be obtained with a small area by utilizing the light reception area of the photoelectric conversion unit PD to the maximum. It becomes possible. Since elements with the same performance can be realized in a much smaller area than conventional solid-state imaging devices, it is possible to reduce the cost of a single chip and at the same time obtain a solid-state imaging device suitable for downsizing electronic equipment such as video equipment .

<2. Second Embodiment: Solid-State Imaging Device>
Next, a solid-state imaging device according to the second embodiment of the present invention will be described. FIG. 12 is a schematic configuration diagram showing an entire solid-state imaging device 90 according to the second embodiment of the present invention.
The solid-state imaging device 90 according to this embodiment is different from the solid-state imaging device 1 according to the first embodiment in the configuration of the charge storage capacitor unit. In addition, since the overall configuration of the solid-state imaging device 90 of the present embodiment is the same as that of FIG. In FIG. 12, parts corresponding to those in FIG.

  As shown in FIG. 12, the second substrate 91 according to the present embodiment includes a semiconductor substrate 78 on which desired impurity regions 31, 32, 33, 34, and 35 and a buried charge storage capacitor portion 74 are formed. , A desired wiring and a multilayer wiring layer 76 on which electrodes are formed. The plurality of MOS transistors formed on the second substrate 91 are a second transfer transistor Tr2, a reset transistor Tr3, an amplification transistor Tr4, and a selection transistor Tr5.

  The semiconductor substrate 78 is formed of an N-type silicon substrate, and a P-type well layer 79 is formed in a region above the semiconductor substrate 78 where the MOS transistor and the charge storage capacitor portion 74 are formed. The P-type well layer 79 can be formed by ion-implanting P-type impurities into the semiconductor substrate 78.

The impurity regions 31, 32, 34, and 35 constituting the second transfer transistor Tr2, the reset transistor Tr3, the amplification transistor Tr4, and the selection transistor Tr5 are formed in desired regions on the P-type well layer surface side, respectively. These impurity regions 31, 32, 34 and 35 are formed by ion-implanting N-type impurities at a high concentration in desired regions of the P-type well layer 79.
The impurity region 31 is used as a floating diffusion region from which signal charges are read, which is shared by the drain of the second transfer transistor Tr2 and the source of the reset transistor Tr3. The impurity region 32 is shared by the drain of the reset transistor Tr3 and the source of the amplification transistor Tr4. The impurity region 34 is shared by the drain of the amplification transistor Tr4 and the source of the selection transistor Tr5. The impurity region 35 is used as the drain of the selection transistor Tr5.

  The charge storage capacitor portion 74 includes a first electrode layer 72, a dielectric layer 71, and a second electrode layer 73 formed in the groove portion 70 of the semiconductor substrate 78. That is, the charge storage capacitor portion 74 of this embodiment example constitutes a trench capacitor.

  The groove portion 70 is formed by opening from the surface of the P-type well layer 79 to a depth reaching the N region of the semiconductor substrate 78. The first electrode layer 72 includes an N-type impurity region formed in contact with the N region of the semiconductor substrate 78 in a region surrounding the peripheral region at the bottom of the groove portion 70. The first electrode layer 72 is formed by ion-implanting N-type impurities at the interface between the P-type well layer 79 and the N region constituting the semiconductor substrate 78. The dielectric layer 71 is formed of a silicon oxide film formed on the inner surface of the groove 70. The second electrode layer 73 is formed of polycrystalline silicon formed so as to fill the groove portion 70 with the dielectric layer 71 interposed therebetween. The polycrystalline silicon constituting the second electrode layer 73 is preferably doped with an N-type impurity. The second electrode layer 73 constituting the charge storage capacitor portion 74 is a channel portion of the second transfer transistor Tr2 formed between the charge storage capacitor portion 74 and the impurity region 31 on the surface side of the semiconductor substrate 78. It is formed so as to be connected to the region to be.

  In the present embodiment, an impurity region 33 is formed by ion-implanting N-type impurities at a high concentration on the surface of the semiconductor substrate 78 other than the region where the P-type well layer 79 is formed. The impurity region 33 and the first electrode layer 72 are electrically connected by an N region having the same potential that forms the semiconductor substrate 78.

  The second electrode layer 73 in the charge storage capacitor portion 74 having such a configuration is used as the source of the second transfer transistor Tr2. A region of the P-type well layer 79 between the charge storage capacitor portion 74 and the impurity regions 31, 32, 34, and 35 is a channel portion of each MOS transistor.

  The multilayer wiring layer 76 is formed on the semiconductor substrate 78. In the multilayer wiring layer 76, the gate electrodes 38, 39, 40, and 41 constituting the MOS transistor, the first wiring layer M1 ′, and the second wiring layer M2 ′ are stacked via the interlayer insulating film 77. ing.

  The gate electrodes 38, 39, 40, and 41 are formed above each channel portion via a gate insulating film (not shown). The gate electrode 38 formed on the P-type well layer 79 between the charge storage capacitor portion 74 and the impurity region 31 serves as the gate electrode of the second transfer transistor Tr2. The gate electrode 39 formed on the P-type well layer 79 between the impurity region 31 and the impurity region 32 is a gate electrode of the reset transistor Tr3. The gate electrode 40 formed on the P-type well layer 79 between the impurity region 32 and the impurity region 34 is a gate electrode of the amplification transistor Tr4. The gate electrode 41 formed on the P-type well layer 79 between the impurity region 34 and the impurity region 35 is a gate electrode of the selection transistor Tr5.

  In the first wiring layer M1 ', a first connection wiring 50, a second connection wiring 49, a selection wiring 48, and a vertical signal line 9 are configured. The first connection wiring 50 is connected to the second electrode layer 73 serving as the source of the second transfer transistor Tr <b> 2 via the contact portion 42 formed in the interlayer insulating film 77. The second connection wiring 49 is connected to the impurity region 31 and the gate electrode 40 of the amplification transistor Tr4 via contact portions 43 and 44 formed in the interlayer insulating film 77, respectively. That is, the impurity region 31 serving as the floating diffusion region and the gate electrode 40 of the amplification transistor Tr4 are electrically connected by the second connection wiring 49. Further, the selection wiring 48 is connected to the gate electrode 41 of the selection transistor Tr5 through a contact portion 45 formed in the interlayer insulating film 77. A selection pulse is supplied to the gate electrode 41 of the selection transistor Tr5 by the selection wiring 48. The vertical signal line 9 is connected to the impurity region 35 which is the drain of the selection transistor Tr5 through a contact portion 46 formed in the interlayer insulating film 77.

  In the second wiring layer M2 ′, a first connection electrode 86 and a second connection electrode 87 are formed, and the first connection electrode 86 and the second connection electrode 87 are exposed on the surface of the multilayer wiring layer 76. Has been. The first connection electrode 86 is connected to the first connection wiring 50 formed of the first wiring layer M <b> 1 ′ via the contact portion 82 formed in the interlayer insulating film 77. Further, the second connection electrode 87 is connected to the impurity region 33 formed in the N region constituting the semiconductor substrate 78 through the contact portion 83 formed in the interlayer insulating film 77. The second connection electrode 87 is connected to the first transfer wiring formed in the multilayer wiring layer 76 of the second substrate 91 (not shown), and the gate of the first transfer transistor Tr1 is connected from the first transfer wiring. A first transfer pulse is supplied to the electrode 19 and the impurity region 33.

  Although not shown in FIG. 12, the second transfer wiring for supplying the second transfer pulse is connected to the gate electrode 38 of the second transfer transistor Tr2. Similarly, a reset wiring for supplying a reset pulse is also connected to the gate electrode 39 of the reset transistor Tr3. These second transfer wiring and reset wiring are formed by a desired wiring layer of a multilayer wiring layer.

  The solid-state imaging device 90 of the present embodiment example has the first connection electrodes 27 and 86 and the second connection electrodes 26 and 87 of the first substrate 80 and the second substrate 91 on the second substrate 91. The first substrates 80 are stacked so that they are connected to each other.

  Also in the solid-state imaging device 90 of the present embodiment example, the first substrate 80 and the second substrate 91 are bonded together by the same method as the solid-state imaging device 1 in the first embodiment. Further, the solid-state imaging device 90 of the present embodiment also has a circuit configuration similar to that of the solid-state imaging device 1 in the first embodiment.

  In the solid-state imaging device 90 of the present embodiment example, the first transfer transistor Tr1 is turned on when the first transfer pulse supplied to the gate electrode 19 of the first transfer transistor Tr1 is set high, and the signal charge is Transferred from the photoelectric conversion unit PD to the impurity region 16. At this time, since the same potential as that of the gate electrode 19 is supplied to the first electrode layer 72 of the second substrate 91, the signal charge is transmitted from the impurity region 16 of the first substrate 80 and the second substrate 91. Is temporarily held by the charge storage capacitor portion 74 formed in the above. At this time, the signal charge is mainly stored in the charge storage capacitor portion 74. Thereafter, each pixel is transferred to the impurity region 31 which is a floating diffusion region and read out for each pixel. Such a driving method is the same as that of the solid-state imaging device 1 in the first embodiment.

  According to the solid-state imaging device 90 of the present embodiment example, by forming the charge storage capacitor portion 74 in the groove portion 70 formed in the semiconductor substrate 78, the wiring layer constituting the charge storage capacitor portion can be reduced. The same effect as the solid-state imaging device 1 in the first embodiment can be obtained.

  In the first embodiment and the second embodiment described above, the charge storage capacitor portion is formed on the second substrate side, but may be formed on the first substrate side. However, for the purpose of increasing the light receiving area, it is preferably formed on the first substrate.

  In the first and second embodiments described above, the present invention is applied to a CMOS type solid-state imaging device in which unit pixels that detect signal charges corresponding to the amount of incident light as physical quantities are arranged in a matrix. Explained with an example. However, the present invention is not limited to application to a CMOS type solid-state imaging device. Further, the present invention is not limited to a column type solid-state imaging device in which column circuits are arranged for each pixel column of a pixel portion in which pixels are formed in a two-dimensional matrix.

  The present invention is not limited to application to a solid-state imaging device that senses the distribution of the amount of incident light of visible light and captures it as an image, but is a solid that captures the distribution of the incident amount of infrared rays, X-rays, or particles as an image. The present invention can also be applied to an imaging device. In a broad sense, the present invention can be applied to all solid-state imaging devices (physical quantity distribution detection devices) such as a fingerprint detection sensor that senses other physical quantity distributions such as pressure and capacitance and captures images as images.

Furthermore, the present invention is not limited to the solid-state imaging device that sequentially scans each unit pixel of the pixel unit in units of rows and reads a pixel signal from each unit pixel. The present invention is also applicable to an XY address type solid-state imaging device that selects an arbitrary pixel in pixel units and reads out signals from the selected pixels in pixel units.
Note that the solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which a pixel portion and a signal processing portion or an optical system are packaged together. Good.

  In addition, the present invention is not limited to application to a solid-state imaging device, but can also be applied to an imaging device. Here, the imaging apparatus refers to a camera system such as a digital still camera or a video camera, or an electronic device having an imaging function such as a mobile phone. Note that the above-described module form mounted on an electronic device, that is, a camera module may be used as an imaging device.

<3. Third Embodiment: Electronic Device>
Next, an electronic apparatus according to a third embodiment of the present invention will be described. FIG. 13 is a schematic configuration diagram of an electronic device 200 according to the third embodiment of the present invention.
An electronic apparatus 200 according to the present embodiment shows an embodiment when the solid-state imaging device 1 according to the first embodiment of the present invention described above is used in an electronic apparatus (camera).

  FIG. 13 shows a schematic cross-sectional configuration of an electronic apparatus 200 according to this embodiment. The electronic device 200 according to the present embodiment is an example of a digital camera capable of taking a still image.

  The electronic apparatus 200 according to the present embodiment includes the solid-state imaging device 1, an optical lens 210, a shutter device 211, a drive circuit 212, and a signal processing circuit 213.

The optical lens 210 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 1. As a result, the signal charge is accumulated in the solid-state imaging device 1 for a certain period.
The shutter device 211 controls a light irradiation period and a light shielding period for the solid-state imaging device 1.
The drive circuit 212 supplies drive signals that control the transfer operation of the solid-state imaging device 1 and the shutter operation of the shutter device 211. Signal transfer of the solid-state imaging device 1 is performed by a drive signal (timing signal) supplied from the drive circuit 212. The signal processing circuit 213 performs various signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  In the electronic device 200 of the present embodiment example, the solid-state imaging device 1 can be miniaturized, and thus the entire electronic device 200 can be downsized. Moreover, since the cost of forming the solid-state imaging device 1 is reduced, the manufacturing cost of the electronic device 200 is also reduced.

  Thus, the electronic device 200 to which the solid-state imaging device 1 can be applied is not limited to a camera, but can be applied to an imaging device such as a digital still camera and a camera module for mobile devices such as a mobile phone.

  In the present embodiment, the solid-state imaging device 1 is configured to be used for an electronic device, but the solid-state imaging device 90 in the second embodiment described above can also be used.

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 2 Pixel 3 Pixel part 4 Vertical drive circuit 5 Column signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control circuit 9 Vertical signal line 10 Horizontal signal line 11 Substrate 12 Semiconductor substrate 13 P type well layer 14 N type well Layer 15 P + type impurity region 16 Impurity region 17 Multilayer wiring layer 18 Interlayer insulating film 18a Adhesive layer 18b Activation layer 19 Gate electrode 22 Second connection wiring 23 First connection wiring 26 Second connection electrode 27 First connection electrode 28 Semiconductor Substrate 29 P-type well layer 30 to 35 Impurity region 36 Multilayer wiring layer 37 Interlayer insulating film 37a Adhesive layer 37b Activation layer 38 to 41 Gate electrode 48 Selection wiring 49 Second connection wiring 50 First connection wiring 51 Charge holding electrode 52 third connection wiring 53 dielectric layer 56 first connection electrode 57 second connection electrode 59 color filter 0 the on-chip lens 61 charge accumulation capacitor section 80 first substrate 81 second substrate

Claims (15)

A photoelectric conversion unit formed on the first substrate, which generates and stores a signal charge corresponding to incident light, and a charge storage capacitor unit formed on the second substrate side, A charge storage capacitor unit that temporarily holds signal charges transferred from the photoelectric conversion unit; and a plurality of MOS transistors formed on the second substrate, the signal charges stored in the charge storage capacitor unit A plurality of pixels having a plurality of MOS transistors for transferring
A first connection electrode formed on the first substrate;
A second connection electrode formed on the second substrate electrically connected to the first connection electrode formed on the first substrate;
Including
The charge storage capacitor portion is formed immediately below the second connection electrode;
The charge storage capacitor section includes two wiring layers including the first connection electrode and the second connection electrode connected to the first connection electrode, a wiring layer formed on the second substrate, A solid-state imaging device composed of a dielectric layer formed therebetween. In the photoelectric conversion unit, accumulation of signal charges is started at the same time for all pixels, and the exposure period is completed by transferring the signal charges accumulated in the photoelectric conversion unit to the charge storage capacitor unit at the same time for all pixels. Has a global shutter function to be terminated,
The solid-state imaging device according to claim 1, wherein signal charges stored in the charge storage capacitor portion are sequentially transferred via the plurality of MOS transistors for each pixel. The solid-state imaging device according to claim 2, wherein the dielectric layer is made of any one of TaO, HfO, and AlO. A first transfer transistor formed on the first substrate and transferring signal charges accumulated in the photoelectric conversion unit to the charge storage capacitor unit;
A plurality of MOS transistors including a second transfer transistor that is formed on the second substrate and that reads out the signal charges accumulated in the charge storage capacitor portion;
The solid-state imaging device according to claim 3, wherein the first connection electrode also serves as a light-shielding film for shielding light from a region serving as a source of the second transfer transistor. The electrical connection between the first connection electrode formed on the first substrate and the second connection electrode formed on the second substrate is such that the first substrate is on the light incident side. The solid-state imaging device according to claim 4, wherein the first substrate and the second substrate are bonded to each other. The first substrate includes a first transfer transistor that transfers signal charges generated and accumulated in a photoelectric conversion unit to the charge storage capacitor unit,
The second substrate includes a second transfer transistor that transfers the signal charge stored in the charge storage capacitor portion to a floating diffusion region,
The solid-state imaging device according to claim 5, wherein a drain of the first transfer transistor, the charge storage capacitor unit, and a source of the second transfer transistor are electrically connected. A photoelectric conversion unit formed on the first substrate, which generates and stores a signal charge corresponding to incident light, and a charge storage capacitor unit formed on the second substrate side, A charge storage capacitor unit for storing signal charges transferred from the photoelectric conversion unit; and a plurality of MOS transistors formed on the second substrate, wherein the signal charges stored in the charge storage capacitor unit are transferred. A plurality of pixels having a plurality of MOS transistors, and
A first connection electrode formed on the first substrate;
A second connection electrode formed on the second substrate that is electrically connected to a first connection electrode formed on the first substrate;
The charge storage capacitor portion is formed immediately below the second connection electrode;
The charge storage capacitor section includes two wiring layers including the first connection electrode and the second connection electrode connected to the first connection electrode, a wiring layer formed on the second substrate, In a solid-state imaging device composed of a dielectric layer formed in the meantime,
Resetting the signal charges accumulated in the photoelectric conversion unit at the same time for all the pixels, and starting accumulation of signal charges;
A step of ending an exposure period by transferring signal charges accumulated in the photoelectric conversion unit to the charge storage capacitor unit at the same time for all pixels;
A step of sequentially transferring signal charges accumulated in the charge accumulating capacity unit for each pixel through the plurality of MOS transistors;
A method for driving a solid-state imaging device including: The first substrate includes a first transfer transistor that transfers signal charges generated and accumulated in a photoelectric conversion unit to the charge storage capacitor unit,
The second substrate includes a second transfer transistor that transfers the signal charge stored in the charge storage capacitor portion to a floating diffusion region,
The drain of the first transfer transistor, the charge storage capacitor portion, and the source of the second transfer transistor are electrically connected,
At the end of the exposure period, by turning on the first transfer transistor, the signal charge accumulated in the photoelectric conversion unit is transferred to the charge storage capacitor unit,
8. The signal charge transfer for each pixel transfers the signal charge stored in the charge storage capacitor portion to the impurity region of the second substrate by turning on the second transfer transistor. 9. A driving method of a solid-state imaging device. 9. The solid-state imaging device according to claim 8, wherein in the transfer of the signal charge for each pixel, the signal charge in the floating diffusion region is reset and the reset signal of the floating diffusion region is acquired before the second transfer transistor is turned on. Driving method. An optical lens,
A photoelectric conversion unit formed on the first substrate, which generates and stores a signal charge corresponding to incident light, and a charge storage capacitor unit formed on the second substrate side, A charge storage capacitor unit that temporarily holds signal charges transferred from the photoelectric conversion unit; and a plurality of MOS transistors formed on the second substrate, the signal charges stored in the charge storage capacitor unit A plurality of pixels having a plurality of MOS transistors for transferring
A first connection electrode formed on the first substrate;
A second connection electrode formed on the second substrate electrically connected to the first connection electrode formed on the first substrate;
Including
The charge storage capacitor portion is formed immediately below the second connection electrode;
The charge storage capacitor section includes two wiring layers including the first connection electrode and the second connection electrode connected to the first connection electrode, a wiring layer formed on the second substrate, A solid-state imaging device composed of a dielectric layer formed therebetween;
A signal processing circuit for processing an output signal output from the solid-state imaging device;
Including electronic equipment. In the photoelectric conversion unit, accumulation of signal charges is started at the same time for all pixels, and the exposure period is completed by transferring the signal charges accumulated in the photoelectric conversion unit to the charge storage capacitor unit at the same time for all pixels. Has a global shutter function to be terminated,
The electronic device according to claim 10, wherein the signal charges stored in the charge storage capacitor portion are sequentially transferred via the plurality of MOS transistors for each pixel. The electronic device according to claim 11, wherein the dielectric layer is made of any one of TaO, HfO, and AlO. A first transfer transistor formed on the first substrate and transferring signal charges accumulated in the photoelectric conversion unit to the charge storage capacitor unit;
A plurality of MOS transistors including a second transfer transistor that is formed on the second substrate and that reads out the signal charges accumulated in the charge storage capacitor portion;
The electronic apparatus according to claim 12, wherein the first connection electrode also serves as a light shielding film for shielding light from a region serving as a source of the second transfer transistor. The electrical connection between the first connection electrode formed on the first substrate and the second connection electrode formed on the second substrate is such that the first substrate is on the light incident side. The electronic device according to claim 13, wherein the electronic device is formed by bonding a first substrate and the second substrate. The first substrate includes a first transfer transistor that transfers signal charges generated and accumulated in a photoelectric conversion unit to the charge storage capacitor unit,
The second substrate includes a second transfer transistor that transfers the signal charge stored in the charge storage capacitor portion to a floating diffusion region,
The electronic device according to claim 14, wherein a drain of the first transfer transistor, the charge storage capacitor unit, and a source of the second transfer transistor are electrically connected.

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