JP2011165280A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a desired discharge performance regarding a bit line regardless of a cell size in a nonvolatile semiconductor memory. <P>SOLUTION: The nonvolatile semiconductor memory includes a cell transistor, a cell bit line connected to the cell transistor, a pre-charge circuit leading to the cell bit line, a lead transistor, and a sense amplifier leading to a read bit line. The gate, drain, and source lines of the lead transistor are respectively connected to the cell bit line, the read bit line, and a grounding conductor. In pre-charge period, the pre-charge circuit pre-charges the cell bit line, and the sense amplifier pre-charges the read bit line. In a subsequent sampling period, the cell transistor is turned ON or OFF according to storage data. The sense amplifier senses the storage data by comparing a potential or current of the read bit line with a reference level. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory. In particular, the present invention relates to a technique for reading data from a nonvolatile semiconductor memory.

  Nonvolatile semiconductor memories such as flash memory and EEPROM (Electrically Erasable and Programmable Read Only Memory) are known. A cell transistor used as a memory cell in such a nonvolatile semiconductor memory has a stacked structure of a control gate and a charge storage layer (floating gate). When electrons are injected into the charge storage layer, the threshold voltage of the cell transistor increases, and when electrons are extracted from the charge storage layer, the threshold voltage of the cell transistor decreases. Such a magnitude of the threshold voltage is associated with the stored data “1” and “0”.

  When reading data, a predetermined read potential is applied to the control gate of the cell transistor. At this time, a cell transistor having a relatively low threshold voltage (hereinafter referred to as “ON cell”) is turned on, while a cell transistor having a relatively high threshold voltage (hereinafter referred to as “OFF cell”) is Turn off. By detecting ON / OFF of such a cell transistor, the stored data stored in the cell transistor (memory cell) can be read.

  According to the technique described in Patent Document 1 (Japanese Patent Laid-Open No. 2003-217287), determination of an ON cell and an OFF cell is performed as follows. First, the bit line connected to the cell transistor is precharged to a predetermined precharge potential. Next, a predetermined read potential is applied to the gate of the cell transistor. In the case of an ON cell, a cell current flows through the ON cell, and the bit line is discharged through the ON cell. As a result, the potential of the bit line is lowered from the precharge potential. On the other hand, in the case of the OFF cell, the cell current does not flow and the bit line is not discharged. Therefore, the potential of the bit line is maintained at the precharge potential. The sense amplifier can determine whether the cell transistor is an ON cell or an OFF cell, that is, stored data, by comparing the potential of the bit line with a reference potential.

JP 2003-217287 A

  In recent years, in order to realize high-speed operation and large capacity of a memory, the size of a memory cell is becoming smaller and smaller. However, as the memory cell becomes smaller, the amount of cell current that can flow through the ON cell also decreases. That is, the discharge speed of the bit line passing through the ON cell is lowered. This leads to an increase in time required for data determination, that is, a decrease in data reading speed. In addition, if the data determination timing is too early, an erroneous determination occurs.

  In one aspect of the present invention, a nonvolatile semiconductor memory includes a cell transistor that functions as a memory cell, a cell bit line connected to the drain or source of the cell transistor, a precharge circuit connected to the cell bit line, a read transistor, And a sense amplifier connected to the read bit line. The gate of the read transistor is connected to the cell bit line, the drain is connected to the read bit line, and the source is grounded. During the precharge period, the precharge circuit precharges the cell bit line, and the sense amplifier precharges the read bit line. In the sampling period after the precharge period, the cell transistor is turned on or off according to the stored data. The sense amplifier senses stored data by comparing the potential or current of the read bit line with a reference level.

  In another aspect of the present invention, a nonvolatile semiconductor memory senses storage data stored in a memory cell by comparing a cell transistor functioning as a memory cell with a potential or current of a bit line and a reference level. And a discharge circuit interposed between the cell transistor and the bit line and configured to discharge the bit line. During the precharge period, the sense amplifier precharges the bit line. In the sampling period after the precharge period, the cell transistor is turned on or off according to the stored data. The discharge circuit discharges only when the cell transistor is turned on or off.

  According to the present invention, the discharge of the bit line connected to the sense amplifier is performed by means different from the ON cell. Therefore, a desired discharge capability can be realized regardless of the size of the memory cell. In other words, the size of the memory cell can be reduced without affecting the data reading. Therefore, both reduction in area and improvement in data reading speed can be achieved.

FIG. 1 is a block diagram schematically showing a configuration of a nonvolatile semiconductor memory according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration example of the nonvolatile semiconductor memory according to the present embodiment. FIG. 3 is a timing chart showing a data read operation of the nonvolatile semiconductor memory according to the present embodiment. FIG. 4 is a circuit diagram showing another configuration example of the nonvolatile semiconductor memory according to the present embodiment. FIG. 5 is a conceptual diagram showing temperature characteristics in the present embodiment. FIG. 6 is a conceptual diagram showing temperature characteristics in a comparative example.

  A nonvolatile semiconductor memory according to an embodiment of the present invention will be described with reference to the accompanying drawings. Examples of the nonvolatile semiconductor memory according to the present embodiment include a flash memory and an EEPROM.

1. Overview FIG. 1 is a block diagram schematically showing a configuration of a nonvolatile semiconductor memory according to the present embodiment. The nonvolatile semiconductor memory includes a cell array 10, a sense amplifier 20, a Y selector 30, a precharge circuit 40, a discharge circuit 50, a reference generation circuit 60, a word line WL, a cell bit line BL-C, and a read bit line BL-R. ing.

  The cell array 10 includes a plurality of memory cells 11 arranged in an array. Each memory cell 11 is a cell transistor 11 having a stacked structure of a control gate and a charge storage layer (floating gate). When electrons are injected into the charge storage layer, the threshold voltage of the cell transistor 11 increases, and when electrons are extracted from the charge storage layer, the threshold voltage of the cell transistor 11 decreases. Such a magnitude of the threshold voltage is associated with the stored data “1” and “0”. The cell transistor 11 having a relatively low threshold voltage is an ON cell, and the cell transistor 11 having a relatively high threshold voltage is an OFF cell.

  Each cell transistor 11 is connected to one word line WL and one cell bit line BL-C. More specifically, the control gate of the cell transistor 11 is connected to the word line WL, and its drain or source is connected to the cell bit line BL-C.

  As shown in FIG. 1, according to the present embodiment, one discharge circuit 50, one read bit line BL-R, and one sense are applied to one cell bit line BL-C. An amplifier 20 is provided. The cell bit line BL-C and the read bit line BL-R are separate bit lines and are electrically separated. The discharge circuit 50 is interposed between the cell bit line BL-C and the read bit line BL-R, and has a function of controlling the potential of the read bit line BL-R according to the potential of the cell bit line BL-C. Have. The sense amplifier 20 is connected to the corresponding read bit line BL-R via the Y selector 30.

  The data read operation in the nonvolatile semiconductor memory according to the present embodiment is as follows. At the time of data read, a predetermined read potential is applied to the selected word line WL, and the read potential is applied to the control gate of the selected cell transistor 11 (selected cell) connected to the selected word line WL. At this time, the selected cell transistor 11 is turned ON or OFF depending on the stored data, that is, the threshold voltage. Specifically, an ON cell having a relatively low threshold voltage is turned ON, and a cell current flows through the selected cell bit line BL-C connected to the ON cell. On the other hand, the OFF cell having a relatively high threshold voltage is turned OFF, and the cell current hardly flows through the selected cell bit line BL-C connected to the OFF cell.

  The data reading period is divided into a precharge period and a sampling period following the precharge period.

  First, in the precharge period, the precharge circuit 40 connected to the selected cell bit line BL-C precharges the selected cell bit line BL-C to a predetermined precharge potential. The Y selector 30 electrically connects the selected read bit line BL-R designated by the select signal YSEL to the corresponding sense amplifier 20. The sense amplifier 20 precharges the selected read bit line BL-R to a predetermined precharge potential.

  Subsequently, in the sampling period, the precharge of the cell bit line BL-C by the precharge circuit 40 is stopped. The potential change of the selected cell bit line BL-C during the sampling period changes depending on whether the selected cell transistor 11 connected to the selected cell bit line BL-C is an ON cell or an OFF cell. In the case of an ON cell, a cell current flows through the ON cell and the selected cell bit line BL-C, and the selected cell bit line BL-C is discharged through the ON cell. As a result, the potential of the selected cell bit line BL-C falls from the precharge potential. On the other hand, in the case of an OFF cell, no cell current flows and the selected cell bit line BL-C is not discharged. Therefore, the potential of the selected cell bit line BL-C is maintained at the precharge potential.

  A discharge circuit 50 interposed between the selected cell bit line BL-C and the selected read bit line BL-R discharges the selected read bit line BL-R according to the state of the selected cell bit line BL-C. For example, when the potential of the selected cell bit line BL-C is a precharge potential, the discharge circuit 50 discharges the selected read bit line BL-R. In this case, the potential of the selected read bit line BL-R is lowered from the precharge potential. On the other hand, when the selected cell bit line BL-C is discharged, the discharge circuit 50 does not discharge the selected read bit line BL-R. In this case, the potential of the selected read bit line BL-R is maintained at the precharge potential. This correspondence may be reversed.

  In any case, the discharge circuit 50 discharges the selected read bit line BL-R only when the selected cell transistor 11 is either an ON cell or an OFF cell. The state (potential, current) of the selected read bit line BL-R reflects the state (potential, current) of the selected cell bit line BL-C, that is, the data stored in the selected cell transistor 11.

  The sense amplifier 20 senses (determines) the storage data stored in the selected cell transistor 11 based on the state (potential, current) of the selected read bit line BL-R. More specifically, the sense amplifier 20 is connected to the reference generation circuit 60 and receives a reference level REF (reference potential or reference current) generated by the reference generation circuit 60. The sense amplifier 20 compares the potential or current of the selected read bit line BL-R with its reference level REF, thereby sensing the data stored in the selected cell transistor 11. The sense amplifier 20 outputs the sensed storage data as output data OUT.

  According to the present embodiment, the discharge of the read bit line BL-R connected to the sense amplifier 20 is performed by the discharge circuit 50 different from the ON cell. Therefore, a desired discharge capability can be realized regardless of the size of the cell transistor 11. In other words, the size of the cell transistor 11 can be reduced without affecting data reading. This greatly contributes to high speed operation and large capacity of the memory.

  The bit line discharge capability of the discharge circuit 50 is designed to achieve a desired read speed. Preferably, the reduction of the cell transistor 11 reduces the bit line discharge capability of the cell transistor 11 (ON cell), but the bit line discharge capability of the discharge circuit 50 is sufficiently higher than the bit line discharge capability of the cell transistor 11. Designed to be As a result, both reduction of the area and improvement of the data reading speed can be achieved.

2. Circuit Configuration Example FIG. 2 is a circuit diagram showing a configuration example of the nonvolatile semiconductor memory according to the present embodiment.

  The cell transistor 11 is an N-channel transistor having a control gate and a charge storage layer (floating gate). The control gate of the cell transistor 11 is connected to the word line WL. The drain of the cell transistor 11 is connected to the cell bit line BL-C, and its source is connected to the ground line. The gate width (channel width) of the cell transistor 11 is W11.

  The precharge circuit 40 includes a precharge transistor 41. The precharge transistor 41 is a P-channel transistor having a single-layer gate structure. A precharge signal PRE for controlling the precharge operation is input to the gate of the precharge transistor 41. The drain of the precharge transistor 41 is connected to the cell bit line BL-C, and its source is connected to the power supply line. The gate width (channel width) of the precharge transistor 41 is W41. The gate width W41 of the precharge transistor 41 is larger than the gate width W11 of the cell transistor 11 (W41> W11).

  The discharge circuit 50 includes a read transistor 51. The read transistor 51 is an N-channel transistor having a single layer gate structure. The gate of the read transistor 51 is connected to the cell bit line BL-C. The drain of the read transistor 51 is connected to the read bit line BL-R, and its source is connected to the ground line. The gate width (channel width) of the read transistor 51 is W51. The gate width W51 of the read transistor 51 is sufficiently larger than the gate width W11 of the cell transistor 11 (W51 >> W11). As a result, the bit line discharge capability of the discharge circuit 50 is sufficiently higher than the bit line discharge capability of the cell transistor 11.

  FIG. 3 is a timing chart showing a data read operation. The data read operation in this example will be described with reference to FIGS.

  In the precharge period TP from time t0 to t1, the precharge signal PRE is at a low level. As a result, the precharge transistor 41 of the precharge circuit 40 is turned on, and the cell bit line BL-C is precharged to High level. A predetermined read potential is applied to the word line WL. The cell transistor 11 is turned on in the case of an ON cell and turned off in the case of an OFF cell. Note that the gate width W41 of the precharge transistor 41 is larger than the gate width W11 of the cell transistor 11, and the precharge of the cell bit line BL-C by the precharge transistor 41 is more than the discharge of the cell bit line BL-C by the ON cell. I'm winning.

  Further, the select signal YSEL becomes High level, and the sense amplifier 20 and the read bit line BL-R are electrically connected. The sense amplifier 20 precharges the read bit line BL-R to High level.

  In the sampling period TS from time t1 to t2, the precharge signal PRE becomes High level. As a result, the precharge transistor 41 is turned off, and the precharge of the cell bit line BL-C by the precharge circuit 40 is stopped.

  When the cell transistor 11 is an ON cell, the operation is as follows. That is, a cell current flows through the cell transistor 11 and the cell bit line BL-C, and the cell bit line BL-C is discharged through the ON cell. As a result, the potential of the cell bit line BL-C is lowered to the low level. In this case, the read transistor 51 of the discharge circuit 50 is turned off. Therefore, the read bit line BL-R is not discharged, and the potential of the read bit line BL-R is maintained at the high level. The sense amplifier 20 compares the potential or current of the read bit line BL-R with the reference level REF and outputs high level output data OUT.

  On the other hand, when the cell transistor 11 is an OFF cell, the operation is as follows. That is, the cell bit line BL-C is not discharged, and the potential of the cell bit line BL-C is maintained at the high level. Accordingly, the read transistor 51 of the discharge circuit 50 is turned on. In this case, a large discharge current flows through the read transistor 51 and the read bit line BL-R, and the read bit line BL-R is rapidly discharged through the read transistor 51. As a result, the potential of the read bit line BL-R falls to the low level. The sense amplifier 20 compares the potential or current of the read bit line BL-R with the reference level REF and outputs Low level output data OUT.

  Thus, according to the present embodiment, the read bit line BL-R connected to the sense amplifier 20 is discharged by using the read transistor 51 instead of the cell transistor 11 (ON cell). Even when the size of the cell transistor 11 is reduced, the desired discharge capability can be realized by using the read transistor 51. In particular, a sufficient discharge capability can be obtained by designing the gate width W51 of the read transistor 51 to be sufficiently larger than the gate width W11 of the cell transistor 11. Thereby, the data reading speed of the sense amplifier 20 is improved.

  Note that only one read transistor 51 is required for one sense amplifier 20. The area increase due to the addition of one read transistor 51 is much smaller than the area reduction due to the reduction of all the cell transistors 11 connected to the read transistor 51.

3. Reference Generation Circuit FIG. 4 shows a configuration example of the reference generation circuit 60 that generates the reference level REF. The reference generation circuit 60 includes a reference transistor 61 and a gate voltage generation circuit 62. The reference transistor 61 is an N-channel transistor having a single layer gate structure. It should be noted that this structure is the same structure as the read transistor 51 described above. The gate of the reference transistor 61 is connected to the gate voltage generation circuit 62. The drain of the reference transistor 61 is connected to the sense amplifier 20, and its source is connected to the ground line.

  The gate voltage generation circuit 62 generates a predetermined gate voltage by resistance voltage division and applies the gate voltage to the gate of the reference transistor 61. The reference transistor 61 generates a reference level REF corresponding to the gate voltage. The gate voltage is appropriately designed so that the generated reference level REF is between the ON cell level and the OFF cell level.

  As a comparative example, consider a case where the reference transistor 61 has the same structure as the cell transistor 11, that is, a stacked structure of a control gate and a charge storage layer (floating gate). In this case, the following problem occurs. When charge enters and exits the charge storage layer, the generated reference level REF changes. This leads to deterioration of read characteristics and reliability. In order to prevent such a change in the reference level REF, it is conceivable to short-circuit the control gate and the charge storage layer. However, in this case, the manufacturing process becomes complicated and the manufacturing cost increases.

  According to the present embodiment, the reference transistor 61 has the same single-layer gate structure as that of the read transistor 51 described above. Therefore, all the problems described in the comparative example are eliminated. Typically, the reference transistor 61 is manufactured by the same process as the read transistor 51. As a result, the material, composition, film thickness, impurity concentration, and the like are the same between the read transistor 51 and the reference transistor 61. However, the size such as the gate width may be different.

  For this reason, in the present embodiment, the read transistor 51 and the reference transistor 61 have the same temperature characteristics. FIG. 5 conceptually shows the temperature characteristics in the present embodiment. Ion represents a bit current flowing through the read transistor 51 and the read bit line BL-R in the case of an ON cell. Ioff represents a bit current flowing through the read transistor 51 and the read bit line BL-R in the case of an OFF cell. Iref represents a reference current generated by the reference transistor 61. Since the read transistor 51 and the reference transistor 61 have the same temperature characteristics, the bit currents Ion and Ioff and the reference current Iref also have the same temperature characteristics.

  FIG. 6 shows a case where the temperature characteristics of the read transistor 51 and the reference transistor 61 are different as a comparative example. In order to guarantee a normal data read operation, the relationship of “Ioff> Iref, Ion <Iref” must always be satisfied within the operation range. Therefore, when the temperature characteristics are different, a large margin is required as shown in FIG. Such a large margin leads to an unreasonable increase in current value and power consumption. On the other hand, the present embodiment is preferable because the temperature characteristics coincide with each other, and a useless margin is omitted as shown in FIG.

  The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the above-described embodiments, and can be appropriately changed by those skilled in the art without departing from the scope of the invention.

10 cell array 11 cell transistor (memory cell)
20 sense amplifier 30 Y selector 40 precharge circuit 41 precharge transistor 50 discharge circuit 51 read transistor 60 reference generation circuit 61 reference transistor 62 gate voltage generation circuit BL-C cell bit line BL-R read bit line WL word line REF reference level PRE Precharge signal YSEL Select signal OUT Output data

Claims (6)

A cell transistor that functions as a memory cell;
A cell bit line connected to the drain or source of the cell transistor;
A precharge circuit connected to the cell bit line;
A read transistor having a gate connected to the cell bit line, a drain connected to the read bit line, and a source grounded;
A sense amplifier connected to the read bit line,
In a precharge period, the precharge circuit precharges the cell bit line, the sense amplifier precharges the read bit line,
In the sampling period after the precharge period, the cell transistor is turned on or off according to the stored data, and the sense amplifier compares the stored data by comparing the potential or current of the read bit line with a reference level. Sense non-volatile semiconductor memory. The nonvolatile semiconductor memory according to claim 1,
A nonvolatile semiconductor memory in which a gate width of the read transistor is larger than a gate width of the cell transistor. The nonvolatile semiconductor memory according to claim 1 or 2,
Furthermore, a reference transistor for generating the reference level is provided,
The non-volatile semiconductor memory, wherein the read transistor and the reference transistor have the same temperature characteristics. A non-volatile semiconductor memory according to any one of claims 1 to 3,
The structure of the reference transistor and the structure of the read transistor are the same except at least in size. A cell transistor that functions as a memory cell;
A sense amplifier configured to sense storage data stored in the memory cell by comparing the potential or current of the bit line with a reference level;
A discharge circuit interposed between the cell transistor and the bit line and configured to discharge the bit line;
During the precharge period, the sense amplifier precharges the bit line,
In the sampling period after the precharge period, the cell transistor is turned on or off according to the stored data, and the discharge circuit is discharged only when the cell transistor is turned on or off. Non-volatile semiconductor memory. The nonvolatile semiconductor memory according to claim 5,
A nonvolatile semiconductor memory having a higher capability of discharging the bit line in the discharge circuit than in the cell transistor.

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