JP2011155198A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric material capacitor structure for attaining high integration density thereof, and improving the characteristics of the ferroelectric material capacitor. <P>SOLUTION: The ferroelectric material capacitor includes a base film underlayer film for growth of a ferroelectric material film in a preferred orientation; a ferroelectric material film formed on the base film; and a pair of electrodes formed on the upper surface of the ferroelectric material film, along a first direction keeping the predetermined interval for applying a voltage to the ferroelectric material film. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a ferroelectric capacitor used in a semiconductor device.

  As the ferroelectric memory (FeRAM: Ferroelectric Random Access Memory) is highly integrated and miniaturized, it has become difficult to accurately manufacture a ferroelectric capacitor included in the ferroelectric memory.

  The basic structure of a conventional ferroelectric capacitor is composed of a laminate of a lower electrode film, a ferroelectric film provided on the lower electrode film, and an upper electrode provided on the ferroelectric film ( For example, see Patent Document 1).

  In particular, the characteristics of the ferroelectric capacitor greatly depend on the crystallinity of the ferroelectric film having a perovskite crystal structure. Therefore, in order to improve the crystallinity of the ferroelectric film, it is necessary to select a suitable base film as a film disposed under the ferroelectric film. Accordingly, the lower electrode film provided under the ferroelectric film is required not only to function as an electrode but also as a base film for forming a ferroelectric film having a good crystal structure. It is. Therefore, noble metal thin films such as Pt and Ir are used as the lower electrode of the ferroelectric capacitor that can play both of these roles.

  However, since these noble metal thin films have the property of hardly volatilizing, it is difficult to perform RIE (Reactive Ion Etching) processing on these noble metal thin films, and in order to form a ferroelectric capacitor structure, the lower electrode When a RIE process is performed on a stack composed of a ferroelectric film and an upper electrode, the ferroelectric capacitor has a tapered shape that narrows from the lower electrode toward the upper electrode. It will be formed as a thing.

  Therefore, when the ferroelectric capacitor has a tapered shape as described above, the capacitance of the capacitor having the structure as described above is a ferroelectric substance sandwiched between both the lower electrode and the upper electrode. Since it is determined by the area of the film, there exists a portion of the ferroelectric film that is not involved in the capacitance of the capacitor in the ferroelectric film having a larger area than the upper electrode. This tendency becomes conspicuous with the miniaturization of the ferroelectric memory. In other words, as the ferroelectric capacitor is miniaturized, the area of the portion of the ferroelectric film that does not contribute to the capacitance of the capacitor increases.

  In addition, when such RIE processing is performed on the ferroelectric capacitor stack, impurities such as hydrogen are mixed into the ferroelectric film, or the ferroelectric film is damaged. The characteristics of the capacitor will be deteriorated.

JP 2005-64342 A

  The present invention has been made in view of the above circumstances, and provides a ferroelectric capacitor structure capable of achieving high integration of a ferroelectric capacitor and improving the characteristics of the ferroelectric capacitor. Is.

  A ferroelectric capacitor according to an aspect of the present invention includes a base film for growing a ferroelectric film in a preferential orientation, the ferroelectric film formed on the base film, and the ferroelectric film And a pair of electrodes for applying a voltage to the ferroelectric film formed at predetermined intervals along the first direction.

  A ferroelectric capacitor device according to another aspect of the present invention is a ferroelectric capacitor device including a plurality of ferroelectric capacitors, and a base film for growing a ferroelectric film in a preferential orientation; Each of the ferroelectric films, comprising: the ferroelectric film formed on a base film; and a plurality of electrodes formed at predetermined intervals along a first direction on the upper surface of the ferroelectric film. The capacitor includes two electrodes adjacent to each other in the first direction among the plurality of electrodes, and a partial ferroelectric film sandwiched between the two electrodes.

  The ferroelectric capacitor structure of the present invention can achieve high integration of the ferroelectric capacitor and improve the characteristics of the ferroelectric capacitor.

1 is a plan view of a ferroelectric memory according to a first embodiment of the present invention. 1 is a cross-sectional view of a ferroelectric memory according to a first embodiment of the present invention. The top view of the ferroelectric memory of 2nd Embodiment which concerns on this invention. Sectional drawing of the ferroelectric memory of 2nd Embodiment which concerns on this invention. The top view of the ferroelectric memory of the 3rd Embodiment concerning this invention. Sectional drawing of the ferroelectric memory of the 3rd Embodiment concerning this invention.

  In the following embodiments, the ferroelectric memory is, for example, “TC parallel unit serial connection type ferroelectric memory”. In the TC parallel unit series connection type ferroelectric memory, both ends of the capacitor (C) are respectively connected between the source and drain of the cell transistor (T), and this is used as a unit cell, and a plurality of the unit cells are connected in series. It is a ferroelectric memory.

  Embodiments according to the present invention will be described below with reference to the drawings. However, the present invention is not limited to this embodiment.

  First, before describing the first embodiment according to the present invention, the background of how the present inventor has made the present invention will be briefly described.

  As described above, high integration is strongly demanded for the ferroelectric memory. Naturally, high integration of the ferroelectric memory needs to be performed while maintaining the characteristics of the plurality of ferroelectric capacitors included in the ferroelectric memory as good. On the other hand, the present inventor thought that the characteristics of the ferroelectric capacitor could be further improved and that the ferroelectric memory could not be highly integrated.

  In view of this, the present inventor considered that the ferroelectric capacitors themselves should be miniaturized and the ferroelectric capacitors can be stacked in multiple stages to achieve high integration of the ferroelectric memory.

  However, as described above, in the conventional ferroelectric capacitor structure, since a difficult-to-process noble metal thin film is used as the lower electrode, there is a limit to further miniaturization. Also, it has been difficult to accurately form a structure in which ferroelectric capacitors having such a structure are stacked in multiple stages.

  Furthermore, in the conventional ferroelectric capacitor structure, there has been a limit to improving the characteristics of the ferroelectric capacitor. The reason will be described below.

  In order to improve the characteristics of the ferroelectric capacitor, it is necessary to improve the crystallinity of the ferroelectric film functioning as a capacitor. Therefore, for example, the ferroelectric film is deposited on the base film formed of a material having a lattice constant having a value as close as possible to the lattice constant in the ideal crystal structure of the ferroelectric film. . The ferroelectric film has good crystallinity by growing in the preferential orientation while being influenced by the crystal structure of the base film. Here, growing in the preferred orientation means that the ferroelectric film is grown as a crystal structure having a specific crystal orientation preferentially by growing while being influenced by the crystal structure of the underlying film. Means that

  However, since the conventional ferroelectric capacitor structure is a sandwich structure in which the ferroelectric film is sandwiched between electrodes as described above, the underlying film has good crystallinity of the ferroelectric film. Therefore, not only a role as a base film for achieving the above, but also a role as an electrode film is required. That is, the base film is selected from materials that can play both of these roles. Therefore, in the conventional ferroelectric capacitor structure, it is difficult to form a base film from a material most suitable for improving the crystallinity of the ferroelectric film. He had sacrificed sex.

  Thus, in the conventional ferroelectric capacitor structure, there is a limit in improving the crystallinity of the ferroelectric film, and therefore there is a limit in improving the characteristics of the ferroelectric film.

  Based on the above, the present inventor has made a conventional structure of a ferroelectric capacitor in order to further improve the characteristics of the ferroelectric capacitor and to achieve high integration of the ferroelectric memory. I thought it needed to be different from the structure. In particular, the inventor can use a base film most suitable for improving the crystallinity of the ferroelectric film, and can separately form the base film and the electrode film. I thought that a capacitor structure was necessary.

  In addition, the present inventor wanted to deposit the ferroelectric film on the base film as much as possible in order to further improve the crystallinity of the ferroelectric film. Furthermore, the present inventor does not need to perform RIE processing on the ferroelectric film as much as possible in order to avoid deteriorating the crystallinity of the ferroelectric film by processing such as RIE. A body capacitor structure was considered preferred. The present inventor particularly wanted to avoid deteriorating the crystallinity of the portion of the ferroelectric film sandwiched between the electrodes by RIE processing.

  Based on such an idea of the present inventor, the present inventor has invented a ferroelectric capacitor having the following structure.

  The structure of the ferroelectric capacitor according to the present invention is a sandwich structure in which a pair of electrodes are provided so as to sandwich the ferroelectric film from above and below the ferroelectric film, as in the structure of a conventional ferroelectric capacitor. A ferroelectric film is formed on a base film for growing a ferroelectric film in a preferential orientation, and a pair of electrodes are formed on the upper surface of the ferroelectric film. is there.

  In the ferroelectric capacitor according to the present invention, by applying a voltage between the pair of electrodes formed on the ferroelectric film, a part of the ferroelectric film sandwiched between the pair of electrodes. An electric field is applied to the electrode to polarize a part of the ferroelectric film in a lateral direction (a direction parallel to the ferroelectric film). Thus, the residual polarization generated in a part of the ferroelectric film is used as a capacitor.

  By making a ferroelectric capacitor in such a structure, a ferroelectric film can be laminated on an optimum underlayer, so that the crystallinity of the ferroelectric film is improved and the characteristics of the ferroelectric capacitor are improved. It can be made even better. Further, since the RIE process is performed only on the electrode film, the process is simple, and the crystallinity of the ferroelectric film sandwiched between the electrodes is not deteriorated. Further, since the formation thereof is simple, it is possible to miniaturize the ferroelectric capacitor and to stack the ferroelectric capacitors in multiple stages with high accuracy.

  Further, such a ferroelectric capacitor structure can reduce the manufacturing cost and the manufacturing time, and makes it possible to easily control the coercive voltage of the ferroelectric capacitor as described below.

  That is, in the conventional ferroelectric capacitor, the coercive voltage is controlled by controlling the composition and film thickness of the ferroelectric film. However, strictly controlling the composition and film thickness of the ferroelectric film is difficult in a fine ferroelectric capacitor. However, in the ferroelectric capacitor structure according to the present invention, since the pair of electrodes are formed on the ferroelectric film, the coercive voltage of the capacitor can be controlled by the distance between the pair of electrodes. is there. Therefore, the width over which the coercive voltage can be controlled is not limited, and it is easy to precisely control the coercive voltage only by processing the electrode film.

  Next, a first embodiment of the present invention will be described.

(First embodiment)
The ferroelectric memory according to the first embodiment will be described with reference to FIGS. However, the present invention is not limited to the ferroelectric memory, and can be used for other semiconductor devices.

  FIG. 1 is a plan view of a ferroelectric memory 1 according to this embodiment. FIG. 2 is a cross-sectional view of the ferroelectric memory 1 of this embodiment. Specifically, FIG. 2 is a cross-sectional view of the ferroelectric memory 1 taken along the lines aa ′, bb ′, and cc ′ shown in FIG.

  As can be seen from FIG. 1, in the ferroelectric memory 1, each electrode film (electrode) is formed on the ferroelectric film 22 at predetermined intervals along the horizontal direction (second direction) in FIG. 23 is formed. Each electrode film 23 includes a contact 5 for electrically connecting the electrode film 23 and a cell transistor (transistor).

  Furthermore, when the plurality of electrode films 23 arranged in a line in the horizontal direction are referred to as an electrode film array 24, the plurality of electrode film arrays 24 are formed on the ferroelectric film 22 so as to be parallel to each other. . In two electrode film rows 24 adjacent to each other in the vertical direction (first direction) in FIG. 1, one electrode film row 24 and the other electrode film row 24 are arranged in a positional relationship in which the phases are shifted in the horizontal direction. Has been. In the two electrode film rows 24 adjacent in the vertical direction, one electrode film row 24 and the other electrode film row 24 may be arranged in a positional relationship such that the phases are the same.

  Each ferroelectric capacitor 2 includes two electrode films 23 adjacent in the vertical direction (first direction) in FIG. 1 and a part of the ferroelectric film 22 sandwiched between the two electrode films 23 (partial strength). Dielectric film). Therefore, a part of the ferroelectric film 22 sandwiched between the two electrode films 23 adjacent in the vertical direction is polarized, for example, as shown by an arrow in FIG.

  Further, each electrode film 23 is commonly used for two ferroelectric capacitors 2 adjacent in the vertical direction so as to sandwich each electrode film 23. Each ferroelectric capacitor 2 may include the electrode film 23 separately instead of the common electrode film 23 as shown in FIG.

  Further, between the ferroelectric capacitors 2 adjacent in the horizontal direction, specifically, between the electrode films 23 adjacent in the horizontal direction in the electrode film rows 24, there are element isolation grooves 4 for preventing interference. Is formed. The element isolation groove 4 is not limited to the position as shown in FIG. 1, and is formed at an appropriate position as necessary, for example, so as to surround each ferroelectric capacitor 2. You may do it.

  The ferroelectric memory 1 of the first embodiment has a planar configuration (layout) as shown in FIG. 1 so that the area thereof is as small as possible, but is not limited to this. Since the ferroelectric capacitor structure of the first embodiment has a simple structure, there are few restrictions on the planar configuration of the ferroelectric memory 1, and the ferroelectric capacitors have various planar configurations. The memory 1 can be formed.

  Next, the cross-sectional structure of the ferroelectric memory according to the present embodiment will be described with reference to FIG.

  Specifically, FIG. 2A is a cross section taken along the line aa ′ in FIG. 1, and FIG. 2B is a cross section taken along the line bb ′ in FIG. 1. Further, FIG. 2C is a cross-sectional view taken along line cc ′ in FIG.

  As shown in FIG. 2A, the ferroelectric memory 1 of this embodiment includes a semiconductor substrate 11 and a cell transistor (transistor / circuit element) 3 provided on the semiconductor substrate 11 (p-type silicon substrate). An interlayer insulating film 12 covering the cell transistor 3 and the semiconductor substrate 11, a silicon oxide insulating film 13 provided on the interlayer insulating film 12, and a ferroelectric provided on the silicon oxide insulating film 13. And a protective film (not shown in FIG. 2) provided so as to cover the ferroelectric capacitor 2.

  Specifically, the semiconductor substrate 11 is provided with source / drain diffusion regions 35.

The cell transistor 3 formed on the semiconductor substrate 11 includes a gate insulating film (silicon oxide film) 31 provided on the semiconductor substrate 11 and a gate electrode film (word line) provided on the gate insulating film 31. ) 32 and a gate cap film (silicon nitride film) 33 provided on the gate electrode film 32. Further, the cell transistor 3 includes a gate sidewall film (silicon nitride film) 34 that covers the sidewalls of the gate insulating film 31, the gate electrode film 32, and the gate cap film 33. The gate electrode 32 is preferably formed of, for example, a polycide film made of polysilicon and a WSi ₂ film.

  Next, an interlayer insulating film 12 is provided so as to cover the cell transistor 3 and the semiconductor substrate 11. Specifically, the interlayer insulating film 12 is formed of a multilayer film including a silicon nitride film and a silicon oxide film.

  The ferroelectric capacitor 2 includes a base film 21 provided on the silicon oxide insulating film 13, a ferroelectric film 22 provided on the base film 21, and the same surface of the ferroelectric film 22. And an electrode film 23 provided on the substrate.

Further, the base film 21 provided on the silicon oxide insulating film 13 is selected from an optimum material for forming a ferroelectric film 22 having a crystal structure such as a perovskite crystal structure. Accordingly, the condition of the base film 21 is required to be a material having a lattice constant having a value close to that of the ferroelectric film, for example. Therefore, the base film 21 is formed of a material selected from, for example, an insulating oxide film such as STO (SrTiO ₃ ), MgO, Al ₂ O ₃ , CeO ₂ , ZrO ₂ , HfO ₂ , and Ta ₂ O _5. Is done. The base film 21 formed of these materials is optimal as a base film of a ferroelectric film having a desired crystal structure such as a perovskite crystal structure, and more specifically, a conventional ferroelectric substance. Compared to a noble metal thin film such as Ir used in capacitors, it is excellent as a base film.

Further, as described above, the ferroelectric film 22 provided on the base film 21 has a desired crystal structure such as a perovskite crystal structure, and has remanent polarization that can be used as a capacitor. is there. For example, the ferroelectric film 22 is obtained by adding Nb to PZT (Pb (Zr _x Ti _1-x ) O ₃ ), BIT (Bi ₄ Ti ₃ O ₁₂ ), SBT (SrBi ₂ Ta ₂ O ₉ ), or SBT. Ferroelectric materials such as materials, ferroelectric materials such as BLT ((Bi, La) ₄ Ti ₃ O ₁₂ ), PZT with various additive elements, and PLZT with various additive elements Can be formed from

The electrode film 23 is formed from a noble metal, a noble metal oxide, a conductive oxide, or the like in order to ensure characteristics necessary for an electrode provided in the ferroelectric capacitor, such as fatigue resistance characteristics, retention characteristics, imprint characteristics, and the like. can do. Specifically, these electrode films 23 are made of, for example, Pt, Ir, IrO ₂ , Ru, RuO ₂ , SrRuO ₃ (SRO), LaNiO ₃ (LNO), (La, Sr) CoO ₃ , YBCO (YBa ₂ Cu ₃ O _X ) (superconductor), a laminate of SRO and IrOx, a noble metal, a noble metal oxide, a conductive complex oxide typified by a perovskite crystal structure, and the like. In particular, IrO ₂ is preferable as a material for the electrode film 23 because it can suppress damage to the ferroelectric film that occurs during the formation of an interlayer insulating film.

  Further, the distance between the electrode films 23 is specifically set such that the distance between the pair of electrodes included in each ferroelectric capacitor 2 is set to a desired value for the coercive voltage of the ferroelectric capacitor 2. Selected.

In detail, a protective film is provided so as to cover the ferroelectric film 2 and the electrode film 23 so as to cover the ferroelectric capacitor 2. This protective film is formed of, for example, alumina (Al ₂ O ₃ ), silicon oxide film, titania (TiOx), silicon nitride film (SiN), or the like. Alternatively, the protective film can be formed of PZT, BST ((Ba, Sr) TiO ₃ ), or the like. By forming this protective film so as to cover the ferroelectric capacitor 2, it is possible to prevent reducing hydrogen from entering the ferroelectric film 22, and the characteristics of the ferroelectric film 22. Deterioration, in particular, deterioration of the polarization characteristics of the ferroelectric film 22 can be suppressed.

  Next, a cross section of the ferroelectric memory 1 of this embodiment shown in FIGS. 2B and 2C will be briefly described. As can be seen from these drawings, the ferroelectric memory 1 of the present embodiment described above further includes an interlayer insulation from the semiconductor substrate 11 in order to electrically connect the cell transistor 3 and the electrode film 23. In order to prevent interference between the contact 5 and each adjacent ferroelectric capacitor 2 that penetrates the film 12, the silicon oxide insulating film 13, and the ferroelectric film 22 and reaches the electrode film 23, the ferroelectric film And element isolation trenches 4 formed in 22.

  The ferroelectric capacitor 2 formed as having the above-described structure is formed by applying a voltage to a pair of electrode films (electrodes) 23 provided in the ferroelectric capacitor 2 so that the ferroelectric capacitor 2 is sandwiched between the pair of electrode films 23. An electric field is applied to a part of the dielectric film 22. A part of the ferroelectric film 22 sandwiched between the pair of electrode films 23 by this electric field is, for example, as indicated by the arrows in FIGS. 1 and 2A. Polarize in the horizontal direction. The remanent polarization generated in a part of the ferroelectric film 22 thus obtained is used as a capacitor.

  Next, a method for producing the ferroelectric memory 1 according to the first embodiment having the above structure will be described.

  First, a plurality of cell transistors 3 are formed on a semiconductor substrate 11 and an interlayer insulating film 12 is deposited so as to cover the cell transistors 3 and the semiconductor substrate 11 in the same manner as in the conventional method for manufacturing a ferroelectric memory. To do.

  Then, a silicon oxide insulating film 13 and a base film 21 are deposited on the interlayer insulating film 12. As a method of depositing the silicon oxide insulating film 13 and the base film 21, any of sputtering, solution method, CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), etc. may be used. Preferably, as the deposition method of the base film 21, an optimum base film 21 is selected according to the material of the ferroelectric film 22 and the like.

  Further, the ferroelectric film 22 is deposited by using a sputtering method, a MOCVD (Metal Organic Chemical Vapor Deposition) method, a sol-gel method, or the like. Preferably, the ferroelectric film 22 is deposited using high temperature (for example, 600 ° C.) MOCVD.

Next, an electrode film 23 is deposited, and a hard mask material is deposited on the electrode film 23. A pattern corresponding to the shape of the electrode provided in the ferroelectric capacitor 2 is provided on the material of the hard mask by using photolithography and RIE processing to form a hard mask. The RIE process at this time is performed at room temperature using a halogen-based gas such as CHF ₃ or CF ₄ .

Then, RIE processing is performed on the electrode film 23 using a hard mask provided with a pattern. For example, when the electrode film 23 is formed of an IrO ₂ film, the RIE processing performed on the electrode film 23 is performed at a temperature of 250 to 400 ° C. in an atmosphere of a mixed gas such as Cl ₂ , O ₂ , and Ar. Will be.

  Further, an electrode film 23 is formed on the ferroelectric film 22, and the element isolation groove 4 is formed on the ferroelectric film 22 using RIE processing, and then the electrode film 23, the ferroelectric film 22, , A protective film is deposited so as to cover.

  In this manner, the ferroelectric memory 1 according to the first embodiment is formed.

Then, the inventor performed characteristic evaluation on the ferroelectric capacitor having the above structure. In this evaluation, the area of each electrode included in the ferroelectric capacitor was set to 0.5 μm × 0.5 μm. The polarization amount of this ferroelectric capacitor is about 30 μC / cm ² or more. The value of this polarization amount is a sufficiently large value even when fatigue, retention characteristics, imprint characteristics, etc. are taken into consideration in the use of a normal ferroelectric memory.

  Next, the present inventor has shown that the fatigue characteristics of the ferroelectric capacitor having the above structure is a test pattern in which a ferroelectric capacitor array is formed by a plurality of ferroelectric capacitors on a semiconductor substrate. And evaluated. In the following, one cycle means one execution of write / erase (W / E).

In this test pattern, the polarization amount of the ferroelectric capacitor did not change until 1 × 10 ¹² cycles. Furthermore, the leakage current was as low as about 10 ⁻⁷ A / cm ² when 2.5 V was applied.

  From these facts, it was confirmed that the ferroelectric memory of the first embodiment does not cause deterioration of reliability such as fatigue characteristics of the ferroelectric memory or deterioration of electrical characteristics such as increase of leakage current. It was.

(Second Embodiment)
Next, a second embodiment will be described.

  The difference between the ferroelectric memory according to the second embodiment and the first embodiment is that the ferroelectric capacitors adjacent to each other in the lateral direction (second direction) in FIGS. The element isolation insulating film is embedded in the element isolation groove formed between the electrode films adjacent to each other in the lateral direction. The element isolation insulating film has the same main component as the ferroelectric film. It is an amorphous film. By doing so, it is possible to easily form the element isolation insulating film while avoiding deterioration of the crystallinity of the ferroelectric film.

  The second embodiment will be described with reference to FIGS.

  A plan view of the ferroelectric memory 1 of the present embodiment is shown in FIG. 4 is a cross-sectional view of the ferroelectric memory 1 of the present embodiment. Specifically, the cross-sectional view taken along the line aa ′ in FIG. 3 is FIG. 4B is a cross-sectional view taken along b ′, and FIG. 4C is a cross-sectional view taken along line cc ′ in FIG.

  As can be seen from FIGS. 3 and 4, the ferroelectric memory 1 of the present embodiment is different from the ferroelectric memory of the first embodiment described above in the following points. That is, in the ferroelectric memory 1 of this embodiment, the main component is the same as that of the ferroelectric film 22 in the element isolation trench 4 formed between the electrode films 23 adjacent in the horizontal direction in FIG. The element isolation insulating film 41 which is an amorphous film is embedded. Other details are the same as those of the ferroelectric memory according to the first embodiment, and a detailed description thereof will be omitted.

  Next, a method for manufacturing the ferroelectric memory 1 of this embodiment will be described.

  Similar to the first embodiment, first, a plurality of cell transistors 3 are formed on a semiconductor substrate 11. Then, an interlayer insulating film 12 is deposited on the plurality of cell transistors 3 and on the semiconductor substrate 11. Further, a silicon oxide insulating film 13 is deposited on the interlayer insulating film 12.

  Next, a base film 21 that is a base of the ferroelectric film 22 is deposited on the silicon oxide film 13. As the base film 21 used here, for example, STO, MgO, or the like can be used as in the first embodiment.

  Then, the base film 21 in the region for forming the element isolation trench 4 between the electrode films 23 adjacent in the horizontal direction (second direction) in FIG. 3 is removed. Specifically, a hard mask material is deposited on the base film 21, and a pattern corresponding to the shape of the element isolation trench 4 is formed on the hard mask material using photolithography and RIE processing. Form. Next, RIE processing is performed on the base film 21 using a hard mask on which a pattern is formed. In this way, only the base film 21 in the region where the element isolation trench 4 is to be formed is removed, and the silicon oxide insulating film 13 is exposed.

  Next, a ferroelectric film 22 is deposited on the underlying film 21 and the exposed silicon oxide insulating film 13. The ferroelectric film 22 is made of a material such as PZT, for example, as in the first embodiment.

  At this time, the ferroelectric film 22 deposited on the exposed silicon oxide-based insulating film 13 in the region where the element isolation trench 4 is to be formed does not crystallize and the amorphous film 41 is not formed. Will be formed. This amorphous film 41 becomes an element isolation insulating film.

  On the other hand, the ferroelectric film 22 deposited on the base film 21 is crystallized to become a ferroelectric film 22 having a predetermined crystal structure such as a perovskite crystal structure and having high crystallinity.

  Thereafter, an electrode film 23 and the like are formed on the crystallized ferroelectric film 22, but the description is omitted because it is the same as in the first embodiment.

  In the ferroelectric capacitor structure of the present embodiment, since the ferroelectric film and the element isolation insulating film can be formed as described above, an element obtained by subjecting the ferroelectric film to RIE processing. It is not necessary to form a separation groove, and deterioration of the crystallinity of the ferroelectric film can be avoided. Furthermore, an element isolation insulating film can be easily formed.

(Third embodiment)
Next, a third embodiment will be described with reference to FIGS.

  FIG. 5 is a plan view showing the ferroelectric memory 1 of the third embodiment, and FIG. 6 is a cross-sectional view taken along the line aa ′ in FIG.

  As is apparent from FIGS. 5 and 6, the ferroelectric memory 1 of the present embodiment is different from the ferroelectric memory of the first embodiment described above in the following points. That is, the same ferroelectric capacitor is further laminated on the ferroelectric capacitor of the first embodiment to form a multistage ferroelectric capacitor. Other details are the same as those of the ferroelectric memory according to the first embodiment, and a detailed description thereof will be omitted.

  In the method of manufacturing the ferroelectric memory 1 according to the third embodiment, the ferroelectric capacitor 2 is formed as a first-stage ferroelectric capacitor, as in the first embodiment. Next, a silicon oxide-based insulating film 13 and a base film 21 are deposited on the first-stage ferroelectric capacitor via the interlayer insulating film 12, and further, the second-stage ferroelectric capacitor is deposited. In order to form a capacitor in the same manner as in the first embodiment, a ferroelectric film 22 and an electrode film 23 are deposited, and each ferroelectric capacitor 2 forms a pair of electrodes on the electrode film 23. Process to prepare. Then, a protective film is deposited. At this time, the first stage so that the electrode film 23 and the contact 5 included in the second-stage ferroelectric capacitor do not overlap the electrode 23 and the contact 5 included in the first-stage ferroelectric capacitor. And the second stage are shifted.

  By repeating such a process a plurality of times, a plurality of ferroelectric capacitors are stacked to form a ferroelectric memory 1 having a multi-stage ferroelectric capacitor as shown in the cross-sectional view of FIG. 6, for example. To do.

  As described above, since the structure of the ferroelectric capacitor of the present embodiment has a simple structure, a ferroelectric memory including a multi-stage ferroelectric capacitor can be easily formed. .

  Also in this embodiment, as in the second embodiment, the element isolation insulating film in the element isolation trench can be an amorphous film having the same main component as the ferroelectric film.

  In addition, this invention is not limited to said each embodiment, Various forms other than these can be taken.

DESCRIPTION OF SYMBOLS 1 Ferroelectric memory 2 Ferroelectric capacitor 3 Cell transistor (transistor / circuit element)
4 Element isolation groove 5 Contact 11 Substrate (p-type silicon substrate)
12 Interlayer Insulating Film 13 Silicon Oxide Film Insulating Film 21 Base Film 22 Ferroelectric Film 23 Electrode Film (Electrode)
24 Electrode film row 31 Gate insulating film (silicon oxide film)
32 Gate electrode film (word line)
33 Gate cap film (silicon nitride film)
34 Gate sidewall film 35 Source / drain diffusion region (silicon nitride film)
41 Amorphous film

Claims (7)

A base film for growing a ferroelectric film in a preferred orientation;
The ferroelectric film formed on the base film;
A pair of electrodes formed on the upper surface of the ferroelectric film at a predetermined interval along a first direction for applying a voltage to the ferroelectric film;
A ferroelectric capacitor comprising:   2. The ferroelectric capacitor according to claim 1, wherein the base film is an insulating metal oxide film. _{3. The} ferroelectric capacitor according to claim 2, wherein the base film is at least one of SrTiO ₃ , MgO, Al ₂ O ₃ , CeO ₂ , ZrO ₂ , HfO ₂ , and Ta ₂ O _5. . A ferroelectric capacitor device comprising a plurality of ferroelectric capacitors,
A base film for growing a ferroelectric film in a preferred orientation;
The ferroelectric film formed on the base film;
A plurality of electrodes formed at predetermined intervals along the first direction on the upper surface of the ferroelectric film,
Each ferroelectric capacitor is composed of two electrodes adjacent to each other in the first direction among the plurality of electrodes, and a partial ferroelectric film sandwiched between the two electrodes. Yes,
A ferroelectric capacitor device. A plurality of the ferroelectric capacitors formed at a predetermined interval along a second direction orthogonal to the first direction;
An element isolation insulating film formed between the ferroelectric capacitors adjacent to each other along the second direction,
The element isolation insulating film is an amorphous structure film having the same main component as the ferroelectric film.
The ferroelectric capacitor device according to claim 4. At least one ferroelectric capacitor is provided on each ferroelectric capacitor,
The ferroelectric capacitor device according to claim 4 or 5, wherein   The ferroelectric capacitor according to any one of claims 1 to 3 or the ferroelectric capacitor device according to any one of claims 4 to 6 on a semiconductor substrate on which a circuit element is formed. A semiconductor device comprising:

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