JP2011149824A - Method of manufacturing infrared sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an infrared sensor that can reduce manufacturing costs while making sensitivity high. <P>SOLUTION: In the method of manufacturing the infrared sensor, a combination of two kinds of conductor materials of a thermocouple of a thermopile 30a is p type polysilicon-n type polysilicon, and the material of an infrared absorption layer 39 is polysilicon of a second conductivity type being the same as that of a source region 44 and a drain region 43 of the second conductivity type in a well region 41 of a first conductivity type, while the material of a gate electrode 46 is the p type polysilicon or the n type polysilicon. The method includes a second conductivity type impurity ion implantation process wherein impurities of the second conductivity type are implanted in a polysilicon layer of non-doped corresponding to the infrared absorption layer 39. In this process, implantation of the impurities of the second conductivity type into the polysilicon layer of non-doped corresponding to the infrared absorption layer 39 and implantation of the impurities of the second conductivity type for forming the source region 44 and the drain region 43 in a silicon substrate 1 are performed simultaneously. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing an infrared sensor.

  Conventionally, as an infrared sensor, a plurality of pixels having a thermal infrared detector on one surface side of a silicon substrate and a MOS transistor arranged in parallel with the thermal infrared detector and reading the output of the thermal infrared detector An infrared sensor has been proposed in which a cavity for thermal insulation is formed for each portion corresponding to each thermal infrared detector in the silicon substrate (for example, Patent Document 1). Here, the thermal infrared detector in the infrared sensor disclosed in Patent Document 1 includes a rectangular frame-shaped support formed on the one surface side of the silicon substrate, and a rectangular disposed inside the support. It has a shaped infrared absorbing portion, and two beam portions connecting the support portion and the infrared absorbing portion. Here, the structure of the infrared absorption part, each beam part, and the support part includes a first silicon oxide film formed on the one surface side of the silicon substrate and a first silicon oxide film formed on the first silicon oxide film. The second silicon oxide film, the thermopile formed on the second silicon oxide film, and the third silicon oxide film formed to cover the thermopile on the opposite side of the second silicon oxide film from the first silicon oxide film side. It is formed by patterning the laminated structure part with the silicon oxide film.

  By the way, although the description about the manufacturing method of a MOS transistor is abbreviate | omitted in the said patent document 1, after forming the gate electrode of a MOS transistor in the manufacturing method of an infrared sensor, p-type polysilicon layer of a thermopile and The formation of an n-type polysilicon layer is described.

Also, conventionally, in the field of infrared sensors, by appropriately setting the impurity concentration of the polysilicon layer in the range of 10 ¹⁸ to 10 ²⁰ cm ⁻³ , the infrared ray reflection is improved while increasing the infrared absorption rate of the detection target. It is known that it can be suppressed (see, for example, Patent Document 2).

JP 2006-170937 A Japanese Patent No. 3287173

By the way, in the infrared sensor disclosed in the above-mentioned Patent Document 1, high sensitivity is achieved by providing an infrared absorption layer made of a polysilicon layer having an impurity concentration in the range of 10 ¹⁸ to 10 ²⁰ cm ⁻³ in the vicinity of the thermopile. Can be considered.

  In such an infrared sensor manufacturing method, a process for forming a thermopile of the thermal infrared detector on the one surface side of the silicon substrate, or a process for forming an infrared absorbing layer on the one surface side of the silicon substrate However, this is necessary separately from the process for forming the MOS transistor on the one surface side of the silicon substrate, and the manufacturing cost increases with the addition of the step of forming the infrared absorption layer.

  The present invention has been made in view of the above reasons, and an object of the present invention is to provide a method of manufacturing an infrared sensor capable of reducing the manufacturing cost while achieving high sensitivity.

  According to a first aspect of the present invention, there is provided a thermal-type infrared detection unit that is formed on one surface side of a silicon substrate and has an infrared absorption layer that absorbs infrared rays and converts the infrared rays into heat, and is supported on the silicon substrate. A MOS transistor arranged in parallel with the thermal infrared detector on the one surface side for taking out the output of the thermal infrared detector, and a cavity is formed immediately below a part of the thermal infrared detector in the silicon substrate. The combination of two kinds of conductor materials of the thermopile thermocouple is a combination of any one of p-type polysilicon-n-type polysilicon, p-type polysilicon-metal, n-type polysilicon-metal, and infrared absorption The material of the layer is the same as the second conductivity type source region and the second conductivity type drain region which are separated in the well region of the first conductivity type of the MOS transistor. A method of manufacturing an infrared sensor, wherein a material of a gate electrode is p-type polysilicon or n-type polysilicon, wherein a non-doped polysilicon layer is formed on the one surface side of a silicon substrate. Polysilicon for patterning the non-doped polysilicon layer so that at least portions corresponding to the infrared absorption layer, the thermopile, and the gate electrode remain among the non-doped polysilicon layer formed in the silicon layer forming step and the polysilicon layer forming step A layer patterning step, and a second conductivity type impurity ion implantation step for injecting a second conductivity type impurity into the non-doped polysilicon layer corresponding to the infrared absorption layer after the polysilicon layer patterning step. In the process of implanting impurity ions, at least an infrared absorption layer Injection and the corresponding non-doped second conductivity type impurity into the polysilicon layer, and an injection of the second conductivity type impurities for the source region and drain region formed on the silicon substrate, and performing at the same time.

  According to the present invention, a polysilicon layer forming step of forming a non-doped polysilicon layer on one surface side of a silicon substrate, and at least an infrared absorbing layer and a thermopile among the non-doped polysilicon layers formed in the polysilicon layer forming step And a polysilicon layer patterning step of patterning the non-doped polysilicon layer so that a portion corresponding to each of the gate electrodes remains, and after the polysilicon layer patterning step, the second conductive layer is transferred to the non-doped polysilicon layer corresponding to the infrared absorption layer. A second conductivity type impurity ion implantation step for injecting a second type impurity, and in the second conductivity type impurity ion implantation step, at least a second conductivity type impurity to the non-doped polysilicon layer corresponding to the infrared absorption layer And source / drain region shape to silicon substrate Since the second conductivity type impurity implantation is simultaneously performed, the infrared absorption layer can be formed without increasing the number of steps as compared with the case where the infrared absorption layer is not provided, and high sensitivity is achieved. However, the manufacturing cost can be reduced.

  The invention according to claim 2 is the invention according to claim 1, wherein the first conductivity type is p-type, the second conductivity type is n-type, and the combination of the thermopile is p-type polysilicon-n-type poly It is either silicon or p-type polysilicon-metal, and corresponds to a portion constituted by p-type polysilicon of the thermopile between the polysilicon layer patterning step and the second conductivity type impurity ion implantation step. A first conductivity type impurity ion implantation step of implanting the first conductivity type impurity into the non-doped polysilicon layer is performed.

  According to this invention, the first conductivity type is p-type, the second conductivity type is n-type, and the thermopile combination is p-type polysilicon-n-type polysilicon, p-type polysilicon-metal. In the manufacture of the infrared sensor according to any one of the above, the first conductivity type impurity ion implantation step is performed after the formation of the source region of the second conductivity type and the drain region of the second conductivity type. Since the n-type impurity which is the second conductivity type in the source region and the drain region can be prevented from diffusing into the channel formation region, the channel length of the MOS transistor can be further shortened, and the MOS transistor It becomes possible to form the transistor with higher reproducibility.

  The invention according to claim 3 is the invention according to claim 1, wherein the first conductivity type is p-type, the second conductivity type is n-type, and the combination of the thermopile is p-type polysilicon-n-type poly. In the second conductivity type impurity ion implantation step, the second doping to the non-doped polysilicon layer corresponding to the portion constituted by the n-type polysilicon of the thermopile is performed. Conductive impurity implantation is also performed at the same time.

  According to the present invention, the first conductivity type is p-type, the second conductivity type is n-type, and the combination of the thermopile is p-type polysilicon-n-type polysilicon, n-type polysilicon-metal. In the manufacture of the infrared sensor of any one of the above, the implantation of the second conductivity type impurity into the non-doped polysilicon layer corresponding to the portion constituted by the n-type polysilicon of the thermopile Compared to the case where the ion implantation process is performed separately, the number of processes can be reduced and the manufacturing cost can be reduced.

  According to a fourth aspect of the present invention, in the first aspect, the first conductivity type is p-type, the second conductivity type is n-type, and the combination of the thermopile is p-type polysilicon-n-type poly The first conductive layer is made of silicon and is transferred between the polysilicon layer patterning step and the second conductivity type impurity ion implantation step to the non-doped polysilicon layer corresponding to the portion of the thermopile formed of p-type polysilicon. In the second conductivity type impurity ion implantation step, a non-doped polysilicon layer corresponding to a portion constituted by n-type polysilicon of the thermopile is performed. The impurity of the second conductivity type is also implanted into the substrate at the same time.

  According to this invention, the thermopile n-type polysilicon is formed in the second conductivity type impurity ion implantation step when the thermopile combination is an infrared sensor that is p-type polysilicon-n-type polysilicon. The implantation of the second conductivity type impurity into the non-doped polysilicon layer corresponding to the portion to be implanted, the implantation of the second conductivity type impurity into the non-doped polysilicon layer corresponding to the infrared absorption layer, the silicon substrate This is performed at the same time as the implantation of the impurity of the second conductivity type for forming the source region and the drain region, so that the cost can be further reduced.

  The invention of claim 1 can form an infrared absorption layer without increasing the number of processes compared to the case where no infrared absorption layer is provided, and can reduce the manufacturing cost while achieving high sensitivity. There is an effect.

The principal part of the pixel part in the infrared sensor of embodiment is shown, (a) is a plane layout figure, (b) is a schematic sectional drawing corresponding to the D-D 'cross section of (a). It is a plane layout figure of the pixel part in the infrared sensor of an embodiment. It is a plane layout figure of the principal part of a pixel part in an infrared sensor same as the above. It is a plane layout figure of the principal part of a pixel part in an infrared sensor same as the above. It is a plane layout figure of the pixel part in an infrared sensor same as the above. It is a plane layout figure of an infrared sensor same as the above. The principal part of the pixel part in an infrared sensor same as the above is shown, (a) is a planar layout view, (b) is a schematic sectional view corresponding to the D-D 'section of (a). The principal part containing the cold junction in an infrared sensor same as the above is shown, (a) is a plane layout figure, (b) is a schematic sectional drawing. The principal part containing the hot junction in an infrared sensor same as the above is shown, (a) is a plane layout view, (b) is a schematic sectional view. It is a schematic sectional drawing of the principal part of the pixel part in an infrared sensor same as the above. It is a schematic sectional drawing of the principal part of the pixel part in an infrared sensor same as the above. It is principal part explanatory drawing of an infrared sensor same as the above. It is an equivalent circuit diagram of an infrared sensor same as the above. It is principal process sectional drawing for demonstrating the manufacturing method of an infrared sensor same as the above. It is principal process sectional drawing for demonstrating the manufacturing method of an infrared sensor same as the above. It is principal process sectional drawing for demonstrating the manufacturing method of an infrared sensor same as the above. It is principal process sectional drawing for demonstrating the manufacturing method of an infrared sensor same as the above. It is a schematic sectional drawing. It is principal process sectional drawing for demonstrating the manufacturing method of an infrared sensor same as the above.

  Hereinafter, the infrared sensor A of the present embodiment will be described based on FIGS. 1 to 13, and thereafter, a method for manufacturing the infrared sensor A will be described with reference to FIGS. 14 to 18.

  The infrared sensor A of the present embodiment is an infrared array sensor, and a plurality of pixel units 2 (see FIG. 6) having a thermal infrared detection unit 3 and a MOS transistor 4 that is a pixel selection switching element include a base substrate 1. Are arranged in an array (here, a two-dimensional array) on one surface side. Here, the base substrate 1 is formed using a silicon substrate 1a. In the present embodiment, m × n (8 × 8 in the example shown in FIGS. 6 and 13) pixel units 2 are formed on the one surface side of one base substrate 1. The number and arrangement of 2 are not particularly limited. Further, in the present embodiment, the temperature sensing unit 30 of the thermal infrared detection unit 3 is configured by connecting a plurality (here, six) of thermopile 30a (see FIG. 2) in series, as shown in FIG. The equivalent circuit of the temperature sensing unit 30 in the thermal infrared detection unit 3 is represented by a voltage source Vs corresponding to the thermoelectromotive force of the temperature sensing unit 30. In this embodiment, the silicon substrate 1 a constitutes a support substrate that supports the thermal infrared detector 3.

Further, in the infrared sensor A of the present embodiment, as shown in FIGS. 2, 3 and 13, one end of the temperature sensing unit 30 of each of the plurality of thermal infrared detection units 3 in each row passes through the MOS transistor 4 described above. A plurality of vertical readout lines 7 commonly connected to each column and a plurality of gate electrodes 46 of the MOS transistors 4 corresponding to the temperature sensing portions 30 of the thermal infrared detectors 3 of each row are commonly connected to each row. A horizontal signal line 6, a plurality of ground lines 8 in which the p ^{+ -type} well regions 41 of the MOS transistors 4 in each column are connected in common to each column, a common ground line 9 in which the ground lines 8 are connected in common, The other end of the temperature sensing unit 30 of the plurality of thermal infrared detectors 3 in each row is provided with a plurality of reference bias lines 5 commonly connected to each row, and all of the thermal infrared detectors 3 Reading the output of the temperature sensing unit 30 in time series And can be. In short, the infrared sensor A of the present embodiment is arranged in parallel with the thermal infrared detector 3 and the thermal infrared detector 3 on the one surface side of the base substrate 1 to read the output of the thermal infrared detector 3. A plurality of pixel portions 2 having the MOS transistors 4 are formed.

  Here, in the MOS transistor 4, the gate electrode 46 is connected to the horizontal signal line 6, the source electrode 48 is connected to the reference bias line 5 via the temperature sensing unit 30, and each reference bias line 5 is connected to the common reference bias line 5a. Are connected in common, the drain electrode 47 is connected to the vertical readout line 7, each horizontal signal line 6 is electrically connected to each pixel selection pad Vsel, and each vertical readout line 7 is individually connected to each other. Are electrically connected to the output pad Vout, the common ground line 9 is electrically connected to the ground pad Gnd, the common reference bias line 5a is electrically connected to the reference bias pad Vref, and the silicon substrate 1a is electrically connected. It is electrically connected to the substrate pad Vdd.

  Therefore, the output voltage of each pixel unit 2 can be read sequentially by controlling the potential of each pixel selection pad Vsel so that the MOS transistors 4 are sequentially turned on. For example, if the potential of the reference bias pad Vref is 1.65, the potential of the ground pad Gnd is 0 V, the potential of the substrate pad Vdd is 5 V, and the potential of the pixel selection pad Vsel is 5 V, the MOS transistor 4 Is turned on, the output voltage of the pixel unit 2 (1.65 V + the output voltage of the temperature sensing unit 30) is read from the output pad Vout, and the potential of the pixel selection pad Vsel is set to 0 V, the MOS transistor 4 is turned off. Thus, the output voltage of the pixel unit 2 is not read from the output pad Vout. In FIG. 6, the pixel selection pad Vsel, the reference bias pad Vref, the ground pad Gnd, the output pad Vout, etc. are all illustrated as pads 80 without being distinguished.

  Hereinafter, the structures of the thermal infrared detector 3 and the MOS transistor 4 will be described. In the present embodiment, as the silicon substrate 1a, a single crystal silicon substrate having an n-type conductivity and the (100) plane of the one surface is used.

  The thermal infrared detector 3 is formed in the formation area A1 of the thermal infrared detector 3 in each pixel unit 2 on the one surface side of the silicon substrate 1a, and the MOS transistor 4 is formed on the silicon substrate 1a. It is formed in the formation region A2 of the MOS transistor 4 in each pixel portion 2 on one surface side.

  Each pixel unit 2 includes an infrared absorption unit 33 (see FIGS. 1B and 2) that absorbs infrared rays. In each pixel unit 2, the infrared absorption unit 33 is provided on the silicon substrate 1a. A cavity portion (digging portion) 11 for thermal insulation from 1 is formed, and an infrared absorption portion 33 is provided inside the inner peripheral line of the cavity portion 11 in plan view on the one surface side of the silicon substrate 1a. 11 is formed. Further, in each pixel portion 2, the thin-film structure portion 3 a is arranged in parallel along the inner circumferential direction of the cavity portion 11 by a plurality of linear slits 13, and each region (planar surface) surrounding the cavity portion 11 in the thermal infrared detector 3. It is separated into a plurality (six in the example shown in FIG. 2) small thin film structure portions 3aa extending inward from the portion surrounding the cavity portion 11 as viewed, and a thermopile 30a is provided for each small thin film structure portion 3aa. All the thermopile 30a are connected in series so that the output change with respect to the temperature change is larger than when the output is taken out for each thermopile 30a, and the adjacent small thin film structures 3aa and 3aa are connected to each other. A connecting piece 3c is formed. Below, each part divided | segmented corresponding to each small thin film structure part 3aa among the infrared absorption parts 33 is called the division | segmentation infrared absorption part 33a.

  In the present embodiment, all of the plurality of thermopiles 30a formed in the thin film structure portion 3a, and in the above example, all six thermopiles 30a are connected in series. However, the present invention is not limited to this. The series circuit of the thermopile 30a may be connected in parallel. In this case, the sensitivity is higher than when all six thermopiles 30a are connected in parallel or when the output is taken out for each thermopile 30a. Further, compared to the case where all six thermopiles 30a are connected in series, the electrical resistance of the temperature sensing unit 30 can be lowered and the thermal noise is reduced, so the S / N ratio is improved. . Here, the number of thermopiles 30a equal to the number of small thin film structures 3aa in the thin film structures 3a may be an even number equal to or greater than 4, and half of the thermopiles 30a are connected in series and the series circuit is connected in parallel. In this case, the sensitivity can be increased and the S / N ratio can be improved.

  Here, in the pixel portion 2, for each small thin-film structure portion 3aa, two planar-view strip-like bridge portions 3bb that connect the portion surrounding the cavity portion 11 and the divided infrared absorbing portion 33a in the thermal infrared detection portion 3; 3bb is formed so as to be spaced apart in the inner peripheral direction of the cavity portion 11, and the two bridge portions 3bb, 3bb and the split infrared absorbing portion 33a are spatially separated and communicated with the cavity portion 11 in a plan view. The slit 14 is formed. Here, the part surrounding the thin film structure 3a in the plan view of the thermal infrared detector 3 has a rectangular frame shape. Note that the bridge portion 3bb has a portion other than the connection portion with the portion surrounding the cavity portion 11 in the infrared absorption portion 33 and the thermal infrared detection portion 3, and the split infrared absorption portion 33a and the thermal type by the slits 13 and 14 described above. The infrared detector 3 is spatially separated from the portion surrounding the cavity 11. Here, in the thermal infrared detecting section 3 of the small thin film structure portion 3aa, the dimension in the extending direction from the portion surrounding the cavity 11 is 93 μm, the dimension in the width direction orthogonal to the extending direction of the small thin film structure section 3aa is 75 μm, Although the width dimension of the bridge portion 3bb is set to 23 μm and the widths of the slits 13 and 14 are set to 5 μm, these values are merely examples and are not particularly limited.

  The thin film structure 3a is formed on the silicon oxide film 1b formed on the one surface side of the silicon substrate 1a, the silicon nitride film 32 formed on the silicon oxide film 1b, and the silicon nitride film 32. The formed temperature sensitive part 30, the interlayer insulating film 50 made of a BPSG film formed so as to cover the temperature sensitive part 30 on the surface side of the silicon nitride film 32, the PSG film formed on the interlayer insulating film 50, and It is formed by patterning a laminated structure part with a passivation film 60 made of a laminated film with an NSG film formed on the PSG film.

In the present embodiment, portions of the silicon nitride film 32 other than the bridge portions 3bb and 3bb of the thin film structure portion 3a constitute the infrared absorbing portion 33 described above, and the silicon substrate 1a, the silicon oxide film 1b, the silicon nitride film 32, and the interlayer The insulating film 50 and the passivation film 60 constitute the base substrate 1. In the present embodiment, the laminated film of the interlayer insulating film 50 and the passivation film 60 is formed across the formation area A1 of the thermal infrared detector 3 and the formation area A2 of the MOS transistor 4. The portion formed in the formation region A1 of the thermal infrared detector 3 also serves as the infrared absorption film 70 (see FIG. 1B). Here, when the refractive index of the infrared absorption film 70 is n ₂ and the center wavelength of the infrared ray to be detected is λ, the thickness t2 of the infrared absorption film 70 is set to λ / 4n _2. The absorption efficiency of infrared rays of the target wavelength (for example, 8 to 12 μm) can be increased, and high sensitivity can be achieved. For example, when n ₂ = 1.4 and λ = 10 μm, t2≈1.8 μm may be set. In the present embodiment, the interlayer insulating film 50 has a thickness of 0.8 μm, the passivation film 60 has a thickness of 1 μm (the PSG film has a thickness of 0.5 μm, and the NSG film has a thickness of 0.5 μm). . In addition, the infrared absorption film 70 is not limited to the above-described configuration, and may be configured by, for example, a silicon nitride film.

  Further, in each pixel portion 2, the inner peripheral shape of the cavity portion 11 is rectangular, and the connecting piece 3c is formed in a cross shape in plan view, and in an oblique direction intersecting with the extending direction of the small thin film structure portion 3aa. Adjacent small thin film structures 3aa, 3aa, adjacent small thin film structures 3aa, 3aa in the extending direction of the small thin film structures 3aa, adjacent small thin film structures in the direction orthogonal to the extending direction of the small thin film structures 3aa 3aa and 3aa are connected.

  The thermopile 30a includes an elongated n-type polysilicon layer (first thermoelectric element) 34 formed on the silicon nitride film 32 and straddling the small thin film structure 3aa and the base substrate 1, and an elongated p-type polysilicon. One end of the layer (second thermoelectric element) 35 is electrically connected by a first connecting metal portion 36 made of a metal material (for example, Al-Si) on the infrared incident surface side of the split infrared absorbing portion 33a. And the other end portion of the n-type polysilicon layer 34 of the thermocouple adjacent to each other on the one surface side of the base substrate 1 and the thermocouples (9 in the example shown in FIG. 1). The other end portion of the p-type polysilicon layer 35 is joined and electrically connected by a second connection metal portion 37 made of a metal material (for example, Al—Si). Here, in the thermopile 30a, the one end portion of the n-type polysilicon layer 34, the one end portion of the p-type polysilicon layer 35, and the first connecting metal portion 36 constitute a hot junction T1 on the split infrared absorbing portion 33a side. The other end portion of the n-type polysilicon layer 34, the other end portion of the p-type polysilicon layer 35, and the second connecting metal portion 37 constitute a cold junction T2 on the base substrate 1 side. In short, each hot junction T1 of the thermopile 30a is formed in a region that overlaps the cavity 11 in the thermal infrared detector 3, and each cold junction T2 is formed in a region that does not overlap the cavity 11 in the thermal infrared detector 3. Has been. In the infrared sensor A of the present embodiment, the portions formed in the bridge portions 3bb and 3bb and the silicon of the base substrate 1 in each n-type polysilicon layer 34 and each p-type polysilicon layer 35 of the thermopile 30a. Infrared rays can also be absorbed at the portion formed on the nitride film 32. As can be seen from the above description, the combination of the two types of conductor materials of each thermocouple of the thermopile 30a is p-type polysilicon-n-type polysilicon, but the two types of conductor materials of each thermocouple. The combination may be any one of p-type polysilicon-n-type polysilicon, p-type polysilicon-metal (for example, aluminum), and n-type polysilicon-metal (for example, aluminum).

  Further, in the infrared sensor A of the present embodiment, the shape of the cavity 11 described above is a quadrangular pyramid, and the depth of the central portion in plan view is larger than that of the peripheral portion, so that the thin film structure The planar layout of the thermopile 30a in each pixel unit 2 is designed so that the hot junction T1 gathers at the center of the unit 3a. That is, in the middle two small thin film structure portions 3aa in the vertical direction of FIG. 2, as shown in FIGS. 2 and 3, the hot junctions T1 are arranged side by side along the juxtaposed direction of the three small thin film structure portions 3aa. On the other hand, in the two small thin film structure portions 3aa on the upper side in the vertical direction, as shown in FIGS. 2 and 4, the small thin film structure portion 3aa in the middle in the juxtaposition direction of the three small thin film structure portions 3aa. In the two small thin film structure portions 3aa on the lower side in the vertical direction, as shown in FIG. 2, the juxtaposed direction of the three small thin film structure portions 3aa In FIG. 1, the hot junctions T1 are concentrated on the side close to the middle small thin film structure 3aa. Therefore, in the infrared sensor A of the present embodiment, the arrangement of the plurality of hot junctions T1 of the upper and lower small thin film structures 3aa in the vertical direction in FIG. 2 is the plurality of hot junctions of the middle small thin film structure 3aa. Since the temperature change of the hot junction T1 can be increased as compared with the case where the arrangement is the same as that of T1, the sensitivity can be improved.

  Further, the small thin film structure portion 3aa is formed from an n-type polysilicon layer that suppresses the warp of the small thin film structure portion 3aa and absorbs infrared rays in a region where the thermopile 30a is not formed on the infrared incident surface side of the silicon nitride film 32. An infrared absorption layer 39 (see FIGS. 1, 2 and 10) is formed. Further, the connecting piece 3c that connects adjacent small thin film structures 3aa, 3aa is provided with a reinforcing layer 39b (see FIG. 7) made of an n-type polysilicon layer that reinforces the connecting piece 3c. Here, the reinforcing layer 39 b is formed integrally with the infrared absorption layer 39. Therefore, in the infrared sensor A of the present embodiment, since the connecting piece 3c is reinforced by the reinforcing layer 39b, it is possible to prevent breakage due to stress generated due to external temperature change or impact during use. Damage during manufacturing can be reduced, and manufacturing yield can be improved. In this embodiment, the length L1 of the connecting piece 3c shown in FIG. 7 is set to 24 μm, the width L2 is set to 5 μm, and the width L3 of the reinforcing layer 39b is set to 1 μm. There is no particular limitation. However, when the base substrate 1 is formed using the silicon substrate 1a and the reinforcing layer 39b is formed of an n-type polysilicon layer as in this embodiment, the reinforcing layer 39b is etched when the cavity 11 is formed. In order to prevent this, the width dimension of the reinforcing layer 39b is set smaller than the width dimension of the connecting piece 3c, and both side edges of the reinforcing layer 39b are located inside the both side edges of the connecting piece 3c in plan view. There is a need.

  In addition, as shown in FIGS. 7 and 12B, the infrared sensor A of the present embodiment has chamfered portions 3d and 3d between the side edges of the connecting piece 3c and the side edges of the small thin film structure portion 3aa. A chamfered portion 3e is also formed between the side edges of the cross-shaped connecting piece 3c which are formed and are substantially orthogonal to each other. Therefore, in the infrared sensor A of the present embodiment, the stress concentration at the connecting portion between the connecting piece 3c and the small thin film structure portion 3aa is smaller than that in the case where the chamfered portion is not formed as shown in FIG. This can alleviate the residual stress generated during the manufacturing process and can reduce the damage during the manufacturing process, thereby improving the manufacturing yield. Further, it is possible to prevent damage due to stress generated due to an external temperature change or impact during use. In the example shown in FIG. 7, each of the chamfered portions 3 d and 3 e is an R chamfered portion having an R of 3 μm, but is not limited to the R chamfered portion, and may be a C chamfered portion, for example.

  By the way, the infrared sensor A of the present embodiment includes a self-diagnosis heater section (fault diagnosis wiring) 139 that warms the hot junction T1 by Joule heat generated by energization. Here, the self-diagnosis heater unit 139 is disposed so as not to overlap the thermopile 30a in a region overlapping the cavity 11 of the silicon substrate 1a in the thermal infrared detection unit 3. Here, in the thermal infrared detecting unit 3, a self-diagnosis heater unit 139 is formed across all the small thin film structures 3aa.

  Specifically, the infrared sensor A of the present embodiment includes, in each pixel unit 2, a portion surrounding the cavity 11 in the thermal infrared detection unit 3, one bridge unit 3bb, a split infrared absorption unit 33a, and the other bridge unit. A self-diagnosis heater unit 139 is provided so as to straddle 3bb and a portion surrounding the cavity 11 in the thermal infrared detection unit 3, and all the self-diagnosis heater units 139 are connected in series. Therefore, in the infrared sensor A according to the present embodiment, the bridge portion 3bb can be bent or not depending on whether or not the m × n number of self-diagnosis heater portions 139 are energized during inspection or use during manufacture. The disconnection of the self-diagnosis heater unit 139 can be detected. Further, in the infrared sensor of the present embodiment, by detecting the output of each temperature sensing unit 30 by energizing the series circuit of m × n self-diagnosis heater units 139 at the time of the above-described inspection and use, It is possible to detect the presence or absence of disconnection of the temperature sensing unit 30, variation in sensitivity (variation in output of the temperature sensing unit 30), and the like. Here, regarding the sensitivity variation, it is possible to detect the sensitivity variation for each pixel unit 2, for example, due to warpage of the thin film structure portion 3 a or sticking of the thin film structure portion 3 a to the silicon substrate 1 a. Sensitivity variation can be detected. Here, in the infrared sensor A of the present embodiment, the self-diagnosis heater unit 139 is folded and meandered in the vicinity of the group of the plurality of hot junctions T1 in plan view, and therefore the self-diagnosis heater unit 139 is energized. Each hot junction T1 can be efficiently warmed by Joule heat generated by this. Here, the self-diagnosis heater unit 139 is formed on the same plane as the n-type polysilicon layer 34 and the p-type polysilicon layer 35 with the same thickness.

The infrared absorbing layer 39, the reinforcing layer 39b, and the self-diagnosis heater unit 139 described above have the same n-type impurity (for example, phosphorus) as the first thermoelectric element 34 and the same impurity concentration (for example, phosphorus). 1 × 10 ¹⁸ cm ⁻³ ) and is simultaneously formed on the n-type polysilicon layer 34. Further, for example, boron may be adopted as the p-type impurity of the p-type polysilicon layer 35, and the impurity concentration may be set to about 1 × 10 ^18, for example. In this embodiment, the impurity concentration of each of the n-type polysilicon layer 34 and the p-type polysilicon layer 35 is 1 × 10 ¹⁸ cm ⁻³ , the resistance value of the thermocouple can be reduced, and the S / N ratio can be improved. . The infrared absorption layer 39, the reinforcing layer 39b, and the self-diagnosis heater unit 139 are doped with the same n-type impurity as the n-type polysilicon layer 34 at the same impurity concentration. The same impurity as that of the p-type polysilicon layer 35 which is the thermoelectric element may be doped with the same impurity concentration.

By the way, in this embodiment, the refractive index of the n-type polysilicon layer 34, the p-type polysilicon layer 35, the infrared absorption layer 39, the reinforcing layer 39b, and the self-diagnosis heater portion 139 is n ₁ , and the center wavelength of the infrared light to be detected when to the lambda, so as to set the n-type polysilicon layer 34, p-type polysilicon layer 35, the infrared-absorbing layer 39, the thickness t1 of the respective reinforcing layers 39b and the self-diagnosis heater unit 139 to lambda / 4n ₁ Therefore, the absorption efficiency of infrared rays having a wavelength to be detected (for example, 8 to 12 μm) can be increased, and high sensitivity can be achieved. For example, when n ₁ = 3.6 and λ = 10 μm, t 1 ≈0.69 μm may be set.

In the present embodiment, the impurity concentration of each of the n-type polysilicon layer 24, the p-type polysilicon layer 35, the infrared absorption layer 39, the reinforcing layer 39b, and the self-diagnosis heater unit 139 is 1 × 10 ¹⁸ cm ⁻³ . Therefore, reflection of infrared rays can be suppressed while increasing the infrared absorption rate, and the S / N ratio of the output of the temperature sensing unit 30 can be increased. Also, the infrared absorption layer 39, the reinforcing layer 39b, and the self Since the diagnostic heater 139 can be formed in the same process as the n-type polysilicon layer 34, the cost can be reduced.

Here, the first connection metal part 36 and the second connection metal part 37 of the temperature sensing part 30 are insulated and separated by the interlayer insulating film 50 on the one surface side of the silicon substrate 1a (FIG. 8). And FIG. 9). That is, the first connection metal portion 36 on the warm junction T1 side is electrically connected to the one end portions of the polysilicon layers 34 and 35 through the contact holes 50a ₁ and 50a ₂ formed in the interlayer insulating film 50, The second connection metal portion 37 on the cold junction T2 side is electrically connected to the other end portions of the polysilicon layers 34 and 35 through contact holes 50a ₃ and 50a ₄ formed in the interlayer insulating film 50. Yes.

Further, as described above, the MOS transistor 4 is formed in the formation region A2 of the MOS transistor 4 in each pixel portion 2 on the one surface side of the silicon substrate 1a. Here, in the MOS transistor 4, as shown in FIGS. 1 and 11, a p-type (p ⁺ ) well region (hereinafter referred to as a p ^{+ -type} well region) 41 is formed on the one surface side of the silicon substrate 1a. In the p ^{+ -type} well region 41, an n-type (n ⁺ ) drain region (hereinafter referred to as an n ⁺ -type drain region) 43 and an n-type (n ⁺ ) source region (hereinafter referred to as an n ^{+ -type} source region) 44) are formed apart from each other. Further, the ^{p +} -type well region 41, ^{n +} -type drain region 43 and the ^{n +} -type p-type surrounding a source region 44 ^{(p ++)} channel stopper region ^{(hereinafter, p ++} type channel stopper regions) 42 Is formed. Further, on the site located between the n ⁺ -type drain region 43 and the n ⁺ -type source region 44 in the p ⁺ -type well region 41, a gate insulating film 45 made of silicon oxide film (thermal oxide film) A gate electrode 46 made of an n-type polysilicon layer is formed. A drain electrode 47 made of a metal material (for example, Al—Si) is formed on the n ⁺ -type drain region 43, and a metal material (for example, Al—Si) is formed on the n ^{+ -type} source region 44. A source electrode 48 is formed. Here, the gate electrode 46, the drain electrode 47, and the source electrode 48 are insulated and separated by the interlayer insulating film 50 described above. That is, the drain electrode 47 is electrically connected to the n ⁺ -type drain region 43 through the contact hole 50 d formed in the interlayer insulating film 50, and the source electrode 48 is connected to the n ^{+ -type} through the contact hole 50 e formed in the interlayer insulating film 50. It is electrically connected to the source region 44.

By the way, in each pixel unit 2 of the infrared sensor A of the present embodiment, the source electrode 48 of the MOS transistor 4 and one end of the temperature sensing unit 30 are electrically connected, and the other end of the temperature sensing unit 30 is the reference bias line 5. Is electrically connected. In each pixel portion 2 of the infrared sensor A of the present embodiment, the drain electrode 47 of the MOS transistor 4 is electrically connected to the vertical readout line 7, and the gate electrode 46 is formed continuously and integrally with the gate electrode 46. It is electrically connected to a horizontal signal line 6 made of n-type polysilicon wiring. In each pixel unit 2, a ground electrode 49 made of a metal material (for example, Al—Si) is formed on the p ^{++ type} channel stopper region 42 of the MOS transistor 4. The p ^{++ -type} channel stopper region 42 is electrically connected to a common ground line 8 for element isolation by biasing to a lower potential than the n ⁺ -type drain region 43 and the n ^{+ -type} source region 44. The ground electrode 49 is electrically connected to the p ^{++ type} channel stopper region 42 through a contact hole 50f formed in the interlayer insulating film 50.

  According to the infrared sensor A of the present embodiment described above, since the infrared absorption layer 39 also absorbs infrared rays from the outside, the temperature of the plurality of hot junctions T1 can be made uniform, and the sensitivity can be improved.

  Further, according to the infrared sensor A of the present embodiment, since the self-diagnosis heater unit 139 is provided to warm the hot junction T1 by Joule heat generated by energization, the self-diagnosis heater unit 139 is energized. By measuring the output of the thermopile 30a, it is possible to determine whether or not there is a failure such as disconnection of the thermopile 30a, so that the reliability can be improved and the self-diagnosis heater unit 139 can detect the thermal infrared detection. Since the portion 3 is arranged so as not to overlap the thermopile 30a in the region overlapping the cavity 11 of the silicon substrate 1a as the support substrate, the self-diagnosis heater unit 139 prevents the heat capacity of the hot junction T1 of the thermopile 30a from increasing. It is possible to improve sensitivity and response speed.

  Here, in the infrared sensor A of the present embodiment, the self-diagnosis heater unit 139 also absorbs infrared rays from the outside during normal times when the self-diagnosis is not performed during use. To improve sensitivity. The self-diagnosis when using the infrared sensor A of the present embodiment is periodically performed by a self-diagnosis circuit (not shown) provided in a separate signal processing IC chip (not shown). There is no need to do it automatically.

  Further, in the infrared sensor A of the present embodiment, the thin film structure portion 3 a is provided in parallel along the inner circumferential direction of the cavity portion 11 by a plurality of linear slits 13, and the cavity portion 11 is formed in the thermal infrared detector 3. Compared to the case where each small thin film structure portion 3aa is separated into a plurality of small thin film structure portions 3aa extending inward from the surrounding portion, and a hot junction T1 of the thermopile 30a is provided for each small thin film structure portion 3aa, and an output is taken out for each thermopile 30a. Since all the thermopiles 30a are electrically connected in such a connection relationship that the output change with respect to the temperature change becomes large, the response speed and the sensitivity can be improved, and the self-diagnosis can be performed across all the small thin film structures 3aa. Since the heater unit 139 is formed, all the thermopile 30a of the thermal infrared detecting unit 3 can be self-diagnosed collectively. In addition, in the infrared sensor A of the present embodiment, since the connecting piece 3c that connects adjacent small thin film structure portions 3aa and 3aa is formed, the warpage of each small thin film structure portion 3aa can be reduced, and the structural stability can be reduced. The sensitivity is stabilized.

  In the infrared sensor A of the present embodiment, the n-type polysilicon layer 34, the p-type polysilicon layer 35, the infrared absorption layer 39, the reinforcing layer 39b, and the self-diagnosis heater portion 139 are set to the same thickness. Therefore, the uniformity of the stress balance of the small thin film structure portion 3aa can be improved, the warpage of the small thin film structure portion 3aa can be suppressed, and the variation in sensitivity for each product and the variation in sensitivity for each pixel portion 2 can be reduced. it can.

  Further, in the infrared sensor A of the present embodiment, the heater for self-diagnosis 139 is made of the same material as the n-type polysilicon layer 34 that is the first thermoelectric element or the p-type polysilicon layer 35 that is the second thermoelectric element. Since it is formed, the self-diagnosis heater portion 139 can be formed simultaneously with the first thermoelectric element or the second thermoelectric element, and the cost can be reduced by simplifying the manufacturing process.

  Further, in the infrared sensor A of the present embodiment, a plurality of pixel units 2 each including an infrared absorption unit 33 and a self-diagnosis heater unit 139 are provided in an array on the one surface side of the silicon substrate 1a that is a support substrate. Therefore, it is possible to grasp the variation in sensitivity of the temperature sensing unit 30 of each pixel unit 2 by energizing the self-diagnosis heater unit 139 of each pixel unit 2 during self-diagnosis at the time of manufacture and use. Become.

  In addition, since the infrared sensor A of the present embodiment includes the MOS transistor 4 for reading the output of the temperature sensing unit 30 for each pixel unit 2, the number of output pads Vout can be reduced, and the size and size can be reduced. Cost reduction can be achieved.

  Hereinafter, the manufacturing method of the infrared sensor A of the present embodiment will be briefly described with reference to FIGS.

  First, a first silicon oxide film 31 having a first predetermined film thickness (for example, 0.3 μm) and a silicon nitride film having a second predetermined film thickness (for example, 0.1 μm) are formed on the one surface side of the silicon substrate 1a. An insulating layer forming step for forming an insulating layer made of a laminated film with the insulating film 32 is performed, and thereafter, using the photolithography technique and the etching technique, the insulating layer corresponding to the formation region A1 of the thermal infrared detecting portion 3 is used. The structure shown in FIG. 14A is obtained by performing an insulating layer patterning process in which a part corresponding to the formation region A2 of the MOS transistor 4 is removed while leaving a part of the part. Here, the silicon oxide film 31 is formed by thermally oxidizing the silicon substrate 1a at a predetermined temperature (for example, 1100 ° C.), and the silicon nitride film 32 is formed by LPCVD.

After the above-described insulating layer patterning step, a well region forming step for forming a p ^{+ -type} well region 41 on the one surface side of the silicon substrate 1a is performed, and subsequently, a p ^{+ -type} well on the one surface side of the silicon substrate 1 is performed. By performing a channel stopper region forming step for forming a p ^{++ type} channel stopper region 42 in the region 41, the structure shown in FIG. 14B is obtained. Here, in the well region forming step, the second silicon oxide film (thermal oxide film) 51 is selectively formed by thermally oxidizing the exposed portion on the one surface side of the silicon substrate 1a at a predetermined temperature. The silicon oxide film 51 is patterned using a photolithography technique and an etching technique using a mask for forming the p ^{+ -type} well region 41, and then a p-type impurity (for example, boron) is applied to a predetermined acceleration voltage. The p ^{+ -type} well region 41 is formed by performing ion implantation after ion implantation (for example, 50 keV) and a predetermined dose (for example, 4 × 10 ¹³ cm ⁻² ). Further, in the channel stopper region forming step, a third silicon oxide film (thermal oxide film) 52 is selectively formed by thermally oxidizing the one surface side of the silicon substrate 1a at a predetermined temperature, and thereafter, p ^{++ type} The third silicon oxide film 52 is patterned using a photolithography technique and an etching technique using a mask for forming the channel stopper region 42, and then p-type impurities (for example, boron) are accelerated to a predetermined degree. Ion implantation is performed with a voltage (for example, 50 keV) and a predetermined dose (for example, 3 × 10 ¹² cm ⁻² ), and then drive-in is performed to form the p ^{++ type} channel stopper region 42. The first silicon oxide film 31, the second silicon oxide film 51, and the third silicon oxide film 52 constitute the silicon oxide film 1b on the one surface side of the silicon substrate 1a.

After the above-described channel stopper region forming step, a gate insulating film 45 made of a silicon oxide film (thermal oxide film) having a predetermined film thickness (for example, 600 mm) is formed on the one surface side of the silicon substrate 1a by thermal oxidation. A film forming process is performed, and subsequently, the gate electrode 46, the horizontal signal line 6 (see FIG. 2), the n-type polysilicon layer 34, the p-type polysilicon layer 35, and the infrared ray absorption are formed on the entire surface of the silicon substrate 1a on the one surface side. A polysilicon layer forming step is performed in which a non-doped polysilicon layer 38 having a predetermined film thickness (for example, 0.69 μm) serving as a basis for the layer 39, the reinforcing layer 39b, and the self-diagnosis heater unit 139 is formed by the LPCVD method. The gate electrode 46, the horizontal signal line 6 and the n-type poly-silicon in the non-doped polysilicon layer 38 using photolithography and etching techniques. A polysilicon layer patterning process is performed for patterning so that portions corresponding to the recon layer 34, the p-type polysilicon layer 35, the infrared absorption layer 39, the reinforcing layer 39b, and the self-diagnosis heater portion 139 remain, and then, a non-doped layer is formed. A p-type impurity (for example, boron) is applied to a portion corresponding to the p-type polysilicon layer 35 in the polysilicon layer 38 with a predetermined acceleration voltage (for example, 60 keV) and a predetermined dose (for example, 7.5 × 10 ^15). A structure shown in FIG. 15A is obtained by performing a p-type polysilicon layer forming step of forming the p-type polysilicon layer 35 by performing ion implantation after cm ⁻² ). In this example, the p-type is the first conductivity type, the n-type is the second conductivity type, and the p-type polysilicon layer forming step corresponds to a non-doped region corresponding to the portion constituted by the p-type polysilicon of the thermopile 30a. This constitutes a first conductivity type impurity implantation step for implanting the first conductivity type impurity into the polysilicon layer. Further, in the present embodiment, the impurity concentration of the p-type polysilicon layer 35 is set to 1 × ¹⁰ 18 ^{cm -3,} the figures are exemplary, not particularly limited, 1 × ^{10 18} ~ What is necessary is just to set suitably in the range of about 1 * 10 < ²⁰ > cm <^-3> .

After the above-described p-type polysilicon layer forming step, the n-type polysilicon layer 34, the infrared absorption layer 39, the reinforcing layer 39b, the self-diagnosis heater portion 139, the gate electrode 46, and the horizontal signal line in the non-doped polysilicon layer 38. 6 is performed after an n-type impurity (for example, phosphorus) is ion-implanted into a portion corresponding to 6 with a predetermined acceleration voltage (for example, 60 keV) and a predetermined dose (for example, 1 × 10 ¹⁶ cm ⁻² ). By performing the n-type polysilicon layer forming step of forming the n-type polysilicon layer 34, the infrared absorption layer 39, the reinforcing layer 39b, the self-diagnosis heater portion 139, the gate electrode 46, and the horizontal signal line 6 as shown in FIG. The structure shown in (b) is obtained. In this embodiment, in the n-type polysilicon layer forming step, the n ⁺ -type drain region 43 and the n ^{+ -type} source region 44 are simultaneously formed on the silicon substrate 1a. In short, in this example, the p-type is the first conductivity type and the n-type is the second conductivity type, and the n-type polysilicon layer forming step transfers the second conductivity to the non-doped polysilicon layer 38 corresponding to the infrared absorption layer 39. A second conductivity type impurity ion implantation step for injecting an impurity of a shape, and in the second conductivity type impurity ion implantation step, at least a second conductivity to the non-doped polysilicon layer 38 corresponding to the infrared absorption layer 39 is formed. The implantation of the conductivity type impurity and the implantation of the second conductivity type impurity for forming the source region 44 and the drain region 43 into the silicon substrate 1a are performed simultaneously. In the second conductivity type impurity ion implantation step, not only the non-doped polysilicon layer 38 corresponding to the infrared absorption layer 39 but also the n-type polysilicon layer 34, the reinforcing layer 39b, the self-diagnosis heater portion 139, the gate electrode 46 and the impurity of the second conductivity type are implanted into the non-doped polysilicon layer 38 corresponding to the horizontal signal line 6. In the present embodiment, the impurity concentration of the n-type polysilicon layer 34 is set to 1 × 10 ¹⁸ cm ⁻³ , and the n ^{+ -type} source region 44 and the n ⁺ -type drain region 43 are set to 1 × 10 ¹⁸ cm ⁻³ . Although these are set, these numerical values are merely examples, and are not particularly limited. The former may be set in a range of about 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ , for example, and the latter may be set to 1 ×, for example. What is necessary is just to set in the range of about 10 < ¹⁷ > ^-1 * 10 < ¹⁹ > cm < ^-3 >.

After the p-type polysilicon layer forming step and the n-type polysilicon layer forming step are completed, an interlayer insulating film forming step for forming an interlayer insulating film 50 on the one surface side of the silicon substrate 1a is performed, Contacts for forming the contact holes 50a ₁ , 50a ₂ , 50a ₃ , 50a ₄ , 50d, 50e, 50f (see FIGS. 8, 9, and 11) in the interlayer insulating film 50 by using the lithography technique and the etching technique. By performing the hole forming step, the structure shown in FIG. Here, in the interlayer insulating film formation step, a BPSG film having a predetermined film thickness (for example, 0.8 μm) is deposited on the one surface side of the silicon substrate 1a by the CVD method, and then at a predetermined temperature (for example, 800 ° C.). A planarized interlayer insulating film 50 is formed by reflow.

  After the contact hole forming step, the first connection metal portion 36, the second connection metal portion 37, the drain electrode 47, the source electrode 48, the reference bias line 5, and the vertical are formed on the entire surface of the silicon substrate 1a on the one surface side. A metal film (for example, Al--) having a predetermined film thickness (for example, 2 μm) serving as a basis for the readout line 7, the ground line 8, the common ground line 9, and the pads Vout, Vsel, Vref, Vdd, Gnd and the like (see FIG. 13). A metal film forming step of forming a Si film) by a sputtering method or the like, and then patterning the metal film using a photolithography technique and an etching technique to thereby form the first connecting metal portion 36 and the second connecting metal. Part 37, drain electrode 47, source electrode 48, reference bias line 5, vertical readout line 7, ground line 8, common ground line 9 and pads Vout, Vsel, ref, Vdd, by performing the metal film patterning step of forming a like Gnd, the structure shown in FIG. 16 (b). Etching in the metal film patterning step is performed by RIE. Moreover, the hot junction T1 and the cold junction T2 are formed by performing this metal film patterning process.

  After the metal film patterning step, a PSG film having a predetermined film thickness (for example, 0.5 μm) and a predetermined film thickness (for example, 0 μm) are formed on the one surface side of the silicon substrate 1a (that is, the surface side of the interlayer insulating film 50). The structure shown in FIG. 17A is obtained by performing a passivation film forming step of forming a passivation film 60 made of a laminated film with an NSG film of .5 μm) by the CVD method. Note that the passivation film 60 is not limited to a stacked film of a PSG film and an NSG film, and may be a silicon nitride film, for example.

  After the above-described passivation film forming step, a thermal insulating layer composed of a laminated film of the silicon oxide film 31 and the silicon nitride film 32, a temperature sensitive portion 30 formed on the thermal insulating layer, and a surface side of the thermal insulating layer The above-described small thin film structure portion 3aa is formed by patterning the laminated structure portion of the interlayer insulating film 50 formed so as to cover the temperature sensitive portion 30 and the passivation film 60 formed on the interlayer insulating film 50. By performing the laminated structure portion patterning step, the structure shown in FIG. 17B is obtained. In the laminated structure patterning step, the slits 13 and 14 are formed.

After the laminated structure patterning step described above, a pad opening for forming a pad opening (not shown) for exposing the pads Vout, Vsel, Vref, Vdd, and Gnd using a photolithography technique and an etching technique. Next, a cavity is formed by forming a cavity 11 in the silicon substrate 1a by anisotropically etching the silicon substrate 1a by introducing a predetermined etchant using the slits 13 and 14 as etchant introduction holes. By performing the forming process, an infrared sensor A in which the pixel portions 2 having the structure shown in FIG. 18 are arranged in a two-dimensional array is obtained. Here, the etching in the pad opening forming step is performed by RIE. In the cavity forming step, a TMAH aqueous solution heated to a predetermined temperature (for example, 85 ° C.) is used as the predetermined etchant. However, the etchant is not limited to the TMAH aqueous solution, and other alkaline solutions (for example, EDP) An aqueous solution or the like may be used. In addition, since all the processes until the cavity forming process is completed are performed at the wafer level, a separation process for separating the individual infrared sensors A may be performed after the cavity forming process is completed. Further, as can be seen from the above description, as for the manufacturing method of the MOS transistor 4, a well-known general MOS transistor manufacturing method is adopted, and a thermal oxide film is formed by thermal oxidation, a photolithography technique and etching. patterning the thermal oxide film by techniques, ion implantation of an impurity, by repeating the basic steps of the drive-in (annealing for diffusing impurities), p ⁺ form well region 41, p ⁺⁺ type channel stopper region 42, n ⁺ form drain regions 43 and an n ^{+ -type} source region 44 are formed.

  According to the manufacturing method of the infrared sensor A of the present embodiment described above, it is formed by the polysilicon layer forming step of forming the non-doped polysilicon layer 38 on the one surface side of the silicon substrate 1a and the polysilicon layer forming step. A polysilicon layer patterning step of patterning the non-doped polysilicon layer 38 so that at least portions corresponding to the infrared absorption layer 39, the thermopile 3a, and the gate electrode 46 remain in the non-doped polysilicon layer 38, and polysilicon layer patterning A second conductivity type impurity ion implantation step of implanting a second conductivity type impurity into the non-doped polysilicon layer 38 corresponding to the infrared absorption layer 39 after the step, and in the second conductivity type impurity ion implantation step, At least non-doped poly corresponding to the infrared absorption layer 39 The implantation of the second conductivity type impurity into the recon layer 38 and the implantation of the second conductivity type impurity for forming the source region 44 and the drain region 43 into the silicon substrate 1a are performed at the same time. The infrared absorption layer 39 can be formed without increasing the number of steps as compared with the case where it is not provided, and the manufacturing cost can be reduced while achieving high sensitivity. In the above-described example, the combination of the two types of conductor materials of the thermocouple of the thermopile 30 a is a combination of p-type polysilicon and n-type polysilicon, and the material of the infrared absorption layer 39 is the same as that of the MOS transistor 4. The second conductivity type polysilicon is the same as the second conductivity type source region 44 and the second conductivity type drain region 43 which are separated in the one conductivity type well region 41, and the material of the gate electrode 46 is n-type polysilicon. Although the case of silicon has been described, the present invention is not limited thereto, and the combination of two types of conductor materials of the thermocouple of the thermopile 30a is p-type polysilicon-n-type polysilicon, p-type polysilicon-metal, n-type polysilicon. The combination of any one of the metals and the material of the infrared absorption layer 39 is the well region 4 of the first conductivity type of the MOS transistor 4 The second conductivity type polysilicon is the same as the second conductivity type source region 44 and the second conductivity type drain region 43, and the material of the gate electrode 46 is p-type polysilicon or n-type polysilicon. I just need it.

  Further, in the manufacturing method of the infrared sensor A described above, the first conductivity type is p-type, the second conductivity type is n-type, and the combination of the thermopile 30a is p-type polysilicon-n-type polysilicon, Between the silicon layer patterning step and the second conductivity type impurity ion implantation step, the first conductivity type impurity is implanted into the non-doped polysilicon layer 38 corresponding to the portion of the thermopile 30a constituted by the p type polysilicon. Since the first conductivity type impurity ion implantation step is performed, the first conductivity type impurity ion implantation step is performed after the formation of the second conductivity type source region 44 and the second conductivity type drain region 43 in the manufacture of the infrared sensor A. Compared with the case where the n-type impurity in the source region 44 and the drain region 43 is the n-type impurity in the second conductivity type. Since it is possible to prevent diffusion into the channel formation region between the source region 44 and the drain region 43 in the well region 41 in the thermal process (for example, drive-in) after the formation of the drain region 43 of the fourth and second conductivity types, the MOS transistor 4 can be made shorter and the MOS transistor 4 can be formed with better reproducibility. Here, the combination of the thermopile 30a is not limited to p-type polysilicon-n-type polysilicon, but also in the case of p-type polysilicon-metal, the polysilicon layer patterning step and the second conductivity type impurity ion implantation step Even if the first conductivity type impurity ion implantation step for implanting the first conductivity type impurity into the non-doped polysilicon layer 38 corresponding to the portion constituted by the p-type polysilicon of the thermopile 30a is performed similarly, An effect is obtained.

  In the method of manufacturing the infrared sensor A described above, the first conductivity type is p-type, the second conductivity type is n-type, and the combination of the thermopile 30a is p-type polysilicon-n-type polysilicon. In the two-conductivity-type impurity ion implantation step, the second-conductivity-type impurity is also implanted into the non-doped polysilicon layer 38 corresponding to the portion constituted by the n-type polysilicon of the thermopile 30a. Compared with the case where the implantation of the second conductivity type impurity into the non-doped polysilicon layer 38 corresponding to the portion composed of the n-type polysilicon 30a is performed separately from the second conductivity type impurity ion implantation step. The number can be reduced and the manufacturing cost can be reduced. Here, the combination of the thermopile 30a is not limited to p-type polysilicon-n-type polysilicon, but also in the case of n-type polysilicon-metal, the n-type polysilicon of the thermopile 30a in the second conductivity type impurity ion implantation step. The same effect can be obtained by simultaneously implanting the second conductivity type impurity into the non-doped polysilicon layer 38 corresponding to the portion constituted by the above.

  In the above infrared sensor manufacturing method, the first conductivity type is p-type, the second conductivity type is n-type, and the combination of the thermopile 30a is p-type polysilicon-n-type polysilicon. Between the layer patterning step and the second conductivity type impurity ion implantation step, the first conductivity type impurity is implanted into the non-doped polysilicon layer 38 corresponding to the portion constituted by the p-type polysilicon of the thermopile 30a. In the second conductivity type impurity ion implantation step, the second conductivity type impurity is implanted into the non-doped polysilicon layer 38 corresponding to the portion constituted by the n type polysilicon of the thermopile 30a. Is also performed at the same time, so that the cost can be further reduced.

  By the way, in the infrared sensor A of this embodiment, in addition to the n-type polysilicon layer 34 and the p-type polysilicon layer 35 on the infrared incident surface side of the silicon nitride film 32, an infrared absorption layer 39, a reinforcing layer 39b, a self-diagnosis. Since the heater portion 139 is formed, the silicon nitride film 32 is prevented from being etched and thinned when the n-type polysilicon layer 34 and the p-type polysilicon layer 35 are formed (here, the above-described polysilicon layer). In the patterning step, the silicon nitride film 32 is prevented from being etched and thinned during over-etching when the non-doped polysilicon layer 38 that is the basis of the n-type polysilicon layer 34 and the p-type polysilicon layer 35 is etched). It is possible to improve the uniformity of the stress balance of the thin film structure portion 3a, and the infrared absorbing portion 33 While achieving form a film also becomes possible to prevent warping of the small thin film structure 3aa, thereby improving the sensitivity. Here, the n-type polysilicon layer 34, the p-type polysilicon layer 35, the infrared absorbing layer 39, the reinforcing layer 39b, and the self-diagnosis heater portion 139 are used as the etching solution (for example, TMAH aqueous solution or the like) used in the above-described cavity portion forming step It is necessary to design the shape in plan view so as not to be exposed on the inner surfaces of the slits 13 and 14 in order to prevent etching.

  The infrared sensor A does not necessarily have to be an infrared array sensor having the pixel unit 2 in an array, and may be at least one set including the thermal infrared detection unit 3 and the MOS transistor 4. Good.

DESCRIPTION OF SYMBOLS 1a Silicon substrate 3 Thermal type infrared detection part 4 MOS transistor 11 Cavity part 30a Thermopile 34 n-type polysilicon layer (n-type polysilicon fine wire)
35 n-type polysilicon layer (p-type polysilicon wire)
36 First connection metal portion 37 Second connection metal portion 38 Non-doped polysilicon layer 39 Infrared absorption layer 41 Well region 43 Drain region 44 Source region 46 Gate electrode T1 Hot junction T2 Cold junction

Claims (4)

  A thermal infrared detector that has an infrared absorption layer that absorbs infrared rays and converts it into heat and a thermopile, is formed on one surface side of the silicon substrate and is supported by the silicon substrate, and a thermal type on the one surface side of the silicon substrate. And a MOS transistor for taking out the output of the thermal infrared detector in parallel with the infrared detector, a cavity is formed in the silicon substrate directly below a part of the thermal infrared detector, and 2 of thermopile thermocouples. The combination of the types of conductor materials is any one of p-type polysilicon-n-type polysilicon, p-type polysilicon-metal, and n-type polysilicon-metal, and the material of the infrared absorption layer is a MOS transistor The second conductivity type polysilicon which is the same as the second conductivity type source region and the second conductivity type drain region which are separated in the well region of the first conductivity type A method of manufacturing an infrared sensor, wherein the material of the gate electrode is p-type polysilicon or n-type polysilicon, and a polysilicon layer forming step of forming a non-doped polysilicon layer on the one surface side of the silicon substrate; A polysilicon layer patterning step of patterning the non-doped polysilicon layer so that at least portions corresponding to the infrared absorption layer, the thermopile, and the gate electrode remain among the non-doped polysilicon layer formed in the polysilicon layer forming step; A second conductivity type impurity ion implantation step for injecting a second conductivity type impurity ion into the non-doped polysilicon layer corresponding to the infrared absorption layer after the polysilicon layer patterning step, and the second conductivity type impurity ion implantation step. In at least the non-dough corresponding to the infrared absorption layer Of the second conductivity type impurity into the polysilicon layer and the second conductivity type impurity implantation for forming the source region and the drain region into the silicon substrate are simultaneously performed. Method.   The first conductivity type is p-type, the second conductivity type is n-type, and the combination of the thermopile is either p-type polysilicon-n-type polysilicon or p-type polysilicon-metal, Between the polysilicon layer patterning step and the second conductivity type impurity ion implantation step, the impurity of the first conductivity type is introduced into the non-doped polysilicon layer corresponding to the portion constituted by the p-type polysilicon of the thermopile. 2. The method of manufacturing an infrared sensor according to claim 1, wherein a first conductivity type impurity ion implantation step is performed.   The first conductivity type is p-type, the second conductivity type is n-type, and the combination of the thermopile is either p-type polysilicon-n-type polysilicon or n-type polysilicon-metal, In the second conductivity type impurity ion implantation step, the impurity of the second conductivity type is simultaneously implanted into a non-doped polysilicon layer corresponding to a portion constituted by n-type polysilicon of the thermopile. The manufacturing method of the infrared sensor of Claim 1.   The first conductivity type is p-type, the second conductivity type is n-type, and the combination of the thermopile is p-type polysilicon-n-type polysilicon, and the polysilicon layer patterning step and the second type A first conductivity type impurity ion implantation step of implanting the first conductivity type impurity into the non-doped polysilicon layer corresponding to the portion constituted by the p-type polysilicon of the thermopile between the conductivity type impurity ion implantation step. In the second conductivity type impurity ion implantation step, the second conductivity type impurity is simultaneously implanted into the non-doped polysilicon layer corresponding to the portion of the thermopile made of n type polysilicon. The method for manufacturing an infrared sensor according to claim 1.

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