JP2011035296A - Semiconductor package and method of manufacturing the same, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package, capable of relaxing stress in a connecting terminal part, and also reducing thickness thereof. <P>SOLUTION: A semiconductor package 1A(1) includes, at least: a semiconductor substrate 2 which has an electrode 3 in one surface thereof; a first conductive part 4 (an adhesion layer 4x, a conductive layer 4y) which is disposed on the semiconductor substrate and whose one end is electrically connected to the electrode; a first insulating layer 5 which is disposed so as to cover at least the first conductive part and has an opening α which exposes the other end of the first conductive part; and a second conductive part 6 which is disposed on the first insulating layer and consists of a main pillar part 6a and a beam 6b, and whose cross section is approximately T-shape, wherein the main pillar part is electrically connected to the first conductive part through the opening α. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor package, a manufacturing method thereof, and an electronic device. More specifically, the present invention relates to a semiconductor package, a manufacturing method thereof, and an electronic device that can reduce stress and can be thinned.

  A semiconductor package mounted on a mounting substrate receives not only stress due to mechanical strain from the outside such as impact and vibration, but also thermal stress generated due to a difference in thermal expansion coefficient between the semiconductor package and the mounting substrate. In a semiconductor package such as a wafer level CSP in which a mounting substrate and a semiconductor chip are electrically and mechanically connected via solder bumps, stress is most likely to be concentrated at the joint portion of the solder bumps. For this reason, conventionally, cracks and peeling are likely to occur in the solder bumps and the periphery thereof, and there has been a problem that the device becomes inoperable when the circuit is disconnected or short-circuited.

  For such problems, for example, a copper post is disposed between the solder bump and the semiconductor chip (for example, see Patent Document 1), or a resin core is disposed inside the post (for example, see Patent Document 2). Although attempts have been made to disperse the stress applied to the bumps, many processes are required to realize these structures, which not only increases manufacturing costs, but also limits the materials that can be used. There is a disadvantage that it ends up. Moreover, since the package becomes thicker in any structure, it is disadvantageous for making the package thinner.

JP 2000-200800 A International Publication No. 00/077844 Pamphlet

The present invention has been devised in view of such a conventional situation, and a first object thereof is to provide a semiconductor package that can relieve stress in a connection terminal portion and can be thinned.
A second object of the present invention is to provide a method for manufacturing a semiconductor package that can relieve stress in the connection terminal portion and can manufacture a thin semiconductor package by a simple process.
A third object of the present invention is to provide a highly reliable electronic device including a semiconductor package that can reduce stress in the connection terminal portion and can be thinned.

According to a first aspect of the present invention, there is provided a semiconductor package comprising: a semiconductor substrate having an electrode on one surface; a first conductive portion disposed on the semiconductor substrate and having one end portion electrically connected to the electrode; A first insulating layer that is disposed so as to cover at least one conductive portion and that has an opening α that exposes the other end of the first conductive portion, and is disposed on the first conductive portion exposed by the opening α, The main column portion is composed of a main column portion and a beam portion, and the cross section is substantially T-shaped, and the main column portion includes at least a second conductive portion electrically connected to the first conductive portion through the opening α. It is characterized by that.
According to a second aspect of the present invention, in the semiconductor package according to the first aspect, when the semiconductor package is mounted on the printed board, the second conductive portion is mounted on the printed board as a connection terminal.
The semiconductor package according to claim 3 of the present invention is the semiconductor package according to claim 1 or 2, wherein the second conductive portion and the first conductive portion are connected to each other at the first conductive portion and the semiconductor substrate. And a second insulating layer disposed between the two.
A semiconductor package according to a fourth aspect of the present invention is the film according to any one of the first to third aspects, wherein the surface of the second conductive portion is made of a metal material that is not easily oxidized and has good wettability with solder. It is characterized by being arranged.
According to a fifth aspect of the present invention, there is provided a semiconductor package manufacturing method comprising: a semiconductor substrate having an electrode on one surface; a first conductive portion disposed on the semiconductor substrate and having one end portion electrically connected to the electrode; A first insulating layer that is disposed so as to cover at least the first conductive portion and has an opening α that exposes the other end of the first conductive portion; and on the first conductive portion exposed by the opening α. A second conductive portion that is composed of a main pillar portion and a beam portion, has a substantially T-shaped cross section, and the main pillar portion is electrically connected to the first conductive portion through the opening α. A method of manufacturing a semiconductor package comprising at least a step A for forming a first conductive part having one end electrically connected to the electrode on a semiconductor substrate having an electrode on one side; and the first conductive part At least an opening that exposes the other end of the first conductive portion. forming a first insulating layer having α, and forming a resist layer having an opening β communicating with the opening and exposing the other end of the first conductive portion on the first insulating layer; It includes at least a step C, a step D for forming a second conductive layer in the surface of the resist layer and the openings α and β, and a step E for removing the resist layer.
An electronic device according to a sixth aspect of the present invention includes at least the semiconductor package according to any one of the first to fourth aspects.

The semiconductor package of the present invention includes a second conductive portion having a substantially T-shaped cross section as a connection terminal. Since such a second conductive portion can be easily deformed in the lateral direction, it can relieve stress and is resistant to thermal distortion and drop impact. Thus, according to the present invention, it is possible to provide a semiconductor package that can relieve stress in the connection terminal portion and can be thinned (hereinafter also referred to as “first effect”).
Further, the present invention can provide a method for manufacturing a semiconductor package that can relieve stress at the connection terminal portion and can manufacture a thin semiconductor package by a simple process (hereinafter referred to as “second”). Also called "effect").
Further, in the present invention, since the stress can be relieved in the connection terminal portion and the semiconductor package that can be thinned is provided, a highly reliable electronic device can be provided (hereinafter also referred to as “third effect”). ).

The figure which shows typically an example (1st embodiment) of the semiconductor package of this invention. The figure which shows the example which uses a 2nd electroconductive part as a connection terminal instead of a solder bump. The figure which shows the manufacturing method of the semiconductor package of FIG. 1 in order of a process. The figure which shows the manufacturing method (2nd embodiment) of the semiconductor package of this invention in order of a process. The figure which shows the example which electroplating protruded from the opening part of the 1st resist layer. The figure which shows the manufacturing method (3rd embodiment) of the semiconductor package of this invention in process order. The figure which shows the manufacturing method (4th embodiment) of the semiconductor package of this invention in order of a process. The figure which shows the manufacturing method (5th embodiment) of the semiconductor package of this invention in order of a process. The figure which shows the manufacturing method (6th embodiment) of the semiconductor package of this invention in process order.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a semiconductor package, a manufacturing method thereof, and an electronic device according to the invention will be described with reference to the drawings. The present embodiment is specifically described for better understanding of the gist of the invention, and does not limit the invention unless otherwise specified.

<First embodiment>
FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor package of the present invention.
A semiconductor package 1A (1) of the present invention includes a semiconductor substrate 2 having an electrode 3 on one surface, a first conductive portion 4 disposed on the semiconductor substrate 2 and having one end portion electrically connected to the electrode 3. The first conductive layer 4 is disposed so as to cover at least the first conductive portion 4 and has an opening α that exposes the other end portion of the first conductive portion 4, and the first conductive layer exposed by the opening α. The main pillar portion 6a and the beam portion 6b are arranged on the portion 4 and have a substantially T-shaped cross section. The main pillar portion 6a is electrically connected to the first conductive portion 4 through the opening α. The second conductive portion 6A (6) is provided at least.

  The semiconductor package 1 of the present invention includes a second conductive portion 6 having a substantially T-shaped cross section. In the semiconductor package 1 of the present invention, as shown in FIG. 2, when mounting on the printed circuit board 10, the second conductive portion 6 is mounted on the printed circuit board 10 as a connection terminal instead of the conventional solder bump. Since such a second conductive portion 6 can be easily deformed in the lateral direction, it can relieve stress and is resistant to thermal distortion and drop impact. Thereby, the semiconductor package 1 of the present invention can relieve stress at the connection terminal portion and can be thinned.

  The semiconductor substrate 2 may be a semiconductor wafer such as a silicon wafer, or may be a semiconductor chip obtained by cutting (dicing) the semiconductor wafer into chip dimensions. When the semiconductor substrate 2 is a semiconductor chip, first, a plurality of sets of various semiconductor elements, ICs, induction elements, etc. are formed on a semiconductor wafer, and then a plurality of semiconductor chips are obtained by cutting into chip dimensions. Can do.

  The electrode 3 is an electrode that is electrically connected to an electronic component (not shown) formed on the semiconductor substrate 2. The electrode 3 is made of, for example, a metal having conductivity such as aluminum (Al), copper (Cu), gold (Au), or an alloy containing Al as a main component and Si or Cu added thereto.

The first conductive portion 4 is a rewiring layer that is disposed on the semiconductor substrate 2 via a passivation film (not shown) such as a nitride film and electrically connects the electrode 3 and an electronic component (not shown).
One end of the first conductive portion 4 is electrically connected to the electrode 3. The other end of the first conductive part 4 is electrically connected to the second conductive part 6 through the opening α.

  Such a first conductive part 4 is, for example, copper (Cu), chromium (Cr), aluminum (Al), titanium (Ti), gold (Au), silver (Ag), titanium-tungsten (Ti-W). An alloy or the like is preferably used, and the thickness is preferably 1 to 10 μm. Thereby, sufficient electrical conductivity is obtained. The first conductive portion 4 can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.

The first insulating layer 5 covers a part of the semiconductor substrate 2 and the first conductive part 4, and has an opening α formed at a position aligned with the other end part of the first conductive part 4.
The material of the first insulating layer 5 is preferably a material having high insulation, excellent heat resistance and chemical resistance, strong mechanical strength, and a Young's modulus of 0.1 to 5 GPa. Specifically, polyimide resin, epoxy resin, phenol resin, silicone resin, ABS resin, polybenzoxador resin and the like are preferable. The thickness of the first insulating layer 5 is, for example, 1 to 20 μm.

The second conductive portion 6A (6) includes a main column portion 6a and a beam portion 6b, and has a substantially T-shaped cross section. In addition, the second conductive portion 6 is electrically connected to the first conductive portion 4 at the main pillar portion 6a through the opening α.
The second conductive portion 6 is made of, for example, copper (Cu), chromium (Cr), aluminum (Al), titanium (Ti), gold (Au), silver (Ag), titanium-tungsten (Ti-W) alloy, or the like. The thickness is preferably 1 to 10 μm. Thereby, sufficient electrical conductivity is obtained. The second conductive portion 6 can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.

  In the example shown in FIG. 1, the main column portion 6 a of the second conductive portion 6 </ b> A (6) has a larger diameter on the upper side. However, this is not limited and depends on the manufacturing method. . Moreover, although the side surface of the beam portion 6b of the second conductive portion 6A (6) is slanted, this may be reversed depending on the manufacturing method, and is not limited.

In such a semiconductor package 1A (1), since the second conductive portion 6 can be easily deformed in the lateral direction, the stress can be relieved, and it is resistant to thermal distortion and drop impact. Further, since the second conductive portion 6 is elastically deformed, it is resistant to repeated bending deformation.
Moreover, the area which the 1st electroconductive part 4 and the 2nd electroconductive part 6 connect is small, and the freedom degree of the wiring pattern of the 1st electroconductive part 4 is large. Since the first conductive portion 4 is not connected to the bump, it can be made thinner than the conventional structure and the wiring can be easily miniaturized.
Moreover, since there is only one insulating layer, the manufacturing process is relatively simple.

  In the semiconductor package 1A (1) of the present invention, as shown in FIG. 2, when mounting on the printed circuit board 10, the second conductive portion 6 is mounted on the printed circuit board 10 as a connection terminal instead of the conventional solder bump. To do. Since the structure has no solder bumps in this way, the operation can be performed without worrying about the type of solder paste applied to the printed circuit board 10 side during board mounting. In addition, since the structure has no solder bumps, it is easy to narrow the terminal pitch.

Next, a method for manufacturing such a semiconductor package 1A (1) will be described.
FIG. 3 is a cross-sectional view showing the semiconductor package manufacturing method (first embodiment) of the present invention in the order of steps. FIG. 3 mainly shows the process of forming the second conductive portion 6.
The method for manufacturing a semiconductor package according to the present invention includes a step A for forming a first conductive part 4 having one end electrically connected to the electrode 3 on a semiconductor substrate 2 having an electrode 3 on one side; A step B of forming a first insulating layer 5 having an opening α that covers at least the conductive portion 4 and exposes the other end of the first conductive portion 4, and the opening α on the first insulating layer 5 Forming a resist layer having an opening β that communicates with the first conductive portion 4 and exposes the other end of the first conductive portion 4, and forms a second conductive layer on the surface of the resist layer and in the openings α and β. And a step E of removing the resist layer, at least in order.

In the semiconductor package manufacturing method of the present invention, the stress can be relieved at the connection terminal portion, and the semiconductor package 1 that can be thinned can be manufactured by a simple process.
Hereinafter, each process is explained in full detail in order.

(A1) First, a first conductive portion 4 having one end electrically connected to the electrode 3 is formed on a semiconductor substrate 2 having the electrode 3 on one surface (step A).
The semiconductor substrate 2 is a semiconductor wafer such as silicon or gallium arsenide.
The electrode 3 is an electrode that is electrically connected to an electronic component formed on the semiconductor substrate 2. The electrode 3 is made of, for example, a metal having conductivity such as aluminum (Al), copper (Cu), gold (Au), or an alloy containing Al as a main component and Si or Cu added thereto.

There are an additive method, a semi-additive method, a subtractive method, a lift-off method, and the like as a method for forming the first conductive portion 4, and among these, a semi-additive method capable of easily forming a fine wiring is more preferable.
In the case of the semi-additive method, the first conductive portion 4 includes an adhesion layer 4x and a conductive layer 4y provided thereon.

The adhesion layer 4x is formed to ensure the adhesion between the first conductive portion 4 and the semiconductor substrate 2 and to easily form the first conductive portion 4. Further, it plays a role of suppressing migration between the electrode 3 of the semiconductor substrate 2 and the first conductive portion 4.
The adhesion layer 4x is formed on the one surface 2a of the semiconductor substrate 2 by vapor deposition, sputtering, CVD, or the like. The material is preferably a metal such as chromium, titanium, tungsten, titanium-tungsten, copper, nickel, and more preferably a laminated structure thereof.

Next, a patterned resist layer is formed on the adhesion layer 4x. The resist layer is laminated with a dry film, or varnish is applied by spin coating or screen printing, and then patterned by photolithography.
Next, the conductive layer 4y is formed by an electrolytic plating method. The material is preferably a metal having excellent electrical conductivity and high heat resistance, such as copper, silver, and nickel. Alternatively, an alloy containing these as a main component or a laminated structure thereof may be used. Among them, copper having a low electrical resistivity and relatively inexpensive is most preferable. As for the thickness of the 1st electroconductive part 4, 1-10 micrometers is preferable. Thereafter, the resist is removed, and unnecessary portions of the adhesion layer are removed by wet etching or dry etching.

(A2) Next, as shown in FIG. 3A, a first insulating layer 5 that covers at least the first conductive portion 4 and has an opening α that exposes the other end of the first conductive portion 4 is formed. Form (step B).
Specifically, a polyimide resin, an epoxy resin, a silicon resin (silicone) polybenzoxazole (PBO), a liquid crystal polymer on one surface 2a of the semiconductor substrate 2 by spin coating, laminating, casting, dispensing, or the like. First insulating liquid resin is applied, and then the applied resin layer is exposed and cured to form the first insulating layer 5. Note that an opening α for obtaining an electrical connection between the first conductive portion 4 and the second conductive portion 6 is formed on the other end portion of the first conductive portion 4 of the first insulating layer 5. The dimension of the opening α is preferably 5 to 50% with respect to the diameter of the beam portion of the second conductive portion 6.

  For patterning the photosensitive resin, photolithography, laser processing, plasma etching, and RIE are also possible. In the case of the laminating method, a sheet-shaped resin patterned in advance can be pressure-bonded by the laminating method. Further, a method of directly forming a film and patterning a resin by a screen marking method is also possible. In these cases, the resin does not need to be photosensitive.

(A3) Next, as shown in FIG. 3B, the first insulating layer 5 has a first opening β that communicates with the opening α and exposes the other end of the first conductive portion 4. One resist layer 20A is formed (step C).
Before forming the second conductive portion 6, the first resist layer 20 </ b> A is formed on the first insulating layer 5.
The first resist layer 20A is laminated with a dry film or coated with varnish using a spin coating method or a screen printing method, and then patterned by photolithography.
The thickness of the first resist layer 20A is, for example, 5 to 400 μm. The opening diameter of the opening β is preferably such that the surface of the first resist layer 20A is larger than the bottom surface (that is, the connecting portion side with the first conductive portion 4), and the ratio is preferably 1.1 to 2.0.

(A4) Next, a second conductive portion 6A (6) is formed in the surface of the first resist layer 20A and in the openings α and β (step D).
As a method for forming the second conductive portion 6, there are an additive method, a semi-additive method, a subtractive method, a lift-off method, and the like, and among these, a subtractive method that facilitates the process is more preferable. In the case of the subtractive method, the second conductive portion 6A (6) includes an adhesion layer 6x and a conductive layer 6y provided thereon.

First, the adhesion layer 6x of the second conductive portion 6A (6) is formed on the entire surface of the first resist layer 20A. The formation method, material, and structure of the adhesion layer 6 x may be the same as those of the adhesion layer 4 x of the first conductive portion 4.
Next, as shown in FIG. 3C, the conductive layer 6y of the second conductive portion 6A (6) is formed. The method for forming the conductive layer 6y of the second conductive portion 6A (6) includes vapor deposition, sputtering, CVD, electrolytic plating, and electroless plating, but an electrolytic plating method that can easily form a thick film is preferable. The material and structure may be the same as the formation of the conductive layer 4y of the first conductive portion 4. Moreover, the thickness shall be 5-200 micrometers, for example.

(A5) Next, as shown in FIG. 3D, a second resist layer 21A is formed on the surface of the second conductive portion 6A (6).
The second resist layer 21A is laminated with a dry film or coated with varnish using a spin coating method or a screen printing method, and then patterned by photolithography. The thickness of the second resist layer 21A is, for example, 1 to 50 μm.

  (A6) Next, as shown in FIG. 3E, unnecessary portions of the conductive layer 6y and the adhesion layer 6x of the second conductive portion 6A (6) are removed by wet etching. The adhesion layer 6x may be removed by dry etching.

(A7) Then, as shown in FIG. 3F, the second resist layer 21A and the first resist layer 20A are peeled and removed (step E).
As a result, the second conductive portion 6A (6) is formed.

(A8) After that, a protective film is attached to the wafer surface, the other surface side of the semiconductor substrate 2 is ground or etched to a predetermined thickness, and then the protective film (not shown) is peeled off.
Subsequently, the back surface of the wafer is attached to a dicing tape (not shown) fixed to a ring-shaped frame (not shown), cut into a predetermined size, and separated into individual chips.
As a result, a semiconductor package 1A (1) as shown in FIG. 1 is obtained. The protective film may be peeled after the wafer is attached to a dicing tape (not shown).

  As shown in FIG. 2, the semiconductor package 1A (1) thus formed is mounted on the printed circuit board 10 on which the solder paste 12 is previously applied on the connection terminals 11, and the solder is heated and melted in a nitrogen atmosphere. Thus, it is mounted on the printed circuit board 10. At this time, the surface of the second conductive portion 6 of the semiconductor package 1A (1) facing the connection terminal 11 of the printed circuit board 10 in FIG. 2 is covered with solder, but further to the side surface of the main pillar portion. More preferably, it is covered with solder.

<Second embodiment>
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
FIG. 4 is a cross-sectional view showing the semiconductor package manufacturing method (second embodiment) of the present invention in the order of steps.
In the following description, portions different from the above-described embodiment will be mainly described, and description of portions similar to those of the above-described embodiment will be omitted.
In the manufacturing method of this embodiment, since the formation method of 2nd electroconductive part 6B (6) differs from 1st embodiment mentioned above, here, the formation method of 2nd electroconductive part 6B (6) is demonstrated in order of a process.

  (B1) First, as shown in FIG. 4A, the first conductive portion 4 (adhesion layer 4x, conductive layer 4y) and the second insulating layer 5 are formed on the semiconductor substrate 2 as in the case of the first embodiment. Then, as shown in FIG. 4B, an adhesion layer 6x of the second conductive portion 6B (6) is formed on the entire surface. The material, formation method, and the like of the adhesion layer 6x may be the same as those in the first embodiment.

(B2) Next, as shown in FIG. 4C, the first resist layer 20B is formed on the adhesion layer 6x. The first resist layer 20B is laminated with a dry film or coated with varnish using a spin coating method or a screen printing method, and then patterned by photolithography. The thickness of the first resist layer 20B is preferably 5 to 400 μm.
The shape of the opening β of the first resist layer 20B is such that the diameter on the front surface side is larger than the bottom surface side (that is, the connection portion side with the first conductive portion 4) like the first resist layer 20A in the first embodiment. There is no need, and conversely, it may be small, or the middle part may be large or small. For this reason, the selectivity of the resist material is widened (note that FIG. 4 shows a case where the opening dimensions are uniform).

  (B3) Next, as shown in FIG. 4 (d), a conductive layer 6y of the second conductive portion 6B (6) is formed by electrolytic plating. The material and formation method of the second conductive portion 6B (6) may be the same as in the first embodiment. The electrolytic plating was continued even after protruding from the opening γ of the first resist layer 20B, and ended when the diameter reached a predetermined size.

(B4) Next, as shown in FIG. 4E, the top of the second conductive portion 6B (6) is flattened by polishing or grinding until a predetermined thickness is reached.
(B5) Then, as shown in FIG. 4F, the first resist layer 20B is peeled and removed, and the unnecessary adhesion layer 6x is further removed. Thereby, the second conductive portion 6B (6) is formed.

  In addition to the first effect described above, the semiconductor package 1B (1) thus manufactured is solder-bonded to the upper surface 6B ′ of the beam portion of the second conductive portion 6B (6) (the connection terminal 11 of the printed circuit board 10). Surface) is flat, and the surface oxide film is thin, and there is little concern about contamination that hinders electrical conduction. For this reason, it is possible to reduce the voids in the solder when mounted on the printed circuit board 10, reduce the defective rate in mounting, and improve the reliability after mounting.

<Third embodiment>
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.
5 and 6 are cross-sectional views showing the semiconductor package manufacturing method (third embodiment) of the present invention in the order of steps.
In the following description, portions different from the above-described embodiment will be mainly described, and description of portions similar to those of the above-described embodiment will be omitted.
In the manufacturing method of this embodiment, since the formation method of 2nd electroconductive part 6C (6) differs from 1st embodiment mentioned above, here, the formation method of 2nd electroconductive part 6C (6) is demonstrated in order of a process.

  (C1) First, as shown in FIG. 5A, the first conductive portion 4 (adhesion layer 4x, conductive layer 4y) and the second insulating layer 5 are formed on the semiconductor substrate 2 as in the case of the first embodiment. Then, as shown in FIG. 5 (b), an adhesion layer 6x forming the main pillar portion 6a of the second conductive portion 6C (6) is formed on the entire surface. The material, formation method, and the like of the adhesion layer 6x may be the same as those in the first embodiment.

(C2) Next, as shown in FIG. 5C, a first resist layer 20C is formed on the adhesion layer 6x. The material, formation method, and the like may be the same as those in the first embodiment.
(C3) Next, as shown in FIG.5 (d), the electroconductive layer 6y which makes the main pillar part 6a of the 2nd electroconductive part 6C (6) is formed using an electrolytic plating method. The material and formation method may be the same as in the first embodiment. The electrolytic plating may or may not protrude from the opening of the first resist layer 20C (FIG. 5 shows the case where the protrusion is made).

(C4) Next, as shown in FIG. 5E, an adhesion layer 6z forming the beam portion 6b of the second conductive portion 6C (6) is formed on the entire surface of the conductive layer 6y. The material, formation method, and the like may be the same as those in the first embodiment.
(C5) Next, as shown in FIG. 5F, a second resist layer 21C is formed on the adhesion layer 6z. The material, formation method, and the like may be the same as those in the first embodiment.
(C6) Next, as shown in FIG. 6A, a conductive layer 6y ′ forming the beam portion 6b of the second conductive portion 6C (6) is formed by using an electrolytic plating method. The material, formation method, and the like may be the same as those in the first embodiment.

(C7) Next, as shown in FIG. 6B, the second resist layer 21C is peeled and removed. Further, the unnecessary adhesion layer 6z is removed. The removal method may be the same as in the first embodiment.
(C8) Then, as shown in FIG. 6C, the first resist layer 20C is peeled off and the adhesion layer 6x is removed. Further, the unnecessary adhesion layer 6ax is removed. As a result, the second conductive portion 6C (6) is formed.

  In the semiconductor package 1C (1) thus manufactured, in addition to the first effect described above, the diameter of the beam portion 6b of the second conductive portion 6C (6) is larger than that of the first embodiment or the second embodiment. Since it can be manufactured with high accuracy, it is easy to control the solder covering the solder up to the main pillar portion of the second conductive portion 6C (6) when mounted on the printed circuit board 10, that is, variation can be reduced.

  In addition, since it is possible to easily control whether the shape of the upper surface of the second conductive portion 6C (6) is a convex shape or a concave shape, it is possible to adjust according to a defect when mounted on the printed circuit board 10. For example, if it is a convex type, since this convex part of the 2nd electroconductive part 6b will strongly contact the connection terminal 11 of a board | substrate when it mounts in the printed circuit board 10, an electrical resistance can be made small. Moreover, if it is a concave type, it can prevent that a semiconductor chip is broken by the impact at the time of mounting.

<Fourth embodiment>
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.
FIG. 7 is a cross-sectional view showing the semiconductor package manufacturing method (fourth embodiment) of the present invention in the order of steps.
In the following description, portions different from the above-described embodiment will be mainly described, and description of portions similar to those of the above-described embodiment will be omitted.
In the manufacturing method of this embodiment, since the formation method of 2nd electroconductive part 6D (6) differs from 1st embodiment mentioned above, here, the formation method of 2nd electroconductive part 6D (6) is demonstrated in order of a process.

(D1) First, as shown in FIG. 7A, the first conductive portion 4 (adhesion layer 4x, conductive layer 4y) and the second insulating layer 5 are formed on the semiconductor substrate 2 as in the case of the first embodiment. Then, as shown in FIG. 7B, an adhesive layer 6x that forms the bottom of the main pillar portion 6a of the second conductive portion 6D (6) is formed on the entire surface thereof. The material, formation method, and the like of the adhesion layer 6x may be the same as those in the first embodiment.
(D2) Next, as shown in FIG. 7C, the adhesion layer 6y of the second conductive portion 6D (6) is formed on the entire surface of the adhesion layer 6x. The material, formation method, and the like may be the same as those in the first embodiment.

(D3) Next, as shown in FIG. 7D, a second resist layer 21D is formed on the adhesion layer 6y. The material, formation method, and the like may be the same as those in the first embodiment.
(D4) Next, as shown in FIG. 7E, a conductive layer 6y ′ of the second conductive portion 6D (6) is formed by electrolytic plating. The material, formation method, and the like may be the same as those in the first embodiment.

(D5) Next, the second resist layer 21D is peeled and removed.
Next, the adhesion layer 6y of the second conductive portion 6D (6) is removed. The removal method may be the same as in the first embodiment.
Then, as shown in FIG. 7F, the first resist layer 20D and the adhesion layer 6x are peeled and removed. Thereby, 2nd electroconductive part 6D (6) is formed.

  The semiconductor package 1D (1) thus manufactured has a diameter at the top of the second conductive portion 6D (6) as compared to the first embodiment and the second embodiment, as in the third embodiment. In addition to being able to be manufactured with high accuracy, the number of plating processes is small, so that the process is simple and can be manufactured at low cost.

<Fifth embodiment>
Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.
FIG. 8 is a cross-sectional view showing a configuration example of the semiconductor package 1E (1) of this embodiment.
In the following description, portions different from the above-described embodiment will be mainly described, and description of portions similar to those of the above-described embodiment will be omitted.

In the semiconductor package 1E (1), the second conductive portion 6 and the first conductive portion 4 are connected to each other between the first conductive portion 4 and the semiconductor substrate 2 at a portion where the second conductive portion 6 and the first conductive portion 4 are connected. Two insulating layers 7 are further provided.
The semiconductor substrate 2 is made of a material having a low coefficient of thermal expansion such as silicon, and the first conductive portion 4 is made of a coefficient of thermal expansion such as copper. For this reason, stress due to the difference is generated under the thermal cycle environment, and problems such as separation of the semiconductor substrate 2 and the first conductive portion 4 or cracks in the semiconductor substrate 2 occur, and reliability is increased. It will decrease.

Therefore, in order to avoid this problem, in the present embodiment, the second insulating layer 7 is disposed under the first conductive portion 4. Thereby, the stress resulting from the difference in thermal expansion coefficient between the semiconductor substrate 2 and the first conductive portion 4 can be relaxed, and the reliability can be maintained.
Similar to the first insulating layer 5, the second insulating layer 7 is made of, for example, a polyimide resin, an epoxy resin, or a silicone resin, and can be formed by, for example, a spin coating method, a printing method, a laminating method, or the like. Moreover, it is preferable that the thickness is 0.5-20 micrometers, for example.
In FIG. 8, the second insulating layer 7 is disposed on the entire surface of the semiconductor substrate 2, but if it is formed at least near the portion where the second conductive portion 6 and the first conductive portion 4 are connected. Good.

<Sixth embodiment>
Hereinafter, a sixth embodiment of the present invention will be described with reference to the drawings.
FIG. 9 is a cross-sectional view showing a configuration example of the semiconductor package 1F (1) of the present embodiment.
In the following description, portions different from the above-described embodiment will be mainly described, and description of portions similar to those of the above-described embodiment will be omitted.

In the semiconductor package 1F (1), a film (metal layer 8) made of a metal material which is not easily oxidized and has good wettability with solder is disposed on the surface of the second conductive portion 6.
When the semiconductor package is mounted on the printed circuit board 10, if the second conductive portion 6 is not covered with solder, the surface oxidation proceeds and the electrical resistance increases, or corrosion occurs and the circuit is short-circuited. Failure may occur.

Therefore, in the semiconductor package 1C (1) of the present embodiment, the metal layer 8 that is unlikely to oxidize or corrode and has excellent wettability with solder is disposed on the surface of the second conductive portion 6.
The metal layer 8 is formed using an electroless plating method after the second conductive portion 6 is formed. The material is preferably a layer containing at least one element of nickel, gold, silver, palladium, and tin, and may be a single layer or a plurality of layers. For example, a single layer structure of tin is 1 to 50 μm, or a two layer structure of nickel and gold, and the thickness is 1 to 20 μm for nickel and 0.1 to 5 μm for gold thereon.

  As described above, the semiconductor package 1 of the present invention as described above can be mounted on various substrates to form various electronic devices as in the conventional semiconductor package with solder bumps. Such an electronic device according to the present invention has high reliability because it can relieve stress at the connection terminal portion and can be thinned.

  The semiconductor package, the manufacturing method thereof, and the electronic device of the present invention have been described above. However, the present invention is not limited to this, and can be appropriately changed without departing from the spirit of the invention.

  The present invention is widely applicable to semiconductor packages, manufacturing methods thereof, and electronic devices.

  1A-1F (1) Semiconductor package, 2 Semiconductor substrate, 3 Electrode, 4 1st electroconductive part, 5 1st insulating layer, 6A-6F (6) 2nd electroconductive part, 7 2nd insulating layer, 8 Metal layer.

Claims (6)

A semiconductor substrate having electrodes on one side;
A first conductive part disposed on the semiconductor substrate and having one end electrically connected to the electrode;
A first insulating layer that is disposed to cover at least the first conductive portion and has an opening α that exposes the other end of the first conductive portion;
The first conductive portion is disposed on the first conductive portion exposed by the opening α, and includes a main pillar portion and a beam portion, and has a substantially T-shaped cross section. The main pillar portion passes through the opening α and the first conductive portion. And a second conductive portion electrically connected to the semiconductor package.   2. The semiconductor package according to claim 1, wherein when mounting on a printed circuit board, the second conductive portion is mounted on the printed circuit board as a connection terminal.   In the part where the second conductive part and the first conductive part are connected, the semiconductor device further comprises a second insulating layer disposed between the first conductive part and the semiconductor substrate. The semiconductor package according to claim 1 or 2.   4. The semiconductor package according to claim 1, wherein a coating made of a metal material that is not easily oxidized and has good wettability with solder is disposed on a surface of the second conductive portion. 5. . A semiconductor substrate having an electrode on one surface; a first conductive portion disposed on the semiconductor substrate and having one end electrically connected to the electrode; and disposed to cover at least the first conductive portion; A first insulating layer having an opening α that exposes the other end of one conductive portion, and a first conductive portion exposed by the opening α, and is composed of a main pillar portion and a beam portion, and the cross section is substantially T And a second conductive part electrically connected to the first conductive part through the opening α.
Forming a first conductive portion having one end electrically connected to the electrode on a semiconductor substrate having an electrode on one surface;
Forming a first insulating layer that covers at least the first conductive portion and has an opening α that exposes the other end of the first conductive portion; and
Forming a resist layer having an opening β communicating with the opening and exposing the other end of the first conductive portion on the first insulating layer;
Forming a second conductive layer in the surface of the resist layer and in the openings α and β; and
And a step E of removing the resist layer at least in order.   An electronic device comprising at least the semiconductor package according to claim 1.

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