JP2011023429A - Method of manufacturing semiconductor device, and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that uniformizes device characteristics by a simple process, and to provide a semiconductor integrated circuit device. <P>SOLUTION: The method of manufacturing the semiconductor device includes: a LOCOS oxide film forming step of forming a LOCOS oxide film 70 in a prescribed region 41 on the surface of a semiconductor substrate 40; a polysilicon forming step of forming a polysilicon film 90 so as to cover the boundary between the LOCOS oxide film 70 and the surface of the semiconductor substrate 40; and an ion implantation step in which ions are implanted into the surface of the semiconductor substrate 40 while using the polysilicon film 90 as a mask so as to form an impurity region 60 on the surface of the semiconductor substrate 40. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor integrated circuit device, and more particularly to a semiconductor device manufacturing method and a semiconductor integrated circuit device for manufacturing a semiconductor device by forming a LOCOS oxide film in a predetermined region on the surface of a semiconductor substrate. .

  Conventionally, a semiconductor that forms a device by forming a LOCOS oxide film on the surface of a semiconductor substrate by a LOCOS (Local Oxidation of Silicon) method, and further using a resist to implant ions using the LOCOS oxide film and the resist as a mask. Device manufacturing methods are known.

  FIG. 10 shows an example of a conventional method for manufacturing a semiconductor device. In FIG. 10, an example of a method for manufacturing an NPN transistor will be described. FIG. 10A shows a LOCOS oxide film forming step. The left side is a plan view and the right side is a cross-sectional view. In the LOCOS oxide film forming step, a LOCOS oxide film 170 is formed by a LOCOS method on the surface of the semiconductor substrate 140 on which the N layer 120 is formed on the silicon substrate 110. As shown in the left plan view, a region for forming a device such as a transistor on the surface of the semiconductor substrate 140 is surrounded by a LOCOS oxide film 170.

  FIG. 10B is a diagram showing a base region forming step. The portion where the impurity region is not formed is covered with the resist 200, and the portion where the impurity region is formed is exposed without being covered with the resist 200. With the resist 200 patterned, ions are implanted into the semiconductor substrate 140, and impurities are implanted. For example, boron or the like is used as the ion. Ions are implanted with high energy, and a portion of the LOCOS oxide film 170 is transmitted through the LOCOS oxide film 170 and implanted. In a portion where the LOCOS oxide film 170 is not present, ions are directly implanted into the N layer 120. A portion where ions are implanted becomes a base region 150 into which impurities are implanted. A portion where the LOCOS oxide film 170 is not present and the N layer 120 of the semiconductor substrate 140 is exposed becomes a high concentration base region 151, and a portion under the LOCOS oxide film 170 becomes a low concentration base region 152.

  FIG. 10C is a diagram showing a heat treatment process. In FIG. 10B, after high-energy ion implantation is performed, the resist 200 is removed and the semiconductor substrate 140 is subjected to heat treatment. As a result, thermal diffusion of the base region 150 is performed, and the implanted impurities are diffused in the base region 150, and the concentration distribution of the impurity concentration goes in the direction of averaging, and the base region 150 expands laterally and downward. To do.

  FIG. 10D is a diagram showing a gate oxide film forming process. In the gate oxide film forming step, a gate oxide film 180 is formed in a portion where the high-concentration base region 151 is exposed. As a result, the surface of the high concentration base region 151 is covered with the gate oxide film 180. The gate oxide film 180 means a thin oxide film similar to the gate oxide film 180 in the process of manufacturing a MOS transistor, and does not necessarily mean that a gate is formed in that region.

  FIG. 11 is a diagram showing a continuation process of FIG. 10 in the conventional method for manufacturing a semiconductor device. FIG. 11A shows the emitter region forming step. In the emitter region forming step, a portion where ions are not implanted is covered with the resist 202. On the other hand, if the organic resist 202 is scraped and mixed into the emitter region 160 when ions are implanted, the characteristics of the emitter region 160 are adversely affected. Therefore, the end of the emitter region 160 is ion-doped with the LOCOS oxide film 170 as a mask. Driving is done. For example, phosphorus may be used as the ion. In addition, since the ion implantation is performed in the region where the gate oxide film 180 is formed using the LOCOS oxide film 170 as a mask, the ion implantation is performed with low energy so as to pass through the gate oxide film 180 and not through the LOCOS oxide film 170. Done. By implantation of low energy ions, an emitter region 160 that is also an impurity region is formed on the surface of the base region 150 that is an impurity region.

  FIG. 11B is a diagram showing a heat treatment process. In the heat treatment step, the semiconductor substrate 140 is subjected to heat treatment, and thermal diffusion of the emitter region 160 is performed. As a result, the impurity concentration of the emitter region 160 is averaged, and the emitter region 160 expands laterally and downward. Note that the N layer 120 functions as a collector region and can form an NPN bipolar transistor. Note that the N layer 120 may be formed on a P-type silicon substrate by, for example, epitaxial growth.

  Further, a Bi-CMOS (Complementary Metal Oxide Semiconductor) integrated circuit device in which a MOS (Metal Oxide Semiconductor) transistor and a bipolar transistor are mixedly mounted on the same semiconductor substrate, the bipolar transistor being connected to a base layer, 2. Description of the Related Art A base extraction electrode having an insulator side wall on a side surface, and an emitter electrode extraction opening and an emitter layer formed in a self-aligned manner using the insulator side wall are known (for example, Patent Document 1). reference).

  The side wall of the insulator of the Bi-CMOS integrated circuit device includes the step of forming an insulating film on the base lead electrode and the entire semiconductor substrate including the side surface of the base lead electrode and the emitter forming region surrounded by the base lead electrode. And a step of growing an insulating film of the TEOS film and a step of anisotropically etching the insulating film of the TEOS film to leave a side wall on the side surface of the base extraction electrode on the emitter formation region.

JP-A-11-111873

  However, in the configuration of the prior art shown in FIGS. 10 and 11 described above, the size of the emitter region 114 is affected by the processing accuracy and the film thickness of the LOCOS oxide film 170, and adjacent devices are affected by variations in the emitter region 160. There was a problem that the characteristics of the film became non-uniform. Further, when the size of the emitter region 160 is increased, the size of the high-concentration base region 151 of the base region 150 is reduced, so that a parasitic operation in the lateral direction occurs even though the bipolar transistor is desired to operate in the vertical direction. As a result, there is a problem that transistor characteristics deteriorate and variations occur.

  FIG. 12 is an enlarged view of a portion A in FIG. As shown in FIG. 12, the lateral position of the LOCOS oxide film 170 may vary depending on the processing accuracy. In addition, the end portion of the LOCOS oxide film 170 has a cross-sectional shape with a sharp tip such as the apex of a triangle in which the film thickness decreases toward the outside. With such a shape, the film thickness slightly changes depending on the position of the end portion of the LOCOS oxide film 170 in the lateral direction, and the lateral size of the emitter region 160 is affected and fluctuates accordingly. Similarly, the high-concentration base region 151 into which impurities are implanted by permeation of the LOCOS oxide film 170 is located below the portion of the LOCOS oxide film 170 where the triangular film thickness changes, so that the processing accuracy of the LOCOS oxide film 170 and The film thickness is affected by the impurity concentration.

  Further, the impurity concentration of the high concentration base region 151 affects the diffusion length of the minority carriers injected from the emitter region 160 during the operation of the transistor. On the other hand, since the low concentration base region 152 is implanted through the thick film portion of the LOCOS oxide film 170, the impurity concentration is lower than that of the high concentration base region 151. Further, since the low concentration base region 152 has a low impurity concentration, the diffusion length of the minority carriers is long. As described above, since there is an impurity concentration gradient from the high concentration base region 151 to the low concentration base region 152, the fractional carriers injected into the high concentration base region 151 are efficiently transferred to the low concentration base region 152, and the transistor There is a problem that the parasitic operation in the lateral direction becomes large.

  Furthermore, in the configuration described in Patent Document 1, it is possible to form the emitter region with the sidewall of the oxide film with high accuracy. However, as described above, a complicated process is required, the manufacturing process is complicated, and the cost is increased. There was a problem of being connected. In addition, there are many processes different from the manufacturing process of a normal MOS transistor, and the bipolar transistor cannot be manufactured in the same process as the MOS transistor, leading to an increase in the number of processes.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor integrated circuit device that can make device characteristics uniform by a simple process.

To achieve the above object, a semiconductor device manufacturing method according to a first aspect of the present invention includes a LOCOS oxide film forming step of forming a LOCOS oxide film (70) in a predetermined region (41) on the surface of a semiconductor substrate (40) ,
A polysilicon forming step of forming a polysilicon film (90) so as to cover the boundary between the LOCOS oxide film (70) and the surface of the semiconductor substrate (40);
Using the polysilicon film (90) as a mask, ion implantation is performed on the surface of the semiconductor substrate (40) to form an impurity region (60) on the surface of the semiconductor substrate (40). It is characterized by including.

  Thereby, a polysilicon film with high processing accuracy can be used as a mask, and an impurity region can be formed with high accuracy by a simple manufacturing process.

A second invention is a method of manufacturing a semiconductor device according to the first invention.
A high energy ion implantation step is performed between the LOCOS oxide film formation step and the polysilicon formation step to perform high energy ion implantation that passes through the LOCOS oxide film (70).

  As a result, it can also be used in the manufacturing process of a semiconductor device in which another impurity region is formed on the surface of the impurity region formed by high-energy ion implantation, and high-precision impurity regions can be formed for various semiconductor devices. It can be performed.

A third invention is a method of manufacturing a semiconductor device according to the first or second invention,
The impurity region (60) is an active region of a transistor.

  Accordingly, the active region of the transistor can be formed with high accuracy, and a transistor with favorable characteristics and less variation can be manufactured.

A fourth invention is a method of manufacturing a semiconductor device according to the third invention.
The transistor is a bipolar transistor.

  As a result, a bipolar transistor with good characteristics and less variation can be manufactured.

A fifth invention is a method of manufacturing a semiconductor device according to the fourth invention.
The bipolar transistor is an NPN transistor,
The active region is an emitter region (60).

A sixth invention is a method of manufacturing a semiconductor device according to the fifth invention,
An end of the emitter region (60) is opposite to an end of the LOCOS oxide film (70).

A seventh invention is a method of manufacturing a semiconductor device according to any one of the first to fifth inventions,
In the LOCOS oxide film forming step, a LOCOS oxide film (70) for defining a MOS transistor formation region is further formed outside the predetermined region (41) on the surface of the semiconductor substrate.
In the polysilicon forming step, further forming a gate of the MOS transistor,
In the impurity forming step, a drain region (62) and a source region (63) of the MOS transistor are further formed, and a MOS transistor is simultaneously formed outside the predetermined region.

  As a result, a semiconductor device with good characteristics and less variation can be manufactured without increasing the number of extra steps while utilizing a process for manufacturing a MOS transistor.

An eighth invention is a method of manufacturing a semiconductor device according to the seventh invention, wherein
The MOS transistor is a CMOS.

A semiconductor integrated circuit device according to a ninth invention comprises a reference voltage generating circuit using the transistor according to any one of the third to eighth inventions,
The reference voltage generation circuit is included.

  As a result, a semiconductor integrated circuit device with good characteristics and less variation can be provided.

  Note that the reference numerals in the parentheses are given for easy understanding, are merely examples, and are not limited to the illustrated modes.

  According to the present invention, it is possible to provide a semiconductor device or a semiconductor integrated circuit device having favorable and uniform characteristics.

It is the figure which showed the LOCOS oxide film formation process. FIG. 1A is a plan view of a semiconductor substrate 40 on which a semiconductor device is manufactured. FIG. 1B is a cross-sectional view of the semiconductor substrate 40. It is the figure which showed the high energy ion implantation process. FIG. 2A is a plan view of the bipolar transistor formation region 41. FIG. 2B is a cross-sectional view of the semiconductor substrate 40. It is the figure which showed the heat processing process. FIG. 3A is a plan view of the bipolar transistor formation region 41. FIG. 3B is a cross-sectional view of the semiconductor substrate 40. It is the figure which showed the gate oxide film formation process. FIG. 4A is a plan view of the bipolar transistor formation region 41. FIG. 4B is a cross-sectional view of the semiconductor substrate 10. It is the figure which showed the polysilicon film formation process. FIG. 5A is a plan view of the bipolar transistor formation region 41. FIG. 5B is a cross-sectional view of the semiconductor substrate 40. It is the figure which showed the ion implantation process. FIG. 6A is a plan view of the bipolar transistor formation region 41. FIG. 6B is a cross-sectional view of the semiconductor substrate 40. It is the figure which showed the heat processing process. FIG. 7A is a plan view of the bipolar transistor formation region 41. FIG. 7B is a cross-sectional view of the semiconductor substrate 40. It is the figure which expanded the part of B of FIG.7 (b). It is a figure explaining the operation example of the NPN-type bipolar transistor which concerns on a present Example. It is the figure which showed an example of the manufacturing method of the conventional semiconductor device. FIG. 10A shows a LOCOS oxide film forming step. FIG. 10B is a diagram showing a base region forming step. FIG. 10C is a diagram showing a heat treatment process. FIG. 10D is a diagram showing a gate oxide film forming process. FIG. 11 is a diagram showing a step subsequent to FIG. 10 in the conventional method for manufacturing a semiconductor device. FIG. 11A shows the emitter region forming step. FIG. 11B is a diagram showing a heat treatment process. FIG. 12 is an enlarged view of a portion A in FIG.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  1 to 7 are views showing a series of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

  FIG. 1 is a diagram showing a LOCOS oxide film forming process. FIG. 1A is a plan view of a semiconductor substrate 40 on which a semiconductor device is manufactured, and FIG. 1B is a cross-sectional view of the semiconductor substrate 40.

  In FIG. 1B, the semiconductor substrate 40 includes a silicon substrate 10, an N layer 20, and a P layer 30. A LOCOS oxide film 70 is formed on the surface of the semiconductor substrate 40. The silicon substrate 10 may be a substrate made of another semiconductor material, but in this embodiment, an example using the silicon substrate 10 will be described. For example, the N layer 20 may be formed by epitaxial growth.

  The surface of the semiconductor substrate 40 has a bipolar transistor formation region 41 and a MOS transistor formation region 42. The semiconductor device manufacturing method according to the present embodiment can manufacture a semiconductor device in which an impurity region is formed with high accuracy while utilizing a normal manufacturing process of a MOS transistor. Accordingly, FIGS. 1 to 7 show an example in which an NPN bipolar transistor is manufactured by the method for manufacturing a semiconductor device according to the present embodiment, and an N-channel MOS transistor is formed on the same semiconductor substrate 40. However, since the semiconductor device manufacturing method according to the present embodiment can be used not only for the process of simultaneously manufacturing the MOS transistors but also for the device manufacturing alone, the MOS transistors need not always be manufactured at the same time. .

  As shown in FIG. 1B, in the LOCOS oxide film formation step, a LOCOS oxide film 70 is formed on the surface of the semiconductor substrate 40 by the LOCOS method. The LOCOS oxide film 70 is formed at a position separating the bipolar transistor formation region 41 and the N-channel MOS transistor 42 for element isolation. Further, since the LOCOS oxide film 70 is also used as a mask at the time of ion implantation, it is provided in the bipolar transistor formation region 41 at a position where a high concentration impurity region is not formed. A P layer 30 is provided between the bipolar transistor formation region 41 and the MOS transistor formation region 42 in the vertical direction (depth direction) of the semiconductor substrate 40 in order to perform element isolation.

  FIG. 1A shows a view in which the N layer 20 of the semiconductor substrate 40 is exposed in a region where most of the surface of the semiconductor substrate 10 is covered with the LOCOS oxide film 70 and is not covered with the LOCOS oxide film 70. ing. Thus, in the LOCOS oxide film formation step, the LOCOS oxide film 70 is formed on the surface of the semiconductor substrate 40, and the LOCOS oxide film 70 functions as an element isolation oxide film or a mask. In FIG. 1A, only the surface of the bipolar transistor formation region 41 is shown. Similarly, in FIGS. 2 to 7, only the bipolar transistor formation region 41 is shown in the plan view. .

  The semiconductor substrate 40 can be configured as a substrate made of various semiconductor materials as long as it is a semiconductor material. For example, the semiconductor substrate may be configured as a silicon substrate. Further, in the method for manufacturing a semiconductor device according to the present embodiment, the case where the semiconductor substrate 40 is N-type conductivity will be described as an example.

  FIG. 2 is a diagram showing a high energy ion implantation process. FIG. 2A is a plan view of the bipolar transistor formation region 41, and FIG. 2B is a cross-sectional view of the semiconductor substrate 40.

  FIG. 2B shows a state in which a resist 100 is applied in a film shape on the surface of the semiconductor substrate 40 and ions are implanted. In the high energy ion implantation process, ions as impurities are implanted into the surface of the semiconductor substrate 10 with high energy, and the base region 50 and the P-type well layer 55 are formed. For example, boron may be used as the ion. In this case, a base region 50 and a P-type well layer 55 which are P-type impurity regions are formed on the surface of the N-type semiconductor substrate 10. The resist 100 is selectively formed by patterning so as to cover portions of the semiconductor substrate 40 where the P-type impurity regions 50 and 55 are not formed.

  After the formation of the resist 100, ions are implanted into the semiconductor substrate 40 with high energy to form the base region 50 and the P-type well layer 55. Since the ions are implanted with high energy, the ions pass through the LOCOS oxide film 70, A base region 50 and a P-type well layer 55 are also formed under the LOCOS oxide film 70. The high energy mentioned here means energy that allows ions implanted into the semiconductor substrate 10 to pass through the LOCOS oxide film 70 and form an impurity region under the LOCOS oxide film 70. The energy value can vary depending on the semiconductor substrate 40, the ion material, and the like.

  In the base region 50, a portion where the surface of the semiconductor substrate 40 is not covered with the LOCOS oxide film 70 becomes a high concentration base region 51 having a high impurity concentration. Further, the lower portion of the LOCOS oxide film 70 covered with the LOCOS oxide film 70 becomes a low-concentration base region 52. Similarly, a P-type well layer 55 including a high-concentration P-type well layer 56 and a low-concentration P-type well layer 57 is also formed in the MOS transistor formation region 42.

  In FIG. 2A, a plan view of the bipolar transistor formation region 41 is shown. A resist 100 is formed in a frame shape, and the LOCOS oxide film 70 functioning as a mask and the base region 50 are exposed in the opening 101 of the resist 100.

  FIG. 3 is a diagram showing a heat treatment process. FIG. 3A is a plan view of the bipolar transistor formation region 41, and FIG. 3B is a cross-sectional view of the semiconductor substrate 40.

  In the heat treatment process, after the resist 100 used in the high energy ion implantation process is removed, the semiconductor substrate 40 is subjected to a heat treatment to diffuse the impurities in the base region 50 and the P-type well layer 55, so that the impurity concentration distribution is uniform. Is achieved. Further, in the heat treatment step, the sizes of the base region 50 and the P-type well layer 55 are expanded laterally and downward.

  FIG. 3B shows the semiconductor substrate 40 in a state in which the base region 50 and the P-type well layer 55 are expanded in the lateral direction and the downward direction as compared with FIG. As shown in FIG. 3B, in the portion where the semiconductor substrate 40 is exposed, the high concentration base region 51 and the high concentration P-type well layer 56 are enlarged, and below the LOCOS oxide film 70 are the low concentration base region 52 and The state where the low concentration P-type well layer 57 is enlarged is shown.

  FIG. 3A transparently shows a plan view of the bipolar transistor formation region 41. In addition, the code | symbol in the parenthesis of a reference code has shown the area | region represented transparently. In FIG. 2A, the LOCOS oxide film 70 and the exposed portion of the semiconductor substrate 40 are shown in the portion covered with the resist 100. On the other hand, in FIG. 2A, in the portion corresponding to the opening 101 of the resist 100, the portion where the LOCOS oxide film 70 is not formed becomes the high concentration base region 51, and the portion where the LOCOS oxide film 70 is formed. Is a low-concentration base region 52.

  Thus, the formation region of the base region 50 and the P-type well layer 55 is controlled by the presence or absence of the resist 100, and the impurity concentration in the base region 50 and the P-type well layer 55 is controlled by the presence or absence of the LOCOS oxide film 70. The

  FIG. 4 is a view showing a gate oxide film forming step. FIG. 4A is a plan view of the bipolar transistor formation region 41, and FIG. 4B is a cross-sectional view of the semiconductor substrate 10.

In the gate oxide film forming step, a gate oxide film 80 is formed on the exposed portions of the surface of the base region 50 and the P-type well layer 55. The gate oxide film 80 is a thin oxide film formed in the gate formation region in the MOS transistor manufacturing process. The thin gate oxide film 80 is formed not only in the MOS transistor formation region 42 but also in the bipolar transistor formation region 41. The gate oxide film may be composed of various materials, but may be composed of, for example, a SiO ₂ oxide film.

  Further, since the region where the gate oxide film 80 is formed is a portion where the surface of the semiconductor substrate 40 is exposed where the LOCOS oxide film 70 does not exist, the surface of the N layer 20, the high concentration base region 51 or the high concentration P type well. It becomes one of the layers 56.

  FIG. 4A shows a transparent plan view of the bipolar transistor formation region 41, which is substantially the same as FIG. 4A, the portion of the high-concentration base region 51 and the portion of the semiconductor substrate 40 where the N layer 20 is exposed are covered with a thin gate oxide film 80. The planar configuration is the same as in FIG.

  FIG. 5 is a diagram showing a polysilicon film forming process. FIG. 5A is a plan view of the bipolar transistor formation region 41, and FIG. 5B is a cross-sectional view of the semiconductor substrate 40.

  In the bipolar transistor formation region 41 of FIG. 5B, a polysilicon film 90 is formed so as to cover the boundary between the LOCOS oxide film 70 and the surface of the semiconductor substrate 40. The polysilicon film 90 is used when forming a gate in the MOS transistor manufacturing process. Therefore, in the MOS transistor formation region 42, the polysilicon film 90 is formed as a gate.

  On the other hand, in the bipolar transistor formation region 41, the polysilicon film 90 is formed to be used as a mask. As described with reference to FIG. 12, the end of the LOCOS oxide film 70 has a shape in which the tip becomes thinner and the thickness becomes thinner as the end approaches the tip, and the processing accuracy cannot be made high. Therefore, in the method of manufacturing the semiconductor device according to the present embodiment, the mask is formed with high accuracy using the polysilicon film 90 with high processing accuracy. Therefore, the end portion of the mask is not the LOCOS oxide film 70 but the polysilicon film 90, and the position of the mask end portion can be determined with high accuracy. Polysilicon is originally a material used as the gate of a MOS transistor, and the gate length and gate width of the MOS transistor are controlled with high precision, so that the polysilicon film 90 is formed with high precision processing. It becomes possible enough.

  Thus, instead of the end portion of the LOCOS oxide film 70 having a problem in processing accuracy as a mask, the end portion as a mask is formed of the polysilicon film 90 with high processing accuracy, so that the mask shape can be formed with high accuracy. Can be processed. Therefore, the polysilicon film 90 is formed so as to straddle the surface of the semiconductor substrate 40 and the inclined portion of the LOCOS oxide film 70 so as to cover the boundary between the LOCOS oxide film 70 and the surface of the semiconductor substrate 40. As a result, the minimum polysilicon film 90 can be formed by using the LOCOS oxide film 70 as it is in the central portion where the thickness of the LOCOS oxide film 70 is sufficient to cover the inclined portion of the tip where the processing accuracy is lowered. A functionally sufficient mask effect can be obtained.

  In addition, since the polysilicon film forming process is a process performed in a normal MOS transistor manufacturing process, there is no need to add an extra process to the MOS transistor manufacturing process in order to manufacture a bipolar transistor. A highly accurate mask can be formed with the same number of steps as in the manufacturing process.

  FIG. 5A shows a plan view of the bipolar transistor formation region 11. The planar structure is such that the polysilicon film 90 surrounds the periphery of the high concentration P-type impurity region 51. The other parts are the same as those shown in FIG.

  FIG. 6 is a diagram showing an ion implantation process. FIG. 6A is a plan view of the bipolar transistor formation region 41, and FIG. 6B is a cross-sectional view of the semiconductor substrate 40.

  In FIG. 6B, a resist 102 is selectively formed on the surface of the semiconductor substrate 40 and patterned. An emitter region 60 that is an impurity region is formed on the surface of the high-concentration base region 51 of the base region 50. Similarly, a drain region 62 and a source region 63 are formed on the surface of the P-type well layer 55. In the ion implantation step, ions are implanted on the surface of the region 50 to further form an impurity region. A collector contact region 61 is formed on the surface of the portion where the N layer 20 is exposed in the bipolar transistor formation region 41.

  In the ion implantation process, patterning of the resist 102 is first performed, and a portion where an impurity region is not formed is covered with the resist 102. Next, ions are implanted using the resist 102, the LOCOS oxide film 70, and the polysilicon film 90 as a mask. In this case, since the LOCOS oxide film 70 is used as a part of the mask, ions are implanted with low energy that does not pass through the LOCOS oxide film 70. Further, since the portion not covered with the LOCOS oxide film 70 is covered with the thin gate oxide film 80, the gate oxide film 80 is ion-implanted with a low energy level that allows the gate oxide film 80 to pass therethrough. For example, phosphorus may be used as the ions to be implanted. As a result, the emitter region 60, the collector contact region 61, the drain region 62, and the source region 63 are formed on the surface of the P-type impurity region 50 with N-type conductivity. Note that since the drain region 62 and the source region 63 are the same impurity region, the arrangement may be reversed.

  The shape and size of the emitter region 60 are determined with high accuracy by the polysilicon film 90 functioning as a mask, and the emitter region 60 can be formed with high accuracy. Thereby, the width of the high concentration base region 51 in the base region 50 can be appropriately ensured.

  FIG. 6A shows a plan view of the bipolar transistor formation region 41, but a mask is formed by the resist 102, the LOCOS oxide film 70, and the polysilicon film 90, and ions are implanted into the emitter region 60. It is shown that it is ready to do.

  FIG. 7 is a diagram showing a heat treatment process. FIG. 7A is a plan view of the bipolar transistor formation region 41, and FIG. 7B is a cross-sectional view of the semiconductor substrate 40.

  In the heat treatment step, the semiconductor substrate 40 is heat-treated after removing the resist 102. As a result, as shown in FIG. 7B, the emitter region 60, the collector contact region 61, the drain region 62, and the source region 63 formed on the surface of the semiconductor substrate 40 expand laterally and downward.

  The emitter region 60, the collector contact region 61, the drain region 62, and the source region 63 are thinly formed on the surface of the semiconductor substrate 40 by low energy ion implantation, and compared with the base region 50 and the P-type well layer 55. The layer is considerably thin. Therefore, the lateral expansion amount due to thermal diffusion is considerably smaller than that during thermal diffusion of the base region 50, and does not penetrate significantly into the high-concentration base region 51, and the end portion of the emitter region 60 is sufficiently controlled. Can do.

  Further, the polysilicon film 90 in the bipolar transistor formation region 41 remains on the semiconductor substrate 40 as in the LOCOS oxide film 70, but the emitter region 60 and the base region 50 are separated by the gate oxide film 80. Since it is electrically disconnected and no voltage is applied, the operation of the bipolar transistor is not adversely affected. In the MOS transistor formation region 42, the polysilicon film 90 is formed and functions as a gate.

  FIG. 7A transparently shows a plan view of the bipolar transistor formation region 41, but the emitter region 60 whose surface is covered with the gate oxide film 80 is surrounded by the polysilicon film 90. The state is shown. Further, a state in which the low concentration base region 52 is formed under the LOCOS oxide film 70 is shown. The portion where the high-concentration base region 51 is not covered with the polysilicon film 90 but is covered only with the gate oxide film 80 and exposed is the base contact region. From here, current input to the base is performed.

  As described above, in the method for manufacturing a semiconductor device according to this embodiment, an NPN-type bipolar transistor can be manufactured through the series of steps shown in FIGS.

  FIG. 8 is an enlarged view of a portion B in FIG. In FIG. 8, a boundary portion between the emitter region 60 and the base region 50 of the completed bipolar transistor is shown. As shown in FIG. 8, even if the lateral position of the LOCOS oxide film 70 changes, the mask is formed by the polysilicon film 90, so that the emitter region 60 is not affected by the LOCOS oxide film 70. It can be formed with high accuracy. Thereby, it is possible to avoid the end of the emitter region 60 from biting into the high-concentration base region 51, and a sufficient lateral region of the high-concentration base region 51 can be secured.

  FIG. 9 is a diagram for explaining an operation example of the NPN bipolar transistor according to the present embodiment. In FIG. 9, the NPN-type bipolar transistor preferably has a normal operation in which the minority carrier electrons injected into the emitter region 60 move vertically and pass through the base region 50 and flow into the N layer 20 as the collector region. It is. However, if the width of the high-concentration base region 51 that surrounds the emitter region 60 from the side is small, the fractional carriers flow in the horizontal direction instead of the vertical direction. Further, since the high concentration base region 51 and the low concentration base region 52 have an impurity concentration gradient, the fractional carriers injected into the high concentration base region 51 are efficiently transferred to the low concentration base region 52. That is, a parasitic operation occurs.

  On the other hand, if the width of the high-concentration base region 51 is sufficiently long, it is possible to suppress a state in which minority carriers are injected into the high-concentration base region 51 and further move to the low-concentration base region 52, thereby preventing a parasitic operation. Can do.

  Returning to FIG. As shown in FIG. 8, a polysilicon film 90 with high processing accuracy is formed so as to cover the boundary between the surface of the LOCOS oxide film 70 and the semiconductor substrate 40, and an ion implantation process is performed using this as a mask, thereby forming an emitter region. An end portion 60 is formed so as to face the polysilicon film 90. Further, by defining the area of the emitter region 60 with a mask of the polysilicon film 90 with high processing accuracy, the variation in the area of the emitter region 60 can be suppressed. In addition, by defining and processing the end of the emitter region 60 as designed, the lateral length of the high-concentration base region 51 surrounding the emitter region 60 from the side is increased, and the bipolar transistor is formed in the vertical direction. Can be operated. Thereby, a bipolar transistor having designed characteristics can be obtained. Furthermore, the bipolar transistor can be manufactured using the same process as that of the MOS transistor. Even when the bipolar transistor and the MOS transistor are manufactured on the same semiconductor substrate 40, the semiconductor device can be manufactured efficiently. it can.

  The semiconductor device manufactured by the semiconductor device manufacturing method according to the present embodiment can be used for various electronic circuits, and can be configured as a reference voltage generation circuit, for example. Then, by housing the semiconductor device in a package, it can be configured as a semiconductor integrated circuit device. Thus, the semiconductor integrated circuit device having excellent characteristics in which the impurity regions are formed as designed and there is no variation in characteristics can be obtained.

  In this embodiment, an example in which an NPN bipolar transistor is manufactured as a semiconductor device has been described. However, various semiconductors can be used as long as the semiconductor manufacturing process executes an ion implantation process using the LOCOS oxide film 70 as a mask. It can be applied to the manufacturing process of the device. Further, a CMOS may be manufactured in the MOS transistor formation region 42. Since the CMOS manufacturing process is the same as the MOS transistor manufacturing process, the present embodiment can be similarly applied.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  The present invention can be used for manufacturing processes of semiconductor devices including bipolar transistors and the like, and semiconductor integrated circuit devices using these as devices.

10, 110 Silicon substrate 20, 120 N layer 30 P layer 40, 140 Semiconductor substrate 41 Bipolar transistor formation region 42 MOS transistor formation region 50, 150 Base region 51, 151 High concentration base region 52, 152 Low concentration base region 60, 160 Emitter region 61 Collector contact region 62 Drain region 63 Source region 70, 170 LOCOS oxide film 80, 180 Gate oxide film 90 Polysilicon film 100, 102, 200, 202 Resist

Claims (9)

A LOCOS oxide film forming step of forming a LOCOS oxide film in a predetermined region of the surface of the semiconductor substrate;
A polysilicon film forming step of forming a polysilicon film so as to cover a boundary between the LOCOS oxide film and the surface of the semiconductor substrate;
A method of manufacturing a semiconductor device, comprising: an ion implantation step of implanting ions on the surface of the semiconductor substrate using the polysilicon film as a mask and forming an impurity region on the surface of the semiconductor substrate.   2. The semiconductor according to claim 1, further comprising a high energy ion implantation step of performing high energy ion implantation that passes through the LOCOS oxide film between the LOCOS oxide film formation step and the polysilicon formation step. Device manufacturing method.   The method of manufacturing a semiconductor device according to claim 1, wherein the impurity region is an active region of a transistor.   The method of manufacturing a semiconductor device according to claim 3, wherein the transistor is a bipolar transistor. The bipolar transistor is an NPN transistor,
The method for manufacturing a semiconductor device according to claim 4, wherein the active region is an emitter region.   6. The method of manufacturing a semiconductor device according to claim 5, wherein an end portion of the emitter region is opposed to an end portion of the LOCOS oxide film. Outside the predetermined region on the surface of the semiconductor substrate, in the LOCOS oxide film forming step, a LOCOS oxide film that defines a MOS transistor formation region is further formed,
In the polysilicon film forming step, further forming a gate of the MOS transistor,
6. The semiconductor according to claim 1, wherein, in the impurity forming step, a drain region and a source region of the MOS transistor are further formed, and a MOS transistor is simultaneously formed outside the predetermined region. Device manufacturing method.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the MOS transistor is a CMOS. A reference voltage generation circuit is configured using the transistor according to any one of claims 3 to 8.
A semiconductor integrated circuit device comprising the reference voltage generation circuit.

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