JP2011008493A - System abnormality detection system by watchdog timer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance safety on control of a system by resetting a module as the need arises when resetting a CPU by a watchdog timer.SOLUTION: This system abnormality detection system by the watchdog timer includes: a programmable controller body 1 including the CPU 7 executing a control program; and the module 2 connected to the programmable controller body 1. The programmable controller body 1 includes: the CPU 7 having a watchdog timer function; and a module reset circuit 9 outputting a forcible reset signal to the module. The CPU 7 outputs, to the module reset circuit 9, a determination signal for determining whether or not to forcibly reset the module in time of system abnormality. The module reset circuit 9 resets the module 2 in response to input of the determination signal.

Description

  The present invention relates to an abnormality detection system for a system using a watchdog timer of a CPU with a built-in watchdog timer in the field of a programmable controller system.

  The programmable controller executes a control program written and created in a ladder language by a user, and performs sequence control on control devices such as various machines and devices connected thereto. The programmable controller inputs ON / OFF information of input devices such as switches and sensors corresponding to the state of the control device, executes logical operations according to the control program, and according to the obtained calculation results, relays, valves, The control device is controlled by outputting an ON / OFF information signal to an output device such as an actuator. In this programmable controller, the control program is stored in the program memory, and an instruction on the control program is fetched and executed by the CPU, so that an output from the actuator or the like is output based on an input signal from an input device such as a sensor. An output signal is output to a device to perform sequence control on a control target.

  Such a programmable controller system has a programmable controller main body with a built-in CPU, memory, etc., and a control program for controlling the control device is stored in the memory, and the control program is executed by the CPU. The various modules connected to the programmable controller main body can be controlled.

  Modules include I / O modules and communication modules. An input device and an output device are connected to the I / O module, and signals are input and output between these devices and the programmable controller main body.

  In the programmable controller main body, it is necessary to stop the execution of the control program when an abnormality occurs, for example, the process does not end within a predetermined time due to a malfunction of the control program. In order to monitor the CPU operation, a watchdog timer may be provided.

  The watchdog timer periodically sends a signal to the control program running on the programmable controller system, and if the signal is not sent to the watchdog timer after a certain period, there is a bug in the control program. The CPU is determined to be in a system abnormal state such as a runaway (system runaway), and the CPU is forced to reset, thereby stopping or restarting the program operation. In addition, as a prior art which monitors a system runaway with a watch dog timer, the following patent documents 1-4 can be mentioned, for example.

  As described above, a mode in which the CPU is forcibly reset includes, for example, an instantaneous power failure in addition to an abnormal program operation due to a CPU runaway. Therefore, even if the CPU is forcibly reset, the system user does not know whether the cause is a system abnormality. When the control is resumed by restarting the CPU, there is a high possibility that the control device will be abnormally controlled again via, for example, the I / O module among the functional modules in the system runaway state. Such system control is not preferable.

JP 2007-323631 A Japanese Patent Laid-Open No. 07-104841 Japanese Patent Laid-Open No. 06-324914 Japanese Patent Laid-Open No. 06-250864

  The problem to be solved by the present invention is that, when an abnormality such as a system runaway is detected by the watchdog timer, the module can be reset as necessary so that the system control when the system control is resumed. It is to increase safety.

  The system abnormality detection method according to the present invention is a system including a programmable controller body and a module that is sequence-controlled by the programmable controller body. The programmable controller body executes a control program for controlling the system in sequence. A CPU having a timer function, and a module reset circuit for forcibly resetting the module, wherein the CPU outputs a system abnormal pulse to the module reset circuit when a system abnormality is detected by a watchdog timer function, and a sequence control state A module reset decision signal that determines whether or not to reset the module according to the CPU, and the module reset circuit receives an input from the CPU when a system abnormal pulse is input from the CPU. It is characterized in that to reset the module in accordance with the module reset determination signal to.

  In the present invention, when the CPU outputs a system abnormal pulse by the watchdog timer function, the module reset circuit determines whether to forcibly reset the module according to the module reset determination signal from the CPU. In other words, if it is not necessary to forcibly reset the module from the control state of the control device, the module is not forcibly reset if the CPU outputs a signal indicating that the module is not forcibly reset to the module reset circuit. On the other hand, when it is necessary to forcibly reset the module from the control state of the control device, a module reset determination signal for forcibly resetting the module is output to the module reset circuit to forcibly reset the module.

  As described above, in the present invention, when the system user forcibly resets the CPU due to a system abnormality, and then the control is restarted by restarting the CPU without eliminating the system abnormality, the module is in a sequence control state. Therefore, the devices in the control target can be controlled efficiently and safely. As a result, the system can be safely controlled without hindering the efficiency of system control, which is preferable.

  Here, the programmable controller is not limited to its name, such as a programmable logic controller, a sequencer, or the like, and includes a case where the programmable controller main body incorporating the CPU and the module are separate or integrated. .

  Further, the module is not limited to its name, and can be applied to all devices, units, devices, and the like.

  According to the present invention, when a system abnormality is detected by the watchdog timer, the module controlled by the CPU can be selectively reset as necessary. As a result, in the present invention, the system abnormality is not eliminated, and even when the CPU is restarted, the module is already reset, so there is no possibility that the control target is abnormally controlled. As a result, in the present invention, safety in system control can be improved from system abnormality.

FIG. 1 is a diagram showing a schematic configuration of a programmable controller system according to an embodiment of the present invention. FIG. 2 is a diagram showing a functional block configuration of the CPU in the programmable controller main body.

  Hereinafter, a system abnormality detection method in a programmable controller system according to an embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 shows a schematic configuration of the system. Referring to FIG. 1, this programmable controller system includes a programmable controller main body 1 including a CPU that executes a control program, a plurality of modules 2 connected to the programmable controller main body 1, and a control target 3. .

  The entirety including the programmable controller main body 1 and the module 2 can be referred to as a programmable controller. Module 2 is a module having various intelligent functions such as an I / O module and a communication module. In the embodiment, the module 2 is an I / O module. A control target 3 is connected to the I / O module 2. The control target 3 includes an input device and an output device (not shown) inside, and also includes a machine and equipment that are also control targets (not shown). The programmable controller main body 1 and the I / O module 2 are connected by a bus 4. The control program is a ladder program, but is not limited to this.

  The programmable controller main body 1 includes a program memory 5 that stores a control program, a work memory 6, a CPU 7 that controls the entire system, an I / O interface 8, and a module reset circuit 9.

  The program memory 5 can store a ladder program, a system control program, various application programs, and the like. One of the application programs is a forced reset program for performing a forced reset according to the embodiment. The work memory 6 is a memory used by the CPU 7 for the work. The I / O interface 8 performs an interface between the CPU 7 and the I / O module 2.

  The CPU 7 includes a ladder program execution unit 7a, a watchdog timer unit 7b, and a module reset determination signal output unit 7c, as functionally shown in FIG.

  The ladder program execution unit 7a executes a ladder program stored in the program memory 5. In accordance with the ladder program, the ladder program execution unit 7a inputs and processes input signals related to the control status of the control device from the input device to the control target 3 via the I / O interface 8 and controls the control device. The output signal to be processed is output. In this case, the ladder program execution unit 7a uses the work memory 6 for the work.

  The watchdog timer unit 7b starts monitoring the watchdog timer as the ladder program execution unit 7a starts executing the ladder program. The watchdog timer unit 7b periodically sends a monitoring signal from the ladder program execution unit 7a to monitor whether there is an abnormality in the ladder program execution of the ladder program execution unit 7a. If a monitoring signal is not sent to the watchdog timer unit 7b even after a predetermined period has elapsed from the ladder program execution unit 7a, the watchdog timer unit 7b has a bug in the control program, and the ladder program execution unit 7a is determined to be in a system abnormal state such as runaway (CPU runaway, system runaway), and the system abnormal pulse is output from the terminal WDT to the module reset circuit 9. A reset signal is input from the module reset circuit 9 to the ladder program execution unit 7a via the terminal RST of the CPU 7, whereby the ladder program execution unit 7a resets the execution of the ladder program.

  Then, the watchdog timer unit 7b also outputs the determination result to the module reset determination signal output unit 7c. The module reset determination signal output unit 7c outputs a module reset determination signal from the terminal MWDT to the module reset circuit 9 in response to the input of the determination result. This module reset determination signal is a signal for determining whether to force reset the I / O module 2 or not.

  The module reset circuit 9 includes a holding circuit 9 a that holds a system abnormal pulse, and a forced reset signal output circuit 9 b that outputs a forced reset signal to the I / O module 2. A system abnormal pulse can be input to the holding circuit 9a from the output terminal WDT of the CPU 7. The holding circuit 9a outputs a reset signal in response to the input of the system abnormal pulse. This reset signal is input to the input terminal RST of the CPU 7, and the CPU 7 is reset. The reset signal is input to the forced reset signal output circuit 9b.

  The forced reset signal output circuit 9b receives the reset signal from the holding circuit 9a and responds to the module reset determination signal from the output terminal MWDT of the CPU 7 if it is a signal for forcibly resetting the I / O module 2. The reset signal is input to the I / O module 2. When a module reset determination signal for resetting the I / O module 2 is input from the CPU 7, the forced reset signal output circuit 9 b outputs a reset signal for forcibly resetting it to the I / O module 2. As a result, the I / O module 2 is forcibly reset. In the drawing, the reset signal is input from the forced reset signal output circuit 9b to the I / O module 2 via the bus 4, but the forced reset signal is not shown by a reset signal line (not shown). The output circuit 9b and the I / O module 2 can be connected and input to the I / O module 2 from the forced reset signal output circuit 9b via the reset signal line.

  As described above, in the present embodiment, when a system abnormal pulse is output from the CPU 7 of the programmable controller body 1, the module reset circuit 9 determines whether to forcibly reset the module 2 according to the module determination signal from the CPU 7. . When it is not necessary to forcibly reset the I / O module 2 from the device control state in the control target 3, the CPU 7 outputs a module reset determination signal that does not forcibly reset the I / O module 2 to the module reset circuit 9. / O Module 2 is not forcibly reset. On the other hand, when it is necessary to forcibly reset the I / O module 2 from the device control state, a module reset determination signal for forcibly resetting the I / O module 2 is output to the module reset circuit 9, and the I / O module 2 is Force reset. Thus, in the present embodiment, when the user forcibly resets the CPU 7 due to a system abnormality and then resumes the control by restarting the CPU, the device can be controlled safely.

1 Programmable controller body 5 Program memory 6 Work memory 7 CPU
9 Module reset circuit 2 I / O module 3 Control target 4 Bus

Claims (1)

In a system including a programmable controller body and one or more modules that are sequence-controlled thereby,
The programmable controller body is
A control program for controlling the system in sequence, and a CPU having a watchdog timer function;
A module reset circuit for forcibly resetting the module;
With
The CPU outputs a system abnormality pulse to the module reset circuit when a system abnormality is detected by the watchdog timer function, and outputs a module reset determination signal that determines whether to reset the module according to a sequence control state,
The module reset circuit, when a system abnormal pulse is input from the CPU, resets the module in accordance with a module reset determination signal input from the CPU.

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