JP2011082875A - Band pass filter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-precision band pass filter (BPF) circuit which has center frequency variance that does not depend on element variation but depends only on a crystal oscillation frequency, and a high Q factor. <P>SOLUTION: The BPF circuit 1 includes: a switch 4 which is connected between input and output for changing over an input signal voltage Vi at a system clock frequency fsc; a switched capacitor Cs connected between the switch 4 and a ground potential; a plurality of sample/hold capacitors C connected between the output and the ground potential; and a plurality of sample/hold switches SW0-SWn connected between the output and the ground potential and connected in series to each sample/hold capacitor C. The sample/hold switches SW0-SWn are sequentially turned on one by one at a sampling clock frequency fsac, a signal voltage appearing in the sample/hold capacitor C during a sample time is held, and the sample/hold switches SW0-SWn are sequentially changed over in a cyclic manner. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a bandpass filter (bandpass filter: hereinafter abbreviated as BPF) circuit, and more particularly to a BPF circuit in which an analog discrete circuit technique is applied to an analog BPF used in an electric circuit.

  When configuring a BPF circuit in an electric circuit, a configuration using a passive filter using a resonance circuit characteristic by combining an inductor and a capacitor is generally used. Alternatively, as another configuration method, there is an active filter configuration in which a resistor, a capacitor, and an amplifier are combined.

  By the way, when configuring a BPF circuit in an integrated circuit, when integrating an inductor or a capacitor as a component, values that can be used as values of the inductor and capacitor are still limited to very small values.

  Therefore, when a low frequency analog BPF circuit is realized in an integrated circuit, an active filter is exclusively used.

  However, the values of the resistors and capacitors constituting the active filter change by about ± 20% and ± 15%, respectively, due to process variations and temperature changes. For this reason, in order to construct a high-precision active filter using these components, it is necessary to perform fine adjustment after the integrated circuit is completed by a technique such as trimming, resulting in a large cost burden.

  As another solution, when a switched capacitor (SC) technology for switching a capacitor instead of a resistor is applied to a BPF circuit, the accuracy can be improved greatly.

  That is, the equivalent resistance Re due to SC is represented by Re = 1 / (f × Cso). Here, f indicates a switching frequency, and Cso indicates a switched capacitance.

  For example, the cut-off frequency fc of the first-order low-pass filter using the resistor Ro and the capacitor Co is represented by fc = 1 / (2πRoCo). In this case, if Ro and Co vary, the cut-off frequency fc varies with these products as they are.

  If SC is used and the resistor Ro is replaced with a switching frequency f and a switched capacitor Cso, the cutoff frequency fc is expressed by the following equation. That is, fc = 1 / (2π · Co · (1 / (f · Cso)) = (f / 2π) · (Cso / Co).

  From this equation, when a crystal oscillator is used as an oscillator having the switching frequency f, the frequency variation of the crystal oscillator is a few tens of ppm, so that it should be possible to obtain accuracy with no problem in practice. Since 2π is a constant, the variation in the cutoff frequency fc is determined by the variation in Cso and Co.

  When a BPF circuit is configured by an integrated circuit, elements manufactured by the same manufacturing process vary with the same tendency. For this reason, for example, the variation in (Cso / Co) when an error of Δ% occurs is expressed as Cso (1 ± Δ) / Co (1 ± Δ) = Cs / Co, even if there is a variation in capacitance. Since the error is canceled relatively, theoretically there is almost no variation.

  However, the relative accuracy of a capacitor formed using the current semiconductor process is about 0.1% to 0.2%. For this reason, variation still occurs in the cutoff frequency fc.

  As a method for further improving accuracy, for example, there is a method of sampling an input frequency, storing an amplitude component as a charge amount in a capacitor, passing a specific frequency, and attenuating other frequency components (for example, Patent Document 1 and (See Patent Document 2).

  However, since the circuits disclosed in Patent Document 1 and Patent Document 2 use resistors in the input stage, there is a problem that the value of the quality factor Q changes due to variations in the manufacturing process and changes in resistance due to temperature. There is a point.

  Furthermore, since the resistance value of the input stage is generally on the order of several hundred kΩ to several MΩ, when configured as an integrated circuit, the shape becomes large, and the signal is attenuated due to the distributed capacitance between the substrates. There is also a problem. Therefore, the conventional BPF circuit having a high Q value has a problem that sufficient accuracy cannot be obtained.

Japanese Patent No. 3676527 Japanese Patent No. 3676528

  An object of the present invention is to provide a BPF circuit having a high Q value and a center frequency fluctuation amount that only depends on the frequency variation of a crystal oscillator, regardless of variations in elements constituting an integrated circuit. is there.

  According to one aspect of the present invention, a switch connected between the input and output and switches an input signal voltage at a system clock frequency, a switched capacitor connected between the switch and a ground potential, and between an output and a ground potential A plurality of sample and hold capacitors connected, and a plurality of sample and hold switches connected between an output and a ground potential, and connected in series to each of the sample and hold capacitors; A band-pass filter circuit that is turned on one by one at a clock frequency, holds the signal voltage appearing at the sample time in the sample-and-hold capacitor, and switches the sample-and-hold switch cyclically and sequentially is provided.

  According to the present invention, it is possible to provide a BPF having a center frequency variation only depending on the frequency variation of the crystal oscillator and a high Q value irrespective of variations in elements constituting the integrated circuit. .

The typical circuit block diagram of the band pass filter circuit which concerns on the 1st Embodiment of this invention. Explanatory drawing of the characteristic of the band pass filter circuit which concerns on the 1st Embodiment of this invention. 1 is a schematic block configuration diagram of a clock generation circuit applied to a bandpass filter circuit according to a first embodiment of the present invention. FIG. 4 is a timing chart of signal waveforms used in the clock generation circuit of FIG. 3. 3 is a specific circuit configuration example of the band-pass filter circuit according to the first embodiment of the present invention. 1 is a circuit configuration example used for simulation of a bandpass filter circuit according to a first embodiment of the present invention. FIG. 7 is an operation timing chart of the bandpass filter circuit of FIG. 6. 7 is an operation waveform example of the band-pass filter circuit according to the first embodiment of the present invention, and is an input / output waveform example of the center frequency f0 in the circuit configuration example of FIG. FIG. 7 is an example of an operation waveform of the band-pass filter circuit according to the first embodiment of the present invention, and is an input / output waveform example when +10 kHz away from the center frequency f 0 in the circuit configuration example of FIG. The enlarged view of the output waveform of FIG. 6 is another specific circuit configuration example of the band-pass filter circuit according to the first embodiment of the present invention. The typical block block diagram of the application example which applied the band pass filter circuit which concerns on 1st Embodiment of this invention to the intermediate frequency BPF of the receiver. The typical circuit block diagram of the band pass filter circuit which concerns on the 2nd Embodiment of this invention. 6 is a specific circuit configuration example of a band-pass filter circuit according to a second embodiment of the present invention. The typical circuit block diagram of the band pass filter circuit which concerns on the modification of the 2nd Embodiment of this invention. The specific circuit structural example of the band pass filter circuit which concerns on the modification of the 2nd Embodiment of this invention.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and the relationship, arrangement, size, and the like of the planar dimensions of each circuit element are different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments shown below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention have the following arrangement of circuit elements and the like. It is not something specific. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

(First embodiment)
A schematic circuit configuration of the band-pass filter circuit according to the first embodiment of the present invention is expressed as shown in FIG. The characteristics of the bandpass filter circuit according to the first embodiment are expressed as shown in FIG. 2, for example.

  In FIG. 2, the Q value of the BPF is obtained by Q = f0 / Δf. Here, f0 represents the center frequency, and Δf represents the frequency width in a range where the Q value of the center frequency f0 is reduced by 3 dB.

  As shown in FIG. 1, the band-pass filter circuit 1 according to the first embodiment is connected between the input and output, and switches the input signal voltage Vi at the system clock frequency fsc, and between the switch 4 and the ground potential. A switched capacitor Cs connected to the output, a plurality of sample and hold capacitors C connected between the output and the ground potential, connected between the output and the ground potential, and connected in series to each of the sample and hold capacitors C A plurality of sample and hold switches SW0, SW1, SW2,..., SWn-1, SWn are provided.

  The sample and hold switches SW0, SW1, SW2,..., SWn-1, SWn are sequentially turned on one by one at the sampling clock frequency fsac to hold the output signal voltage Vo appearing at the sample time in the sample and hold capacitor C. Then, the sample and hold switches SW0, SW1, SW2,..., SWn−1, SWn are switched cyclically and sequentially. (N + 1) is the number of switches. The output signal voltage Vo is amplified through a buffer amplifier 3 having a high input impedance to obtain a buffer output voltage Vout.

  As shown in FIG. 3, a schematic block configuration of a clock generation circuit applied to the bandpass filter circuit according to the first embodiment includes a crystal oscillator 10 and an oscillator and counter 12 connected to the crystal oscillator 10. And a sampling clock generation counter 14 connected to the oscillator and counter 12.

  As shown in FIG. 3, the crystal oscillator 10 supplies a crystal oscillation signal Sx having a crystal oscillation frequency fx to the oscillator and the counter 12. The oscillator and counter 12 receives the crystal oscillation signal Sx having the crystal oscillation frequency fx, and outputs the sampling signal Ss having the sampling frequency fs and the system clock signal Ssc having the system clock frequency fsc.

  The sampling clock generating counter 14 receives the sampling signal Ss having the sampling frequency fs from the oscillator and the counter 12, and outputs sampling clock signals S0, S1, S2, S3,..., Sn having the sampling clock frequency fsac.

  A timing chart of signal waveforms used in the clock generation circuit 16 of FIG. 3 is expressed as shown in FIG.

  FIG. 4 shows a crystal oscillation signal Sx having a crystal oscillation frequency fx, a system clock signal Ssc having a system clock frequency fsc, a sampling signal Ss having a sampling frequency fs, and sample / hold switches SW0, SW1, SW2,. The waveforms of sampling clock signals S0, S1, S2,..., Sn-1, Sn that switch -1 and SWn are shown. The waveforms of the sampling clock signals S0, S1, S2,..., Sn-1, Sn are synchronized with the sampling clock frequency fsac. The sampling clock frequency fsac is synchronized with the center frequency f0 of the input signal voltage Vi.

  As the sampling frequency fs, a frequency n times the center frequency f0 is used, which can be generated by a highly stable oscillator such as the crystal oscillator 10.

  As shown in FIG. 4, the sampling signal Ss having the sampling frequency fs is divided by 1 / (n + 1), shifted by one clock, and the sampling clock signals S0, S1, S2, S3 having the sampling clock frequency fsac. ... Sn is generated.

  Sampling clock signals S0, S1, S2, S3,..., Sn are respectively supplied to sample and hold switches SW0, SW1, SW2,..., SWn-1, SWn, and sequentially switch the sample and hold capacitors C. The sampling and holding switches SW0, SW1, SW2,..., SWn-1, SWn by the sampling clock signals S0, S1, S2, S3,..., Sn constitute one cycle every (n + 1) times. In this way, the potential of the sample and hold capacitor C is sampled and held.

  Therefore, if the center frequency f0 of the input signal voltage Vi is completely synchronized with the frequencies of the sampling clock signals S0, S1, S2, S3,..., Sn, the voltage value stored in the sample and hold capacitor C becomes constant, Finally, the voltage equivalent stored in the sample and hold capacitor C is output as the output signal voltage Vo.

  If the center frequency f0 of the input signal voltage Vi does not coincide with the frequency of the sampling clock signals S0, S1, S2, S3,..., Sn, the voltage in the sample and hold capacitor C is canceled and the amplitude is attenuated. That is, the characteristics of the band pass filter can be obtained.

  The Q value according to the configuration of the BPF 1 according to the first embodiment shown in FIG. 1 is expressed by the equation (1) by the equivalent resistance Re = 1 / (fsc × Cs) using the SC technique.

Q = π · f0 · n · C · Re = π · f0 · n · C · / (fsc · Cs)
= Π · n · (f0 / fsc) · (C / Cs) (1)

Here, the frequency for switching the switched capacitor Cs is equal to the system clock frequency fsc. In general, fsc> = fs holds.

  Therefore, when the crystal oscillator 10 having a stable frequency is used for generating the system clock frequency fsc, the variation in the Q value is only the relative variation in the capacitance ratio C / Cs.

  Since the relative variation of the capacitors in the integrated circuit is about ± 0.1% to ± 0.2%, the variation of the Q value becomes very small.

  Further, if fsc = fs is established, the Q value is expressed by equation (2).

Q = π · (f0 / fs) · n · (C / Cs) = π · (C / Cs) (2)

The Q value is simply a value obtained by multiplying the capacitance ratio C / Cs by a constant π. That is, if the BPF circuit 1 having a variable center frequency having the relationship of fsc = fs is configured, the BPF circuit 1 having a constant Q value can be configured regardless of the center frequency f0.

  The system clock frequency fsc and the sampling frequency fs may be supplied from the same clock source. Alternatively, the system clock frequency fsc and the sampling frequency fs may be generated by dividing or multiplying the center frequency f0 of the input signal voltage Vi.

  The system clock frequency fsc and the sampling frequency fs may be asynchronous, but it is desirable to synchronize in consideration of the point that beat noise is likely to occur. That is, it is desirable that the signal sources of these system clock frequency fsc and sampling frequency fs are generated from the same oscillation circuit or the same clock signal input. Alternatively, it is desirable to generate the system clock frequency fsc and the sampling frequency fs by dividing or multiplying the input signal voltage from the center frequency 0.

  Similarly, a phase locked loop (PLL) circuit or a delay locked loop (DLL) circuit is configured using the same clock source to generate an arbitrary system clock frequency fsc and sampling frequency fs. You may use the method.

  As described above, according to the BPF circuit 1 according to the first embodiment, in order to generate the system clock frequency fsc and the sampling and holding sampling frequency fs from the crystal oscillator 10, the crystal oscillator 10 is excluded, A stable center frequency f0 and a high Q value can be obtained without substantially affecting the variation of other passive elements.

  A specific circuit configuration example of the BPF circuit 1 according to the first embodiment is expressed as shown in FIG. 5, the sample and hold switches SW0, SW1, SW2,..., SWn−1, SWn of FIG. 1 are replaced with n-channel MOS transistors Q0, Q1, Q2,. Is composed of n-channel MOS transistors QA and QB. Sampling clock signals S0, S1, S2,..., Sn-1, Sn are supplied to the gates of the n-channel MOS transistors Q0, Q1, Q2,. Gate signals Sc and / Sc synchronized with the system clock signal Ssc are supplied to the gates of the n-channel MOS transistors QA and QB, respectively. The basic operation is the same as that of the BPF circuit 1 of FIG.

  A circuit configuration example used for the simulation of the BPF circuit 1 according to the first embodiment is shown in FIG. In the BPF circuit 1 of FIG. 6, the operation timing chart of the switching signals S0, S1, S2,..., S15 is expressed as shown in FIG.

  In FIG. 6, the sample and hold switches SW0, SW1, SW2,..., SWn-1, SWn of FIG. 1 are replaced with n-channel MOS transistors Q0, Q1, Q2,. Is constituted by analog switches 20 and 22 and an inverter 18. The basic operation is the same as that of the BPF circuit 1 of FIG.

6 and 7, the operating conditions are as follows. That is, the center frequency f0 is 450 kHz, the number of switch stages (n + 1) is 16, the value of the sample and hold capacitor C is 5 pF, the system clock frequency fsc is 7.2 MHz, and the value of the switched capacitor Cs is 0.1 pF. It is. The period Tw of the sampling clock signals S0, S1, S2,..., S15 is 1/450 kHz = 2.22 μsec, and the pulse width Ts is 1 / (450 kHz × 16) = 0.139 μsec. The equivalent resistance Re value at this time is Re = 1 / (7.22 × 10 ⁶ · 0.1 × 10 ⁻¹² ) = 1.39 × 10 ⁶ Ω.

  In the circuit configuration example of FIG. 6, an input / output waveform example of the center frequency f0 is expressed as shown in FIG. As shown in FIG. 8, with respect to the input signal voltage Vi = 300 mVpp, the output signal voltage Vo = 275 mVpp is obtained, and thus the attenuation value is about −0.75 dB.

  In the circuit configuration example of FIG. 6, an example of input / output waveforms when +10 kHz away from the center frequency f0 is expressed as shown in FIG. Further, the waveform of the enlarged output signal voltage Vo is expressed as shown in FIG. As shown in FIGS. 9 and 10, the output signal voltage Vo = 41 mVpp is obtained, and the amount of attenuation is −20 log (41/275) = compared to the output signal voltage Vo = 275 mVpp at the center frequency f0. -16.5 dB.

  The theoretical amount of attenuation L is expressed by equation (3).

L = 20 log {(1+ (Q · G) ² )} (3)

Here, G = (h to (1 / h)) and h = (f0 + Δf) / f0.

  Therefore, if Δf = 10 kHz, the theoretical attenuation is -16.87 dB, which is almost the same as the actual value.

  When further attenuation is required, the BPF circuit 1 according to the first embodiment may be connected in a cascade of several stages. This is because the attenuation is added in dB at each frequency point.

  Another specific circuit configuration example of the BPF circuit 1 according to the first embodiment is expressed as shown in FIG. In FIG. 11, the sample and hold switches SW0, SW1, SW2,..., SWn-1, SWn of FIG. 1 are replaced with n-channel MOS transistors Q0, Q1, Q2,. Is constituted by analog switches 20 and 22 and an inverter 18. Further, the analog switch 20 is composed of a parallel CMOS transfer switch of an n-channel MOS transistor Qn1 and a p-channel MOS transistor Qp1 and an inverter 19 for connecting these gates. Similarly, the analog switch 22 is composed of a parallel CMOS transfer switch of an n-channel MOS transistor Qn2 and a p-channel MOS transistor Qp2 and an inverter 21 for connecting between these gates. The basic operation is the same as that of the BPF circuit 1 of FIG. 1, FIG. 5, or FIG.

(Application examples)
An application example in which the BPF circuit 1 according to the first embodiment is applied to the intermediate frequency BPF of the receiver 7 is expressed as shown in FIG. As shown in FIG. 12, the receiver 7 includes a low noise amplification circuit 24 connected to the antenna 9, a frequency conversion circuit 26 connected to the low noise amplification circuit 24, and a low pass filter connected to the frequency conversion circuit 26. 28, the BPF circuit 1 according to the first embodiment connected to the low-pass filter 28, the intermediate frequency amplifier circuit 30 connected to the BPF circuit 1, the detection circuit 32 connected to the intermediate frequency amplifier circuit 30, A clock generation circuit 16 connected to the crystal oscillator 10, a frequency synthesizer 36 connected to the clock generation circuit 16, and a local oscillation circuit 34 connected to the frequency synthesizer 36 and supplying a local oscillation frequency signal to the frequency conversion circuit 26. With. The clock generation circuit 16 generates a system clock signal Ssc and sampling clock signals S0, S1, S2,..., Sn-1, Sn for the BPF circuit 1.

  The low-pass filter 28 is a low-pass filter that attenuates a frequency component more than twice the center frequency f0 of the BPF circuit 1 according to the first embodiment. Depending on the required characteristics of the BPF circuit 1, the values of the sample-and-hold capacitor C, the switched capacitor Cs, and the number of switch stages n can be adapted. In the BPF circuit 1 according to the first embodiment applied to the receiver 7, since the variation in the BPF characteristics is very small, a complete unadjusted filter can be applied.

  According to the first embodiment, it is possible to provide a high-precision BPF circuit that does not depend on element variations but depends only on the crystal oscillation frequency fx.

  According to the first embodiment, while obtaining a high Q value, it is possible to keep the variation in the center frequency f0 and the Q value very small with respect to the component variation. In particular, by integrating on a single chip, the effect can be exhibited more greatly.

  For example, in the case of an AM radio intermediate frequency filter, if the center frequency is 450 kHz and the passband is ± 3 kHz, ± 0.1% = 1000 ppm when trying to suppress variation in the center frequency within ± 0.5 kHz. The following accuracy is required. Furthermore, a Q value of 75 or more is required, and in view of adjacent interference, a higher Q value is required to increase selectivity. In such a field, the present invention can provide a BPF circuit that operates in a systematic and stable manner.

(Second Embodiment)
A schematic circuit configuration of the band-pass filter circuit according to the second embodiment of the present invention is expressed as shown in FIG.

As shown in FIG. 13, the BPF circuit 2 according to the second embodiment includes a first switch 6 connected between the first input and output, and for switching the first input signal voltage Vi ⁺ at the system clock frequency fsc. a first switched capacitor Cs1 is connected between the ground potential and the first switch 6 is connected between the second input and output, the second input signal voltage Vi ^- second switch for switching the system clock frequency fsc 8, a second switched capacitor Cs2 connected between the second switch 8 and the ground potential, a plurality of sample and hold capacitors C connected between the first output and the second output, and a first output And a plurality of sample and hold switches SW0, SW1, SW2,..., SWn-1, SWn connected in series to each of the sample and hold capacitors C.

  The sample and hold switches SW0, SW1, SW2,..., SWn-1, SWn are sequentially turned on one by one at the sampling clock frequency fsac to hold the signal voltage appearing at the sample time in the sample and hold capacitor C. The sample and hold switches SW0, SW1, SW2,..., SWn−1, SWn are cyclically and sequentially switched.

  In addition, the BPF circuit 2 according to the second embodiment includes a differential amplifier circuit 5 connected between the first output and the second output, as shown in FIG. A differential output voltage Vout is obtained from the output of the differential amplifier circuit 5.

Further, the first switch 6 and the second switch 8 are switched with a phase difference of 180 ° from each other. That is, as shown in FIG. 13, A of A ⁺ terminal and the second switch 8 of the first switch 6 ^- terminal is turned on at the same time, the A ⁺ terminal and the second switch 8 of the first switch 6 a ^- at the same time the terminal is turned off at the same time, B in the B ⁺ terminal of the first switch 6 and a second switch 8 ^- performing a switching operation of the terminal is turned on at the same time.

  A specific circuit configuration example of the BPF circuit 2 according to the second embodiment is expressed as shown in FIG. In FIG. 14, the sample and hold switches SW0, SW1, SW2,..., SWn-1, SWn of FIG. 13 are replaced with n-channel MOS transistors Q0, Q1, Q2,. Is composed of n-channel MOS transistors QA1 and QB1, and the switch 8 is composed of n-channel MOS transistors QA2 and QB2. Sampling clock signals S0, S1, S2,..., Sn-1, Sn are supplied to the gates of the n-channel MOS transistors Q0, Q1, Q2,. The gate signals Sc and / Sc synchronized with the system clock signal Ssc are supplied to the gates of the n-channel MOS transistors QA1 and QB1, respectively. The gates of the n-channel MOS transistors QA2 and QB2 are synchronized with the system clock signal Ssc. The gate signals Sc and / Sc are supplied respectively. The basic operation is the same as that of the BPF circuit 2 of FIG.

  As in the first embodiment, the system clock frequency fsc and the sampling frequency fs may be supplied from the same clock source.

  The system clock frequency fsc and the sampling frequency fs may be generated by dividing or multiplying the center frequency f0 of the first or second input signal voltage.

  Similarly to the first embodiment, the system clock frequency fsc and the sampling frequency fs may be generated using a PLL circuit or a DLL circuit.

  Further, the system clock frequency fsc may be equal to the sampling frequency fs.

  Similarly to FIG. 3, the system clock frequency fsc and the sampling frequency fs are connected to the crystal oscillator 10, receive the crystal oscillation signal Sx having the crystal oscillation frequency fx, and output the sampling signal Ss and the system clock signal Ssc. A sampling clock generated by an oscillator and counter 12 and connected to the oscillator and counter 12 to receive a sampling signal Ss and output sampling clock signals S0, S1, S2,..., Sn-1, S It may be generated by the generation counter 14.

  The first switch 6 and the second switch 8 and the plurality of sample and hold switches SW0, SW1, SW2,..., SWn-1, SWn may all be constituted by p-channel MOS transistors or CMOS transistors. .

(Modification)
A schematic circuit configuration of a band-pass filter circuit according to a modification of the second embodiment is expressed as shown in FIG.

  In the BPF circuit 2 according to the modification of the second embodiment, the first switch 6 and the second switch 8 are switched in the same direction. The operation of switching the first switch 6 and the second switch 8 simultaneously to the input side and then switching to the output side is performed alternately.

That is, as shown in FIG. 15, A of A ⁺ terminal and the second switch 8 of the first switch 6 ^- terminal is turned on at the same time, the A ⁺ terminal and the second switch 8 of the first switch 6 a ^- at the same time the terminal is turned off at the same time, B in the B ⁺ terminal of the first switch 6 and a second switch 8 ^- performing a switching operation of the terminal is turned on at the same time.

That is, the switch 6 and the switch 8 are moved down to the A ⁺ terminal and the A ⁻ terminal side, and the input signal is charged to the first switched capacitor Cs1 and the second switched capacitor Cs2. In the next clock, B ⁺ terminal and B ^- on the terminal side defeat switch 6 and the switch 8, and transmits the charging amount to the sample and hold capacitor C.

  A specific circuit configuration example of the BPF circuit 2 according to the modification of the second embodiment is expressed as shown in FIG. In FIG. 16, the sample and hold switches SW0, SW1, SW2,..., SWn-1, SWn of FIG. 15 are replaced with n-channel MOS transistors Q0, Q1, Q2,. Is composed of n-channel MOS transistors QA1 and QB1, and the switch 8 is composed of n-channel MOS transistors QA2 and QB2. Sampling clock signals S0, S1, S2,..., Sn-1, Sn are supplied to the gates of the n-channel MOS transistors Q0, Q1, Q2,. Gate signals Sc and / Sc synchronized with the system clock signal Ssc are supplied to the gates of the n-channel MOS transistors QA1 and QB1, respectively. The gates of the n-channel MOS transistors QA2 and QB2 are also synchronized with the system clock signal Ssc. The gate signals Sc and / Sc are supplied respectively. The basic operation is the same as that of the BPF circuit 2 in FIG.

  Similar to the second embodiment, the system clock frequency fsc and the sampling frequency fs may be supplied from the same clock source.

  The system clock frequency fsc and the sampling frequency fs may be generated by dividing or multiplying the center frequency f0 of the first or second input signal voltage.

  Similarly to the second embodiment, the system clock frequency fsc and the sampling frequency fs may be generated using a PLL circuit or a DLL circuit.

  Further, the system clock frequency fsc may be equal to the sampling frequency fs.

  Similarly to FIG. 3, the system clock frequency fsc and the sampling frequency fs are connected to the crystal oscillator 10, receive the crystal oscillation signal Sx having the crystal oscillation frequency fx, and output the sampling signal Ss and the system clock signal Ssc. A sampling clock generated by an oscillator and counter 12 and connected to the oscillator and counter 12 to receive a sampling signal Ss and output sampling clock signals S0, S1, S2,..., Sn-1, S It may be generated by the generation counter 14.

  The first switch 6 and the second switch 8 and the plurality of sample and hold switches SW0, SW1, SW2,..., SWn-1, SWn may all be constituted by p-channel MOS transistors or CMOS transistors. .

  The BPF circuit 2 according to the second embodiment and its modification can cancel common mode noise and double the Q value. For example, the present invention can be applied to an application in which only a specific frequency is allowed to pass or a radio receiver.

(Other embodiments)
As described above, the present invention has been described according to the first to second embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  Since the band-pass filter circuit described in the first to second embodiments of the present invention can realize a filter having good phase linearity and flat group delay, it is suitable for a transversal filter. Can be configured easily.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

  The band-pass filter circuit of the present invention can be applied to a wide range of fields such as a radio receiver for AM broadcasting and FM broadcasting, and a narrow band filter, a transversal filter, a digital filter for a radio receiver as a purpose of passing only a specific frequency. It is.

DESCRIPTION OF SYMBOLS 1, 2 ... Band pass filter circuit 3 ... Buffer amplifier 5 ... Differential amplifier 4, 6, 8 ... Switch 7 ... Receiver 9 ... Antenna 10 ... Crystal oscillator 12 ... Oscillator and counter 14 ... Counter 16 for sampling clock generation ... Clock generation circuits 18, 19, 21 ... inverters 20, 22 ... analog switch 24 ... low noise amplifier circuit (LNA)
26 ... Frequency conversion circuit (MIX)
28 ... Low-pass filter (LPF)
30 ... Intermediate frequency amplifier (IFA)
32 ... Detection circuit (DET)
34 ... Local oscillation circuit (LO)
36 ... Frequency synthesizer (SYNTHE)
f0 ... center frequency fx ... crystal oscillation frequency fs ... sampling frequency fsc ... system clock frequency fsac ... sampling clock frequency Sx ... crystal oscillation signal Ss ... sampling signal Ssc ... system clock signals S0, S1, S2, ..., Sn-1, Sn ... sampling clock signal SW0, SW1, SW2, ..., SWn-1, SWn ... sample-hold switch Vi, Vi ^+, Vi ^- ... input signal voltage Vo ... output signal voltage Vout ... output voltage C ... sample and hold capacitor
(n + 1) ... Number of switch stages Cs ... Switched capacitor

Claims (21)

A switch connected between the input and output and switching the input signal voltage at the system clock frequency;
A switched capacitor connected between the switch and a ground potential;
A plurality of sample and hold capacitors connected between the output and ground potential;
A plurality of sample and hold switches connected in series between each of the sample and hold capacitors, the sample and hold switches being sequentially turned on one by one at a sampling clock frequency. The band-pass filter circuit is characterized in that a signal voltage appearing at a sampling time is held in the sample-and-hold capacitor, and the sample-and-hold switch is cyclically and sequentially switched.   The band-pass filter circuit according to claim 1, wherein the system clock frequency and the sampling frequency are supplied from the same clock source.   The band-pass filter circuit according to claim 1, wherein the system clock frequency and the sampling frequency are obtained by dividing or multiplying a center frequency of the input signal voltage.   4. The band-pass filter circuit according to claim 3, wherein the system clock frequency and the sampling frequency are generated using a PLL circuit or a DLL circuit.   The band-pass filter circuit according to claim 1, wherein the system clock frequency is equal to the sampling frequency.   The system clock frequency and the sampling frequency are generated by an oscillator and a counter that are connected to a crystal oscillator, receive a crystal oscillation signal of the crystal oscillation frequency, and output a sampling signal and a system clock signal. 2. The band-pass filter circuit according to claim 1, wherein the band-pass filter circuit is generated by a sampling clock generation counter that is connected to the oscillator and the counter, receives the sampling signal, and outputs a sampling clock signal.   2. The band-pass filter circuit according to claim 1, wherein each of the switch and the plurality of sample / hold switches is composed of a MOS transistor.   The switch includes first and second analog switches connected in series between input and output and switched at a system clock frequency, and an inverter connected between gates of the first and second analog switches. The band-pass filter circuit according to claim 1.   9. The band according to claim 8, wherein each of the first and second analog switches includes a parallel CMOS transfer switch of an n-channel MOS transistor and a p-channel MOS transistor, and an inverter for connecting the gates thereof. Pass filter circuit. A first switch connected between the first input and output and switching the first input signal voltage at a system clock frequency;
A first switched capacitor connected between the first switch and a ground potential;
A second switch connected between the second input and output and for switching the second input signal voltage at the system clock frequency;
A second switched capacitor connected between the second switch and a ground potential;
A plurality of sample and hold capacitors connected between the first output and the second output;
A plurality of sample and hold switches connected in series to each of the sample and hold capacitors, the sample and hold switches sequentially one by one at a sampling clock frequency. A band-pass filter circuit which is turned on, holds a signal voltage appearing at a sample time in the sample-and-hold capacitor, and sequentially switches the sample-and-hold switch cyclically.   The band pass filter circuit according to claim 10, further comprising a differential amplifier circuit connected between the first output and the second output.   The band-pass filter circuit according to claim 10, wherein the first switch and the second switch are switched with a phase difference of 180 ° from each other.   The band-pass filter circuit according to claim 10, wherein the first switch and the second switch are alternately switched to the input side and then simultaneously switched to the output side.   The band-pass filter circuit according to claim 10, wherein the system clock frequency and the sampling frequency are supplied from the same clock source.   The band-pass filter circuit according to claim 10, wherein the system clock frequency and the sampling frequency are obtained by dividing or multiplying a center frequency of the first or second input signal voltage.   The band-pass filter circuit according to claim 12, wherein the system clock frequency and the sampling frequency are generated using a PLL circuit or a DLL circuit.   The band-pass filter circuit according to claim 10, wherein the system clock frequency is equal to the sampling frequency.   The system clock frequency and the sampling frequency are generated by an oscillator and a counter that are connected to a crystal oscillator, receive a crystal oscillation signal of the crystal oscillation frequency, and output a sampling signal and a system clock signal. 11. The band-pass filter circuit according to claim 10, wherein the band-pass filter circuit is generated by a sampling clock generation counter that is connected to the oscillator and the counter, receives the sampling signal, and outputs a sampling clock signal.   11. The band-pass filter circuit according to claim 10, wherein each of the first and second switches and the plurality of sample-and-hold switches is composed of a MOS transistor. A low noise amplifier connected to the antenna;
A frequency conversion circuit connected to the low noise amplifier circuit;
A low pass filter connected to the frequency conversion circuit;
The bandpass filter circuit according to claim 1 connected to the lowpass filter;
An intermediate frequency amplifier circuit connected to the bandpass filter circuit;
A detection circuit connected to the intermediate frequency amplifier circuit;
A clock generator connected to a crystal oscillator;
A frequency synthesizer connected to the clock generation circuit;
A local oscillation circuit connected to the frequency synthesizer and supplying a local oscillation frequency signal to the frequency conversion circuit, and the clock generation circuit generates a system clock signal and a sampling clock signal supplied to the bandpass filter circuit A receiver characterized by that.   A transversal filter circuit comprising the band-pass filter circuit according to claim 1.

Images