JP2011082305A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively suppress a spread of wetting of an underfill resin on a surface of a substrate and to make the size of a semiconductor device small. <P>SOLUTION: The semiconductor device 100 has an insulating layer (104) formed on one surface of the substrate 102 and having an opening for exposing an electrode, and a semiconductor chip 150 mounted on the one surface of the substrate 102 and flip-chip connected to the electrode. Here, an upper surface of the insulating layer includes, at least in an outer circumferential region of the semiconductor chip 150, first unevenness of 0.15 to 1 &mu;m in line roughness measured within a measurement range of 50 &mu;m with a resolution of 0.1 nm using a laser microscope and second unevenness of 100 to 200 nm in average surface roughness measured within a measurement range of 2 &mu;m with a resolution of 0.1 nm in a horizontal (X, Y) direction using an atomic force microscope. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In the application process of underfill resin when mounting a semiconductor chip on a substrate surface such as a multilayer wiring board with a solder resist layer formed on the surface by flip chip connection, the underfill resin spreads over the substrate surface as a whole. There was a problem of popping out locally. For this reason, conventionally, it has been necessary to provide a region where the underfill resin wets and spreads, and there is a problem that the size of the semiconductor device increases.

  In Patent Document 1 (Japanese Patent Laid-Open No. 2001-110825), a semiconductor chip in which a flux is applied to the surface side to which a ball-shaped solder electrode is connected is mounted on a wiring board, and then an underscore is formed between the semiconductor chip and the wiring board. A method for manufacturing a semiconductor device is described in which a cleaning liquid is forcibly sprayed onto a fill resin portion to perform flux cleaning, and then a plasma treatment is performed by exposing the wiring substrate to an oxygen plasma atmosphere. As a result, it is possible to improve the flowability of the resin at the time of injecting the resin into the underfill resin portion, to prevent generation of voids in the underfill resin at the time of resin injection, and to shorten the resin injection time. Has been.

  In Patent Document 2 (Japanese Patent Laid-Open No. 2001-127085), a semiconductor pellet having a large number of electrodes and a conductive pad corresponding to the electrode position of the semiconductor pellet having a planar shape larger than the outer diameter of the semiconductor pellet are formed. The wiring board is opposed to the wiring board by a small distance, the pellet electrode and the conductive pad of the wiring board are electrically connected, and a liquid resin is injected between the semiconductor pellet and the wiring board to cure the resin. In the semiconductor device bonded and integrated, the wiring board has a plasma irradiation surface formed in a region including a conductive pad inward from an intermediate position between the peripheral edge and the semiconductor pellet peripheral edge, and a resin is disposed in the plasma irradiation surface. A semiconductor device characterized by this is described. As a result, the adhesiveness between the semiconductor pellet and the wiring board is good, the amount of the resin supplied in a fixed amount from the semiconductor pellet is stable, and the moisture resistance is good.

JP 2001-110825 A JP 2001-127085 A

  However, even with the techniques described in Patent Document 1 and Patent Document 2, it is difficult to effectively suppress the wetting and spreading of the underfill resin.

According to the present invention,
A substrate having an electrode formed on one surface;
An insulating layer formed on one surface of the substrate and having an opening exposing the electrode;
A semiconductor chip mounted on one surface of the substrate and flip-chip connected to the electrodes;
On the surface of the insulating layer opposite to the surface in contact with the one surface of the substrate, at least in the semiconductor chip outer peripheral region,
First irregularities having a line roughness of 0.15 μm or more and 1 μm or less when measured with a laser microscope at a resolution of 0.1 μm and a measurement range of 50 μm;
An average surface roughness of 100 nm or more and 200 nm or less when measured in a measurement range of 2 μm square with a resolution of 0.1 nm in the horizontal (X, Y) direction using an atomic force microscope on the first unevenness. Two irregularities,
A semiconductor device in which is formed is provided.
Moreover, according to the present invention,
A step of forming first irregularities having a line roughness of 0.15 μm or more and 1 μm or less when measured in a measurement range of 50 μm with a resolution of 0.1 μm on an insulating layer formed on one surface of a substrate When,
An average surface roughness of 100 nm or more and 200 nm or less when measured in a measurement range of 2 μm square with a resolution of 0.1 nm in the horizontal (X, Y) direction using an atomic force microscope on the first unevenness. Forming the two irregularities;
Flip chip connecting a semiconductor chip onto the substrate;
A method for manufacturing a semiconductor device is provided.

  The present inventor has found that when the unevenness in the above range is formed on the surface of the insulating layer, wetting and spreading of the underfill resin can be effectively suppressed. According to this configuration, since the unevenness including the rough first unevenness and the fine second unevenness is formed on the opposite surface of the insulating layer, the underfill resin wets and spreads due to the resistance due to these unevennesses. It suppresses and acts to suppress the spread of wetting and stays with the size of the wetting spread within a certain range. Thereby, the size of the semiconductor device can also be reduced.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, and the like are also effective as an aspect of the present invention.

  According to the present invention, wetting and spreading of the underfill resin on the substrate surface can be effectively suppressed, and the size of the semiconductor device can be reduced.

It is a top view which shows the structure of the step in the middle of manufacture of the semiconductor device in embodiment of this invention. It is sectional drawing which shows the structure of the stage in the middle of manufacture of the semiconductor device in embodiment of this invention. It is sectional drawing of the semiconductor device explaining the manufacture procedure of the semiconductor device in embodiment of this invention. It is sectional drawing of the soldering resist film explaining the manufacturing procedure of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing procedure of the semiconductor device in embodiment of this invention. It is a top view which shows the structure of the semiconductor device in embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing procedure of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing procedure of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing procedure of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing procedure of the semiconductor device in embodiment of this invention. It is a figure which shows the effect of the semiconductor device in embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, similar constituent elements are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  FIG. 1 is a plan view showing a configuration at a stage during the manufacture of the semiconductor device according to the present embodiment. FIG. 2 is a cross-sectional view showing a configuration at a stage during the manufacture of the semiconductor device according to the present embodiment. FIG. 2A is a cross-sectional view taken along the line aa in FIG. FIG. 2B is an enlarged cross-sectional view of a portion surrounded by a broken line in FIG.

  The semiconductor device 100 includes a substrate 102 having an electrode (not shown) formed on one surface, a solder resist film 104 (insulating layer) formed on one surface of the substrate 102 and having an opening exposing the electrode, and one surface of the substrate 102. And a semiconductor chip 150 mounted thereon. The substrate 102 can be a multilayer wiring substrate in which a plurality of wiring layers are connected. In the present embodiment, the semiconductor chip 150 is a flip chip (flip chip, FC) type in which the connection electrodes (bumps) 152 are connected to face the electrodes (not shown) of the substrate 102. Here, the connection electrode 152 may be arranged along the outer periphery of the semiconductor chip 150 (peripheral bump) and may be arranged almost on the entire surface of the semiconductor chip 150 (area bump) in plan view. Here, an example of a peripheral bump will be described.

  Here, in the present embodiment, unevenness is formed on the surface (upper surface in the drawing) opposite to the surface in contact with the substrate 102 of the solder resist film 104. In the present embodiment, in a region that does not overlap with the semiconductor chip 150 in a plan view of the upper surface of the solder resist film 104, that is, in the outer peripheral region of the semiconductor chip 150, finer unevenness (first unevenness) is formed on the rough unevenness (first unevenness) surface. The fine irregularities 104a having the two irregularities) are formed. Further, a rough unevenness 104b in which only rough unevenness is formed is formed at a position overlapping the semiconductor chip 150 in a plan view of the upper surface of the solder resist film 104. The configuration of the fine unevenness 104a and the rough unevenness 104b will be described later.

In the present embodiment, the manufacturing method of the semiconductor device 100 can be manufactured by the following procedure.
A step of forming rough irregularities (first irregularities) on the upper surface of the solder resist film 104;
A step of positioning and mounting the semiconductor chip 150 on an electrode (not shown) on the substrate 102, heating and melting the connection electrodes (bumps) 152 to electrically connect the substrate 102 and the semiconductor chip 150;
A step of forming fine irregularities (second irregularities) having a smaller roughness than the rough irregularities on the rough irregularities; and an underfill resin 120 between the semiconductor chip 150 and the substrate 102 connected on the substrate 102 The process of injection and curing.

  Further, in the step of forming rough unevenness, the rough unevenness can be formed by wet blasting, and in the step of forming fine unevenness, the fine unevenness can be formed by plasma treatment in which plasma is irradiated for a certain period of time. In this embodiment, after the step of forming rough unevenness, the semiconductor chip 150 is mounted on the substrate 102, and in the step of forming fine unevenness, plasma is applied to the surface of the solder resist film 104 using the semiconductor chip 150 as a mask. Can be irradiated. As another example to be described later, in the step of forming fine irregularities, the surface of the solder resist film 104 can be irradiated with plasma in a state where a portion where the semiconductor chip 150 is mounted is covered with a mask.

  Next, with reference to FIG. 3 and FIG. 4, a specific manufacturing procedure of the semiconductor device 100 in the present embodiment will be described. FIG. 3 is a cross-sectional view of the semiconductor device 100 showing a configuration at a stage during the manufacture of the semiconductor device 100 according to the present embodiment. FIG. 4 is a cross-sectional view of the solder resist film 104 showing a configuration at a stage during the manufacture of the semiconductor device according to the present embodiment.

  First, a solder resist film 104 having an opening exposing an electrode (not shown) formed on the one surface is formed on one surface of the substrate 102. At this time, the top surface of the solder resist film 104 is not formed with unevenness such as fine unevenness 104a and rough unevenness 104b except for unevenness formed unintentionally in the manufacturing process (FIG. 4A). In FIG. 4A, the upper surface of the solder resist film 104 is shown to be substantially flat.

  Subsequently, a process for roughening the upper surface of the solder resist film 104 is performed on the entire surface of the substrate 102 by, for example, a wet blast method using a polishing liquid 110 (FIG. 3A). This treatment can be the same as the wet blast treatment generally used for the purpose of removing residues and improving interlayer adhesion in the manufacturing process of the substrate 102, for example. Thereby, rough unevenness 104b having a rough roughness is formed on the surface of the solder resist film 104 (FIG. 4B).

  Next, the semiconductor chip 150 is mounted on the solder resist film 104. At this time, Flip Chip (Flip Chip, FC) connection is performed in which the connection electrode 152 of the semiconductor chip 150 is connected to face the electrode exposed on one surface of the substrate 102 (FIG. 3B).

  Thereafter, the entire surface of the substrate 102 is irradiated with plasma 112 (FIG. 3C). At this time, as will be described later, if the irradiation time of the plasma 112 is too short, impurities on the surface of the solder resist film 104 are simply removed, and fine irregularities are not formed, so that the underfill resin 120 is wetted and spread. There is a risk that it cannot be stopped. Therefore, it is necessary to irradiate the plasma 112 for a time sufficient to form fine irregularities 104a having a desired roughness range described later on the surface of the solder resist film 104. As a result, the upper surface of the solder resist film 104 is further roughened, finer irregularities are formed on the rough irregularities 104b, and fine irregularities 104a are formed (FIG. 4C). This treatment can be the same as the plasma treatment generally used for surface cleaning and resin adhesion improvement before applying the underfill resin. Thereby, it can also process simultaneously with a washing process.

  At this time, in the region where the semiconductor chip 150 is mounted on the upper surface of the solder resist film 104, the semiconductor chip 150 serves as a mask, so that the influence of the plasma 112 irradiation becomes smaller than the outside. Therefore, as shown in FIG. 2, in the upper surface of the solder resist film 104, in the region that overlaps the semiconductor chip 150 in plan view, the rough unevenness 104b remains rough and does not overlap the semiconductor chip 150, that is, the semiconductor chip. In the outer peripheral region 150, fine irregularities 104a in which finer irregularities are formed are formed. In other words, in the present embodiment, on the upper surface of the solder resist film 104, rough rough unevenness 104b is formed on the inner periphery of the connection electrode 152 of the semiconductor chip 150, and fine including rough unevenness and fine unevenness on the outer periphery of the connection electrode 152. Unevenness 104a is formed.

Here, the fine irregularities 104a are
First irregularities having a line roughness of 0.15 μm or more and 1 μm or less when measured in a measurement range of 50 μm with a resolution of 0.1 μm using a laser microscope;
An average surface roughness of 100 nm or more and 200 nm when measured in a measurement range of 2 μm square with a resolution of 0.1 nm in the horizontal (X, Y) direction using an atomic force microscope (AFM) (measurement condition 2). It can be set as the structure containing the following 2nd unevenness | corrugations.

Here, the measurement of the measurement condition 1 can be performed under the following conditions using, for example, a laser microscope.
Measuring device: VK-9500 (Keyence Corporation)
Measurement conditions: x3000 field of view, weighted average ± 8 smoothing treatment Measurement area: 50 μm / line roughness measurement Measurement resolution: 0.02 μm

Moreover, the measurement of the measurement condition 2 can be performed on condition of the following using AFM, for example.
Measuring device: L-traceII / NanoNavi station (SII-NT)
Measurement conditions: SIS mode scanner, 90 μm piezo element measurement area: 2 μm ² / average surface roughness (Ra) measurement measurement resolution: 0.01 nm

  On the other hand, the rough unevenness 104b can be configured to have a rougher surface roughness than the fine unevenness 104a. The rough unevenness 104b is a first in which the line roughness when measured with a laser microscope at a resolution of 0.1 μm in a measurement range of 50 μm (measurement condition 1) is 0.15 μm or more and 1 μm or less in the same manner as the fine unevenness 104a. It can be set as the structure which has an unevenness | corrugation. However, the rough unevenness 104b is an average when measured in a measurement range of 2 μm square with a resolution of 0.1 nm in the horizontal (X, Y) direction using an atomic force microscope (AFM) (measurement condition 2). The surface roughness is not included in the second unevenness of 100 nm to 200 nm.

  Next, the application process of the underfill resin 120 will be described. FIG. 5 is a cross-sectional view showing a procedure for applying the underfill resin 120. First, the underfill resin 120 is supplied from the needle 200 (FIG. 5A). At this time, the underfill resin 120 is dropped on the outer periphery of the connection electrode 152 of the semiconductor chip 150 on the upper surface of the solder resist film 104.

  Here, in this embodiment, the upper surface of the solder resist film 104 is uneven, and the difference in roughness between the inner periphery and the outer periphery of the connection electrode 152 of the semiconductor chip 150 on the upper surface of the solder resist film 104. There is. When the rough unevenness 104b having a rough roughness, the rough unevenness 104a including the rough unevenness and the fine unevenness are formed on the upper surface of the solder resist film 104, the following changes are caused respectively.

  Since the wettability is increased by increasing the surface area at the portion where the rough unevenness 104b is formed, the force that the resin tries to permeate due to the capillary phenomenon when the underfill resin 120 is applied increases. Further, since the wettability is increased, the shape of the resin (fillet) surrounding the chip is stabilized. On the other hand, since the resistance due to the fine unevenness 104a is large at the location where the fine unevenness 104a is formed, the spread of the underfill resin can be suppressed by the resistance.

  In this embodiment, since rough rough irregularities 104b are formed on the inner periphery of the connection electrode 152 of the semiconductor chip 150 on the upper surface of the solder resist film 104, the underfill resin is formed on the inner periphery side of the connection electrode 152 by capillary action. Easy to penetrate. Therefore, a part of the underfill resin 120 spreads under the semiconductor chip 150 and spreads to the opposite side and spreads wet to a certain size.

  On the other hand, fine irregularities 104 a including rough irregularities and fine irregularities are formed on the outer periphery of the connection electrode 152 of the semiconductor chip 150 on the upper surface of the solder resist film 104. For this reason, the presence of rough irregularities improves the wettability and spreads evenly in a stable shape, and resistance due to fine irregularities is generated, the spread of wetting is suppressed, the function of suppressing the spreading of wetness occurs, and a certain range Stay in the size of the wet spread inside. In this embodiment, not only wetting and spreading are suppressed by simply forming the fine irregularities 104a, but also the penetration of the underfill resin 120 below the semiconductor chip 150 can be promoted by forming the rough irregularities 104b. It is possible to effectively suppress the underfill resin from spreading to the outer periphery of the connection electrode 152 of the semiconductor chip 150 on the upper surface of the resist film 104.

  Thereafter, the underfill resin 120 is baked and cured. As described above, the semiconductor chip 150 or the underfill resin 120 is adhered to the substrate 102 (FIGS. 6 and 7). 7 is a cross-sectional view taken along line bb of FIG. As shown in FIG. 6 and FIG. 7, in this embodiment, the wet spread of the underfill resin 120 can be kept within a certain size.

  The underfill resin 120 can be supplied using a jet dispenser 210 as shown in FIG. Thereby, the wetting spread of the underfill resin 120 can be further reduced.

(Other examples)
Moreover, in the above embodiment, the example which formed the fine unevenness | corrugation 104a only in the outer periphery which does not overlap with the semiconductor chip 150 by planar view was demonstrated. However, the fine irregularities 104a can be formed on the entire upper surface of the solder resist film 104. That is, in the above embodiment, the example in which the irradiation of the plasma 112 for forming the fine unevenness 104a is performed after the semiconductor chip 150 is connected to the substrate 102 is shown. However, the irradiation of the plasma 112 is performed. Can be performed on the entire surface of the substrate 102 before mounting.

  Also in this procedure, the supply of the underfill resin 120 may be performed according to the procedure described with reference to FIGS. 5 and 8, but may be performed as follows. The following procedure is a method generally referred to as a pre-resin in which the underfill resin 120 is first applied onto the substrate 102. Hereinafter, a description will be given with reference to FIGS. 9 and 10.

  In FIG. 9, fine unevenness 104a including rough unevenness and fine unevenness is formed over the entire surface of the solder resist film 104. Here, before the semiconductor chip 150 is mounted, the underfill resin 120 is supplied onto the substrate 102 (FIG. 9A). Here, the underfill resin 120 may be a liquid resin such as NCP (Non Conductive Paste), ACP (Anisotropic Conductive Paste), and an active resin having a flux function. Thereafter, the semiconductor chip 150 is mounted on the underfill resin 120 while being heated, and the bonding with the electrode (not shown) on the substrate 102 is completed (FIG. 9B). Also in this example, since the fine unevenness 104a is formed on the surface of the solder resist film 104, wetting and spreading of the solder resist film 104 can be suppressed (FIG. 9C).

  Further, as shown in FIG. 10, the underfill resin 120 can be formed into a film shape with NCF (Non Conductive Film), ACF (Anisotropic Conductive Film), or the like. In this case, the same procedure as shown in FIG. 9 can be used.

FIG. 11 is a process cross-sectional view showing still another manufacturing procedure of the semiconductor device 100 according to the present embodiment.
Here, as shown in FIG. 3A, first, rough irregularities 104b are formed on the entire upper surface of the solder resist film 104 by wet blasting. Next, a mask 160 that protects a region where the semiconductor chip 150 is mounted on the substrate 102 is formed, and the entire surface of the substrate 102 is irradiated with the plasma 112 using the mask 160 (FIG. 11A). Thereby, even on the substrate 102 on which the semiconductor chip 150 is not mounted, the fine unevenness 104a and the rough unevenness 104b can be formed on the upper surface of the solder resist film 104 (FIG. 11B).

  Thereafter, the underfill resin 120 is dropped on the substrate 102 using the needle 200, the jet dispenser 210, or the like (FIG. 11C). Here, unevenness is formed on the upper surface of the solder resist film 104, and there is a difference in roughness between the inner periphery and the outer periphery of the connection electrode 152 of the semiconductor chip 150 on the upper surface of the solder resist film 104. Therefore, the same effect as described with reference to FIG. 5 can be obtained (FIGS. 11D and 11E). Thereafter, the semiconductor chip 150 is mounted on the substrate 102 as described with reference to FIGS. 9 and 10.

Next, the effect of the semiconductor device 100 in the present embodiment will be described.
According to the semiconductor device 100 in the present embodiment, the step of applying the underfill resin 120 by forming the fine irregularities 104a having a desired surface roughness range including rough irregularities and fine irregularities on the upper surface of the solder resist film 104. In this case, it is possible to suppress spread of the resin wetting. Therefore, an area that must be ensured in design for wet spreading can be reduced, and the semiconductor device can be reduced in size.

FIG. 12 is a diagram showing the measurement results of the surface roughness and the underfill resin wetting and spreading when wet blast processing and plasma irradiation processing are performed on the upper surface of the solder resist film 104. The “determination” column in FIG. 12 indicates the degree of wetting and spreading of the underfill resin. X may be defective, Δ may be defective, ◯ is good, and ◎ is better.
Sample 1: The wet blasting process for forming the rough unevenness 104b on the upper surface of the solder resist film 104 was performed, and the plasma irradiation process was not performed.
Samples 2 to 8: The wet blasting process for forming the rough unevenness 104b on the upper surface of the solder resist film 104 was performed in the same manner, and then the process of plasma irradiation was performed.
Plasma irradiation is performed under an oxygen gas atmosphere, gas pressure of 26 Pa, power of 300 W, plasma irradiation time of sample 2:30 seconds, sample 3: 60 seconds, sample 4: 90 seconds, sample 5: 120 seconds, sample 6: 150. Second, sample 7: 180 seconds, sample 8: 210 seconds.
Sample 9: The wet blasting process for forming the rough unevenness 104b on the upper surface of the solder resist film 104 was not performed, and then the plasma irradiation process was performed for 150 seconds under the same conditions as in the sample 6.

Here, laser microscope measurement roughness was performed under the following conditions.
Measuring device: VK-9500 (Keyence Corporation)
Measurement conditions: x3000 field of view, weighted average ± 8 smoothing treatment Measurement area: 50 μm / line roughness measurement Measurement resolution: 0.02 μm

AFM measurement roughness was performed under the following conditions.
Measuring device: L-traceII / NanoNavi station (SII-NT)
Measurement conditions: SIS mode scanner, 90 μm piezo element measurement area: 2 μm ² / average surface roughness (Ra) measurement measurement resolution: 0.01 nm

  In sample 1 (plasma treatment time 0 second (no plasma irradiation)), the laser microscope measurement roughness (line roughness) was 0.203 μm, and the AFM measurement roughness (average surface roughness) was 61 nm. In this case, both the average value and variation of the wet spread of the underfill resin 120 were large.

  In sample 2 (plasma treatment time 30 seconds), the laser microscope measurement roughness (line roughness) was 0.203 μm, and the AFM measurement roughness (average surface roughness) was 63.5 nm. Sample 2 is subjected to plasma irradiation, but the underfill resin 120 has a greater wetting spread than sample 1. This is considered to be because the surface is smoother than the sample 1 and the underfill resin 120 is easily wetted and spread by removing impurities on the surface by plasma irradiation.

  With sample 7 (plasma treatment time 180 seconds) and sample 8 (plasma treatment time 210 seconds), the laser microscope measurement roughness (line roughness) could be measured, but the AFM measurement roughness (average surface roughness) was accurate. It could not be measured. This is because a phenomenon occurs in which the surface of the substrate is excessively shaved and the solder resist scraps of the substrate are reattached to the measurement surface. Regarding the wetting and spreading of the underfill resin 120, the surface unevenness increases too much, and the resin wetting and spreading suppressing force acts strongly, so that the resin cannot spread outside and remains in the vicinity of the end face of the semiconductor chip. Therefore, the resin may crawl up to the back side of the semiconductor chip. In addition, bleeding may occur or the substrate surface may deteriorate.

  Further, in sample 9 (no treatment by wet blasting, plasma treatment time 150 seconds), the laser microscope measurement roughness (line roughness) was 0.118 μm, and the AFM measurement roughness (average surface roughness) was 150 nm. . Also in this case, the average value of the wetting spread of the underfill resin 120 was small, but the variation was large.

  On the other hand, in sample 3 (plasma treatment time 60 seconds) and sample 4 (plasma treatment time 90 seconds), the laser microscope measurement roughness (line roughness) is 0.15 μm or more, and the AFM measurement roughness (average surface roughness) is It was 100 nm or more (200 nm or less). By forming such fine irregularities 104a, it was possible to reduce the average value of the wetting spread of the underfill resin 120 to some extent and to reduce the variation to some extent.

  Further, in sample 5 (plasma treatment time 120 seconds) and sample 6 (plasma treatment time 150 seconds), the laser microscope measurement roughness (line roughness) is 0.15 μm or more, and the AFM measurement roughness (average surface roughness). It became 120 nm or more (200 nm or less). By forming such fine irregularities 104a, the average value of the wetting spread of the underfill resin 120 can be further reduced and the variation can be reduced.

  From the above results, in order to effectively suppress the wetting and spreading of the underfill resin on the substrate surface, the lower limit of the laser microscope measurement roughness (line roughness) is set to about 0.15 μm or more in consideration of the margin. More preferably, it can be about 0.20 μm or more. Further, the upper limit of the roughness measured by the laser microscope (line roughness) can be set to about 1 μm or less in consideration of a margin. Further, in order to suppress the exposure of the filler in the solder resist, the upper limit of the laser microscope measurement roughness (line roughness) is more preferably about 0.30 μm or less.

  In order to effectively suppress the wetting and spreading of the underfill resin on the substrate surface, the lower limit of the AFM measurement roughness (average surface roughness) can be about 100 nm or more, more preferably about 120 nm or more. . The upper limit of the AFM measurement roughness (average surface roughness) can be about 200 nm or less.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

DESCRIPTION OF SYMBOLS 100 Semiconductor device 102 Substrate 104 Solder resist film 104a Fine unevenness 104b Rough unevenness 110 Polishing liquid 112 Plasma 120 Underfill resin 150 Semiconductor chip 152 Connection electrode 160 Mask 200 Needle 210 Jet dispenser

Claims (5)

A substrate having an electrode formed on one surface;
An insulating layer formed on one surface of the substrate and having an opening exposing the electrode;
A semiconductor chip mounted on one surface of the substrate and flip-chip connected to the electrodes;
On the surface of the insulating layer opposite to the surface in contact with the one surface of the substrate, at least in the semiconductor chip outer peripheral region,
First irregularities having a line roughness of 0.15 μm or more and 1 μm or less when measured with a laser microscope at a resolution of 0.1 μm and a measurement range of 50 μm;
An average surface roughness of 100 nm or more and 200 nm or less when measured in a measurement range of 2 μm square with a resolution of 0.1 nm in the horizontal (X, Y) direction using an atomic force microscope on the first unevenness. Two irregularities,
A semiconductor device in which is formed. The semiconductor device according to claim 1,
The first unevenness has a line roughness of 0.20 μm or more and 1 μm or less when measured in a measurement range of 50 μm with a resolution of 0.1 μm using a laser microscope,
The second unevenness is a semiconductor device having an average surface roughness of 120 nm or more and 200 nm or less when measured in a measurement range of 2 μm square with a resolution of 0.1 nm in the horizontal (X, Y) direction using an atomic force microscope. . The semiconductor device according to claim 1 or 2,
A semiconductor device in which an underfill resin is formed between the semiconductor chip and the substrate. A step of forming first irregularities having a line roughness of 0.15 μm or more and 1 μm or less when measured in a measurement range of 50 μm with a resolution of 0.1 μm on an insulating layer formed on one surface of a substrate When,
An average surface roughness of 100 nm or more and 200 nm or less when measured in a measurement range of 2 μm square with a resolution of 0.1 nm in the horizontal (X, Y) direction using an atomic force microscope on the first unevenness. Forming the two irregularities;
Flip chip connecting a semiconductor chip onto the substrate;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 4,
In the step of forming the first unevenness, the first unevenness is formed by a wet blast method,
A method of manufacturing a semiconductor device, wherein in the step of forming the second unevenness, the second unevenness is formed by irradiating plasma.

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