JP2011077684A - Electronic circuit unit, serial transmission system, and transmission control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a data error from being caused, while reducing cost and power consumption, by a structure without requiring a dedicated CLK unit for a reference CLK nor a PLL in each unit. <P>SOLUTION: In relation to the electronic circuit unit for receiving data by serial transmission from another electronic circuit unit, each of the electronic circuit unit and the other electronic circuit unit includes a clock generator for generating a reference clock; and the electronic circuit unit further includes a monitoring means to monitor deviation of the reference clock of the electronic circuit unit from that of the other electronic circuit unit, and a correction instruction means to instruct the clock generator of the electronic circuit unit to correct the deviation of the reference clock detected by the monitoring means. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electronic circuit unit, a serial transmission system, and a transmission control method in a system that performs serial transmission between cards (electronic circuit units) on which electronic components are mounted.

  In recent years, data communication between cards has been widely performed by using high-speed serial communication in a wireless communication base station apparatus such as a W-CDMA (Wideband-Code Division Multiple Access) base station. In that case, a mode in which a CLK card or the like that supplies a reference CLK (Clock) is mounted in the apparatus is often used.

An example of the configuration of such a general serial transmission system is shown in FIG.
In this general configuration example, in order to perform high-speed serial transmission from the card A (306) to the card B (301), a CLK card (310) that supplies a reference CLK in the apparatus is provided. In the CLK card (310), a reference CLK generator (311) and a CLK buffer (312) for outputting the reference CLK to each card are required. Further, in the card A that transmits data and the card B that receives data, it is necessary to synchronize with the reference CLK. Therefore, it is necessary to provide a PLL (Phase Locked Loop) circuit (303) (309).

A detailed configuration of the above-described receiving-side card B (301) is shown in the block diagram of FIG.
The high-speed serial signal input to the card B (301) is input to the Deserializer unit (402), serial-parallel converted, aligned, and written to the FIFO (First In, First Out) unit (405). Since the extracted CLK and the CLK (302) in the own card are locked by the PLL (303), the write address and the read address in the FIFO unit (405) do not approach or separate from each other. The data written in the FIFO unit (405) is read according to the Read address and output to the card.

  As a system for performing communication between cards, a reference source for supplying a reference signal to a plurality of communication cards includes a reference generator, each of the plurality of communication cards includes a CLK generator and a PLL, and a clock for each communication card. In some cases, the frequency is controlled in a manner that depends on the reference signal, and even when a failure occurs in the reference signal, switching to the redundant reference signal is performed (for example, see Patent Document 1).

JP 2005-533404 A

  However, when the above-described general serial transmission system is used, it is necessary to provide a CLK card as a device separately from each card, and there is a problem that device cost and power consumption increase.

  Further, even the device disclosed in Patent Document 1 described above requires a reference source as a device, and it is necessary to provide each card with a PLL, which can reduce the cost and cost of the CLK card for the reference CLK and the PLL. Even power consumption was not considered.

  In addition, when a configuration without a CLK card or a PLL of each card is used, the CLK source on the transmission side and the CLK source on the reception side are different, so the write address and the read address on the reception card side may approach or separate from each other. There is a risk that a data error will occur.

  The present invention has been made in view of such a situation, and does not require a dedicated CLK unit for the reference CLK or a PLL in each unit, and is capable of realizing low cost and low power consumption while realizing a data error. It is an object of the present invention to provide an electronic circuit unit, a serial transmission system, and a transmission control method that do not cause an error.

  In order to achieve such an object, an electronic circuit unit according to the present invention is an electronic circuit unit that receives data by serial transmission from another electronic circuit unit, and the electronic circuit unit and the other electronic circuit unit are: A clock generator for generating a reference clock, and the electronic circuit unit is detected by a monitoring means for monitoring a difference between a reference clock in the electronic circuit unit and a reference clock in the other electronic circuit unit; and the monitoring means Correction instruction means for causing the clock generator of the electronic circuit unit to correct the deviation of the reference clock.

  The serial transmission system according to the present invention includes the electronic circuit unit according to the present invention described above and the other electronic circuit unit, and is configured to be capable of serial transmission from the other electronic circuit unit to the electronic circuit unit. It is characterized by that.

  The transmission control method according to the present invention is a transmission control method for serially transmitting data from another electronic circuit unit to the electronic circuit unit, wherein the electronic circuit unit and the other electronic circuit unit generate a reference clock. A monitoring step for monitoring a shift of a reference clock in the electronic circuit unit and a reference clock in the other electronic circuit unit, and a shift of the reference clock detected by the monitoring step. And a correction instruction step for correcting the clock generator.

  As described above, according to the present invention, a dedicated CLK unit for the reference CLK and a PLL in each unit are not required, and it is possible to realize low cost and low power consumption while causing data errors. No serial transmission is possible.

It is a block diagram which shows the structure outline of embodiment of this invention. 1 is a block circuit diagram showing a configuration example of a serial transmission system as an embodiment of the present invention. It is a block circuit diagram which shows the structural example of the receiving side card | curd in this serial transmission system. It is a block diagram which shows the structure outline of other embodiment of this invention. It is a block circuit diagram which shows the structural example of a general serial transmission system. It is a block circuit diagram which shows the structural example of the receiving side card | curd in a general serial transmission system.

  Next, an embodiment to which an electronic circuit unit, a serial transmission system, and a transmission control method according to the present invention are applied will be described in detail with reference to the drawings.

First, an outline of the present embodiment will be described.
As shown in FIG. 1, the serial transmission system according to the present embodiment includes a transmission side card having a configuration for performing transmission by serial transmission, and a reception side card having a configuration for performing reception by serial transmission. Each card includes a clock generator that generates a reference clock.

  The receiving card includes monitoring means for monitoring the difference between the reference clock in the receiving card and the reference clock in the transmitting card. Also provided is a correction instruction means for causing the clock generator in the receiving card to correct the deviation of the reference clock detected by the monitoring means.

  By providing such a configuration, a dedicated CLK card for a reference clock and a PLL in each unit are not required, and a configuration that does not cause a data error while realizing low cost and low power consumption. be able to.

  More specifically, in the present embodiment, when performing high-speed serial transmission between a plurality of cards in an apparatus of a wireless communication system such as a W-CDMA base station, a CLK source serving as a common reference such as a CLK card is used. It is characterized in that two cards are provided in each card that performs data transmission without needing to perform switching control autonomously and perform no error transmission by controlling the frequency of the CLK source in the card. .

Here, the general inter-card serial transmission system has the following problems.
First, when high-speed serial transmission is performed between a plurality of cards in a device of a wireless communication system, each card is supplied with a CLK (Reference CLK) which is a common reference in the device, and each card has a PLL circuit and a Reference CLK. Had to be synchronized. When such a general configuration is used, it is necessary to provide a CLK card for generating a reference CLK in the device and a PLL circuit for synchronizing with the CLK in each card, which causes a problem that the configuration cost of the device increases. . Further, the provision of each circuit also has problems such as an increase in the number of wirings of a BWB (Back Wiring Board) and an increase in power consumption as a device. Further, when the reference CLK is not delivered, there is a problem that an error occurs every certain cycle because the CLK synchronization is not achieved in each card.

  On the other hand, in this embodiment, by adding a circuit that realizes monitoring means, correction instruction means, etc. as this embodiment that can be realized at low cost to a receiving-side card that performs high-speed serial transmission, There is no need for a CLK card, and the number of BWB lines can be reduced and the power consumption of the apparatus can be reduced.

2 and 3 show an embodiment of the present invention. FIG. 2 shows a schematic configuration of the entire apparatus.
Here, a configuration example in the case of performing high-speed serial transmission between two cards in a radio base station apparatus such as a W-CDMA base station is shown. A card A (102) having a configuration of a transmitting side card for transmitting data and a card B (101) having a configuration of a receiving side card for receiving data are connected by a BWB (103). .

  The card B (101) includes a buffer (105) for receiving a high-speed serial signal, a CLK generator (106) for generating a reference clock in the card B, and a CLK adjustment circuit (104) according to the present embodiment. Prepare. The card A (102) includes a buffer (107) for transmitting a high-speed serial signal and a CLK generator (108) for generating a reference clock in the card A.

FIG. 3 shows a detailed block diagram in the card B (101) which is the receiving side card.
The card B (101) is parallel-converted with a Deserializer unit (201) that performs serial-parallel conversion on the received high-speed serial signal, and a Clock Recovery unit (202) that extracts CLK synchronized with the received high-speed serial signal. A Word Align unit (203) that performs data alignment, a Primary FIFO (204) unit for synchronizing the aligned data with the CLK in the card, and Write Pointer Gen that generates a write address for the Primary FIFO unit (204) Section (207), Read Pointer Gen section (208) that generates a read address for the Primary FIFO section (204), and Secondary FIFO section (212) that stores the same data as the data stored in the Primary FIFO section (204) A Write Pointer Gen unit (210) that generates a write address for the secondary FIFO unit (212) and a read address for the secondary FIFO unit (212). Read Pointer Gen unit (211), Pointer monitoring unit (209), SEL (Selector) unit (205), and F / F (Flip / Flop) unit that performs CLK synchronization to the CLK generator (106) (206).

  The Pointer monitoring unit (209) compares the values of each Read / Write Pointer, generates the Reset signals of the Primary FIFO unit (204) and the Secondary FIFO unit (212), and compares the Read / Write addresses. To generate a control signal for the frequency of the CLK generator (106) in the card B. In addition, the SEL unit (205) generates a control signal for selecting which signal.

  The SEL unit (205) selects either the data read from the Primary FIFO unit (204) or the data read from the Secondary FIFO unit (212) according to the control of the Pointer monitoring unit (209), and the subsequent F / F section (206).

Next, details of the operation according to the present embodiment will be described with reference to FIGS.
First, the card A (102) outputs a high-speed serial signal at CLK synchronized with the CLK generator (108) in the card A (102). The output high-speed serial signal is received by the card B (101) via the BWB (107). Here, in the card B (101), it is necessary to synchronize data with the CLK generator (106) provided in the card B (101).

  The high-speed serial signal input into the card is input to the Deserializer unit (201). The Deserializer unit (201) performs serial-parallel conversion on the signal received from the card A and outputs data to the subsequent stage. At this time, the data is still synchronized with the CLK generator (108) in the card A (102).

  The high-speed serial signal input to the card is also input to the Clock Recovery unit (202). The Clock Recovery unit (202) extracts CLK from the data change point of the input high-speed serial signal and outputs CLK to the subsequent stage. The extracted CLK is synchronized with the CLK generator (108) in the card A (102) on the transmission side.

  The parallel data output from the Deserializer unit (201) is input to the Word Align unit (203). Here, MSB-LSB of parallel data is determined, and parallel data alignment is performed. The aligned parallel data is written to the primary FIFO unit (204) and the secondary FIFO unit (212) according to the respective write addresses. The Write address is generated by the CLK generated by the Clock Recovery unit.

  The data written in the primary FIFO unit (204) is read at a read address synchronized with the CLK generator (106) in the card B and output to the SEL unit (205).

Here, the Write address is a Write address synchronized with the CLK of the card A, and the Read address is a Read address synchronized with the CLK of the card B.
Therefore, there is a possibility that the difference between the write address and the read address may be reduced or widened due to a subtle difference between the CLK of the card A and the card B. If the write address and the read address are the same, data NG is generated.

  Therefore, in this embodiment, the Pointer monitoring unit (209) monitors the difference between the Write address and the Read address, that is, the interval of the Read / Write position to the Primary FIFO unit (204) (monitoring means), and this Write address and Read address. Control is performed when the position interval approaches. There are two types of control, which will be described below.

  The first control is the frequency control of the card's CLK generator. The Pointer monitoring unit monitors the address difference. When the moving speed of the Write address is faster than the moving speed of the Read address, the control for increasing the CLK frequency of the own card, that is, the CLK frequency is increased (high frequency). Take control. Conversely, when the moving speed of the Write address is slower than the moving speed of the Read address, control is performed to slow down the CLK frequency of the card, that is, control to lower (lower) the CLK frequency (correction instruction means). . For example, the early control is defined as “1”, and the late control is defined as “0”.

  A control signal (correction instruction signal) from the Pointer monitoring unit (209) is digital-analog converted by the CLK source frequency control unit (214) and transmitted to the CLK generator (106) in the card B. In this way, for example, the frequency of the CLK generator (106) of the own card is controlled by a VCXO (Voltage Controlled Xtal Oscillator) or the like.

  The second control is control of the SEL unit (205). When the difference between the Read address and the Write address for the Primary FIFO unit (204) is normal, that is, when the position interval is equal to or larger than a predetermined threshold, the SEL unit (205) receives parallel data from the Primary FIFO unit (204). Control to select. On the contrary, when the difference between the Read address and the Write address for the Primary FIFO unit (204) approaches, that is, when the position interval becomes less than a predetermined threshold, the SEL unit (205) becomes the Secondary FIFO unit (212). Control is performed so as to select parallel data from (switching means).

  The Read Pointer Gen (211) and Write Pointer Gen (210) on the Secondary FIFO part side are read / write addresses by a predetermined ratio than the Read Pointer Gen (208) and Write Pointer Gen (207) on the Primary FIFO part side. It is set to generate each address of Read / Write so as to widen the difference.

  The Pointer monitoring unit (209) performs, for example, the above-described first control while controlling the SEL unit (205) to select the data on the secondary FIFO unit (212) side. When the CLK generator (106) is controlled and the difference between the read / write addresses on the primary FIFO unit (204) side is restored (returns to a state where there is a sufficient position interval), the primary to the SEL unit (205) is restored. Control is performed to select data on the FIFO unit (204) side.

As described above, according to the present embodiment, the following effects can be obtained.
The first effect is that since it is not necessary to provide a common CLK card as a device (serial transmission system), the cost and power consumption of the entire device can be reduced.

  The second effect is that since it is not necessary to provide a PLL circuit for each card, the cost of a single card can be reduced and the design can be facilitated.

  A third effect is that a highly reliable system configuration by no error transmission is possible by providing the circuit of this embodiment on the receiving card side.

  Each of the above-described embodiments is a preferred embodiment of the present invention, and the present invention is not limited to this, and various modifications can be made based on the technical idea of the present invention.

For example, in the above-described embodiment, one of the two cards to be connected is described as being a card having a configuration on the reception side and the other is a card having a configuration on the transmission side. If it is a system to perform, it will not be limited to this structure, The system structure provided with the structure as a receiving side card | curd in which both cards mentioned above may be sufficient.
In this case, the serial transmission system is configured as schematically shown in FIG. 4, and communication by serial transmission can be performed bi-directionally between the two cards.

101 Card B (an example of an electronic circuit unit)
102 Card A (an example of a sending card)
103 BWB (an example of connection means)
106 CLK generator 203 Word Align unit 204 Primary FIFO unit 207, 210 Write Pointer Gen unit 208, 211 Read Pointer Gen unit 212 Secondary FIFO unit 209 Pointer monitoring unit (an example of monitoring unit, correction instruction unit, and switching unit)
205 SEL unit (an example of selection means)

Claims (16)

An electronic circuit unit that receives data by serial transmission from another electronic circuit unit,
The electronic circuit unit and the other electronic circuit unit each include a clock generator for generating a reference clock,
The electronic circuit unit is:
Monitoring means for monitoring the deviation of the reference clock in the electronic circuit unit and the reference clock in the other electronic circuit unit;
An electronic circuit unit, comprising: correction instruction means for causing the clock generator of the electronic circuit unit to correct a deviation of the reference clock detected by the monitoring means. First memory means for storing received data;
First write address generation means for generating a first write address for writing data to the first memory means;
First read address generation means for generating a first read address for reading data from the first memory means;
With
The monitoring means monitors a position interval between the first write address and the first read address in the first memory means, thereby allowing a reference clock in the electronic circuit unit and a reference in the other electronic circuit unit. The electronic circuit unit according to claim 1, wherein a clock shift is monitored. The correction instruction means includes
If the moving speed of the first Write address is faster than the moving speed of the first Read address, send a correction instruction to the clock generator to increase the clock frequency,
3. The correction instruction is transmitted to the clock generator to lower the clock frequency when the moving speed of the first write address is slower than the moving speed of the first read address. The electronic circuit unit described. Second memory means for storing the received data;
Second write address generation means for generating a second write address for writing data to the second memory means;
Second read address generation means for generating a second read address for reading data from the second memory means;
With
The second write address generation means and the second read address generation means are configured such that a position interval between the second write address and the second read address in the second memory means is the first memory means in the first memory means. 3. The second write address and the second read address are generated so as to be wider by a predetermined ratio than a position interval between the write address and the first read address. Or the electronic circuit unit of 3. Selection means for selecting an output from the first memory means and an output from the second memory means as an output to the subsequent stage from the first memory means and the second memory means When,
Switching means for switching selection by the selection means according to the monitoring result by the monitoring means;
The electronic circuit unit according to claim 4, further comprising: The switching means, as a monitoring result by the monitoring means,
When the position interval between the write address and the read address in the first memory means is equal to or greater than a predetermined threshold, the output to the subsequent stage is output from the first memory means,
6. The electronic circuit unit according to claim 5, wherein when the position interval is less than the predetermined threshold, the output to the subsequent stage is switched to the output from the second memory means.   7. The electronic circuit unit according to claim 4, wherein the first memory means and the second memory means are FIFO (First In, First Out). An electronic circuit unit according to any one of claims 1 to 7 and the other electronic circuit unit.
A serial transmission system configured to be capable of serial transmission from the other electronic circuit unit to the electronic circuit unit. The other electronic circuit unit is an electronic circuit unit having a configuration for performing transmission,
9. The serial transmission system according to claim 8, wherein the electronic circuit unit is an electronic circuit unit having a configuration for receiving. The other electronic circuit unit has the same configuration as the electronic circuit unit,
9. The serial transmission system according to claim 8, wherein serial transmission is possible from the electronic circuit unit to the other electronic circuit unit. A transmission control method for serially transmitting data from another electronic circuit unit to the electronic circuit unit,
The electronic circuit unit and the other electronic circuit unit each include a clock generator for generating a reference clock,
A monitoring step of monitoring a shift of a reference clock in the electronic circuit unit and a reference clock in the other electronic circuit unit;
And a correction instructing step for causing the clock generator of the electronic circuit unit to correct the deviation of the reference clock detected by the monitoring step. The electronic circuit unit comprises first memory means for storing received data;
In the monitoring step, by monitoring a position interval between a first write address for writing data to the first memory means and a first read address for reading data from the first memory means, 12. The transmission control method according to claim 11, wherein a difference between a reference clock in the circuit unit and a reference clock in the other electronic circuit unit is monitored. In the correction instruction step,
If the moving speed of the first Write address is faster than the moving speed of the first Read address, send a correction instruction to the clock generator to increase the clock frequency,
13. The correction instruction is transmitted to the clock generator to lower the clock frequency when the moving speed of the first write address is slower than the moving speed of the first read address. The transmission control method described. The electronic circuit unit comprises second memory means for storing the received data;
The second write address for writing data to the second memory means and the second read address for reading data from the second memory means are the second write address and the second read address. The position interval is generated so as to be wider by a predetermined ratio than the position interval of the first write address and the first read address in the first memory means. 14. The transmission control method according to 12 or 13.   The output from the first memory means and the second memory means to the subsequent stage is output from the first memory means and from the second memory means according to the monitoring result of the monitoring step. The transmission control method according to claim 14, further comprising a switching step of switching to any one of the outputs. In the switching step, as a monitoring result by the monitoring step,
When the position interval between the write address and the read address in the first memory means is equal to or greater than a predetermined threshold, the output to the subsequent stage is output from the first memory means,
16. The transmission control method according to claim 15, wherein when the position interval is less than the predetermined threshold, the output to the subsequent stage is switched to the output from the second memory means.

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