JP2010133886A - Semiconductor test device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to return to an arbitrary address of a pattern memory, while aiming at simplification of hardware and shortening of a testing period. <P>SOLUTION: A semiconductor test device is equipped with a pattern memory 2 for memorizing the pattern data PAT for performing DUT 101 test. This device includes an address generation part 3 which generates the address which reads out the pattern data PAT of the pattern memory 2 which carries out increment of the address, and an address storage part 5 which stores the address which outputs into the pattern memory 2 from the address generation part 3 and outputs the stored address into the address generation part 3. By storing the address to be restored in the address storage part 5, when the required address stored in the address generation part 3 is output, it is made possible to return to an arbitrary address. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus that tests a device under test, and more particularly to a semiconductor test apparatus that includes a pattern memory that stores pattern data for testing a device under test.

  2. Description of the Related Art Conventionally, a semiconductor test apparatus including a pattern memory that stores pattern data is known as a test for performing measurement by inputting a predetermined test signal to a device under test (hereinafter referred to as DUT). FIG. 6 shows an outline of a conventional semiconductor test apparatus. This semiconductor test apparatus is schematically configured to include a DUT 101, an ALPG 102, and a PE 103. The DUT 101 is a semiconductor device such as a memory, IC, or LSI, and is a device under test to be tested. An ALPG (Algorithmic Pattern Generator) 102 is a controller for generating pattern data of the DUT 101. A PE (Pin Electronics) 103 is a test unit that performs a test by inputting a test signal to the DUT 101.

  The ALPG 102 includes a PG 111, a clock generation unit 112, and a user information setting unit 113, and is schematically configured. PG 111 is a pattern generator for generating pattern data. The clock generation unit 112 is for generating a reference clock CLK which is a test operation reference. The user information setting unit 113 stores information set by the user, and will be described here assuming that an address control signal CTR and an initial address SA, which will be described later, are set. These pieces of information are output to the PE 103.

  The PE 103 includes a plurality (n: n is a natural number) of individual control units 120-1 to 120-n (collectively referred to as individual control units 120). The individual control unit 120 is a mechanism for individually applying test signals to the DUT 101, and includes TGs 121-1 to 121-n (collectively referred to as TG 121) and individual pattern generation units 122-1 to 123-n. (Collectively referred to as individual pattern generator 122) and signal generators 123-1 to 122-n (collectively referred to as signal generator 123).

  The TG 121 is a timing generator that generates timing for applying a test signal to the DUT 101, and generates pattern timing output from the PG 111 of the ALPG 102 and the reference clock CLK to generate the test timing of the DUT 101. The individual pattern generation unit 122 generates individual pattern data for the DUT 101. The pattern data output from the PG 111 of the ALPG 102 is pattern data common to all the DUTs 101 (hereinafter referred to as common pattern data CPAT), and individual patterns for applying different pattern data to the DUTs 101, respectively. The individual pattern generator 122 generates data (hereinafter referred to as pattern data PAT). The signal generation unit 123 generates a test signal using the timing output from the TG 121 and the pattern data PAT output from the individual pattern generation unit 122 (the pattern PAT generated individually for the DUT 101), and outputs the test signal to the DUT 101. Apply.

  The individual pattern generation unit 122 will be described with reference to FIG. The individual pattern generation unit 122 includes a pattern memory 131, an address generation unit 132, and an address register 133. The pattern memory 131 stores a plurality of pattern data PAT individually corresponding to the DUT 101, and the pattern data PAT read from the pattern memory 131 is output to the signal generation unit 123. The address generation unit 132 calculates and generates an address for reading the pattern data PAT stored in the pattern memory 131, and outputs the generated address (referred to as address 132A) to the address register 133. The address register 133 is a register for temporarily holding the address 132A output from the address generation unit 132, and the held address is output to the pattern memory 131 as the address 133A.

  The address generator 132 reads the pattern data PAT from the pattern memory 131 by incrementing the input address or outputting the same address without incrementing the address based on the control of the address control signal CTR. Generate an address for If the address control signal CTR indicates “0”, the input address is output as it is, and if the address control signal CTR indicates “1”, an address obtained by incrementing the input address is output. The address generator 132 receives the address 133A output from the address register 133, and the address to be incremented is the address 133A.

  An initial address SA is input to the address register 133. Therefore, the initial address SA is held in the address register 133, and this initial address SA is output to the pattern memory 131 and the address generation unit 132 as the address 133A. That is, by using the initial address SA as the start address, the address generation unit 132 increments to access consecutive addresses from the initial address SA.

  As shown in FIG. 8, the pattern memory 131 is divided into a plurality of areas. In each area, a control pattern necessary for testing the DUT 101 is described. The control pattern is composed of a command and one or a plurality of data for executing the command, and each of the command and data constitutes pattern data PAT stored in one address. For example, as a control pattern of the data area B, a command is stored at address 03, and five data for executing the command are stored at addresses 04 to 08. These are all pattern data PAT.

  By designating the address 03 as the initial address SA and the address generation unit 132 sequentially incrementing the address, the command and the pattern data PAT of each data are read and output to the signal generation unit 123.

  As shown in FIGS. 6 and 7, the TG 121 of the individual control unit 120 and the pattern memory 131 and the address register 133 of the individual pattern generation unit 122 are input with the reference clock CLK generated by the clock generation unit 112. The operation is performed at the timing of CLK.

  Next, the operation of the above configuration will be described using the timing chart of FIG. 9, CTR (0) has an initial value for the address control signal CTR, and CTR (1), CTR (2),... Are the values of the address control signal CTR at each time. The values of these address control signals CTR are set in the user information setting unit 113 in advance. Here, it is assumed that all the address control signals CTR are “1”. That is, it is assumed that the address generation unit 3 always controls the address increment at all times.

  Further, ADD (0), ADD (1),... In FIG. ADD (0) indicates an initial address SA, and this initial address SA is set in the user information setting unit 113. Both the address 132A output from the address generator 132 and the address 133A output from the address register 133 are both initially set to ADD (0). PAT (ADD (m)) indicates pattern data in ADD (m) of the pattern memory 131 (m is a natural number).

  The address generation unit 132 increments the address based on the address control signal CTR, or outputs the input address as it is. Since the address control signals CTR all indicate “1”, the input address is always incremented at all times. An address 133A output from the address register 133 is input to the address generation unit 132, and the initial value is ADD (0). Accordingly, the address generation unit 132 starts from time t0 and increments the address every time in synchronization with the rising timing of the reference clock CLK. Therefore, continuous addresses in the order of ADD (1), ADD (2),... Are generated as the address 132A.

  The address register 133 holds the address 132A generated by the address generator 132 at a timing delayed by one clock of the reference clock CLK. Therefore, starting from time t1, in synchronization with the rising timing of the reference clock CLK, consecutive addresses in the order of ADD (1), ADD (2),... Are held in the register.

  The pattern memory 131 receives the address 133A output from the address register 133 and reads the pattern data PAT. The timing at which the pattern memory 131 reads the pattern data PAT is delayed by one clock from the timing at which the address register 133 holds the address. Therefore, data is read in the order of PAT (ADD (1)), PAT (ADD (1)),... In synchronization with the rising timing of the reference clock CLK starting from time t2. The read pattern data PAT is sequentially output to the signal generator 123.

As described above, the address generation unit 132 sequentially increments the address, so that the pattern data PAT of continuous addresses is output from the pattern memory 131 to the signal generation unit 123. As a semiconductor test apparatus that performs the above-described configuration and operation, there is a technique disclosed in Patent Document 1, for example.
JP 2007-93547 A

  As shown in FIG. 6, the ALPG 102 and PE 103 of the semiconductor test apparatus are provided as separate and independent hardware, and the operation of the PE 103 is controlled by the ALPG 102. Since the control side and the controlled side are divided between separate and independent devices, it is desirable that the operation control of the PE 103 by the ALPG 102 be simple. This is because when the operation control is complicated by the ALPG 102, the hardware becomes extremely complicated. In particular, the ALPG 102 and the PE 103 are connected by a cable, and when complicated operation control is performed, the number of signal lines included in the cable is greatly increased. If complicated operation control is performed, the test operation of the DUT 101 itself is significantly slowed down. In recent semiconductor test equipment, shortening the test time is an indispensable issue, so it is necessary to simplify the hardware while simplifying the test time by making the operation control by the ALPG 102 as simple as possible. .

  For this reason, the address control for the pattern memory 131 does not allow flexible access to an arbitrary address, but controls by increment using a 1-bit address control signal CTR. The control by the 1-bit address control signal CTR provides extremely simple operation control, and can sufficiently satisfy the demands for shortening the test time and simplifying the hardware.

  On the other hand, when the address control is performed in increments, the address can only be increased one by one, and therefore it is not possible to return to the previously accessed address. For this reason, complicated control such as control for jumping to an address accessed previously, loop processing for repeating specific processing, or the like cannot be performed during one test. Therefore, in order to return to a specific address, it is necessary to end the test once and then start the test again.

  For example, in the case of a loop process in which the control pattern of the data area B is repeatedly executed in the pattern memory 131 shown in FIG. 8, the address 03 is first set as the initial address SA, and then the address control by increment is performed. Thus, continuous access to address 08 is performed. Since it is not possible to return to address 03 next to address 08, the test of DUT 101 is terminated, the initial address SA is set to address 03 and set to a testable state, and then the test is started again. Then, the address is incremented from address 03 and the test is performed. For this reason, when performing the loop processing, it is necessary to finish the test after the pattern data PAT up to the last address (address 08) is read and to perform initial setting in order to start the test again. Accordingly, after the test is completed, the initial setting is performed, and the time required to start the test again is wasted, resulting in a significant time loss. For example, when the number of loop processes is x (x is a natural number), a significant time loss occurs x times, and the test speed is significantly reduced.

  Therefore, an object of the present invention is to make it possible to return to an arbitrary address of a pattern memory while simplifying hardware and shortening a test time.

  In order to solve the above problems, a semiconductor test apparatus according to claim 1 of the present invention is a semiconductor test apparatus having a pattern memory for storing pattern data for testing a device under test, and increments an address. An address generation unit that generates an address for reading pattern data of the pattern memory, and an address storage unit that stores an address output from the address generation unit to the pattern memory and outputs the stored address to the address generation unit And.

  According to this semiconductor test apparatus, since the address to be temporarily restored is stored in the address storage unit and input to the address generation unit, the address can be restored to the address once accessed. In addition, since the address of the pattern memory is controlled by increment control, the address can be controlled with simple control, and the hardware can be simplified and the test time can be shortened.

  A semiconductor test apparatus according to a second aspect of the present invention is the semiconductor test apparatus according to the first aspect, wherein the address generation unit and the address storage unit are each controlled by a 1-bit control signal. .

  According to this semiconductor test apparatus, since the address generation unit and the address storage unit are controlled by a 1-bit control signal, the address can be controlled very easily.

  A semiconductor test apparatus according to a third aspect of the present invention is the semiconductor test apparatus according to the first aspect, wherein one of the address output from the address generation unit and the address output from the address storage unit is selected. And a selector for outputting to the address generation unit.

  According to this semiconductor test apparatus, by providing the selector, it is possible to control to freely select one of the incremented address and the address to be restored.

  A semiconductor test apparatus according to a fourth aspect of the present invention is the semiconductor test apparatus according to the third aspect, wherein the address generation unit, the address storage unit, and the selector are each controlled by a 1-bit control signal. Features.

  According to this semiconductor test apparatus, the address generation unit, the address storage unit, and the selector are controlled by a 1-bit control signal, so that the address can be controlled very easily.

  A semiconductor test apparatus according to a fifth aspect of the present invention is the semiconductor test apparatus according to the third aspect, comprising a plurality of individual pattern generation units each provided with the pattern memory, the address generation unit, the address storage unit, and the selector. And a controller configured to be independent of the test unit and controlling the test unit.

  According to this semiconductor test apparatus, the test unit and the controller are constituted by independent devices, and the test unit is controlled by the control of the controller. It is possible to return to an arbitrary address by temporarily storing the address in the address storage unit while making the control from the controller simple by incrementing the address. ALPG can be applied as the controller, and PE can be applied as the test unit.

  A semiconductor test apparatus according to a sixth aspect of the present invention is the semiconductor test apparatus according to the first aspect, wherein the address storage section includes a plurality of address storage registers for storing addresses output from the address generation section to the pattern memory. It is characterized by.

  According to this semiconductor test apparatus, it is possible to set a plurality of addresses to be restored by storing different addresses in a plurality of address storage registers.

  A semiconductor test apparatus according to a seventh aspect of the present invention is the semiconductor test apparatus according to the first aspect, wherein the address storage unit sequentially stores addresses output from the address generation unit to the pattern memory. It is characterized by having.

  According to this semiconductor test apparatus, since a plurality of addresses can be stored in the address storage FIFO, a plurality of addresses to be restored can be set.

  The semiconductor test apparatus according to an eighth aspect of the present invention is the semiconductor test apparatus according to the first aspect, wherein the address storage unit includes an address memory that stores a plurality of addresses output from the address generation unit to the pattern memory. It is characterized by.

  According to this semiconductor test apparatus, since a plurality of addresses can be stored in the address memory, a plurality of addresses to be restored can be set.

  The semiconductor test apparatus of the present invention can return to an arbitrary address by storing the address output to the pattern memory in the address storage unit. In addition, since the address generation unit performs address control by incrementing the address, the address of the pattern memory can be generated with very simple control. This makes it possible to perform flexible address control for returning to an arbitrary address while simplifying the hardware and shortening the test time.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an individual pattern generation unit 1. As described in FIG. 6, the semiconductor test apparatus is provided with the ALPG 102 and the PE 103, but these configurations are substantially the same as those described in the background art. However, the configuration of the individual pattern generation unit is different from the conventional one. Hereinafter, the individual pattern generation unit 1 in the present embodiment will be described. The overall configuration of the semiconductor test apparatus will be described with reference to FIG. 6, and the configuration of the pattern memory will be described with reference to FIG. 8. In the following embodiments, the configuration other than the individual pattern generation unit 1 is the same as the background art. This will be described using reference numerals.

  The individual pattern generation unit 1 includes a pattern memory 2, an address generation unit 3, an address register 4, an address storage register 5, and a selector 6. The pattern memory 2, the address generation unit 3, and the address register 4 are the same as those described in the background art. As shown in FIG. 6, the PE 103 is provided with a plurality of individual pattern generation units 1. The individual pattern generation unit 1 generates pattern data (hereinafter referred to as pattern data PAT) individually corresponding to the DUT 101, but the individual pattern generation unit 1 corresponds to a plurality of connection pins of one DUT 101. May be provided. The PE 103 may be provided with one individual pattern generation unit 1.

  The pattern memory 2 is a memory for storing pattern data PAT. The memory is divided into a plurality of areas, and a control pattern for testing the DUT 101 is stored in each area. The control pattern is composed of a command and data, and there may be a case where a plurality of data is provided for one command. Since the command or data is stored at one address, the control pattern is stored at a plurality of consecutive addresses. For example, in FIG. 8, a command is stored at address 03 in data area B, and data for executing the command is stored at addresses 04-08. The pattern data PAT output from the pattern memory 2 is input to the signal generation unit 123, and the signal generation unit 123 generates a test signal to be applied to the DUT 101.

  Based on the address control signal CTR, the address generator 3 performs an increment control of the input address and outputs the address 3A. The address 3A is for designating the address of the pattern memory 2. The address generator 3 receives an address 6A output from a selector 6 described later, and increments the address 6A. The address generation unit 3 outputs the address 6A as it is as the address 3A when the address control signal CTR indicates “0”, and increments the address 6A when the address control signal CTR indicates “1”. This address is output as address 3A.

  The address register 4 is an address that temporarily holds the address 3A output from the address generator 3. The address 3A held by the address register 4 is output as the address 4A. An initial address SA is input to the address register 4 and a start address of the pattern memory 2 is designated. For example, when the control pattern of the data area B is designated, the initial address SA becomes the address 03. The address 03 set as the initial address SA is incremented by the address generation unit 3 so that the command or data of the address in the area is sequentially read. Note that the address generated by the address generation unit 3 may be directly input to the pattern memory 2. In this case, the address register 4 need not be provided, but a means for setting the initial address SA in the address generator 3 must be provided.

  An address storage register 5 as an address storage unit is a register that stores (saves) an address 4A output to the pattern memory 2 in order to restore the address. The address is stored based on the address control signal CTR, and the stored address is output to the selector 6 as the address 5A. When the address storage signal ADS indicates “0”, the address 4A is not stored. When the address storage signal ADS indicates “1”, the address 4A is stored. The address storage register 5 stores one address and does not store a plurality of addresses. Therefore, the address 4A at the time when the address storage signal ADS indicates “1” is stored, but when the address storage signal ADS next becomes “1”, the previously stored address 4A is lost, The latest address 4A is stored.

  The selector 6 inputs the address 4A output from the address register 4 and the address 5A output from the address storage register 5, and selectively outputs one of the addresses. The address output by the selector 6 is assumed to be an address 6A. The selector 6 operates based on the select signal SEL. When the select signal SEL indicates “0”, the address 4A is selected and output, and when the select signal SEL indicates “1”, the address 5A is selected. Select to output. The address 6A output from the selector 6 is input to the address generator 3 as described above.

  The pattern memory 2, the address register 4, the address storage register 5, and the selector 6 operate in synchronization with the reference clock CLK. The address generation unit 3 operates based on the address control signal CTR. Since the address control signal CTR is synchronized with the reference clock CLK in the ALPG 102, the address generation unit 3 also substantially includes the reference clock CLK. The operation is performed in synchronization with the above.

  The address control signal CTR, the address storage signal ADS, and the select signal SEL are each 1-bit (binary) control signals. These control signals are input from outside the PE 103. Since the PE 103 is controlled by the ALPG 102, a signal is output from the ALPG 102 here. The ALPG 102 is provided with a user information setting unit 113, which outputs an address control signal CTR, an address storage signal ADS, and a select signal SEL from the user information setting unit 113. The user information setting unit 113 stores output timings of these signals in advance. Of course, each control signal may be output from a control mechanism other than the ALPG 102.

  The address control signal CTR, the address storage signal ADS, and the select signal SEL are illustrated as one-bit control signals. However, the present invention is not limited to this, and control of a small number of bits such as 2 bits or 3 bits is possible. It may be a signal. For example, by using a 2-bit control signal, it is possible to control the address to be incremented conditionally. However, since the control signal exhibits an advantageous effect as the number of bits is small, it is desirable that the control signal is a 1-bit control signal.

  In the present invention, two control signals of an address storage signal ADS and a select signal SEL are newly added. These signals are 1-bit signals. Therefore, even if the control signal is added, the address control is hardly complicated. A control signal line for transmitting a control signal from the ALPG 102 is newly added. However, since the control signal line is for transmitting a 1-bit control signal, the hardware is hardly changed compared to the conventional one. . In addition, since the address control is very simple, there is almost no problem that the test time becomes redundant.

  The initial address SA input to the address register 4 is also input from the outside. Here, the initial address SA is input from the user information setting unit 113 of the ALPG 102. The initial address SA is information indicating an address and is information composed of a signal of a plurality of bits. However, the initial address SA is used only at the initial setting, and is used when a test operation is performed. It is not something. Therefore, if the initial address SA is set first, it will not be used during the test, so that the problem of complicated address control does not occur.

  When the test of the DUT 101 is performed, the test of the DUT 101 is actually started after performing the initial setting such as the setting of the initial address SA in order to start the test. The initial setting is only the initial setting operation and does not participate in the subsequent test operation. Therefore, even if a multi-bit initial address SA is used at the time of this initial setting, the control is not so complicated.

  The operation in the above configuration will be described with reference to the timing chart of FIG. 2, the initial value of the address control signal CTR is CTR (0), the value at time t0 is CTR (1), the value at time t1 is CTR (2),. As the address control signal CTR, a value “1” or “0” is input to the address generator 3 in synchronization with the rising timing of the reference clock CLK. Therefore, the address control signal CTR shows a value of “1” or “0” at each time, but in the following description, it will be assumed that “1” is shown at all times. That is, the address generation unit 3 increments the address at all times. Of course, the address control signal CTR may indicate “0”, and in this case, the address is not incremented.

  ADD (0) is the initial address SA, and ADD (1), ADD (2),... Here, the initial values of the address 3A output by the address generation unit 3, the address 4A held by the address register 4 and the address stored in the address storage register 5 are all ADD (0). To do. ADD (0) becomes the initial address SA set in the address register 4. In FIG. 2, PAT (ADD (m)) indicates the pattern data of the address ADD (m) stored in the pattern memory 2 (m is a natural number).

  As described above, the address control signal CTR indicates “1” at all times. For this reason, since the address is incremented at all times, the address generation unit 3 generates consecutive addresses such as ADD (1), ADD (2),... At each time.

  The address register 4 temporarily holds the address 3A output from the address generator 3, but the timing of holding is only one clock (for the reference clock CLK) than the timing at which the address generator 3 outputs the address 3A. Running late. Therefore, the address register 4 holds continuous addresses such as ADD (1), ADD (2),... At a timing delayed by one clock from the address 3A output from the address generator 3. The held address is output as address 4A.

  The address storage signal ADS input to the address storage register 5 changes from “0” to “1” in synchronization with the rising timing of the reference clock CLK at time t1. Therefore, the address 4A inputted at this timing is stored. At time t1, since the address 4A output from the address register 4 is ADD (1), the address storage register 5 holds ADD (1). The address storage signal ADS changes from “1” to “0” in synchronization with the rising timing of the reference clock CLK at time t2. Therefore, the address storage register 5 holds ADD (1) until the address storage signal ADS next changes to “1”.

  The select signal SEL input to the selector 6 changes from “0” to “1” in synchronization with the rising timing of the reference clock CLK at time t3. At this timing, the selector 6 switches from the address 4A selected so far to the address 5A and performs output. Accordingly, at time t3, the address output from the selector 6 is ADD (1) stored in the address storage register 5. Then, since it changes from “1” to “0” in synchronization with the rising timing of the reference clock CLK at time t 4, the selector 6 switches from address 5 A to address 4 A again to perform output.

  Since the address generator 3 receives the output of the selector 6, when the output of the selector 6 is switched to ADD (1) at time t3, ADD (2) obtained by incrementing the ADD (1) is output as the address 3A. . At time t4, the address register 4 holds ADD (2), and the selector 6 switches the selection to the address 4A held by the address register 4, so that the address generator 3 has ADD ( 2) is input, and ADD (3) obtained by incrementing ADD (2) is output. Thereafter, continuous addresses such as ADD (4), ADD (5),... Are generated in synchronization with the rising timing of the reference clock CLK.

  Since the pattern data PAT read from the pattern memory 2 is delayed by one clock from the address 4A held in the address register 4, the initial address PAT (ADD (0)) is read until time t1. From time t2 to time t4, PAT (ADD (1)), PAT (ADD (2)), and PAT (ADD (3)) are read. On the other hand, at time t5, the pattern data PAT (ADD (1)) corresponding to the address 4A output from the address register 4 at time t4, that is, ADD (1), is read again. That is, ADD (1) stored in the address storage register 5 can return the address from ADD (3) up to that point.

  Therefore, by temporarily storing the incremented address in the address storage register 5, it is possible to return to the stored address and generate the address by increment control again. For example, when a control pattern consisting of pattern data PAT of consecutive addresses is repeatedly executed, a loop process is performed. In the case of loop processing, after the last address of the loop range is read, it is necessary to return to the start address of the loop range. At this time, the head address generated by the address generation unit 3 is stored in the address storage register 5 and the selector 6 is controlled so that the head address is read after the last address. As a result, loop processing can be realized.

  As described above, when the pattern data PAT is read from the pattern memory 2, reading is not performed from an arbitrary address but is performed by performing increment control based on the 1-bit address control signal CTR. . Therefore, since it can be realized by extremely simple address control, the hardware can be simplified and the test time can be greatly reduced. Then, by storing the address to be restored in the address storage unit 5 and switching the output of the selector 6, the address can be restored to an arbitrary address. For this reason, in order to restore the address, it is not necessary to perform initial setting in order to end the test and start the test again, so that the address restoration time can be greatly shortened. Further, as described above, the address control is performed by newly adding the address storage signal ADS and the select signal SEL. However, since both signals are 1-bit signals, the address control is hardly complicated. . For this reason, it becomes possible to perform flexible address control for returning to an arbitrary address while simplifying hardware and shortening the test time.

  Next, a modified example will be described. FIG. 3 shows a first modification. In the above-described embodiment, an example in which one address storage register 5 is provided as an address storage unit has been described. However, in this modification, a plurality (k: k is a natural number) of address storage registers 10-1 to 10-10 as address storage units. -K (collectively referred to as address storage register 10) is provided. Other configurations are the same as those of the embodiment. The address 4A output from the address register 4 is input to all the address storage registers 10, and all the address storage registers 10 output addresses to the selector 6. Thus, by providing a plurality of address storage registers 10, a plurality of addresses can be temporarily stored.

Each address storage register 10 is supplied with an address storage signal ADS. The address storage signal ADS individually associated with each address storage register 10 can freely select which address storage register 10 stores the address 4A. Further, since the selector 6 receives addresses from the k address storage registers 10, it determines which address is selected and output by the select signal SEL. Therefore, each address storage signal ADS is a 1-bit control signal, but the total information amount is k bits. Further, since the select signal SEL also selects one control signal from the k addresses, the information amount is k bits or log ₂ k bits.

  Since a plurality of addresses can be temporarily stored, a plurality of addresses to be restored can be set. By storing the address 4A output from the address register 4 in each address storage register 10 at different timings, k addresses can be designated as return destinations. For example, in the case of multiple loops, since a plurality of addresses must be selected as return destinations, multiple loop processing cannot be performed when there is one address storage register as in the above-described embodiment. . In this respect, the present invention can flexibly cope with processing such as multiple loops.

  However, as described above, the address storage signal ADS and the select signal SEL require a plurality of bits of information. For this reason, the embodiment is more advantageous from the viewpoint of controllability. Therefore, when the actual processing of the DUT 101 requires complex processing such as a multiple loop, the configuration as in this modification is adopted, and when not required, the configuration as in the above-described embodiment is adopted. Which configuration is adopted can be freely selected as appropriate according to the processing contents and the like.

  Next, a second modification will be described with reference to FIG. In this modification, an address storage FIFO 20 is provided as an address storage unit. Two control signals are input to the address storage FIFO 20. One control signal is the address storage signal ADS, and the other control signal is the address output signal ADL. The address storage signal ADS is a control signal for storing an address in the address storage FIFO 20. The address output signal ADL is a signal for controlling the output of the address stored in the address storage FIFO 20.

  The address storage FIFO 20 is a FIFO (First In First Out) type storage means, and sequentially stores the addresses 4A output from the address register 4 based on the address storage signal ADS. A plurality of addresses can be stored in the address storage FIFO 20 in order from the top. Then, based on the address output signal ADL, it is output to the selector 6 in order from the address stored at the head. The address output signal ADL is also connected to the selector 6, and the selection of the selector 6 is switched to the address storage FIFO 20 side in synchronization with the output timing of the address from the address storage FIFO 20. In the above-described embodiment, the selector 6 is controlled by the select signal SEL. However, in this modification, the select signal SEL also serves to control the address storage FIFO 20. The address storage signal ADS is also used in the above-described embodiment. Therefore, no control signal is added.

  In this modification, since the address storage FIFO 20 is employed, a plurality of addresses can be stored and output. Since the address storage signal ADS and the address output signal ADL are 1-bit control signals and no control signals are added, the control complexity is substantially the same as that of the above-described embodiment, and the addresses are restored to a plurality of addresses. To be able to.

  However, since the address storage FIFO 20 is a FIFO method, there is an aspect in which an address once taken out is lost unless it is stored again. Depending on the processing contents, the embodiment or the first modification described above is adopted. Alternatively, it is freely selected as to whether to adopt this modification.

  Next, Modification 3 will be described with reference to FIG. In this modification, an address storage memory 30 is used as an address storage unit, and a storage memory control unit 31 that controls the address storage memory 30 is provided. The address storage memory 30 can store a plurality of input addresses. Since the address stored in the address storage memory 30 (address 4A output from the address register 4) is written in the memory as data, the address stored in the address storage memory 30 will be described below as address data.

  The storage memory control unit 31 performs control to specify an address of address data stored in the address storage memory 30 (that is, an address in the address storage memory 30). A 1-bit address storage signal ADS is input to the address storage memory 30 and the storage memory control unit 31. The address storage memory 30 uses this signal as a write enable signal (WEN: Write Enable), and the storage memory control unit 31 uses this signal for increment. Address data is stored in the address storage memory 30 in order from the top address, and the storage memory control unit 31 increments the address when the address storage signal ADS turns on the write enable of the storage memory control unit 31. ing. Then, by inputting an incremented address (WAD: Write Address) to the address storage memory 30, address data (DN: Data Input) can be stored in order from the top of the address storage memory 30.

  The 1-bit select signal SEL input to the selector 6 is also input to the address storage memory 30. The select signal SEL input to the address storage memory 30 is used as a read enable signal (REN: Read Enable), and the address data (DT: Data Output) stored in the address storage memory 30 when this signal is turned on. ) Is output. Accordingly, when the select signal SEL is turned on, the address data is output from the address storage memory 30, and at the same time, the selection of the selector 6 is switched to the address storage memory 30 side, so that the address data is output to the address generation unit 3. Become so.

  An address selection signal ADR is input to the address storage memory 30 (RAD: Read Address). Since the address storage memory 30 stores a plurality of address data, the address of the output address data is designated by the address selection signal ADR. In order to designate the address of the address storage memory 30, the address storage signal ADS has a plurality of bits of information.

  In the present modification, a plurality of addresses can be stored in the address storage memory 30 as address data, and any address data in the memory can be output. Therefore, the address taken out as in the address storage FIFO 20 in the modification 2 Will not be lost. However, since the address selection signal ADR has an information amount of a plurality of bits, the control is more complicated than in the second modification. Further, since the address storage memory 30 is a memory, it requires a wide mounting area. In the case where various types of hardware are mounted on a small-sized substrate, the above-described embodiment is more advantageous. On the other hand, when the processing is like a multiple loop, it is necessary to access the address once taken out, so it is desirable to adopt the configuration as in this modification.

It is a block diagram which shows schematic structure of the separate pattern control part of embodiment. It is a timing chart of operation in an embodiment. It is a block diagram which shows schematic structure of the separate pattern control part of the modification 1. FIG. 10 is a block diagram illustrating a schematic configuration of an individual pattern control unit according to a second modification. FIG. 10 is a block diagram illustrating a schematic configuration of an individual pattern control unit according to Modification 3. It is a figure which shows schematic structure of a semiconductor test apparatus. It is a block diagram which shows schematic structure of the separate pattern control part of a prior art. It is a figure which shows an example of a structure of a pattern memory. It is a timing chart of operation in conventional technology.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Individual pattern generation part 2 Pattern memory 3 Address generation part 4 Address register 5 Address storage register 6 Selector 10 Address storage register 20 Address storage FIFO
30 Address storage memory 101 DUT
102 ALPG 103 PE
120 Individual Control Unit 122 Individual Pattern Generation Unit 123 Signal Generation Unit 131 Pattern Memory 132 Address Generation Unit 133 Address Register

Claims (8)

A semiconductor test apparatus including a pattern memory for storing pattern data for testing a device under test,
An address generation unit that generates an address for incrementing the address and reading the pattern data of the pattern memory;
Storing an address to be output from the address generator to the pattern memory, and outputting the stored address to the address generator;
A semiconductor test apparatus comprising: The semiconductor test apparatus according to claim 1, wherein the address generation unit and the address storage unit are each controlled by a 1-bit control signal. The selector which selects any one of the address output from the said address generation part and the address output from the said address storage part, and outputs to the said address generation part is provided. Semiconductor test equipment. The semiconductor test apparatus according to claim 3, wherein the address generation unit, the address storage unit, and the selector are each controlled by a 1-bit control signal. A test unit including a plurality of individual pattern generation units provided with the pattern memory, the address generation unit, the address storage unit, and the selector;
A controller that is configured as an independent device from the test unit, and that controls the test unit;
The semiconductor test apparatus according to claim 3, further comprising:   The semiconductor test apparatus according to claim 1, wherein the address storage unit includes a plurality of address storage registers for storing addresses output from the address generation unit to the pattern memory.   The semiconductor test apparatus according to claim 1, wherein the address storage unit includes an address storage FIFO for sequentially storing addresses output from the address generation unit to the pattern memory.   The semiconductor test apparatus according to claim 1, wherein the address storage unit includes an address memory that stores a plurality of addresses output from the address generation unit to the pattern memory.

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