JP2010123743A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the destruction of an IC by excessive current when a backward voltage is applied between any two terminals out of three terminals including a power supply terminal, a ground terminal, and an output terminal. <P>SOLUTION: A P-channel type MOS transistor Q2 and an N-channel type MOS transistor Q1 are connected in series to form a first inverter. A P-channel type MOS transistor Q4 and an N-channel type MOS transistor Q3 are connected in series to form a second inverter. A P-channel type MOS transistor Q6 for protection against a backward voltage is connected to the back gates of the P-channel type MOS transistors Q2 and Q4. An N-channel type MOS transistor Q5 for protection against a backward voltage is connected to the back gates of the N-channel type MOS transistors Q1 and Q3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a protection circuit against reverse voltage and overvoltage.

  Conventionally, a semiconductor integrated circuit (hereinafter referred to as an IC) formed using a CMOS process is known. A simplified version of such an IC is shown in FIG. As shown in the figure, a power supply terminal 50 for supplying a power supply potential VDD to the IC and a ground terminal 51 for supplying a ground potential VSS are provided, and a wiring is provided between the power supply terminal 50 and the ground terminal 51 via wiring. P-channel MOS transistor Q2 and N-channel MOS transistor Q1 are connected in series to form a first inverter.

  Further, a second inverter is formed in which the output signal of the first inverter is applied to the input terminal. Similarly, the second inverter is formed by connecting a P-channel MOS transistor Q4 and an N-channel MOS transistor Q3 in series via a wiring between the power supply terminal 50 and the ground terminal 51.

An output terminal 52 is connected to the output terminal of the second inverter via wiring. The output terminal 52 is provided with diodes D3 and D4 for electrostatic breakdown protection. This type of IC is well known and is described, for example, in Patent Document 1.
JP 2007-329324 A

  By the way, in a vehicle-mounted sensor IC, for example, a position detection sensor IC for detecting the position of an engine crank or cam, any two of three terminals of a power supply terminal 50, a ground terminal 51, and an output terminal 52 are used. Even when a voltage of an arbitrary polarity or an overvoltage is applied between the terminals, the user is required not to break the sensor IC.

  For example, in the circuit of FIG. 7, a power supply potential VDD (for example, +5 V) is applied to the power supply terminal 50 between the power supply terminal 50 and the ground terminal 51 during normal operation, and a lower potential is applied to the ground terminal 51. (For example, 0 V) is applied, but a reverse voltage may be applied between the power supply terminal 50 and the ground terminal 51 in some cases.

  In this case, a relatively high potential is applied to the ground terminal 51 with respect to the power supply terminal 50. Then, an excessive current may flow in the electrostatic breakdown protection diodes D3 and D4 in FIG. 7, but even if the electrostatic breakdown protection diodes D3 and D4 are removed, an excessive current flows in the IC body. There was a risk of IC destruction.

  FIG. 8 is a cross-sectional view of an IC for explaining such a current path. Q3 and Q4 in the figure correspond to the transistors Q3 and Q4 in FIG. As shown in the figure, a P well 54 is formed on the surface of the N type semiconductor substrate 53, Q 3 is formed on the surface of the P well 54, and Q 4 is formed on the surface of the N type semiconductor substrate 53. The power supply terminal 50 is connected to the N-type semiconductor substrate 53 (the back gate BG (n) of Q4) through the N + layer, and the ground terminal 51 is connected to the P well 54 (the back gate BG (p of Q3) through the P + layer. ))It is connected to the.

First, as shown in FIG. 8A, when a reverse voltage is applied between the power supply terminal 50 and the ground terminal 51, the + (positive) potential applied to the ground terminal 51 becomes Q3 via the wiring. Applied to the back gate BG (p), a current flows through a path of the power source terminal 50 to which the drain D (n) of Q3 → the drain D (p) of Q4 → the back gate BG (n) of Q4 → −potential is applied. . At this time, the PN junction formed by the drain D (p) of Q4 and the N-type semiconductor substrate 53 is forward-biased. In parallel with this, a current path of the ground terminal 51 → the back gate BG (p) of Q3 → the back gate BG (n) of Q4 → the power supply terminal 50 is also generated.
The same applies to the transistors Q1 and Q2.

  Also, as shown in FIG. 8B, when a reverse voltage is applied between the power supply terminal 50 and the output terminal 52, the + (positive) potential applied to the output terminal 52 is Q4 through the wiring. A current flows through a path of the power supply terminal 50 to which the drain D (p) is applied and the back gate BG (n) of Q4 is applied with a negative potential. At this time, the PN junction formed by the drain D (p) of Q4 and the N-type semiconductor substrate 53 is forward-biased.

  Further, as shown in FIG. 8C, when a reverse voltage is applied between the ground terminal 51 and the output terminal 52, the + potential applied to the ground terminal 51 becomes the back gate BG of Q3 via the wiring. A current flows through a path of the output terminal 52 to which the drain D (n) of Q3 is applied, and the − potential is applied to (p). At this time, the PN junction formed by the drain D (n) of Q3 and the P well 54 is forward biased.

  The semiconductor integrated circuit according to the present invention includes a power terminal, a ground terminal, a first P-channel MOS transistor and a first N-channel transistor connected in series between the power terminal and the ground terminal to form an inverter. A MOS transistor, an output terminal connected to a connection node of the first P-channel MOS transistor and the first N-channel MOS transistor, a second P-channel MOS transistor for reverse voltage protection, The second P-channel MOS transistor has a source connected to the back gate of the first P-channel MOS transistor, a drain connected to the power supply terminal, and a gate connected to the ground terminal. It is connected.

  According to another aspect of the present invention, there is provided a semiconductor integrated circuit including an internal circuit including a first P-channel MOS transistor and a first N-channel MOS transistor that are connected in series with a power supply terminal and a ground terminal, and form an inverter; A second P-channel MOS transistor connected between the source of the first P-channel MOS transistor and the power supply terminal for supplying a power supply potential to the internal circuit, and a third P for reverse voltage protection The third P-channel MOS transistor has a source connected to the back gate of the second P-channel MOS transistor, a drain connected to the power supply terminal, A gate is connected to the ground terminal.

  In addition to the above configuration, the resistor connected between the gate of the second P-channel MOS transistor and the ground terminal, and the resistor when an overvoltage is applied between the power supply terminal and the ground terminal. And an overvoltage protection circuit that raises the gate voltage of the second P-channel MOS transistor from the ground potential of the ground terminal by passing a current through the second terminal.

  According to the semiconductor integrated circuit of the present invention, even when a reverse voltage is applied between any two terminals among the three terminals of the power supply terminal, the ground terminal, and the output terminal, the semiconductor integrated circuit is destroyed by an excessive current. Can be prevented.

  Further, by providing an overvoltage protection circuit, the internal circuit of the IC can be protected even when an overvoltage is applied between the power supply terminal and the ground terminal. As a result, the internal circuit of the semiconductor integrated circuit can be formed without using a high breakdown voltage transistor, so that the chip size of the semiconductor integrated circuit can be reduced.

An IC according to an embodiment of the present invention will be described with reference to the drawings.
[First Embodiment]
As shown in FIGS. 1 to 5, the IC according to the present embodiment includes a P-channel MOS transistor Q6 for reverse voltage protection connected to the back gates of the P-channel MOS transistors Q2 and Q4, and an N-channel. An N-channel MOS transistor Q5 for reverse voltage protection connected to the back gates of the MOS transistors Q1 and Q3 is provided.

  The detailed configuration of the IC will be described below. As shown in the figure, a power supply terminal 50 for supplying a power supply potential VDD to the IC and a ground terminal 51 for supplying a ground potential VSS are provided, and a wiring is provided between the power supply terminal 50 and the ground terminal 51 via wiring. P-channel MOS transistor Q2 and N-channel MOS transistor Q1 are connected in series to form a first inverter.

  Further, a second inverter is formed in which the output signal of the first inverter is applied to the input terminal. Similarly, the second inverter is formed by connecting a P-channel MOS transistor Q4 and an N-channel MOS transistor Q3 in series via a wiring between the power supply terminal 50 and the ground terminal 51. An output terminal 52 is connected to the output terminal of the second inverter via wiring.

  The source S (p) of the P-channel MOS transistor Q6 for reverse voltage protection is connected to the N-type back gate BG (n) (N-type semiconductor substrate 53) of the P-channel MOS transistors Q2 and Q4, and its drain D (p) is connected to the power supply terminal 50, and its gate is connected to the ground terminal 51. In this case, the source S (p) of Q6 is connected to the N + layer on the surface of the N-type semiconductor substrate 53.

  The source S (n) of the N-channel MOS transistor Q5 for reverse voltage protection is connected to the P-type back gate BG (p) (P well 54) of the N-channel MOS transistors Q1 and Q3, and its drain. D (n) is connected to the ground terminal 51, and its gate is connected to the power supply terminal 50. In this case, the source S (n) of Q5 is connected to the P + layer on the surface of the P well 54.

[Description of operation]
Next, an operation when a reverse voltage is applied to the above-described IC will be described with reference to FIGS. In FIGS. 2 to 4, illustration of Q <b> 1 and Q <b> 2 is omitted, but has the same configuration as Q <b> 3 and Q <b> 4, respectively.

  First, as shown in FIG. 2, when a reverse voltage is applied between the power supply terminal 50 and the ground terminal 51, the + potential is the source S (n) of Q1, the source S (n) of Q3, and the drain of Q5. There is no PN junction that is applied to the gates of D (n) and Q6, but then forward biased in the previous path, so there is no current path. The negative potential is applied to the source S (p) of Q2, the source S (p) of Q4, the drain D (p) of Q6, and the gate of Q5, but is forward-biased in the path ahead. Since no PN junction exists, no current path is generated. This is because the back gates BG (n) of Q2 and Q4 are connected to the power supply terminal 50 through Q6 which is a switching element. Similarly, the back gates BG (p) of Q1 and Q3 are connected to the ground terminal 51 through Q5 which is a switching element. Thus, when a reverse voltage is applied between the power supply terminal 50 and the ground terminal 51, no excessive current is generated in the IC.

  Next, as shown in FIG. 3, when a reverse voltage is applied between the power supply terminal 50 and the output terminal 52, the + potential is applied to the drain D (p) of Q4 and the drain D (p of Q4). ) And the back gates BG (n) of Q2, Q4 and Q6 are forward-biased. However, since there is no forward-biased PN junction in the path beyond the back gate BG (n) of Q2, Q4, and Q6 via this PN junction, no current path is generated. Further, the + potential is also applied to the drain D (n) of Q3. However, since there is no forward-biased PN junction in the path ahead of the drain D (n) of Q3, no current path is generated.

  Next, as shown in FIG. 4, when a reverse voltage is applied between the ground terminal 51 and the output terminal 52, -potential is applied to the drain D (n) of Q3, and the drain D (n) of Q3. And the back gate BG (p) of Q1, Q3 and Q5 are forward-biased. However, since there is no forward-biased PN junction in the path beyond the back gate BG (p) of Q1, Q3, and Q5 via this PN junction, no current path is generated. The negative potential is also applied to the drain D (p) of Q4. However, since there is no forward-biased PN junction in the path ahead of the drain D (p) of Q4, no current path is generated.

  Next, as shown in FIG. 5, a case where a positive voltage is applied between the power supply terminal 50 and the ground terminal 51, that is, a case where the potential of the power supply terminal 50 is higher than the potential of the ground terminal 51 will be described. For example, this is a case where the potential of the power supply terminal 50 is 5V and the potential of the ground terminal 51 is 0V. In this case, Q5 is turned on, the back gates BG (n) of the N-channel MOS transistors Q1, Q3 are set to the ground potential VSS, Q6 is turned on, and the back gates of the P-channel MOS transistors Q2, Q4 BG (p) is set to the power supply potential VDD. As a result, the IC performs a normal operation.

[Second Embodiment]
Next, as shown in FIG. 6, the IC according to the present embodiment supplies the internal circuit 10, a P-channel MOS transistor Q <b> 18 for supplying the power supply potential VDD to the internal circuit 10, and the ground potential VSS to the internal circuit 10. An N channel type MOS transistor Q17 is provided. As in the first embodiment, a reverse voltage protection P-channel MOS transistor Q110 connected to the back gate of the P-channel MOS transistor Q18 is provided, and the back-gate of the N-channel MOS transistor Q17 is provided. A connected N-channel MOS transistor Q19 for protecting the reverse voltage is provided.

  Further, an overvoltage protection circuit 11 is provided for protecting the internal circuit 10 when an overvoltage is applied between the power supply terminal 50 and the ground terminal 51.

  Further, an output circuit 12 to which the output signal of the internal circuit 10 is applied is provided. The configuration of the output circuit 12 is the same as that of the first embodiment, and is provided with a P-channel MOS transistor Q112 for reverse voltage protection and an N-channel MOS transistor Q111 for reverse voltage protection.

The detailed configuration of the IC will be described below.
[Internal circuit]
First, although the internal circuit 10 is shown as two CMOS inverters, this is shown in a simplified manner for convenience, and actually includes a large number of inverters, logic circuits, analog circuits, and the like. The first inverter is formed of a P-channel MOS transistor Q12 and an N-channel MOS transistor Q11 connected in series. The output signal of the first inverter is applied to the second inverter at the next stage. The second inverter is formed of a P-channel MOS transistor Q14 and an N-channel MOS transistor Q13 connected in series.

  A P-channel MOS transistor Q18 for supplying power supply potential is connected between the commonly connected source of Q12 and Q14 and the power supply line extending from the power supply terminal 50. That is, the source of Q18 is connected to the power supply line, and its drain is connected to the commonly connected source of Q12 and Q14. The gate of the P channel type MOS transistor Q18 is connected to a ground line extending from the ground terminal 51 via a resistor R2. The source S (p) of the P-channel MOS transistor Q110 for protecting the reverse voltage is connected to the N-type back gate of the P-channel MOS transistor Q18, and the drain D (p) is supplied via the power line. The gate is connected to the ground terminal 51 through a ground line.

  An N-channel MOS transistor Q17 for supplying a ground potential is connected between the commonly connected source of Q11 and Q13 and the ground line. The gate of N channel type MOS transistor Q17 is connected to the power supply line. The source S (n) of the N-channel MOS transistor Q19 for reverse voltage protection is connected to the P-type back gate of the N-channel MOS transistor Q17, and its drain D (n) is connected to the ground line. The gate is connected to the power line.

  According to this configuration, when a reverse voltage is applied between the power supply terminal 50 and the ground terminal 51, generation of an excessive current can be prevented. The reason is that a current path is not formed as in the first embodiment.

[Overvoltage protection circuit]
Next, the overvoltage protection circuit includes a resistor R2 connected between the gate of the P-channel MOS transistor Q18 for supplying power supply potential and the ground line, and an overvoltage is applied between the power supply terminal 50 and the ground terminal 51. At this time, the gate potential of the second P-channel MOS transistor Q18 is raised from the potential of the ground terminal 51 by causing a current to flow through the resistor R2.

  As shown in the figure, the configuration example of the overvoltage protection circuit includes a Zener diode D1 having a cathode connected to the drain of a P-channel MOS transistor Q18, and an NPN type connected between the anode of the Zener diode D1 and the ground line. Bipolar transistor Q117, NPN bipolar transistor Q118 forming a current mirror with bipolar transistor Q117, P-channel MOS transistor Q114 connected between bipolar transistor Q118 and the power supply line, and P-channel MOS transistor Q114 And a P-channel MOS transistor Q113 that forms a current mirror and is connected to the resistor R2.

  In this case, it is preferable to connect a resistor R1 between the Zener diodes D1 and Q18 in order to limit the current flowing through the Zener diode D1. In order to clamp and protect the voltage applied to the internal circuit 10, it is preferable to connect a clamping diode D2 between the ground terminal 51 and the drain of Q18.

  According to this overvoltage protection circuit, when an overvoltage is applied between the power supply terminal 50 and the ground terminal 51, a current flows through the resistor R2 by the P-channel MOS transistor Q113. When a current flows through the resistor R2, the gate potential of Q18 rises from the ground potential VSS. Then, the impedance of Q18 becomes high, the power supply potential VDD 'supplied to the internal circuit 10 becomes lower than the power supply voltage VDD applied to the power supply terminal 50, and the internal circuit 10 is protected from overvoltage.

[Output circuit]
The configuration of the output circuit is the same as that of the first embodiment. As shown, a P-channel MOS transistor Q16 and an N-channel MOS transistor Q15 are connected in series to form an inverter. A connection node between the P-channel MOS transistor Q16 and the N-channel MOS transistor Q15 is connected to the output terminal 52 through a wiring.

  The source S (p) of the P-channel MOS transistor Q112 for reverse voltage protection is connected to the N-type back gate of the P-channel MOS transistor Q16, and its drain D (p) is connected to the power supply terminal 50 via the power supply line. And the gate thereof is connected to the ground terminal 51 through a ground line.

  The source S (n) of the N-channel MOS transistor Q111 for reverse voltage protection is connected to the P-type back gate of the N-channel MOS transistor Q15, and its drain D (n) is grounded via a ground line. The gate is connected to the power supply terminal 50 through a power supply line.

[Description of operation]
First, the operation when a reverse voltage is applied to the above-described IC will be described.
(A) In the case where a reverse voltage is applied between the power supply terminal 50 and the ground terminal 51. The + potential is the source S (n) of Q17, the drain D (n) of Q19, the source S (n) of Q15, and the Q111. Although applied to the drain D (n), there is no forward-biased PN junction in the path ahead, and no current path is created.

  Further, the + potential is applied to the drain D (p) of Q113 → the back gate BG (n) of Q113 → the source S (p) of Q115 and the back gate BG (n) through the resistor R2. There is no forward-biased PN junction and no parasitic current path occurs. Further, although the + potential is applied to the emitters E (n) of Q117 and Q118, there is no forward-biased PN junction and no current path is generated.

  -The potential is the drain D (p) of Q116, the source S (p) of Q114, the source S (p) of Q113, the drain D (p) of Q115, the source S (p) of Q18, and the drain D (p of Q110) ), Applied to the source S (p) of Q16 and the drain D (p) of Q112, but there is no forward-biased PN junction in the subsequent path, and no current path is generated. For this reason, the generation of excessive current does not occur. Note that the voltage applied to the internal circuit 10 is clamped to a low voltage when the diode D2 is forward-biased.

(B) When a reverse voltage is applied between the power supply terminal 50 and the output terminal 52, the + potential is applied to the drain D (p) of Q16, and the back gate BG of Q16 and Q16, Q112. The PN junction formed by (n) is forward-biased. However, since there is no forward-biased PN junction in the path beyond the back gate BG (p) of Q112 and Q116 via this PN junction, no current path is generated.

  Furthermore, although the + potential is also applied to the drain D (n) of Q15, there is no forward-biased PN junction in the path ahead of the drain D (n) of Q15, so that no current path is generated. .

(C) When a reverse voltage is applied between the output terminal 52 and the ground terminal 51-the potential is applied to the drain D (n) of Q15 and the drain D (n) of Q15 and the back gate of Q15, Q111 A PN junction formed with BG (p) is forward-biased. However, since there is no forward-biased PN junction in the path ahead of the back gates BG (p) of Q15 and Q111 via this PN junction, no current path is generated.

  Furthermore, although the -potential is also applied to the drain D (p) of Q16, there is no forward-biased PN junction in the path ahead of the drain D (p) of Q16, so no current path is generated. .

  It is to be noted that the electrostatic breakdown protection diodes D3 and D4 as shown in FIG. 7 are not formed, and by adopting the above-described configuration, it is possible to prevent the generation of an excessive current due to the application of the reverse voltage, and the IC due to the excessive current. Can be prevented.

Next, an operation when a positive voltage and an overvoltage are applied to the above-described IC will be described.
(D) When a positive voltage is applied between the power supply terminal 50 and the ground terminal 51 In this case, as usual, a positive power supply potential VDD (for example, +5 V) is applied to the power supply terminal 50 and the ground terminal 51 is grounded. This is a case where a potential VSS (for example, 0 V) is applied.

  In this case, Q19 and Q111 for reverse voltage protection are turned on, and the back gates BG (p) of Q17 and Q15 are set to the ground potential VSS. Further, Q110, Q112, Q115, and Q116 for reverse voltage protection are turned on, and the back gates BG (n) of Q18, Q16, Q113, and Q114 are set to the power supply potential VDD. Thereby, the back gate potential of each transistor is set to a normal bias state. At the same time, power supply to the internal circuit 10 is started by turning on Q17 for supplying ground potential and Q18 for supplying power supply potential.

  The operation of the overvoltage protection circuit 11 will be described. Assume that power is supplied to the internal circuit 10 now. When the power supply potential of the internal circuit 10 (VDD ′ = Q18 drain potential) is lower than the protective potential = (Vbe of Q117 + Z1 voltage of D1), Q117 is in an off state, and Q118, Q114, Q113, R2 Since no current flows and the Q18 gate potential is 0V, the overvoltage protection operation is not performed.

  When the power supply potential VDD rises and VDD ′> protection potential, the Zener diode is turned on, current flows through Q117, Q118, Q114, Q113, and resistor R2, the Q18 gate potential rises above the ground potential VSS, and the drain of Q8 It has the effect of lowering the potential, that is, VDD ′. For this reason, VDD ′ converges to the vicinity of the protective potential, and no overvoltage is applied to the internal circuit 10.

(E) When an overvoltage is applied between the power supply terminal 50 and the output terminal 52 -The potential is applied to the source S (n) of Q15 and the back gate BG (p) of Q15 PN junction formed in the forward direction is forward-biased. As a result, the source potential of Q111 becomes close to the negative potential. Since the gate potential of Q111 is a positive potential, Q111 is turned on. The ground terminal 51 of the IC has a potential increased by a voltage obtained by adding the rising voltage of the PN junction and the voltage due to the on-resistance of Q111.

  As a result, a voltage of Vds (source-drain voltage) of applied voltage-PN junction rising voltage-Q111 is applied between the power supply terminal 50 and the ground terminal 51. That is, the voltage between the power supply terminal 50 and the ground terminal 51 is lower than the applied voltage (overvoltage) between the power supply terminal 50 and the output terminal 52. The internal circuit 10 is protected from overvoltage by a synergistic effect of the operation of the output circuit 12 and the overvoltage protection operation of the overvoltage protection circuit 11 described above.

(F) When an overvoltage is applied between the output terminal 52 and the ground terminal 51 + potential is applied to the source S (p) of Q16, and the source S (p) of Q16 and the back gate BG (n of Q16) PN junction formed in the forward direction is forward-biased. As a result, the source potential of Q112 becomes substantially equal to the applied voltage. Since the gate potential of Q112 is -potential, Q112 is turned on. The power supply terminal 50 of the IC becomes a potential that is lowered from the applied voltage by a voltage obtained by adding the rising voltage of the PN junction and the voltage due to the on-resistance of Q112.

  As a result, between the power supply terminal 50 and the ground terminal 51 of the IC, a voltage of applied voltage-PN junction rising voltage-Q112 Vds (source-drain voltage) is applied. That is, the voltage between the power supply terminal 50 and the ground terminal 51 is lower than the applied voltage (overvoltage) between the output terminal 52 and the ground terminal 51. The internal circuit 10 is protected from overvoltage by a synergistic effect of the operation of the output circuit 12 and the overvoltage protection operation of the overvoltage protection circuit 11 described above.

  As described above, the internal circuit 10 is protected from overvoltage application. Further, in the IC, transistors other than the transistors of the internal circuit 10 are applied with an overvoltage, so it is necessary to form them with high breakdown voltage transistors. However, the transistors Q11, Q12, Q13, and Q14 constituting the internal circuit 10 are It can be formed by a low breakdown voltage transistor having a relatively small pattern area. Thereby, the effect that the chip size of the IC can be reduced is obtained.

  Needless to say, the present invention is not limited to the above-described embodiment, and modifications can be made without departing from the scope of the invention. For example, the overvoltage protection circuit 11 is not limited to the circuit of the embodiment, and other types of circuits may be used. In the embodiment, the N-type semiconductor substrate 53 is used and the P-well 54 is formed on the surface of the CMOS device structure. Conversely, the P-type semiconductor substrate is used and the N-well is formed on the surface. An N channel MOS transistor may be formed on a P type semiconductor substrate, and a P channel MOS transistor may be formed on an N well.

1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. 1 is a cross-sectional view of a semiconductor integrated circuit according to a first embodiment of the present invention. 1 is a cross-sectional view of a semiconductor integrated circuit according to a first embodiment of the present invention. 1 is a cross-sectional view of a semiconductor integrated circuit according to a first embodiment of the present invention. 1 is a cross-sectional view of a semiconductor integrated circuit according to a first embodiment of the present invention. It is sectional drawing of the semiconductor integrated circuit by the 2nd Embodiment of this invention. It is a circuit diagram of the semiconductor integrated circuit of a prior art example. It is sectional drawing of the semiconductor integrated circuit of a prior art example.

Explanation of symbols

10 Internal circuit 11 Overvoltage protection circuit 12 Output circuit 50 Power supply terminal 51 Ground terminal 52 Output terminal 53 N-type semiconductor substrate 54 P-well

Claims (10)

A power terminal;
A grounding terminal;
A first P-channel MOS transistor and a first N-channel MOS transistor which are connected in series between the power supply terminal and the ground terminal and form an inverter;
An output terminal connected to a connection node between the first P-channel MOS transistor and the first N-channel MOS transistor;
A second P channel type MOS transistor for reverse voltage protection,
The second P-channel MOS transistor has a source connected to the back gate of the first P-channel MOS transistor, a drain connected to the power supply terminal, and a gate connected to the ground terminal. A semiconductor integrated circuit. A second N-channel MOS transistor for reverse voltage protection;
The second N-channel MOS transistor has a source connected to the back gate of the first N-channel MOS transistor, a drain connected to the ground terminal, and a gate connected to the power supply terminal. The semiconductor integrated circuit according to claim 1. A power terminal;
A grounding terminal;
An internal circuit comprising a first P-channel MOS transistor and a first N-channel MOS transistor connected in series and forming an inverter;
A second P-channel MOS transistor connected between a source of the first P-channel MOS transistor and the power supply terminal for supplying a power supply potential to the internal circuit;
A third P channel type MOS transistor for reverse voltage protection,
The third P-channel MOS transistor has a source connected to the back gate of the second P-channel MOS transistor, a drain connected to the power supply terminal, and a gate connected to the ground terminal. A semiconductor integrated circuit. A second N-channel MOS transistor connected between a source of the first N-channel MOS transistor and the ground terminal and for supplying a ground potential to the internal circuit;
A third N-channel MOS transistor for reverse voltage protection,
The third N-channel MOS transistor has a source connected to the back gate of the second N-channel MOS transistor, a drain connected to the ground terminal, and a gate connected to the power supply terminal. The semiconductor integrated circuit according to claim 3. A resistor connected between the gate of the second P-channel MOS transistor and the ground terminal, and by passing an electric current through the resistor when an overvoltage is applied between the power supply terminal and the ground terminal; 5. The semiconductor integrated circuit according to claim 3, further comprising an overvoltage protection circuit that raises a gate potential of the second P-channel MOS transistor from a potential of the ground terminal. The overvoltage protection circuit includes a Zener diode having a cathode connected to the drain of the second P-channel MOS transistor, a first bipolar transistor connected between the anode of the Zener diode and the ground terminal,
A second bipolar transistor forming a current mirror with the first bipolar transistor;
A fourth P-channel MOS transistor connected between the second bipolar transistor and the power supply terminal;
A fifth P-channel MOS transistor which forms a current mirror with the fourth P-channel MOS transistor and is connected to the resistor;
6. The semiconductor integrated circuit according to claim 5, wherein when an overvoltage is applied between the power supply terminal and the ground terminal, a current is passed through the resistor by the fifth P-channel MOS transistor. A sixth P-channel MOS transistor for reverse voltage protection;
The sixth P-channel MOS transistor has a source connected to the back gate of the fourth P-channel MOS transistor, a drain connected to the power supply terminal, and a gate connected to the ground terminal. The semiconductor integrated circuit according to claim 6. A seventh P-channel MOS transistor for reverse voltage protection;
The seventh P-channel MOS transistor has a source connected to the back gate of the fifth P-channel MOS transistor, a drain connected to the power supply terminal, and a gate connected to the ground terminal. The semiconductor integrated circuit according to claim 6 or 7, wherein An output circuit to which an output signal of the internal circuit is applied;
The output circuit is connected in series between the power supply terminal and the ground terminal, and an eighth P-channel MOS transistor and a fourth N-channel MOS transistor forming an inverter;
An output terminal connected to a connection node between the eighth P-channel MOS transistor and the fourth N-channel MOS transistor;
A ninth P-channel MOS transistor for reverse voltage protection,
The ninth P-channel MOS transistor has a source connected to the N-type back gate of the eighth P-channel MOS transistor, a drain connected to the power supply terminal, and a gate connected to the ground terminal. 9. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit is connected. A fifth N-channel MOS transistor for reverse voltage protection;
The fifth N-channel MOS transistor has a source connected to the back gate of the fourth N-channel MOS transistor, a drain connected to the ground terminal, and a gate connected to the power supply terminal. The semiconductor integrated circuit according to claim 9.

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