JP2010147324A - Solar cell element and method of manufacturing solar cell element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solar cell element which has more superior power generation efficiency than before. <P>SOLUTION: The solar cell element 100A has an n-type semiconductor region 2, a p-type semiconductor layer 5, a p-type electrode 6, and an n-type electrode 9. The p-type semiconductor layer 5 is formed adjacently to part of the reverse side of the n-type semiconductor region 2, the p-type electrode 6 is formed at a position opposed to the n-type semiconductor region 2 across the p-type semiconductor layer 5, and the n-type electrode 9 is formed on the reverse surface side of the n-type semiconductor region 2 adjacently to a region where the p-type semiconductor layer 5 is not formed, the p-type semiconductor layer 5 being made smaller in concentration of p-type conductivity type determining elements as being closer to the reverse surface of the n-type semiconductor region 2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solar cell element using a semiconductor junction and a manufacturing method thereof.

  Conventionally, a solar cell element in which the area of the electrode on the light receiving surface side is reduced is widely known. For example, after an n-type electrode and a p-type electrode are formed on the non-light-receiving surface side, one of the n-type or p-type electrode and a light-receiving surface electrode (finger electrode) provided on the light-receiving surface side are provided on the semiconductor substrate. An example is a back-contact solar cell element that is electrically connected by a through conductor.

  In recent years, the development of back contact type solar cell elements in which electrodes are provided only on the back surface side and electrodes are not provided on the light receiving surface side has become active (see, for example, Patent Document 1).

JP-A-2005-101240

  The solar cell element capable of receiving light on the entire light receiving surface is, for example, a pn formed of an n-type crystalline silicon substrate and a p-type amorphous silicon film formed in a predetermined region on the non-light receiving surface side of the substrate. There is a solar cell element having a junction. In such a solar cell element, there are many defects in the vicinity of the pn junction interface, and carrier recombination loss due to these defects contributes to a decrease in open circuit voltage and power generation efficiency.

  Patent Document 1 discloses a solar cell element having a pin junction in which an i-type amorphous silicon film and a p-type amorphous silicon film are formed in this order in a predetermined region on the non-light-receiving surface side of an n-type single crystal silicon substrate. Is disclosed. In the solar cell element having such a configuration, the defect density in the pin junction region is small due to the presence of the i-type amorphous silicon film. On the other hand, since the i-type amorphous silicon film is substantially an insulating film, it is a cause of hindering carrier tunneling in the pin junction region. ing.

  This invention is made | formed in view of the said subject, and it aims at providing the solar cell element excellent in power generation efficiency conventionally.

  In order to solve the above-mentioned problem, the invention of claim 1 includes a semiconductor substrate having a first conductivity type, including a first surface and a second surface, and a first region of the first surface of the semiconductor substrate. A semiconductor layer having a second conductivity type and a concentration of a dopant that contributes to the second conductivity type increases as the distance from the first surface of the semiconductor substrate increases; and on the semiconductor layer And a first electrode made of a conductive material.

  According to a second aspect of the present invention, in the solar cell element according to the first aspect, the concentration of the dopant contributing to the second conductivity type in the semiconductor layer is continuously from the semiconductor substrate toward the first electrode. It is characterized by increasing.

  The invention according to claim 3 is the solar cell element according to claim 1, wherein the semiconductor layer includes a plurality of layers having different concentrations of dopants contributing to the second conductivity type, and each of the plurality of layers. Contains a dopant that contributes to the second conductivity type at a substantially constant concentration.

  Invention of Claim 4 contains the dopant which contributes to a said 1st conductivity type in the solar cell element in any one of Claim 1 thru | or 3 in a density | concentration higher than the said semiconductor substrate, The said semiconductor substrate The first doped layer provided in the second region of the first surface of the first and the second electrode provided on the first doped layer.

The invention according to claim 5 is the solar cell element according to claim 4, wherein the concentration of the dopant contributing to the second conductivity type contained in the semiconductor layer is a junction interface between the semiconductor layer and the semiconductor substrate. 1 × 10 ¹⁷ (cm ⁻³ ) or more and 1 × 10 ²⁰ (cm ⁻³ ) or less in the vicinity, and 1 × 10 ²¹ (cm ⁻³ ) or more and 1 in the vicinity of the junction interface between the semiconductor layer and the first electrode. It is characterized by being below 10 < ^{22 >} (cm <^-3> ).

  A sixth aspect of the present invention is the solar cell element according to the fourth or fifth aspect, wherein the dopant contributing to the first conductivity type is contained at a higher concentration than the semiconductor substrate, and And a second doped layer provided on the second surface.

  According to a seventh aspect of the present invention, in the solar cell element according to the sixth aspect, the first and second doped layers are provided as a thermal diffusion layer on an outer edge portion of the semiconductor substrate.

  According to an eighth aspect of the present invention, in the solar cell element according to any one of the first to third aspects, the semiconductor layer is formed on substantially the entire first surface of the semiconductor substrate. It further includes a second electrode having a transparent conductive layer on the second surface side of the substrate.

  The invention according to claim 9 is the solar cell element according to claim 8, wherein a dopant contributing to the first conductivity type is contained at a higher concentration than the semiconductor substrate, and the second surface of the semiconductor substrate is provided on the second surface. The semiconductor device further includes a doped layer provided, and the second electrode is provided on the doped layer.

  Invention of Claim 10 WHEREIN: In the solar cell element of Claim 9, the density | concentration of the dopant which contributes to the said 1st conductivity type in the said dope layer becomes high toward the said 2nd electrode from the said semiconductor substrate, It is characterized by that.

  The invention of claim 11 provides a step of preparing a semiconductor substrate of a first conductivity type, and a semiconductor layer having a second conductivity type in the first region of the first surface of the semiconductor substrate. A step of forming the dopant to develop the second conductivity type closer to a bonding interface with the substrate, a step of forming a first electrode on the semiconductor layer, and a step of forming the first electrode of the semiconductor substrate. Forming a second electrode in the second region of the first surface.

  According to a twelfth aspect of the present invention, in the method for manufacturing a solar cell element according to the eleventh aspect, in the step of forming the semiconductor layer, the semiconductor layer is formed using a gas containing at least silane and diborane, and the semiconductor layer is formed. The diborane flow rate is increased from the start to the end of layer formation.

  According to a thirteenth aspect of the present invention, in the method for manufacturing a solar cell element according to the eleventh aspect, in the step of forming the semiconductor layer, the second conductivity type is expressed on the first surface of the semiconductor substrate. After forming a doped layer having a substantially uniform dopant concentration, the semiconductor substrate is further exposed to a gas to diffuse the dopant from the surface of the doped layer.

  According to a fourteenth aspect of the present invention, in the method for manufacturing a solar cell element according to the eleventh aspect, in the step of forming the semiconductor layer, the second conductivity type is expressed on the first surface of the semiconductor substrate. After forming a doped layer having a substantially uniform dopant concentration, the dopant is further diffused from the surface of the doped layer by a coating diffusion method.

  According to the inventions of claims 1 to 14, since the concentration of the dopant contained in the semiconductor layer is relatively small in the vicinity of the junction interface with the semiconductor substrate, the defect density is in the vicinity of the junction interface. Is reduced, and recombination loss of carriers is suppressed. Moreover, since the concentration of the dopant contained in the semiconductor layer is relatively higher as it is closer to the junction interface with the first electrode, the contact resistance at the junction interface is reduced. Thereby, high power generation efficiency is realized in the solar cell element.

<First Embodiment>
<Overall structure of solar cell element>
FIG. 1 is a diagram showing a cross-sectional structure of solar cell element 100A according to the first embodiment of the present invention. FIG. 2 is a plan view showing the back side of the solar cell element 100A.

  In the present embodiment, description will be made using n-type as the first conductivity type and p-type as the second conductivity type.

  The solar cell element 100A according to the first embodiment includes a first surface 1a and a second surface 1b, and is doped with an n-type dopant (for example, P (phosphorus)), thereby being n-type. A semiconductor substrate 1 having an n-type semiconductor region 2 exhibiting a conductivity type, a doped layer 3 containing an n-type dopant (for example, P) at a higher concentration than the n-type semiconductor region 2, an amorphous silicon, and a p-type A p-type semiconductor layer 5 that exhibits p-type conductivity by being doped with a dopant (for example, B (boron)), a p-type electrode (first electrode) 6, an n-type electrode (second electrode) 9, An antireflection layer 4 is mainly provided.

  The solar cell element 100 </ b> A has a pn junction between the n-type semiconductor region 2 and the p-type semiconductor layer 5 of the semiconductor substrate 1. A pn junction formation region in the first surface 1a side of the semiconductor substrate 1 is referred to as a first region 1aa. Moreover, the area | region in which the back side doped layer (1st doped layer) 3a was formed among the 1st surface 1a sides of the semiconductor substrate 1 is called 2nd area | region 1ab. In addition, in the solar cell element 100A, the front surface side indicates the light receiving surface side (upper side in the drawing in FIG. 1), and the rear surface side indicates the back side of the front surface (the lower side in the drawing in FIG. 1).

  Solar cell element 100A has a structure (back contact) in which p-type electrode 6 and n-type electrode 9 are arranged only on the back surface side of solar cell element 100A. Thereby, in the solar cell element 100A, the conversion efficiency is improved, and since the electrode does not exist as a convex portion on the light receiving surface side, the aesthetic improvement is also realized.

  The semiconductor substrate 1 is, for example, a polycrystalline silicon substrate having n-type conductivity. A preferred example of the dimensions of the semiconductor substrate 1 is a size of about 10 cm × 10 cm to 21 cm × 21 cm and a thickness of 300 μm or less. Further, the thickness is more preferably 200 μm or less. The resistivity of the semiconductor substrate 1 is preferably about 0.3 to 5 Ω · cm.

  Preferably, a fine concavo-convex structure (texture structure) is formed on the second surface 1b side of the semiconductor substrate 1 by performing a roughening process prior to the formation of the doped layer 3 (see FIG. 8 (a)). When the semiconductor substrate 1 has such a structure, the reflection loss of light on the light receiving surface of the solar cell element 100A is reduced.

The doped layer 3 includes a back-side doped layer (first doped layer) 3 a provided in the second region 1 ab of the first surface 1 a of the semiconductor substrate 1 and a surface provided on the second surface 1 b of the semiconductor substrate 1. And a side doped layer (second doped layer) 3b. Here, “provided in the second region 1ab of the first surface 1a” and “provided in the second surface 1b” are formed on the first (second) surface of the semiconductor substrate 1. And a case where it is formed in the semiconductor substrate 1. Such a doped layer 3 is formed to have a thickness of about 20 nm to 5 μm. Preferably, the n-type semiconductor region 2 contains an n-type dopant at a concentration of about 1 × 10 ¹⁵ to 1 × 10 ¹⁷ (cm ⁻³ ), and the doped layer 3 is 1 × 10 ¹⁶ to 1 × 10 ^20. It contains an n-type dopant having a concentration of about (cm ⁻³ ). The effects obtained by forming the doped layer 3 in such a manner on the semiconductor substrate 1 will be described later.

  The p-type semiconductor layer 5 is formed on the first region 1aa of the first surface 1a of the semiconductor substrate 1. The p-type semiconductor layer 5 has a dopant concentration gradient in the thickness direction (vertical direction in the drawing). The dopant concentration of the p-type semiconductor layer 5 increases continuously (including the case of increasing continuously and monotonously) from the interface with the semiconductor substrate 1 toward the interface with the first seed layer 7. The p-type semiconductor layer 5 is preferably formed to have a thickness of about 5 nm to 30 nm.

  The p-type electrode 6 and the n-type electrode 9 are extraction electrodes for extracting generated electric power to the outside. In FIG. 2, each of the p-type electrode 6 and the n-type electrode 9 is a comb-like electrode having a plurality of electrode fingers, and the electrode fingers of the p-type electrode 6 and the n-type electrode 9 are alternately arranged (however, FIG. In FIG. 1, for convenience of illustration, only one electrode finger of both electrodes is shown).

  The p-type electrode 6 includes a first seed layer 7 and a first back electrode 8. The first seed layer 7 and the first back electrode 8 are sequentially formed on the surface of the p-type semiconductor layer 5 that is not connected to the semiconductor substrate 1 (the lower surface in the case of FIG. 1). .

  The n-type electrode 9 includes a second seed layer 10 and a second back electrode 11. The second seed layer 10 and the second back surface electrode 11 are sequentially formed on the back surface of the semiconductor substrate 1 in the formation region (first region) of the back surface side doped layer 3a.

  The first seed layer 7 and the second seed layer 10 function as a current collector in the p-type electrode 6 and the n-type electrode 9 and also serve as a base layer when the first back electrode 8 and the second back electrode 11 are formed by plating. Also plays a role as. The first seed layer 7 and the second seed layer 10 are formed to a thickness of about several hundred nm to several μm. The first seed layer 7 and the second seed layer 10 are, for example, Ni (nickel), W (tungsten), Co (cobalt), and alloys thereof, or alloys of Ni, W, Co, P, and B Formed of a conductive material. Alternatively, the first seed layer 7 and the second seed layer may be formed using a highly reflective material such as ITO (indium tin oxide) or Ag (silver). In this case, since the light incident from the light receiving surface side is reflected by the first seed layer 7 and the second seed layer 10, the transmission loss of the incident light is reduced.

  The first back electrode 8 and the second back electrode 11 are external extraction electrodes for the electric power generated in the solar cell element 100A. The first back electrode 8 and the second back electrode 11 have a thickness of about several μm. The first back electrode 8 and the second back electrode 11 are preferably formed of Cu. Alternatively, Ag, Al (aluminum), Cr (chromium), Ti (titanium), W, Mo (molybdenum), Ta (tantalum), Pt (platinum), Au (gold), Ni, Co, and alloys thereof A general electrode material may be used. Note that the first back electrode 8 and the second back electrode 11 can be formed without providing the first seed layer 7 and the second seed layer 10.

  The antireflection layer 4 is a layer provided for the purpose of reducing the reflection loss of light incident on the solar cell element 100A from the light receiving surface side. The antireflection layer 4 also serves as a protective layer for the semiconductor substrate 1. The antireflection layer 4 is formed so as to cover the surface side doped layer 3b. By forming the antireflection layer 4 in this way, the effect of passivation to the bulk and the surface of the semiconductor substrate 1 is increased, and the effect of improving the open circuit voltage and the short circuit current density can be obtained.

The constituent material and thickness of the antireflection layer 4 are determined in consideration of the difference in refractive index from the semiconductor substrate 1. The antireflection layer 4 is made of SiO ₂ (silicon oxide), SiN (silicon nitride), TiO ₂ (titanium oxide), MgF (magnesium fluoride), or the like, which is a material having a refractive index of about ₂ , and has a thickness of 50 to 200 nm. It is a preferable example that it is formed.

<Effect of dope layer formation>
Next, an effect obtained by providing the solar cell element 100A with the doped layer 3 in the above-described form will be described.

  First, in the doped layer 3, the surface-side doped layer 3 b is an FSF layer (surface electric field layer) having an effect (surface electric field effect) of reducing carrier recombination loss due to defects near the interface on the surface side of the semiconductor substrate 1. ). On the other hand, the back-side doped layer 3a functions as a BSF layer (back-side field layer) having an effect of reducing recombination loss (back-side field effect) due to carrier defects in the vicinity of the back-side interface of the semiconductor substrate 1. That is, providing the doped layer 3 on both surfaces of the semiconductor substrate 1 has an effect of improving the power generation efficiency in the solar cell element 100A.

  Preferably, the doped layer 3 is a thermal diffusion that heats the semiconductor substrate 1 to a temperature of about 900 ° C. in an atmosphere in which an n-type dopant atom such as P exists, and diffuses the n-type dopant atom into the semiconductor substrate 1. It is a thermal diffusion layer formed by the method (details will be described later). During such heating, metal impurities (for example, Fe, Cu, Al, etc.) contained in the semiconductor substrate 1 (in the n-type semiconductor region 2) diffuse and move to the doped layer 3 side, A metal gettering effect is obtained in which the concentration of these metal impurities in the n-type semiconductor region 2 is reduced. Thereby, since carrier recombination due to the presence of impurity atoms in n-type semiconductor region 2 is reduced, power generation efficiency in the solar cell element is further improved.

  In particular, the reduction of Fe impurities having a relatively large capture cross-sectional area with respect to holes also has an effect of improving the lifetime of the semiconductor substrate 1 made of polycrystalline silicon. In addition, from the viewpoint of providing a function as an FSF layer or a BSF, the doped layer 3 made of amorphous silicon is stacked on the surface of the semiconductor substrate 1 instead of the thermal diffusion layer as described above. May be.

  If the impurity concentration in the n-type semiconductor region 2 is reduced, carrier recombination due to the presence of impurity atoms in the n-type semiconductor region 2 is reduced, so that the doped layer 3 is formed as described above. It can be said that the solar cell element 100A has improved power generation efficiency by improving the quality of the n-type semiconductor region 2.

  On the other hand, dope layer 3 is not formed in the pn junction location of solar cell element 100A. That is, in the solar cell element 100A, a region containing impurities at a high concentration like the doped layer 3 does not exist in the vicinity of the pn junction interface. Thereby, in solar cell element 100A, the defect density at the pn junction interface is kept low, the defect density at the interface is kept low, and the recombination loss of carriers at the interface is reduced.

<Relationship between p-type semiconductor layer formation mode and power generation efficiency>
Next, the relationship between providing the concentration gradient as described above in the dopant concentration of the p-type semiconductor layer 5 and the power generation efficiency will be described.

  In general, in a solar cell element having a pn junction, defects near the pn junction interface cause carrier recombination loss near the junction interface. In a solar cell element having many defects near the pn junction interface and large recombination loss of carriers, it is difficult to obtain high power generation efficiency. Therefore, it is important to reduce the defect density near the pn junction interface to improve the power generation efficiency of the element. Become.

  In the p-type semiconductor layer 5 of the solar cell element 100A, as described above, the dopant concentration is relatively smaller in the region closer to the pn junction interface. As a result, the defect density in the vicinity of the pn junction interface of the p-type semiconductor layer 5 is smaller than in other regions of the p-type semiconductor layer 5. With such a configuration, in solar cell element 100A, the recombination loss of carriers in the vicinity of the pn junction interface is suppressed, and the power generation efficiency is improved.

Specifically, the dopant concentration of the p-type semiconductor layer 5 at the junction interface with the semiconductor substrate 1 is preferably 1 × 10 ¹⁷ (cm ⁻³ ) or more and 1 × 10 ²⁰ (cm ⁻³ ) or less. is there. By setting it as such a range, the influence of the defect in the pn junction interface vicinity is reduced, and it is hard to produce a malfunction in a recombination current and an open circuit voltage. Further, it is difficult to reduce the carrier tunneling probability in the p-type semiconductor layer 5, and the fill factor is unlikely to decrease.

  In the p-type semiconductor layer 5 of the solar cell element 100A, since the dopant concentration in the vicinity of the interface with the first seed layer 7 that is the semiconductor / metal junction interface is relatively high, the contact resistance (contact resistance) at the interface is sufficient. It is a small value. Thereby, in the solar cell element 100A, the electric power can be taken out satisfactorily.

The dopant concentration of the p-type semiconductor layer 5 at the junction interface with the first seed layer 7 is preferably 1 × 10 ²¹ (cm ⁻³ ) or more and 1 × 10 ²² (cm ⁻³ ) or less. By setting it as such a range, a contact resistance does not increase easily and a curve factor does not decrease easily. In addition, the internal electric field at the pn junction is unlikely to decrease.

  As described above, in the solar cell element 100 </ b> A, the dopant concentration of the p-type semiconductor layer 5 increases as the distance from the first surface 1 a of the semiconductor substrate 1 increases. Thereby, in the vicinity of the junction interface between the semiconductor substrate 1 and the p-type semiconductor layer 5, the defect density is small, the recombination loss of carriers is suppressed, and the p-type semiconductor layer 5, the first seed layer 7, and the vicinity of the junction. Then, contact resistance is small. With such a configuration, high power generation efficiency is realized in the solar cell element 100A.

<Method for producing solar cell element>
Next, a method for manufacturing the solar cell element 100A according to the first embodiment will be described. In the following description, a case where P is used as an n-type dopant and B is used as a p-type dopant will be described as an example. Furthermore, the case where the semiconductor substrate 1 manufactures the solar cell element 100A which has a surface uneven structure is demonstrated as an example. FIG. 3 is a diagram showing a flow of manufacturing steps of the solar cell element 100A. 4 and 5 are diagrams schematically showing the structure of the element in the middle of the manufacturing process.

  First, an n-type polycrystalline silicon ingot containing P as a n-type dopant atom at a predetermined concentration is formed by a casting method or the like, and cut into a predetermined size and thickness, whereby an n-type polycrystalline silicon substrate ( A semiconductor substrate 1) is obtained (step S1). In order to normalize the sliced surface of the obtained semiconductor substrate 1, it is slightly etched with an alkaline solution or a mixed solution.

  Subsequently, the surface of the semiconductor substrate 1 (that is, the surface on the light receiving surface side) is roughened by dry etching or wet etching, so that the surface of the semiconductor substrate 1 has unevenness having a function of reducing light reflectance. Form a structure.

  After the surface concavo-convex structure is formed by the reactive ion etching method, the etching residue remaining on the surface (uneven structure forming surface) of the semiconductor substrate 1 is removed.

  Next, as shown in FIG. 4A, a mask 20 is formed on the back side of the semiconductor substrate 1 so as to cover a region other than the region where the back side doped layer 3a is to be formed (step S2). That is, the region where the p-type semiconductor layer 5 is to be formed is covered with at least the mask 20 on the back surface side of the semiconductor substrate 1. The mask 20 may be formed as a thick film by a so-called application method such as application and baking of a liquid material, or may be formed as a thin film by a thin film formation method such as a CVD method or a sputtering method. .

Subsequently, as shown in FIG. 4B, a doped layer 3 is formed (step S3). For the formation of the doped layer 3, a coating thermal diffusion method is used in which paste-like P ₂ O ₅ (diphosphorus pentoxide) is applied to the entire front surface and back surface of the semiconductor substrate 1 on which the mask 20 is formed and thermally diffused. Can do. Alternatively, the mask 20 is formed also on the side surface of the semiconductor substrate 1, and a gas phase thermal diffusion method in which POCl ₃ (phosphorus oxychloride) in a gas state is thermally diffused as a diffusion source or ions that directly diffuse P ⁺ ions are used. A mode using a method such as a driving method may be used. In these methods, the semiconductor substrate 1 is heated to about 500 ° C. to 950 ° C. By such treatment, the doped layer 3 is formed on the front surface and the back surface of the semiconductor substrate 1 except for the formation region of the mask 20. The doped layer 3 may also be formed on the side surface of the semiconductor substrate 1.

  After the doped layer 3 is formed, the mask 20 is removed by etching with hydrofluoric acid or the like. FIG. 4C shows the semiconductor substrate 1 from which the mask 20 has been removed.

  Instead of using the mask 20, a high-concentration n-type doped layer is once formed on the entire surface of the semiconductor substrate 1 by a thermal diffusion method, and then a portion that does not need to remain as the doped layer 3 is etched and removed. A method may be used. Specifically, after a high-concentration n-type doped layer is formed on the entire surface of the semiconductor substrate 1, a resist is applied to a region where the doped layer is left as the doped layer 3, and then hydrofluoric acid or hydrofluoric acid and nitric acid are used. Etching is performed using the mixed solution, and the resist film is finally removed. In such a case, the etching may be performed by a mechanical method such as laser scribing or sand blasting. When the dopant concentration of the surface layer of the doped layer 3 is high, it is preferable to control the doping profile by etching with a mixed solution of hydrofluoric acid and nitric acid.

Subsequently, the semiconductor substrate 1 on which the doped layer 3 is formed is cleaned (step S4). The semiconductor substrate 1 is cleaned by wet cleaning or dry cleaning. Further, in order to remove the oxide film, the semiconductor substrate 1 is immersed in hydrofluoric acid or NH ₄ F (ammonium fluoride) solution, and then washed with water.

  After the above-described cleaning, as shown in FIG. 4D, the p-type semiconductor layer 5 is formed (step S5). For the formation of the p-type semiconductor layer 5, a PECVD method, a CatCVD method, a vapor deposition method, a sputtering method, or the like can be used. The p-type semiconductor layer 5 is masked with a metal mask or the like in a non-formation region (a region excluding a region where a pn junction is scheduled to be formed on the back surface of the semiconductor substrate 1), and then on the back surface of the semiconductor substrate 1. A thickness of 5 nm to 30 nm is formed.

For example, if the PECVD method is used, H ₂ (hydrogen), SiH ₄ (silane), and B ₂ H ₆ (diborane) are used as source gases, the gas pressure in the chamber of the PECVD apparatus is 1 to 5 Torr, and the substrate. A preferred example is to form B-doped amorphous silicon under a growth condition of 100 ° C. to 200 ° C.

  At this time, the closer to the back surface of the semiconductor substrate 1, the smaller the B concentration, and the farther from the back surface of the semiconductor substrate 1 (the closer to the region where the first seed layer 7 is to be formed in the p-type semiconductor layer 5), the B concentration becomes. In order to form the p-type semiconductor layer 5 so as to be large, the p-type semiconductor layer 5 may be formed while changing the gas flow ratio of silane and diborane. Specifically, the flow rate ratio of diborane may be increased as time passes. For example, the flow rate ratio of hydrogen, silane, and diborane is 1: 1: 0.001 in 30 seconds from the start to the end of formation. A suitable example is changing from 1: 1 to 0.1.

  Further, as another method of forming the p-type semiconductor layer 5, after forming a doped layer having a uniform B concentration on the back surface of the semiconductor substrate 1 (for example, by using the PECVD method, the flow rate ratio of the source gas is made constant, After the formation of the B-doped amorphous silicon layer, a method of diffusing B from the surface of the doped layer by exposing the semiconductor substrate 1 to a gas plasma of diborane in the chamber may be used.

  Alternatively, after a doped layer having a uniform B concentration is formed on the back surface of the semiconductor substrate 1, a PBF (polyboron film), which is a liquid material, is applied to the back surface of the doped layer (the surface opposite to the semiconductor substrate 1). Thus, the p-type semiconductor layer 5 may be formed using a method (coating diffusion method) for diffusing B into the doped layer.

  In order to form the p-type semiconductor layer 5 in a desired region on the back surface of the semiconductor substrate 1, a photolithography method or the like may be used in addition to the method of masking the non-formed region with the above-described metal mask or the like.

  Next, as shown in FIG. 5A, the antireflection layer 4 is formed (step S6). The antireflection layer 4 can be formed by PECVD, sputtering, or vapor deposition. In the case of forming the antireflection layer 4 made of SiN, it is performed by a PECVD method using ammonia, hydrogen and silane as source gases, or a sputtering method using an etching gas.

  Next, as shown in FIG. 5B, the first seed layer 7 and the second seed layer 10 are formed (step S7). The first seed layer 7 and the second seed layer 10 are formed of Ni, W, Co, and alloys thereof, or alloys of Ni, W, Co, P, and B. The first seed layer 7 and the second seed layer 10 can be formed by electroless plating. In this case, it is preferable to form the chemical solution at a temperature of 150 ° C. or less and a thickness of 1 μm or less. The first seed layer 7 and the second seed layer 10 function as a base layer when the first back electrode 8 and the second back electrode 11 are formed later.

  It is necessary to form the first seed layer 7 constituting the p-type electrode 6 and the second seed layer 10 constituting the n-type electrode 9 so that they are not continuous (so as to be insulated from each other). This is because, when performing electroless plating for forming each, the formation target region (in the case of the first seed layer 7, in the p-type semiconductor layer 5, substantially the entire surface opposite to the connection surface with the semiconductor substrate 1). In the case of the second seed layer 10, it is realized by selectively activating only the formation region (first region) of the back-side doped layer 3 a on the back side of the semiconductor substrate 1. Alternatively, after forming the metal layer constituting the first seed layer 7 and the second seed layer 10 on the entire back surface side of the semiconductor substrate by electroless plating, unnecessary portions may be removed using a laser. Good. Instead of removing by laser, a method of covering other than unnecessary portions with a resist film or the like and etching away the unnecessary portions can be used.

  Finally, as shown in FIG. 5C, the first back electrode 8 and the second back electrode 11 are formed (step S8). As the first back electrode 8 and the second back electrode 11, it is preferable to form Cu as a forming material by electrolytic plating. In addition, after performing electroless plating, a drying process is performed at the temperature of 50-350 degreeC for the adhesive strength improvement.

  The first back electrode 8 and the second back electrode 11 are formed by applying a conductive paste by various coating methods such as screen printing, doctor blade method, or dispenser coating method in addition to electrolytic plating. Various vacuum film forming methods such as a firing method, a sputtering method, and a vapor deposition method can also be used. As a material for forming the back electrode, Cu, Ag, Al, Cr, Ti, W, Mo, Ta, Pt, Au, Ni, Co and alloys thereof can be used according to the manufacturing method.

  Through the above steps, the solar cell element 100A according to the first embodiment is completed.

<Second Embodiment>
Next, a solar cell element 100B according to the second embodiment will be described. FIG. 6 is a diagram showing a cross-sectional structure of solar cell element 100B according to the second embodiment. In addition, about the component which show | plays the effect similar to 100 A of solar cell elements which concern on 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted below.

  Solar cell element 100B according to the present embodiment is different from solar cell element 100A in that p-type semiconductor layer 5 is composed of two layers having different dopant concentrations.

  Specifically, the p-type semiconductor layer 5 of the solar cell element 100 </ b> B is a dopant in contact with the first seed layer 7 and the first p-type semiconductor layer 5 a bonded to the semiconductor substrate 1 and having a relatively low dopant concentration. It consists of two layers, the second p-type semiconductor layer 5b having a relatively high concentration.

  Also in the solar cell element 100B having such a configuration, similarly to the solar cell element 100A, the defect density is small in the vicinity of the junction interface between the p-type semiconductor layer 5 and the semiconductor substrate 1, and the recombination loss of carriers is suppressed. In addition, the contact resistance at the junction interface between the p-type semiconductor layer 5 and the first seed layer 7 is also reduced. Therefore, high power generation efficiency is realized also in the solar cell element 100B.

The dopant concentration of the first p-type semiconductor layer 5a is 1 × 10 ¹⁷ (cm ⁻³ ) or more and 1 × 10 ²⁰ (cm ⁻³ ) or less, and the dopant concentration of the second p-type semiconductor layer 5b is 1 × 10 ²¹ ( It is preferable that it is not less than cm ^{−3 and not} more than 1 × 10 ²² (cm ⁻³ ). The thickness of the p-type semiconductor layer 5 is preferably about 5 nm to 30 nm, and the thickness ratio of the low-concentration p-type semiconductor layer 5a to the high-concentration p-type semiconductor layer 5b is preferably about 5: 1 to 3: 2. This is an example.

  However, in the solar cell element 100B, since the dopant concentration changes discontinuously at the interface between the first p-type semiconductor layer 5a and the second p-type semiconductor layer 5b, carrier recombination is likely to occur near the interface. . Accordingly, the recombination loss of carriers inside the p-type semiconductor layer 5 is slightly larger than that of the solar cell element 100A, but the effect of improving the power generation efficiency can be sufficiently obtained.

  The solar cell element 100B can be formed by substantially the same process as in the case of the first embodiment shown in FIGS. In order to make the p-type semiconductor layer 5 have the above-described two-layer structure, for example, if a method by PECVD is used, the flow rate ratio of diborane, silane, and hydrogen is set to a predetermined value and the first p-type semiconductor layer is formed. 5a may be formed, and then the second p-type semiconductor layer 5b may be formed with a larger flow ratio of diborane to silane.

  As described above, high power generation efficiency is also realized in the solar cell element 100B according to the second embodiment.

<Third Embodiment>
In the first and second embodiments, the back contact solar cell element has been described, but the configuration in which the concentration gradient is provided in the thickness direction with respect to the dopant concentration of the p-type semiconductor layer is provided on both the front and back surfaces of the element. It is applicable also to the solar cell element which has an electrode. In this embodiment, a solar cell element having such a configuration will be described.

  FIG. 7 is a diagram showing a cross-sectional structure of a solar cell element 200 according to the third embodiment. The solar cell element 200 includes an n-type semiconductor layer 202 containing an n-type dopant such as P, a doped layer 203 containing an n-type dopant at a higher concentration than the n-type semiconductor layer 202, and a p-type such as B. A p-type semiconductor layer 205 containing the dopant, a p-type electrode 206, and an n-type electrode 209. In the solar cell element 200, the n-type semiconductor layer 202 and the p-type semiconductor layer 205 form a pn junction. In the solar cell element 200, the p-type electrode 206 side is the light-receiving surface side (front surface side), and the n-type electrode 209 side is the back surface side.

The doped layer 203 is a layer formed on the back side of the semiconductor substrate 201 which is a polycrystalline silicon substrate exhibiting n-type conductivity. Further, the n-type semiconductor layer 202 is a layer constituting a portion other than the doped layer 203 in the semiconductor substrate 201. The n-type semiconductor layer 202 contains an n-type dopant at a concentration of about 1 × 10 ¹⁵ to 1 × 10 ¹⁷ (cm ⁻³ ), and the doped layer 203 has an n-type concentration of about 1 × 10 ¹⁶ to 1 × 10 ^20. Contains a type of dopant. In addition to the method of forming a diffusion layer on the semiconductor substrate 201, the doped layer 203 may be formed by a method of forming an amorphous silicon film containing an n-type dopant at a high concentration on the surface of the semiconductor substrate 201. The semiconductor substrate 201 is preferably formed to a thickness of about 50 μm to 300 μm, and the doped layer 203 is preferably formed to a thickness of about 5 nm to 5 μm.

  The p-type semiconductor layer 205 is formed on the entire light receiving surface side of the semiconductor substrate 201. The p-type semiconductor layer 205 is doped with a dopant so that the dopant concentration continuously increases from the interface with the semiconductor substrate 201 toward the interface with the first transparent conductive layer 207. That is, similar to the p-type semiconductor layer 5 in the solar cell element 100A, in the p-type semiconductor layer 205, the dopant concentration is relatively small in the vicinity of the pn junction interface (junction interface with the semiconductor substrate 201). The dopant concentration is relatively high in the vicinity of the bonding interface (bonding interface with the first transparent conductive layer 207).

  The p-type electrode 206 is formed at a predetermined position of the first transparent conductive layer 207 formed on the entire surface of the p-type semiconductor layer 205 opposite to the surface bonded to the semiconductor substrate 201 and the first transparent conductive layer 207. And the first electrode 208. The n-type electrode 209 includes a second transparent conductive layer 210 formed on the entire back surface of the semiconductor substrate 201 and a second electrode 211 formed at a predetermined position of the second transparent conductive layer.

The first transparent conductive layer 207 and the second transparent conductive layer 210 are current collectors in the solar cell element 200, such as ITO, Ga or Al doped ZnO, fluorine doped SnO _{2 and} other metal oxides. It is formed of a translucent conductive material.

  The first electrode 208 and the second electrode 211 are external extraction electrodes in the solar cell element 200, and are the same as the first back electrode 8 and the second back electrode 11 in the solar cell element 100A according to the first embodiment. It is formed of an electrode material.

  Also in the solar cell element 200 having such a configuration, the dopant concentration of the p-type semiconductor layer 205 is relatively low as in the solar cell element 100A, and therefore, the pn junction interface (the junction between the p-type semiconductor layer 205 and the semiconductor substrate 201). In the vicinity of the interface), the defect density is small, the recombination loss of carriers is reduced, and the dopant concentration of the p-type semiconductor layer 205 is relatively high, so that the metal / semiconductor junction interface (p-type semiconductor layer 205). The contact resistance at the bonding interface between the first transparent conductive layer 207 and the first transparent conductive layer 207 is also reduced.

  Thus, also in the p-type semiconductor layer 205 of the solar cell element 200, the same structure and effect as the p-type semiconductor layer 5 of the solar cell element 100A can be obtained. Therefore, high power generation efficiency is also realized in solar cell element 200 according to the present embodiment having a configuration in which electrodes are provided on both sides of the front and back surfaces of the element.

<Modification>
In the above-described embodiment, the case where the semiconductor substrate 1 is an n-type polycrystalline silicon substrate has been described. However, the material of the semiconductor substrate 1 is not limited to polycrystalline silicon, but may be single crystal silicon or another semiconductor. Good.

  In the case of the above-described first and second embodiments, there may be a region that does not belong to either the first region 1aa or the second region 1ab on the back surface of the semiconductor substrate 1. It is good also as an aspect in which the back surface of the board | substrate 1 is exposed, and you may make it form an insulating layer.

  In the first and second embodiments described above, the mode in which the surface-side doped layer 3b is formed on the entire light-receiving surface side of the semiconductor substrate 1 has been described. However, instead of the surface-side doped layer 3b, i A type of amorphous silicon layer or insulating layer may be formed.

  In addition, as described above, in the first and second embodiments, it is preferable to form a concavo-convex structure on the light receiving surface side of the semiconductor substrate 1 in order to reduce the reflection loss of light on the light receiving surface, The aspect which forms the antireflection layer 4 in the light-receiving surface shape of the semiconductor substrate 1 which has such an uneven structure is shown. However, the aspect of reducing the reflection loss of light on the light receiving surface is not limited to this.

  FIG. 8 is a schematic cross-sectional view showing the structure on the light receiving surface side of the semiconductor substrate 1 and the formation mode of the antireflection layer 4. FIG. 8A shows a structure provided in the solar cell element 100A according to the first embodiment. That is, the light-receiving surface itself of the semiconductor substrate 1 has a concavo-convex structure, and the antireflection layer 4 formed thereon is also formed in a manner that inherits the concavo-convex structure.

  Instead of this, as shown in FIG. 8 (b), the uneven structure is not formed on the light receiving surface of the semiconductor substrate 1, and the uneven structure is formed on the surface of the antireflection layer 4 provided thereon. Good. Even in the solar cell element having such a structure, an effect of reducing reflection loss of light can be obtained.

  The antireflection layer 4 having a concavo-convex structure on the surface is formed, for example, after the antireflection layer 4 is once formed to have a flat surface on the light receiving surface side of the semiconductor substrate 1 having a flat surface. Thus, it may be performed by performing a process such as etching, or by appropriately adjusting the formation conditions of the antireflection layer 4 so that the concavo-convex structure is directly formed in the film growth process. You may do it.

  In the above-described second embodiment, the case where the p-type semiconductor layer 5 is composed of two layers of the first p-type semiconductor layer 5a and the second p-type semiconductor layer 5b has been described. The layer 5 may be configured by three or more layers having different concentrations.

  In the third embodiment, the dopant concentration of the p-type semiconductor layer 205 is continuously increased from the junction interface with the semiconductor substrate 201 toward the junction interface with the first transparent conductive layer 207. Although the case where the concentration gradient that increases is described has been described, the p-type semiconductor layer 205 is configured by a plurality of layers having different dopant concentrations, like the solar cell element 100B according to the second embodiment. It may be.

  Further, in the above-described third embodiment, with respect to the solar cell element 200, the p-type electrode 206 side (the lower side in the drawing in FIG. 7) is the light receiving surface side, and the n-type electrode 209 side (the in the drawing in FIG. 7). Although the case where the upper side is the back side has been described, the p-type electrode 206 side may be the back side, and the n-type electrode 209 side may be the light receiving surface side. Also in this aspect, the solar cell element 200 achieves the same effect as when the p-type electrode 206 side is the light-receiving surface side and the n-type electrode 209 side is the back surface side, and thus high power generation efficiency is realized.

  In the solar cell element 200 according to the third embodiment, a concentration gradient may be provided for the concentration of the n-type dopant in the doped layer 203. Specifically, the concentration of the n-type dopant in the doped layer 203 is relatively smaller as it is closer to the n-type semiconductor layer 202 and close to the concentration of the n-type dopant in the n-type semiconductor layer 202. A concentration gradient may be provided, and a concentration gradient may be provided such that the closer to the n-type electrode 209, the higher the concentration.

  By forming the doped layer 203 as described above, in the solar cell element 200, the defect density is reduced near the interface between the doped layer 203 and the n-type semiconductor layer 202, and the recombination loss near the junction interface is reduced. In addition, the contact resistance can be reduced at the bonding interface between the doped layer 203 and the second transparent conductive layer 210. Thereby, the further improvement of power generation efficiency can be aimed at.

  Note that the solar cell element 200 provided with the doped layer 203 may also have a mode in which the p-type electrode 206 side is the back surface side and the n-type electrode 209 side is the light receiving surface side.

(Example)
As an example, a solar cell element 100A according to the first embodiment was produced.

As the semiconductor substrate 1, a polycrystalline silicon substrate having a size of 10 cm × 10 cm, a thickness of 200 μm, and doped with P as a n-type dopant at a concentration of 1 × 10 ¹⁶ (cm ⁻³ ) was prepared. The resistivity of the semiconductor substrate 1 was 0.5 Ω · m.

The surface of the semiconductor substrate 1 was roughened by a reactive ion etching method. Roughening is performed in an RIE apparatus at a flow rate of 12 sccm for CHF ₃ , 72 sccm for Cl ₂ , 9 sccm for O _2, and 65 sccm for SF ₆ , a reaction pressure of 50 mTorr, RF power of 500 W, and 3 minutes. It was. Thereafter, ultrasonic cleaning was performed to remove etching residues.

A thermal diffusion method was used to form the doped layer 3. The heating temperature of the semiconductor substrate 1 at that time was set to 800 ° C. As the diffusion mask 20, a thick SiO ₂ film was formed by a coating method. The dopant concentration of the obtained doped layer 3 was 2 × 10 ¹⁷ (cm ⁻³ ).

The p-type semiconductor layer 5 was formed by PECVD using B as a p-type dopant. The p-type semiconductor layer 5 was formed to a thickness of 23 nm. The gas pressure in the chamber of the PECVD apparatus was 0.5 Torr, and the substrate temperature was 170 ° C. The B concentration was controlled by changing the flow rate ratio of SiH ₄ and B ₃ H ₆ from 1: 0.001 to 1: 0.1 during 30 seconds.

  As the antireflection layer 4, a SiN layer was formed to a thickness of 100 nm. The SiN layer was formed by using PECVD and using ammonia, hydrogen, and silane as source gases.

  As the first seed layer 7 and the second seed layer 10, a Ni layer was formed to a thickness of 0.3 μm. The Ni layer was formed by electroless plating. Nickel hypophosphite was used as the chemical for plating, and the chemical temperature was set to 90 ° C. or lower.

  As the 1st back electrode 8 and the 2nd back electrode 11, Cu electrode was formed in thickness of 80 micrometers. The formation of the Cu electrode was performed by electrolytic plating. In addition, after electrolytic plating formation, the drying process was performed at 150 degreeC in order to improve adhesive strength.

  In addition, about the solar cell element produced in this way, the concentration distribution (concentration profile) of B in the thickness direction of the p-type semiconductor layer 5 was measured by SIMS (secondary ion mass spectrometer). FIG. 9 is a diagram showing a concentration profile of B contained in the p-type semiconductor layer 5 for the solar cell element according to the example. In FIG. 9, the horizontal axis indicates the distance from the junction interface between the p-type semiconductor layer 5 and the first seed layer 7, and the vertical axis indicates the B concentration on a logarithmic scale. Note that the position of the distance d = 23.0 (nm) in the figure indicates the junction interface between the p-type semiconductor layer 5 and the semiconductor substrate 1.

As shown in FIG. 9, in the solar cell element according to the example, the B concentration of the p-type semiconductor layer 5 is about 3 × 10 ²¹ (cm ⁻³ ) at the junction interface with the first seed layer 7. It is about 2 × 10 ¹⁹ (cm ⁻³ ) at the bonding interface with the substrate 1, and decreases approximately monotonically from the bonding interface with the first seed layer 7 to the bonding interface with the semiconductor substrate 1. That is, it can be said that the B concentration in the p-type semiconductor layer 5 increases monotonously from the junction interface with the semiconductor substrate 1 to the junction interface with the first seed layer 7.

About the solar cell element as described above, the current-voltage characteristics at the time of light irradiation were measured, and the short circuit current I _sc , the open circuit voltage V _oc , the _fill factor FF, and the conversion efficiency η were obtained.

(Comparative Example 1)
As Comparative Example 1, the p-type semiconductor layer 5 has the same configuration as that of the solar cell element according to the example except that the B concentration is substantially constant at 1 × 10 ²¹ (cm ⁻³ ) and the thickness is 20 nm. A solar cell element was produced. Also in such a solar cell element, current-voltage characteristics at the time of light irradiation were measured, and a short circuit current I _sc , an open circuit voltage V _oc , a _fill factor FF, and a conversion efficiency η were obtained.

(Comparative Example 2)
As Comparative Example 2, instead of the p-type semiconductor layer 5, an i-type amorphous silicon layer having a thickness of 15 nm, a thickness of 10 nm, and a B concentration of 5 × are formed in the first region 1aa on the back surface side of the semiconductor substrate 1. A solar cell element having the same configuration as that of the solar cell element according to the example was manufactured except that a substantially constant p-type amorphous silicon layer was formed in this order at 10 ²⁰ (cm ⁻³ ).

  The PECVD method was used to form the i-type and p-type amorphous silicon layers. The gas pressure in the chamber of the PECVD apparatus was 0.5 Torr for all, and the substrate temperature was 170 ° C. for all. As the source gas, hydrogen and silane were used for forming the i-type amorphous silicon layer, and hydrogen, silane and diborane were used for forming the p-type amorphous silicon layer.

Also in such a solar cell element, current-voltage characteristics at the time of light irradiation were measured, and a short circuit current I _sc , an open circuit voltage V _oc , a _fill factor FF, and a conversion efficiency η were obtained.

(Comparative Example 3)
As a comparative example 3, instead of the p-type semiconductor layer 5, a p-type amorphous silicon layer and a dopant B are provided with a gradient in the first region 1aa on the back surface side of the semiconductor substrate 1 with a gradient. Except that the amorphous silicon layer was formed in this order, a solar cell element having the same configuration as the solar cell element according to the example was produced. The total thickness of the i-type amorphous silicon layer and the p-type amorphous silicon layer is 18 nm. The B concentration in the p-type amorphous silicon layer is non-doped at the junction interface with the i-type amorphous silicon layer, and 1 × 10 ²¹ (cm ⁻³ ) at the junction interface with the first seed layer 7. . Further, the concentration of the dopant B is increased approximately monotonically from the junction interface with the first seed layer 7 to the i-type amorphous silicon layer.

  The i-type amorphous silicon layer was formed by PECVD. The gas pressure in the chamber of the PECVD apparatus was 0.5 Torr, and the substrate temperature was 170 ° C. Further, hydrogen and silane were used as the source gas.

The formation of the p-type amorphous silicon layer was also performed by PECVD. The gas pressure in the chamber of the PECVD apparatus was 0.5 Torr, and the substrate temperature was 170 ° C. The concentration of B was controlled by changing the flow rate ratio of SiH ₄ and B ₂ H ₆ from 1: 0 to 1: 0.1 in 30 seconds.

Also in such a solar cell element, current-voltage characteristics at the time of light irradiation were measured, and a short circuit current I _sc , an open circuit voltage V _oc , a _fill factor FF, and a conversion efficiency η were obtained.

(Comparison of Example and Comparative Example)
Table 1 shows the evaluation results of the solar cell elements according to Examples and Comparative Examples 1 to 3 obtained as described above. In addition, the value shown in Table 1 is normalized with the value obtained for the solar cell element of Comparative Example 2 being 1.00.

  Table 1 shows that, in the solar cell element according to the example, a power generation efficiency η having a larger value than that of any of the solar cell elements of Comparative Examples 1 to 3 was obtained. That is, as in the embodiment, a pn junction is formed by the n-type semiconductor region 2 and the p-type semiconductor layer 5, and is closer to the n-type semiconductor region 2 with respect to the dopant concentration contained in the p-type semiconductor layer 5. It was confirmed that the power generation efficiency higher than that of the conventional solar cell element can be obtained by forming the concentration gradient so as to increase as the distance increases and decrease as the distance increases.

It is a figure which shows the cross-section of 100 A of solar cell elements. It is a top view which shows the back surface side of 100 A of solar cell elements. It is a figure which shows the manufacturing process of 100 A of solar cell elements. It is process sectional drawing for demonstrating the manufacturing method of 100 A of solar cell elements. It is process sectional drawing for demonstrating the manufacturing method of 100 A of solar cell elements. It is a figure which shows the cross-section of the solar cell element 100B. 3 is a view showing a cross-sectional structure of a solar cell element 200. FIG. 2 is a schematic cross-sectional view showing a structure of a light receiving surface side of a semiconductor substrate 1 and a formation mode of an antireflection layer 4. FIG. It is a figure which shows the density | concentration profile of B in the p-type semiconductor layer 5 about the solar cell element which concerns on an Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 N type semiconductor region 3 Doped layer 3a Back side doped layer 3b Front side doped layer 5 P type semiconductor layer 5a First p type semiconductor layer 5b Second p type semiconductor layer 6 P type electrode 9 N type electrode 100A, B, 200 Solar cell element

Claims (14)

A semiconductor substrate including a first surface and a second surface and having a first conductivity type;
A concentration of a dopant provided in the first region of the first surface of the semiconductor substrate and having a second conductivity type and contributing to the second conductivity type is from the first surface of the semiconductor substrate. A semiconductor layer that grows with increasing distance,
A first electrode provided on the semiconductor layer and made of a conductive material;
A solar cell element characterized by comprising: The solar cell element according to claim 1,
The solar cell element, wherein a concentration of a dopant contributing to the second conductivity type in the semiconductor layer continuously increases from the semiconductor substrate toward the first electrode. The solar cell element according to claim 1,
The semiconductor layer includes a plurality of layers having different concentrations of dopants contributing to the second conductivity type,
Each of the plurality of layers contains a dopant that contributes to the second conductivity type at a substantially constant concentration. In the solar cell element according to any one of claims 1 to 3,
A first doped layer containing a dopant contributing to the first conductivity type at a higher concentration than the semiconductor substrate and provided in a second region of the first surface of the semiconductor substrate; and the first doped layer And a second electrode provided on the solar cell element. In the solar cell element according to claim 4,
The concentration of the dopant contributing to the second conductivity type contained in the semiconductor layer is 1 × 10 ¹⁷ (cm ⁻³ ) or more and 1 × 10 ²⁰ (cm ³ ) in the vicinity of the junction interface between the semiconductor layer and the semiconductor substrate. ^-3 ) or less, and is 1 × 10 ²¹ (cm ⁻³ ) or more and 1 × 10 ²² (cm ⁻³ ) or less in the vicinity of the junction interface between the semiconductor layer and the first electrode. Battery element. In the solar cell element according to claim 4 or 5,
A solar cell comprising a dopant that contributes to the first conductivity type at a concentration higher than that of the semiconductor substrate, and further comprising a second doped layer provided on the second surface of the semiconductor substrate. element. In the solar cell element according to claim 6,
The solar cell element, wherein the first and second doped layers are provided as thermal diffusion layers on an outer edge portion of the semiconductor substrate. In the solar cell element according to any one of claims 1 to 3,
The semiconductor layer is formed on substantially the entire surface of the first surface of the semiconductor substrate,
The solar cell element further comprising a second electrode having a transparent conductive layer on the second surface side of the semiconductor substrate. The solar cell element according to claim 8, wherein
A dopant that contributes to the first conductivity type at a higher concentration than the semiconductor substrate; and further comprising a doped layer provided on the second surface of the semiconductor substrate, wherein the second electrode is on the doped layer A solar cell element, characterized in that it is provided on the solar cell element. In the solar cell element according to claim 9,
The solar cell element, wherein a concentration of a dopant contributing to the first conductivity type in the doped layer increases from the semiconductor substrate toward the second electrode. Preparing a semiconductor substrate of a first conductivity type;
In the first region of the first surface of the semiconductor substrate, the concentration of the dopant that causes the semiconductor layer having the second conductivity type to develop the second conductivity type is smaller as the semiconductor interface is closer to the junction interface with the semiconductor substrate. A step of forming so that
Forming a first electrode on the semiconductor layer;
Forming a second electrode in a second region of the first surface of the semiconductor substrate;
A method for producing a solar cell element, comprising: In the manufacturing method of the solar cell element according to claim 11,
In the step of forming the semiconductor layer, the semiconductor layer is formed using a gas containing at least silane and diborane, and the flow rate of the diborane is increased from the start to the end of the formation of the semiconductor layer. Manufacturing method of solar cell element. In the manufacturing method of the solar cell element according to claim 11,
In the step of forming the semiconductor layer, after forming a doped layer having a substantially uniform concentration of the dopant that develops the second conductivity type on the first surface of the semiconductor substrate, the semiconductor substrate is further gasified The method for manufacturing a solar cell element is characterized in that the dopant is diffused from the surface of the doped layer. In the manufacturing method of the solar cell element according to claim 11,
In the step of forming the semiconductor layer, after forming a doped layer having a substantially uniform concentration of the dopant for expressing the second conductivity type on the first surface of the semiconductor substrate, further, by a coating diffusion method, The manufacturing method of the solar cell element characterized by diffusing the dopant from the surface of the doped layer.

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