JP2010140239A - Apparatus and method for shortening interrupt latency - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and method that ensure a response within a fixed time by effectively shortening interrupt latency, which is the time from the generation of a request for interrupt handling by a device to the invocation of a handler for interrupt handling. <P>SOLUTION: The apparatus includes a general purpose CPU and an interrupt processor for executing an interrupt handling program for executing interrupt handling prioritized over other processing. The interrupt processor includes an interrupt handling execution unit for executing interrupt handling, a memory for storing the interrupt handling program for executing interrupt handling, an interrupt detection part for detecting an execution request requesting the execution of interrupt handling, and an interrupt handling selection part for selecting whether to execute interrupt handling on the general purpose CPU or on the interrupt handling execution unit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an apparatus and a method capable of shortening an interrupt latency, which is a time from when a device requests execution of interrupt processing to when an interrupt processing handler is called, and guaranteeing a response within a predetermined time.

  Conventionally, when an interrupt process occurs, the interrupt controller that detects the interrupt request notifies the CPU of the interrupt request, and the CPU executes the interrupt process based on the interrupt process program stored in the storage device. FIG. 1 is a block diagram showing a specific example of conventional interrupt processing execution.

  In FIG. 1, when the interrupt controller 2 detects an interrupt request from any of the plurality of devices 1, 1,..., The interrupt controller 2 notifies the interrupt request to the CPU 3, and the CPU 3 responds to the interrupt request. Process 4 is performed.

  Conventional interrupt processing is performed in the following procedure. When the external interrupt is not prohibited, the CPU 3 raises an external interrupt exception and calls an OS (operating system) 6 exception handler. In the exception handler, the state of the program (hereinafter referred to as context information) executed immediately before the interrupt occurs is saved, and it is confirmed by reading the register of the interrupt controller 2 which device caused the interrupt. When a device is specified, an interrupt processing routine of the device driver 7 corresponding to the specified device is called (this processing is hereinafter referred to as dispatch) (first level). In the interrupt processing routine, only processing with high urgency is executed (second level), and a signal is transmitted so that the main processing can be executed later, and the processing ends. Thereafter, when time is available, the signal is received, and main processing is executed (third level). Further, more advanced processing is executed by the middleware or application 8 (fourth level).

  It is desirable to complete the interrupt processing in a short time so as not to affect other tasks. However, if there is even one device that requires a considerable amount of time for interrupt processing, the interrupt processing occupies the CPU 3, and other processing enters a wait state until the interrupt processing handler is called from the interrupt request. It may be difficult to shorten the interrupt latency, which is time. That is, there is a potential problem that the process 5 including the first level and the second level of the interrupt process becomes a bottleneck, and the execution of the interrupt process is delayed.

For example, in Patent Document 1, a processor for high-speed interrupt processing and a processor for low-speed interrupt processing are provided. During execution of high-speed interrupt processing, the processor for low-speed interrupt processing is stopped and the CPU register associated with interrupt processing is changed. A high-speed interrupt processing method is disclosed in which the interrupt latency is shortened by shortening the save and return times. Patent Document 2 includes a main general-purpose CPU and a priority interrupt dedicated CPU having another register. When interrupt processing occurs, the priority interrupt dedicated CPU executes interrupt processing to save register saving and restoration times. A semiconductor device that shortens the interrupt latency by eliminating it is disclosed.
JP-A-49-95548 JP-A-9-185591

  However, the high-speed interrupt processing method disclosed in Patent Document 1 is substantially the same as that executed by a single processor because a plurality of processors are not executed simultaneously. In Patent Document 2, it is possible to eliminate the time for saving and restoring the CPU registers associated with interrupt processing, but the number of CPUs dedicated to priority interrupts is required as many as the number of interrupt signals generated.

  The present invention has been made in view of such circumstances, and effectively reduces the interrupt latency, which is the time from when a device requests execution of interrupt processing until the interrupt processing handler is called, within a certain period of time. It is an object of the present invention to provide an apparatus and a method that can guarantee the response of the system.

  In order to achieve the above object, an apparatus according to a first aspect of the present invention includes a general-purpose CPU and an interrupt processor that executes an interrupt processing program for executing an interrupt process that has priority over other processes. The processor includes an interrupt processing execution unit that executes interrupt processing, a memory that stores an interrupt processing program for executing interrupt processing, an interrupt detection unit that detects an execution request that requests execution of interrupt processing, and an interrupt processing An interrupt process selection unit that selects whether to execute the program by the general-purpose CPU or the interrupt process execution unit.

  According to a second aspect of the present invention, in the first aspect, the interrupt processor includes a timer that counts time, and the interrupt processing selection unit performs a predetermined condition every time a predetermined time elapses due to time count by the timer. A signal serving as a basis for determining whether or not is satisfied, the interrupt processing execution unit determines whether or not a predetermined condition is satisfied based on the output signal, and the interrupt processing Select whether to execute interrupt processing in the execution unit.

  According to a third aspect of the present invention, in the second aspect, the interrupt processor is capable of executing a plurality of interrupt processes up to a fixed number of tasks, and the interrupt process execution unit includes the interrupt process. Each time, it is determined whether or not a condition that can be executed by the round robin method is satisfied.

  According to a fourth aspect of the present invention, in the third aspect of the present invention, the apparatus according to the third aspect further includes a state register that stores information about an interrupt state for each interrupt process, and the interrupt processing execution unit stores the interrupt stored in the state register. Whether or not a condition that can be executed is satisfied is determined based on the information on the state.

  Next, in order to achieve the above object, a method according to the fifth invention includes a general-purpose CPU and an interrupt processor that executes an interrupt processing program for executing an interrupt process that has priority over other processes. An execution request that requests execution of interrupt processing is detected, and it is selected whether the interrupt processing is executed by the general-purpose CPU or the interrupt processor.

  Further, the method according to a sixth invention is the method according to the fifth invention, wherein the interrupt processor includes a timer for measuring time, and the interrupt processing selection unit is configured to execute a predetermined condition every time a predetermined time elapses due to time measurement by the timer. A signal serving as a basis for determining whether or not is satisfied, the interrupt processing execution unit determines whether or not a predetermined condition is satisfied based on the output signal, and the interrupt processing Select whether to execute interrupt processing in the execution unit.

  The method according to a seventh aspect is the method according to the sixth aspect, wherein the interrupt processor is capable of executing a plurality of interrupt processes up to a fixed number of tasks, wherein the interrupt process execution unit Each time, it is determined whether or not a condition that can be executed by the round robin method is satisfied.

  The method according to an eighth aspect of the present invention is the method according to the seventh aspect, further comprising: a state register that stores information about an interrupt state for each interrupt process, wherein the interrupt processing execution unit stores the interrupt stored in the state register. Whether or not a condition that can be executed is satisfied is determined based on the information on the state.

  According to the present invention, by using a dedicated interrupt processor for executing interrupt processing and executing interrupt processing completely independently of a general-purpose CPU, for example, device drivers, OSs and the like can use unnecessary interrupt inhibition time. If it is provided, it is possible to avoid interrupting the execution of interrupt processing that requires real-time performance when the processing time is long, etc., greatly shortening the interrupt latency, and responding within a certain time Can be guaranteed. In addition, external interrupt processing can be executed for a device that does not have an interrupt function.

  An apparatus for reducing interrupt latency according to an embodiment of the present invention will be specifically described below with reference to the drawings. The following embodiments do not limit the invention described in the claims, and all combinations of characteristic items described in the embodiments are essential to the solution. It goes without saying that it is not limited.

  The present invention can be implemented in many different modes and should not be construed as being limited to the description of the embodiment. The same symbols are attached to the same elements throughout the embodiments.

  In the embodiment of the present invention, the interrupt latency can be greatly reduced by executing the interrupt process completely independently of the general-purpose CPU by the dedicated interrupt processor for executing the interrupt process. Further, by limiting the maximum execution time of each interrupt processing routine executed in the round robin method, it is possible to ensure that the requested interrupt processing routine starts to be executed within a certain time. Furthermore, external interrupt processing can be executed even for devices that do not have an interrupt function.

  FIG. 2 is a block diagram showing a configuration example of a semiconductor device capable of shortening the interrupt latency according to the embodiment of the present invention. The semiconductor device 10 according to the embodiment of the present invention includes a general-purpose CPU 30 and an interrupt processor 20. The general-purpose CPU 30, the interrupt processor 20, the devices 11, 11,..., And the memory 40 are connected to be able to perform data communication with each other via a bus 50.

  The interrupt processor 20 of the semiconductor device 10 is an I / O-based processor dedicated to interrupt processing. The interrupt processor 20 includes an interrupt detection unit 21, an interrupt process selection unit 22, an interrupt process execution unit 23, an internal memory 24, and a timer 25. The interrupt processing execution unit 23 is connected to the bus 50 via the bus interface 26.

  The interrupt detection unit 21 corresponds to the conventional interrupt controller 2 shown in FIG. 1, and detects an execution request (hereinafter referred to as an interrupt request) that requests execution of interrupt processing from the devices 11, 11,. The interrupt detection unit 21 notifies the interrupt processing selection unit 22 instead of notifying the general-purpose CPU 30 of the interrupt request directly.

  The interrupt process selection unit 22 selects whether the interrupt process is executed by the general-purpose CPU 30 or the interrupt process execution unit 23. For example, the type of interrupt processing in the interrupt request from the device 11 is detected, the type of interrupt processing is a process that requires real-time processing, and there is no urgency, but the processing time is too long to be executed by the general-purpose CPU 30. In this case, an interrupt request is notified to the interrupt processing execution unit 23 so as to execute the interrupt processing inside the interrupt processor 20 (processing 62). In the case of other processing, an interrupt request is notified to the general-purpose CPU 30 as in the conventional case (processing 61).

  The interrupt processing program is downloaded from the general-purpose CPU 30 to the internal memory 24 in the interrupt processor 20 via the bus 50. Accordingly, the interrupt processing execution unit 23 that has received the interrupt request calls the corresponding interrupt processing program from the internal memory 24 to execute the interrupt processing, and notifies the general-purpose CPU 30 of the completion of the interrupt processing (processing 62).

  FIG. 3 is an explanatory diagram of the principle of shortening the interrupt latency in the semiconductor device 10 according to the embodiment of the present invention. FIG. 3A shows an interrupt latency T1 when there is an interrupt request from the device B in a conventional semiconductor device not provided with the interrupt processor 20, and FIG. 3B shows an embodiment of the present invention. The interrupt latency T2 when there is an interrupt request from the device B in the semiconductor device 10 is shown.

  As shown in FIG. 3A, after the interrupt request of the device B is issued at time t = 0, the general CPU 30 is reached after a certain time t1. Until the time t = t2, the interrupt processing prohibition period ΔT by the general-purpose CPU 30 is reached, and the execution of the interrupt processing is started when the time t = t2. FIG. 3A illustrates the case where the general-purpose CPU 30 has the interrupt processing prohibition period ΔT, but when the prohibition period ΔT does not exist, execution of the interrupt processing is started from t = t1. .

  When starting execution of interrupt processing, first, context information that is information relating to the status of another program being executed at time t = t2 is saved and dispatched. Such processing is executed by calling an OS handler. In the example of FIG. 3, when executing the interrupt process of the device B having an interrupt request, it is necessary to execute the interrupt process A of the device A. Therefore, the handler of the device driver corresponding to the device A After calling to execute the interrupt process A, it is necessary to dispatch by calling the handler of the OS again.

  Thereafter, the handler of the device driver corresponding to the device B is called at time t = t3 to execute the interrupt processing B for the interrupt request, so that the interrupt latency T1 is the time t3 from time t = 0 to t = t3. .

  On the other hand, in FIG. 3B, after the interrupt request of the device B is issued at the time t = 0, there is no prohibition period for interrupt processing by the general-purpose CPU 30. Therefore, the interrupt process B1 is executed at time t = t4 after the processing wait time of another interrupt process routine has elapsed. In this case, the interrupt latency T2 is a time t4 from time t = 0 to t = t4, and the interrupt latency can be greatly shortened. For convenience of illustration, it is described that the interrupt process A having a long processing time is executed after the interrupt process B1, but in reality, the interrupt process A is executed by the general-purpose CPU 30. Needless to say, the processing is performed in parallel with the interrupt processing B1.

  Returning to FIG. 2, the interrupt processor 20 includes a timer (interval timer) 25 for executing interrupt processing corresponding to polling processing at regular intervals. That is, when the devices 11, 11,... Do not have an interrupt function, a polling process is normally executed. Since the polling process generates a signal at regular time intervals, the load on the CPU, bus, etc. is large. Therefore, in the present embodiment, a timer interrupt is internally generated at a constant cycle by the timer 25.

  An interrupt processing routine, which will be described later, is executed by the interrupt processing execution unit 23 by a timer interrupt that occurs at a constant period. Instead of the general-purpose CPU 30, the state of the device is confirmed in an interrupt processing routine to be executed, and an interrupt request is notified to the CPU 30 when a predetermined condition is satisfied (process 63 in FIG. 2). Therefore, for example, a memory device that does not have an interrupt function can also have an interrupt function for the general-purpose CPU 30. FIG. 4 compares the case where the general-purpose CPU 30 executes polling processing as in the prior art and the case where interrupt processing is executed inside the interrupt processor 20 when the device 11 does not have an interrupt function. It is a time chart.

  4A shows a time chart of the general-purpose CPU 30 when the general-purpose CPU 30 executes the polling process, and FIG. 4B shows a general-purpose CPU 30 when the interrupt processor 20 executes the interrupt process. And the time chart of the processor 20 for interruption is shown.

  In FIG. 4A, the task A is executed by the general-purpose CPU 30 from time TS0 to time TS1. At time TS1, control is passed to the OS, and task B is executed at time TS2. In the task B, a determination process for determining whether or not a predetermined condition is satisfied is executed. When it is determined that the predetermined condition is not satisfied, the control is returned to the OS at time TS3, and from time TS4. Task C is executed. Thereafter, when it is determined that the predetermined condition is satisfied at the time TS5 by repeating the same process, the task B starts executing the process when the predetermined condition is satisfied.

  On the other hand, in FIG. 4B, the task A is executed by the general-purpose CPU 30 from time TS0 to time TS1. The process is the same as that shown in FIG. 4A until control is passed to the OS at time TS1. In FIG. 4B, after the control is transferred to the OS at time TS1, a determination process is performed by the interrupt processor 20 to determine whether or not a predetermined condition is satisfied at a constant period by the timer 25. Executed.

  That is, when the interrupt processor 20 executes a determination process for determining whether or not a predetermined condition is satisfied independently of the general-purpose CPU 30 at time TS2 ′ and determines that the predetermined condition is not satisfied, The determination process ends at time TS3 ′. Thereafter, when the interrupt processor 20 executes the determination process at a constant cycle, executes the determination process at time TS6, and determines that the predetermined condition is satisfied at time TS7, the general-purpose CPU 30 at time TS8. An interrupt request is notified to task B, and at time TS9, task B starts execution of processing when a predetermined condition is satisfied.

  As can be seen from a comparison between FIG. 4A and FIG. 4B, it is not necessary to start task B each time by repeatedly generating a timer interrupt of the interrupt processor 20, and the number of times control is returned to the OS. Decrease. In addition, since the determination process in task B is not necessary, the load on the general-purpose CPU 30 can be reduced. Therefore, even when the device 11 does not have an interrupt function, external interrupt processing can be executed without executing polling processing.

  FIG. 5 is a schematic diagram showing a detailed configuration of the interrupt processor 20 according to the embodiment of the present invention. In FIG. 5, a case where interrupt processing is executed by a so-called round robin method will be described as an example. The interrupt processor 20 according to the present embodiment is premised on being incorporated into a SoC (System on a Chip) as one IP core (Intelligent Property Core).

  In FIG. 5, a bus 50 is a local bus of the general-purpose CPU 30. The general-purpose CPU 30 can access the control register 51 and the internal memory 24 via the bus 50. The interrupt processing execution unit 23 also functions as a bus master for the bus 50. Most of the processing is completed inside the interrupt processor 20 and occupies the bus 50 shared with the general-purpose CPU 30 only when the device 11 is accessed.

  Of the interrupt requests from each device 11 and the timer interrupt requests from the timer 25, a maximum of n (n is a natural number) interrupt requests are notified to the interrupt processing execution unit 23. Here, n is a fixed value, and is determined by hardware when the interrupt processing execution unit 23 is incorporated into the SoC. In the internal memory 24, n interrupt processing routines are downloaded in advance from the general-purpose CPU 30 via the bus 50.

  One interrupt processing execution unit 23 executes the interrupt processing routines P0, P1,... Pn-1 stored in the internal memory 24 while sequentially switching them. The interrupt processing routine Pi (i is an integer from 0 to n-1) is executed only when the interrupt processing routine Pi is valid and the interrupt request is active. The interrupt processing routine Pi is executed only once per interrupt request, and when necessary, the interrupt request is finally notified to the general-purpose CPU 30.

  While no other process interrupts during the execution of the interrupt process, if the interrupt process routine does not end within the predetermined time Timeout, the interrupt process execution unit 23 forcibly controls the next interrupt process routine Pi + 1. give. Saving of context information when switching interrupt processing routines is executed by hardware by the interrupt processing execution unit 23.

  The control register 51 corresponds to the number of interrupt processing routines Pi, and is configured as a 32-bit register, for example. FIG. 6 is a schematic diagram showing the correspondence between the interrupt request and the interrupt processing routine Pi or the interrupt request R to the general-purpose CPU 30.

  FIG. 7 is an exemplary diagram showing the configuration of the logical switch Sj (j is an integer from 0 to m−1, m is a natural number) and St. In the example of FIG. 7, a signal r indicating that an interrupt request is notified to the general-purpose CPU 30 is output by combining one AND circuit and one NOT circuit. The signals output from the logic switches S0, S1,..., S (m−1) and St in FIG. 6 are r0, r1,. The interrupt request R notified to the general-purpose CPU 30 is specified by the OR circuit.

  Note that an enable signal (ENABLE), a request signal (REQUEST), and a select signal (SELECT) are input to the logical switches S0, S1, ..., S (m-1) and St. The enable signal indicates whether or not to output an interrupt signal, and the request signal indicates whether or not an interrupt request has been accepted. The select signal indicates whether to notify the general-purpose CPU 30 of the interrupt request or the interrupt processing execution unit 23. The same applies to the input to the AND circuit of the logic circuit Hj (j is an integer of 0 to m-1) in FIG.

  As shown in FIG. 6, whether the interrupt request is notified to the general-purpose CPU 30 or the interrupt processing execution unit 23 is determined by the select signal shown in FIG. The logic circuit G includes a plurality of logic switches Sj and a logic switch St for the timer 25, and output signals r0, r1,..., R (from the plurality of logic switches Sj and the logic switch St for the timer 25). The output signal specified by the OR circuit from m-1) and rt is notified to the general-purpose CPU 30 as an interrupt request R.

  Each logic circuit Hi (i is an integer from 0 to n-1) is assigned to m (m is a natural number) interrupt request 0, interrupt request 1, ..., interrupt request (m-1), and timer interrupt request. Correspondingly, AND circuits are provided, and when an interrupt request j (j is an integer from 0 to m−1) or a timer interrupt request is issued, an interrupt request j (j is an integer from 0 to m−1). ) Or only the AND circuit to which the timer interrupt request is issued outputs the signal pj or pt in the ON state, and the arbitrary interrupt processing routine Pi corresponding to the interrupt request j by the OR circuit (i is an integer of 0 to n−1). Only becomes active.

  FIG. 8 is a schematic diagram showing the configuration of the control register 51 according to the embodiment of the present invention. The control register 51 includes register groups 71, 71,... Corresponding to the interrupt processing routines P0 to Pn-1, respectively, and the interrupt processing program start address register (START) and end address register (END), respectively. ), An instruction pointer (IAR) indicating an address currently being executed, a status register (STAT), an enable register (ENABLE), and a request register (REQUEST).

  The interrupt processing execution unit 23 that has received the interrupt request i, when the processing order of the interrupt processing routine Pi comes around, inquires from the internal memory 24 while referring to the register group 71 shown in FIG. 8 corresponding to Pi. Pi is read and interrupt processing is executed. When the interrupt process is completed, the general CPU 30 is notified of the completion of the interrupt process.

  FIG. 9 is a view showing an example of a bit arrangement of the status register (STAT) according to the embodiment of the present invention. In the example of FIG. 9, in order from bit 0, a V (Valid) bit indicating whether or not the interrupt processing routine Pi is valid, a T (Trigger) bit indicating whether or not an interrupt request is generated, and interrupt processing And an I (Interrupt) bit indicating whether or not an interrupt request has been notified to the general-purpose CPU 30.

  As shown in FIG. 8, the interrupt processing execution unit 23 inquires the status registers (STAT) of the register groups 71, 71,... Of the control register 51, and executes the corresponding interrupt processing routine Pi. The register group 72 includes general-purpose registers GPR0, GPR1,..., GPRi used in the interrupt processing routine Pi. Most of the processing is completed inside the interrupt processor 20, and it is sufficient to perform data communication via the bus 50 only when processing for the devices 11, 11,... Occurs. The communication load on the bus 50 can be greatly reduced as compared with the execution time of.

  A register ENABLE provided in each register group 71 indicates whether an interrupt signal is output, and a register REQUEST indicates whether an interrupt request is accepted. The register REQUEST indicates whether or not the processing for the interrupt request is in a pending state (status), and is similar to a register generally called an interrupt status register.

  The register TIMER writes the timeout period of the interrupt processing routine, and the register SELECT indicates whether to notify the interrupt request to the general-purpose CPU 30 or the interrupt processing execution unit 23.

  FIG. 10 is a view showing an example of the interrupt processing routine Pi identification method by the register STAT according to the embodiment of the present invention. In FIG. 10, only one register ENABLE (FIG. 10 (a)), one register REQUEST (FIG. 10 (b)) and one control register 51 included in the register group 71 corresponding to the interrupt processing routines P0 to Pn-1 are provided. A case where each of the register SELECTs has a 32-bit configuration will be described. Each register bit corresponds to each interrupt request signal. For example, the interrupt request number 0 corresponds to bit 0 (MSB) of the register REQUEST, and the timer interrupt corresponds to bit 31 (LSB) of the register. The register ENABLE and the register REQUEST are provided for each interrupt processing routine Pi, and can be associated with one or a plurality of interrupt request numbers.

  For example, when the value of the register ENABLE is 32′b11110... 000, the interrupt request numbers 0, 1 and 2 are valid. Here, when the value of the register SELECT becomes 32′b1100... 000, the interrupt request numbers 0 and 1 are processed inside the interrupt processor 20 (process 62 in FIG. 2), and the interrupt request number 2 means that the general-purpose CPU 30 performs processing (processing 61 in FIG. 2). When there is an interrupt request from the device 11 and bit 0 or bit 1 of the register REQUEST is set to “1”, the corresponding interrupt processing routine Pi is executed by the interrupt processing execution unit 23.

  As shown in the internal memory 24 of FIG. 5, the interrupt processing execution unit 23 executes the interrupt processing routine Pi while sequentially switching in a round robin manner. FIG. 11 is an explanatory diagram of processing for explaining the operation of the interrupt processing routine Pi. FIG. 11 is described in a programming language style for easy understanding, but shows processing performed by the interrupt processing execution unit 23 in hardware.

  In FIG. 11, when an interrupt request is generated (T = 1) and the corresponding interrupt processing routine Pi is valid (V = 1), the time-out value specified by the register TIMER is loaded into the register TLEFT indicating the remaining time. The value of the register TLEFT is automatically decreased until it becomes “0” in synchronization with the clock of the interrupt processor 20.

  Next, the flag P indicating that the interrupt process is being executed is set to ‘1’, and the start address register (START) is set to the current execution address (IAR = START) to start the execution. When the current execution address of the interrupt processing routine Pi reaches the end address register (END) (IAR = END), an interrupt request is notified to the general-purpose CPU 30 (I = 1) if necessary, and the flag P is set to “0”. To finish the process. If the interrupt processing routine Pi does not end within the time-out period specified by the register TIMER, the values stored in the register group 72 (general-purpose register GPRI, count register CTR, etc.) used by the interrupt processing routine Pi are saved. Then, control is forcibly passed to the next interrupt processing routine (task switch).

  When the order of the same interrupt processing routine comes again, when the flag P = 1, the context information of the previously saved register group 72 is returned to each register. However, if there are as many register groups 72 as the number n of interrupt processing routines, saving and restoring are not necessary. Since the execution address at the time of the previous task switch remains in the register IAR, execution is resumed from the address remaining in the register IAR, and the current execution address of the interrupt processing routine Pi is stored in the end address register (END). The interrupt processing routine Pi continues to be executed until it reaches (IAR = END) or until time-out and task switching is performed.

  In a normal CPU, processing necessary for task switching is performed by software such as an OS. However, as described above, in the present invention, the processing necessary for the task switch is executed by hardware, so that the OS is unnecessary.

  Further, the maximum value Tmax of the interrupt latency is equal to the maximum value of the time until the next processing order comes after execution of the interrupt processing routine by the round robin method. Therefore, the maximum value Tmax of the interrupt latency can be expressed by equation (1). That is, since the number n of interrupt processing routines is a fixed value, it is guaranteed that the interrupt processing is executed within the time of Expression (1).

  Tmax = Timeout × n + overhead time (1)

  Here, the overhead time means the time required for saving context information and the like, and is much shorter than the task switching time by the OS.

  In the case of an interrupt processing routine executed on a normal CPU, it is a rule to describe the processing so that it can be processed in as short a time as possible in consideration of the influence on other interrupt processing. In the present invention, even when an interrupt processing routine that requires a long processing time is used, the latency for other interrupt processing is not affected. Therefore, it does not matter if the main processing as performed at the third level in FIG. 1 is included in the interrupt processing routine.

  As described above, according to the present embodiment, by using the dedicated interrupt processor 20 for executing interrupt processing and executing interrupt processing completely independently of the general-purpose CPU 30, for example, a device driver, OS, etc. If there is an unnecessary interrupt prohibition time, even if a device driver handler with a long processing time is running, interrupt processing that requires real-time performance is immediately executed without being affected by it. can do. In addition, external interrupt processing can be executed for a device that does not have an interrupt function.

  The present invention is not limited to the above-described embodiments, and various changes and improvements can be made within the scope of the present invention.

It is a block diagram which shows the specific example of the conventional interruption process execution. It is a block diagram which shows the structural example of the semiconductor device which can shorten the interrupt latency concerning embodiment of this invention. It is explanatory drawing of the principle which shortens the interrupt latency in the semiconductor device which concerns on embodiment of this invention. 6 is a time chart for comparing a case where a general-purpose CPU executes polling processing and a case where interrupt processing is executed by an interrupt processor when a device does not have an interrupt function. It is a schematic diagram which shows the detailed structure of the processor for interruption concerning embodiment of this invention. It is a schematic diagram which shows matching with the interruption request | requirement and interruption processing routine or interruption to general purpose CPU. It is an illustration figure which shows the structure of a logic switch. It is a schematic diagram which shows the structure of the control register which concerns on embodiment of this invention. It is an illustration figure of the bit arrangement | sequence of the status register (STAT) based on embodiment of this invention. It is an illustration figure of the interrupt processing routine Pi specific method by the register | resistor STAT which concerns on embodiment of this invention. It is explanatory drawing of the process explaining operation | movement of the interruption process routine Pi.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Device 20 Interrupt processor 21 Interrupt detection part 22 Interrupt process selection part 23 Interrupt process execution unit 24 Internal memory 25 Timer (interval timer)
30 General-purpose CPU
51 Control register

Claims (8)

A general-purpose CPU;
An interrupt processor that executes an interrupt processing program for executing an interrupt process that has priority over other processes;
The interrupt processor is:
An interrupt processing execution unit for executing interrupt processing;
A memory for storing an interrupt processing program for executing the interrupt processing;
An interrupt detection unit that detects an execution request that requests execution of interrupt processing;
An interrupt processing selection unit that selects whether to execute interrupt processing by the general-purpose CPU or the interrupt processing execution unit. The interrupt processor includes a timer for measuring time,
The interrupt processing selection unit
Each time a predetermined time elapses due to the time measured by the timer, a signal serving as a basis for determining whether or not a predetermined condition is satisfied is output,
The interrupt processing execution unit is
The apparatus according to claim 1, wherein it is determined whether or not a predetermined condition is satisfied based on the output signal, and whether or not to execute interrupt processing in the interrupt processing execution unit is selected. The interrupt processor is capable of executing a plurality of interrupt processes up to a certain number of tasks,
The interrupt processing execution unit is
The apparatus according to claim 2, wherein it is determined whether a condition capable of being executed in a round-robin manner is satisfied for each interrupt process. It has a status register that stores information about the status of interrupts for each interrupt process,
The interrupt processing execution unit is
The apparatus according to claim 3, wherein it is determined whether or not a condition that can be executed is satisfied based on information on an interrupt state stored in the state register. A general-purpose CPU;
An interrupt processor that executes an interrupt processing program for executing an interrupt process that has priority over other processes;
Detects an execution request that requests execution of interrupt processing,
A method for selecting whether the interrupt processing is executed by the general-purpose CPU or the interrupt processor. The interrupt processor includes a timer for measuring time,
The interrupt processing selection unit
Each time a predetermined time elapses due to the time measured by the timer, a signal serving as a basis for determining whether or not a predetermined condition is satisfied is output,
The interrupt processing execution unit is
6. The method according to claim 5, wherein it is determined whether or not a predetermined condition is satisfied based on the output signal, and whether or not to execute interrupt processing in the interrupt processing execution unit is selected. The interrupt processor is capable of executing a plurality of interrupt processes up to a certain number of tasks,
The interrupt processing execution unit is
The method according to claim 6, wherein a determination is made as to whether a condition capable of being executed in a round robin manner is satisfied for each interrupt process. It has a status register that stores information about the status of interrupts for each interrupt process,
The interrupt processing execution unit is
The method according to claim 7, wherein it is determined whether or not a condition that can be executed is satisfied based on information on an interrupt state stored in the state register.

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