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JP2010027691A - Semiconductor device - Google Patents

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JP2010027691A
JP2010027691A JP2008184091A JP2008184091A JP2010027691A JP 2010027691 A JP2010027691 A JP 2010027691A JP 2008184091 A JP2008184091 A JP 2008184091A JP 2008184091 A JP2008184091 A JP 2008184091A JP 2010027691 A JP2010027691 A JP 2010027691A
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wiring
drive signal
signal transmission
emitter
emitter sense
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JP5206188B2 (en
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Shigeru Hasegawa
滋 長谷川
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which applies a desired signal (gate drive signal) to the gate of a power device by suppressing the effect of electromagnetic induction and gate oscillation. <P>SOLUTION: The semiconductor device comprises the power device arranged on a base board, a gate drive signal input terminal, an emitter sensing terminal, a drive signal transmission wiring made of metal plate which connects the gate of power device to the gate drive signal input terminal, and an emitter sensing wiring of metal plate which connects the emitter of power device to the emitter sensing terminal. The drive signal transmission wiring and the emitter sensing wiring are arranged parallel to the base board. The drive signal transmission wiring and the emitter sensing wiring comprise superposed regions where they overlap each other without contacting to each other. In the superposed region, the direction of current flow in the drive sinal transmission wiring is opposite to that of the emitter sensing wiring. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は駆動信号伝送用配線とエミッタセンス配線を有するパワーデバイスを備える半導体装置に関する。   The present invention relates to a semiconductor device including a power device having a drive signal transmission line and an emitter sense line.

電力制御に用いられる半導体装置として半導体パワーモジュールがある。半導体パワーモジュールにはパワーデバイスが用いられる。パワーデバイスの一例として、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）が挙げられる。ＩＧＢＴはゲート駆動信号によりオンオフの制御がなされるものであり、高電圧・大電流のスイッチングが可能である。ＩＧＢＴを含む半導体パワーモジュールはモータ等を駆動するインバータなどに幅広く使用されている。   There is a semiconductor power module as a semiconductor device used for power control. A power device is used for the semiconductor power module. An example of a power device is an insulated gate bipolar transistor (IGBT). The IGBT is controlled to be turned on and off by a gate drive signal, and can switch high voltage and large current. Semiconductor power modules including IGBTs are widely used in inverters that drive motors and the like.

前述の通りパワーデバイスはゲート駆動信号によりオンオフの動作制御が成される。従って、正確な動作制御のためにはゲート駆動信号が所定の電圧値でパワーデバイスのゲートに印加されることが要求される。すなわち、パワーデバイスの正確で安定的な制御は、ゲート駆動信号が外的な要因によって影響を受けてしまっては成し得ないものである。そして、特許文献１−４には、ノイズなどの影響を受けずに所望のゲート駆動信号をパワーデバイスのゲートに印加することを目的とする技術が記載されている。   As described above, the power device is controlled to be turned on and off by the gate drive signal. Therefore, for accurate operation control, it is required that the gate drive signal be applied to the gate of the power device at a predetermined voltage value. That is, accurate and stable control of the power device cannot be achieved if the gate drive signal is affected by external factors. Patent Documents 1-4 describe a technique for applying a desired gate drive signal to the gate of a power device without being affected by noise or the like.

特開２００３−４６０５８号公報JP 2003-46058 A 特開２００３−１７９２０３号公報JP 2003-179203 A 特開２０００−２１４８２１号公報JP 2000-214821 A 特開平４−２１１２００号公報JP-A-4-211200

図１６は本発明の課題を説明するための半導体装置の図である。以後図１６を参照して半導体装置の構成を説明する。まず、半導体装置の筐体底部を構成するベース基板１００には絶縁基板１０２、１０４、１０６、１０８、１１０、１１２が配置される。図から明らかなように絶縁基板１０２と１１０は同一形状であり、絶縁基板１０４と１１２も同一形状である。この半導体装置は前述した複数の絶縁基板上に素子が配置され、素子と半導体装置外部或いは素子同士を配線で接続することで動作するものである。   FIG. 16 is a diagram of a semiconductor device for explaining the problem of the present invention. Hereinafter, the configuration of the semiconductor device will be described with reference to FIG. First, insulating substrates 102, 104, 106, 108, 110, and 112 are arranged on the base substrate 100 that forms the bottom of the housing of the semiconductor device. As is apparent from the figure, the insulating substrates 102 and 110 have the same shape, and the insulating substrates 104 and 112 also have the same shape. This semiconductor device operates by arranging elements on the above-described plurality of insulating substrates and connecting the elements to the outside of the semiconductor device or to each other by wiring.

絶縁基板１０２の配線パターン１１４上にはＩＧＢＴ１１６、１１８が配置される。さらに同絶縁基板１０２にはダイオード素子１２０、１２２が配置される。ＩＧＢＴ１１６、１１８およびダイオード素子１２０、１２２はそれぞれはんだで固定されている。以後、ＩＧＢＴのゲート、エミッタ、コレクタの接続についてそれぞれ説明する。   IGBTs 116 and 118 are arranged on the wiring pattern 114 of the insulating substrate 102. Further, diode elements 120 and 122 are arranged on the insulating substrate 102. The IGBTs 116 and 118 and the diode elements 120 and 122 are fixed with solder, respectively. Hereinafter, the connection of the gate, emitter, and collector of the IGBT will be described.

ＩＧＢＴ１１８のゲート電極と配線パターン１２６とはアルミワイヤ１２４で接続されている。ＩＧＢＴ１１６のゲート電極も同様に配線パターン１２８と接続される。配線パターン１２６、１２８は共に絶縁基板１０４に配置されるものである。これら配線パターン１２６、１２８はそれぞれゲートバランス抵抗１３０、１３２を介して配線パターン１３４と接続される。さらに、配線パターン１３４はリード線１３６により絶縁基板１１２の配線パターン１４０と接続される。配線パターン１４０には外部端子との接続部であるゲート接続部１４２が配置されている。すなわち、ゲート駆動信号はゲート接続部１４２から配線パターン１４０、リード線１３６を経由し、ゲートバランス抵抗１３０、１３２、配線パターン１２８、１２６、アルミワイヤ１２４と伝送されＩＧＢＴ１１６、１１８のゲートに入力される。   The gate electrode of the IGBT 118 and the wiring pattern 126 are connected by an aluminum wire 124. Similarly, the gate electrode of the IGBT 116 is connected to the wiring pattern 128. The wiring patterns 126 and 128 are both arranged on the insulating substrate 104. These wiring patterns 126 and 128 are connected to the wiring pattern 134 via gate balance resistors 130 and 132, respectively. Further, the wiring pattern 134 is connected to the wiring pattern 140 of the insulating substrate 112 by lead wires 136. The wiring pattern 140 is provided with a gate connection part 142 which is a connection part with an external terminal. That is, the gate drive signal is transmitted from the gate connection portion 142 via the wiring pattern 140 and the lead wire 136 to the gate balance resistors 130 and 132, the wiring patterns 128 and 126, and the aluminum wire 124 and input to the gates of the IGBTs 116 and 118. .

一方ＩＧＢＴ１１６、１１８のエミッタはアルミワイヤ１４４を介してダイオード１２０、１２２にそれぞれ接続される。ダイオード１２０、１２２はアルミワイヤ１４６によりエミッタ配線パターン１４８へと接続される。エミッタ配線パターン１４８にはエミッタ接続部１５０が配置される。エミッタ接続部１５０はエミッタ主電極が接続されるべき部分である。さらに、エミッタ配線パターン１４８にはリード線１５２が接続される。リード線１５２は絶縁基板１０８に配置される配線パターン１５４とエミッタ配線パターン１４８とを接続する。配線パターン１５４にはエミッタセンス接続部１５６が設けられる。エミッタセンス接続部１５６はエミッタセンス端子が接続されるべき部分である。   On the other hand, the emitters of IGBTs 116 and 118 are connected to diodes 120 and 122 via aluminum wires 144, respectively. The diodes 120 and 122 are connected to the emitter wiring pattern 148 by an aluminum wire 146. An emitter connection portion 150 is disposed on the emitter wiring pattern 148. The emitter connection portion 150 is a portion to which the emitter main electrode is to be connected. Further, a lead wire 152 is connected to the emitter wiring pattern 148. The lead wire 152 connects the wiring pattern 154 disposed on the insulating substrate 108 and the emitter wiring pattern 148. An emitter sense connection 156 is provided in the wiring pattern 154. The emitter sense connection portion 156 is a portion to which an emitter sense terminal is to be connected.

最後にＩＧＢＴ１１６、１１８のコレクタについてであるが、これは配線パターン１１４と接続される。配線パターン１１４には、コレクタ主電極が接続されるべきコレクタ接続部１５８が配置される。   Finally, regarding the collectors of the IGBTs 116 and 118, this is connected to the wiring pattern 114. In the wiring pattern 114, a collector connection portion 158 to which a collector main electrode is to be connected is disposed.

なお、基板１００には絶縁基板１０２と同等の絶縁基板１１０が配置される。絶縁基板１１０には絶縁基板１０２と同様にＩＧＢＴ、ダイオードが配置される。絶縁基板１０２のＩＧＢＴのエミッタはエミッタ配線パターン１４８に接続され、コレクタは配線パターンを介してコレクタ接続部１６０と接続される点は絶縁基板１０２と同様である。そして、絶縁基板１１０に配置されるＩＧＢＴのゲート電極は絶縁基板１１２の配線パターンに繋がれ、ゲートバランス抵抗を介して配線パターン１４０へと接続される。図１６の半導体装置の例では、絶縁基板１０２、１１０に搭載されたＩＧＢＴはゲート接続部１４２から伝送されるゲート駆動信号によりオンオフのスイッチングを行う。   Note that an insulating substrate 110 equivalent to the insulating substrate 102 is disposed on the substrate 100. As with the insulating substrate 102, IGBTs and diodes are arranged on the insulating substrate 110. The IGBT emitter of the insulating substrate 102 is connected to the emitter wiring pattern 148, and the collector is connected to the collector connection portion 160 via the wiring pattern, similar to the insulating substrate 102. The gate electrode of the IGBT disposed on the insulating substrate 110 is connected to the wiring pattern of the insulating substrate 112 and is connected to the wiring pattern 140 via a gate balance resistor. In the example of the semiconductor device in FIG. 16, the IGBTs mounted on the insulating substrates 102 and 110 are switched on and off by a gate drive signal transmitted from the gate connection part 142.

このような半導体装置では、大電流のオンオフ制御を行うため主電流の時間変化が大きい。この主電流の大きなｄＩ／ｄｔに起因する電磁界がゲート駆動信号の伝送経路に誘導起電力を生じ、ＩＧＢＴなどパワーデバイスのゲートにそのまま上乗せされて印加される問題があった。その結果ゲートに対して所望の電圧を印加できない問題があった。   In such a semiconductor device, the time change of the main current is large because on / off control of a large current is performed. There is a problem that an electromagnetic field caused by dI / dt having a large main current generates an induced electromotive force in the transmission path of the gate drive signal, and is applied directly to the gate of a power device such as an IGBT. As a result, there is a problem that a desired voltage cannot be applied to the gate.

ここで特に複数のＩＧＢＴのゲートにゲート駆動信号を供給する場合には、外部端子の取出し位置や素子レイアウトの都合上、ゲート駆動信号を伝送すべき配線（以後駆動信号伝送用配線と称する）の配線経路長がＩＧＢＴによって異なることが一般である。このような配線経路長の比較的長いＩＧＢＴは電磁誘導の影響を受けやすいものである。図１６の例においてもＩＧＢＴ１１６、１１８のゲートにゲート駆動信号を伝送すべきリード線１３６は絶縁基板１１０に搭載されたＩＧＢＴの配線より配線経路長が長く、電磁誘導による影響を受けやすい。このように素子レイアウトの都合上止むを得ず一部の駆動信号伝送用配線を長くすると、その長い配線のみ誘導起電力の影響を受けやすく、結果として半導体装置内の複数のＩＧＢＴが均一な動作ができないという問題があった。   Here, particularly when supplying a gate drive signal to the gates of a plurality of IGBTs, a wiring for transmitting the gate drive signal (hereinafter referred to as a drive signal transmission wiring) is taken into account for convenience of the external terminal extraction position and element layout. In general, the wiring path length varies depending on the IGBT. Such a relatively long wiring path length IGBT is susceptible to the influence of electromagnetic induction. Also in the example of FIG. 16, the lead wire 136 that should transmit a gate drive signal to the gates of the IGBTs 116 and 118 has a wiring path length longer than that of the IGBT wiring mounted on the insulating substrate 110 and is easily affected by electromagnetic induction. In this way, if part of the drive signal transmission wiring is unavoidable due to the element layout, only the long wiring is easily affected by the induced electromotive force. As a result, the plurality of IGBTs in the semiconductor device operate uniformly. There was a problem that could not.

また、このような問題は駆動信号伝送用配線が線状の場合に限られず例えば、図１７で示されるように駆動信号伝送用配線として平板状の駆動信号伝送用配線２００を用いる場合にも生じるものである。図１７の例では、図１６におけるリード線１３６が駆動信号伝送用配線２００に置き換わり、図１６におけるリード線１５２がエミッタセンス配線２０２に置き換えそれに伴う接続が異なることを除き図１６の構成と同様である。図１７において、前述の駆動信号伝送用配線２００とエミッタセンス配線２０２はベース基板２０５上に形成された配線パターンに棒状中継導体２０３、２０４によって接続され、接続部２０６、２０７で外部端子と接続される。なお、図１８は図１７におけるＡ矢示図であり、図１９は図１７におけるＢ矢示図である。   Such a problem is not limited to the case where the drive signal transmission wiring is linear, but also occurs when, for example, a flat drive signal transmission wiring 200 is used as the drive signal transmission wiring as shown in FIG. Is. In the example of FIG. 17, the lead wire 136 in FIG. 16 is replaced with the drive signal transmission wiring 200, the lead wire 152 in FIG. 16 is replaced with the emitter sense wiring 202, and the connections associated therewith are different. is there. In FIG. 17, the drive signal transmission wiring 200 and the emitter sense wiring 202 described above are connected to a wiring pattern formed on a base substrate 205 by rod-shaped relay conductors 203 and 204, and are connected to external terminals by connection portions 206 and 207. The 18 is an arrow A diagram in FIG. 17, and FIG. 19 is an arrow B diagram in FIG.

また、上述のような半導体装置では、主電流、電圧、使用温度などの条件により、主電流ターンオフ時や短絡時にゲートに電気的発振が発生する場合（ゲート発振）があり問題であった。上述したこれらの問題は、ＩＧＢＴを搭載する半導体装置に限らず、制御電極を有するパワーデバイスを搭載する半導体装置一般に起こり得る問題である。   Further, the semiconductor device as described above has a problem in that electrical oscillation may occur in the gate (gate oscillation) when the main current is turned off or short-circuited depending on conditions such as the main current, voltage, and operating temperature. These problems described above are not limited to semiconductor devices on which IGBTs are mounted, but are problems that can occur in general in semiconductor devices on which power devices having control electrodes are mounted.

本発明は、上述のような課題を解決するためになされたもので、電磁誘導の影響やゲート発振を抑制してパワーデバイスのゲートに所望の信号（ゲート駆動信号）を印加することができる半導体装置を提供することを目的とする。   The present invention has been made to solve the above-described problems, and is a semiconductor capable of applying a desired signal (gate drive signal) to the gate of a power device while suppressing the influence of electromagnetic induction and gate oscillation. An object is to provide an apparatus.

本願の発明にかかる半導体装置は、ベース基板上の絶縁基板に配置されるパワーデバイスと、外部からのゲート駆動信号が入力されるゲート駆動信号入力端子と、外部に接続されるエミッタセンス端子と、該パワーデバイスのゲートと該ゲート駆動信号入力端子とを接続する金属製の平板である駆動信号伝送用配線と、該パワーデバイスのエミッタと該エミッタセンス端子とを接続する金属製の平板であるエミッタセンス配線とを備える。
該駆動信号伝送用配線と該エミッタセンス配線は該ベース基板と平行に配置され、該駆動信号伝送用配線と該エミッタセンス配線は互いに接触せずに重なる重畳領域を有し、該重畳領域では該駆動信号伝送用配線を流れる電流と該エミッタセンス配線を流れる電流の向きは逆方向であることを特徴とする。 A semiconductor device according to the present invention includes a power device disposed on an insulating substrate on a base substrate, a gate drive signal input terminal to which an external gate drive signal is input, an emitter sense terminal connected to the outside, Drive signal transmission wiring that is a metal flat plate that connects the gate of the power device and the gate drive signal input terminal, and an emitter that is a metal flat plate that connects the emitter of the power device and the emitter sense terminal Sense wiring.
The drive signal transmission wiring and the emitter sense wiring are arranged in parallel with the base substrate, and the drive signal transmission wiring and the emitter sense wiring have an overlapping region that does not contact each other, and the overlapping region has the overlapping region. The direction of the current flowing through the drive signal transmission line and the direction of the current flowing through the emitter sense line are opposite to each other.

本願の発明にかかる半導体装置は、第１の絶縁基板上に配置された第１のパワーデバイスと、第２の絶縁基板上に配置された第２のパワーデバイスと、外部からのゲート駆動信号が入力されるゲート駆動信号入力端子と、外部に接続されるエミッタセンス端子と、
該第１のパワーデバイスのゲートと該ゲート駆動信号入力端子とを接続する金属製の第１の駆動信号伝送用配線と、該第２のパワーデバイスのゲートと該ゲート駆動信号入力端子とを接続する金属製の第２の駆動信号伝送用配線と、該第１のパワーデバイスのエミッタと該エミッタセンス端子とを接続する金属製の第１のエミッタセンス配線と、該第２のパワーデバイスのエミッタと該エミッタセンス端子とを接続する金属製の第２のエミッタセンス配線とを備える。
該第１の駆動信号伝送用配線と該第１のエミッタセンス配線は、互いに接触せず重なる第１の重畳領域を有し、該第２の駆動信号伝送用配線と該第２のエミッタセンス配線は、互いに接触せず重なる第２の重畳領域を有し、該第１の重畳領域では該第１の駆動信号伝送用配線を流れる電流と該第１のエミッタセンス配線を流れる電流の向きは逆方向であり、該第２の重畳領域では該第２の駆動信号伝送用配線を流れる電流と該第２のエミッタセンス配線を流れる電流の向きは逆方向であり、該第１の駆動信号伝送用配線の長さと該第２の駆動信号伝送用配線の長さは等しく、該第１のエミッタセンス配線の長さと該第２のエミッタセンス配線の長さは等しいことを特徴とする。 The semiconductor device according to the present invention includes a first power device disposed on a first insulating substrate, a second power device disposed on a second insulating substrate, and an external gate drive signal. An input gate drive signal input terminal, an emitter sense terminal connected to the outside,
A metal first drive signal transmission wiring for connecting the gate of the first power device and the gate drive signal input terminal, and a gate of the second power device and the gate drive signal input terminal are connected. A second drive signal transmission wiring made of metal, a first emitter sense wiring made of metal connecting the emitter of the first power device and the emitter sense terminal, and an emitter of the second power device And a second emitter sense wire made of metal for connecting the emitter sense terminal and the emitter sense terminal.
The first drive signal transmission line and the first emitter sense line have a first overlapping region that does not contact each other and overlap, and the second drive signal transmission line and the second emitter sense line Has a second overlapping region that does not contact each other and overlaps, and in the first overlapping region, the direction of the current flowing through the first drive signal transmission line and the direction of the current flowing through the first emitter sense line are reversed. And the direction of the current flowing through the second drive signal transmission line and the direction of the current flowing through the second emitter sense line in the second overlapping region is opposite, and the first drive signal transmission direction The length of the wiring is equal to the length of the second drive signal transmission wiring, and the length of the first emitter sense wiring is equal to the length of the second emitter sense wiring.

本発明により、半導体装置に搭載されたパワーデバイスのゲートに印加されるべきゲート駆動信号が電磁誘導に影響されることなく所望の制御を行うことができる。   According to the present invention, it is possible to perform desired control without the gate drive signal to be applied to the gate of the power device mounted on the semiconductor device being affected by electromagnetic induction.

実施の形態１
本実施形態は電磁誘導の影響を抑制して、所望のゲート駆動信号をパワーデバイスのゲートに印加できる半導体装置に関する。本実施形態の半導体装置の構成を図１、２、３に示す。図１は本実施形態の半導体装置の絶縁基板および搭載される素子について説明する図である。図２は図１の構成を備える半導体装置の配線の一部について説明する図である。図３は図２で説明する配線の断面構造について説明する図である。 Embodiment 1
The present embodiment relates to a semiconductor device capable of suppressing the influence of electromagnetic induction and applying a desired gate drive signal to the gate of a power device. The configuration of the semiconductor device of this embodiment is shown in FIGS. FIG. 1 is a diagram for explaining an insulating substrate and mounted elements of the semiconductor device of this embodiment. FIG. 2 is a diagram for explaining a part of wiring of a semiconductor device having the configuration of FIG. FIG. 3 is a view for explaining the cross-sectional structure of the wiring described in FIG.

図１を参照して本実施形態の半導体装置の絶縁基板の配置等について説明する。半導体装置の筐体底部を構成するベース基板１０には絶縁基板１１、１２、１３、１４、１５が配置される。絶縁基板１１の配線パターン４７にはＩＧＢＴ１６、１７およびダイオード２０、２１がそれぞれはんだ付けされる。   The arrangement of the insulating substrate of the semiconductor device of this embodiment will be described with reference to FIG. Insulating substrates 11, 12, 13, 14, and 15 are disposed on the base substrate 10 that forms the bottom of the housing of the semiconductor device. The IGBTs 16 and 17 and the diodes 20 and 21 are soldered to the wiring pattern 47 of the insulating substrate 11, respectively.

ＩＧＢＴ１６、１７のゲートはそれぞれ絶縁基板１２に配置された配線パターン３４とアルミワイヤで接続される。配線パターン３４はそれぞれバランス抵抗２６を経由して駆動信号伝送用配線パターン２５と接続される。駆動信号伝送用配線パターン２５には棒状中継導体４２が設置されている。   The gates of the IGBTs 16 and 17 are connected to the wiring pattern 34 disposed on the insulating substrate 12 by an aluminum wire. Each wiring pattern 34 is connected to the driving signal transmission wiring pattern 25 via the balance resistor 26. A rod-shaped relay conductor 42 is provided on the drive signal transmission wiring pattern 25.

ＩＧＢＴ１６、１７のエミッタはアルミワイヤ３７を介してダイオード２０、２１のアノードにそれぞれ接続される。さらにダイオード２０、２１はアルミワイヤ３８により絶縁基板１３の配線パターン３９と接続される。配線パターン３９にはエミッタ接続部２９が配置される。エミッタ接続部２９とは、配線パターン３９を外部と接続されるべきエミッタ主電極と接続を行う部分である。また、ＩＧＢＴ１７のエミッタは、エミッタセンスを用意するために、アルミワイヤ３６により棒状中継導体２７が配置される配線パターン４８に接続される。   The emitters of the IGBTs 16 and 17 are connected to the anodes of the diodes 20 and 21 via aluminum wires 37, respectively. Furthermore, the diodes 20 and 21 are connected to the wiring pattern 39 of the insulating substrate 13 by an aluminum wire 38. An emitter connecting portion 29 is disposed on the wiring pattern 39. The emitter connection portion 29 is a portion for connecting the wiring pattern 39 to an emitter main electrode to be connected to the outside. Further, the emitter of the IGBT 17 is connected to a wiring pattern 48 on which the rod-shaped relay conductor 27 is arranged by an aluminum wire 36 in order to prepare an emitter sense.

ＩＧＢＴ１６、１７のコレクタは絶縁基板１１の配線パターン４７と接続される。つまり、ＩＧＢＴ１６、１７の裏面に形成されたコレクタが配線パターン４７と接続される。配線パターン４７にはコレクタ接続部２８が配置される。コレクタ接続部２８とは、配線パターン４７を外部と接続されるべきコレクタ主電極端子と接続を行う部分である。このように図１においては、ＩＧＢＴ１６、１７のゲートは棒状中継導体４２と接続され、エミッタはエミッタ接続部２９と棒状中継導体２７とに接続され、コレクタはコレクタ接続部２８と接続される。   The collectors of the IGBTs 16 and 17 are connected to the wiring pattern 47 of the insulating substrate 11. That is, the collectors formed on the back surfaces of the IGBTs 16 and 17 are connected to the wiring pattern 47. A collector connection portion 28 is disposed on the wiring pattern 47. The collector connection portion 28 is a portion that connects the wiring pattern 47 to a collector main electrode terminal to be connected to the outside. In this way, in FIG. 1, the gates of the IGBTs 16 and 17 are connected to the rod-shaped relay conductor 42, the emitter is connected to the emitter connection portion 29 and the rod-shaped relay conductor 27, and the collector is connected to the collector connection portion 28.

なお、絶縁基板１４に形成されたＩＧＢＴ１８、１９およびダイオード２２、２３については上述と同様の接続関係であるから詳述しないが、ＩＧＢＴ１８、１９およびダイオード２２、２３は配線パターン３９を挟んでＩＧＢＴ１６、１７、およびダイオード２０、２１と対照となるように配置されている。そしてＩＧＢＴ１８、１９のゲートは棒状中継導体４６と接続され、エミッタはダイオード２２、２３を介してエミッタ接続部２９と接続され、コレクタはコレクタ接続部３０と接続される。なお、ＩＧＢＴ１９のエミッタはアルミワイヤにより棒状中継導体３３が配置される配線パターン４９にも接続されている。   The IGBTs 18 and 19 and the diodes 22 and 23 formed on the insulating substrate 14 are not described in detail because they have the same connection relation as described above. However, the IGBTs 18 and 19 and the diodes 22 and 23 17 and the diodes 20 and 21 are arranged to be in contrast. The gates of the IGBTs 18 and 19 are connected to the rod-shaped relay conductor 46, the emitter is connected to the emitter connection part 29 via the diodes 22 and 23, and the collector is connected to the collector connection part 30. The emitter of the IGBT 19 is also connected to a wiring pattern 49 on which the rod-shaped relay conductor 33 is arranged by an aluminum wire.

次いで、図２を参照して本実施形態の半導体装置の配線について説明する。図２は図１の構成に加えて、駆動信号伝送用配線４０とエミッタセンス配線４１が表された平面図である。なお、図２では図の簡略化のためにアルミワイヤを省略している。駆動信号伝送用配線４０、エミッタセンス配線４１共に平板状の金属である。これらは、駆動信号伝送用配線４０がエミッタセンス配線４１に重畳するように配置されている。   Next, the wiring of the semiconductor device of this embodiment will be described with reference to FIG. FIG. 2 is a plan view showing a drive signal transmission wiring 40 and an emitter sense wiring 41 in addition to the configuration of FIG. In FIG. 2, aluminum wires are omitted for simplification of the drawing. Both the drive signal transmission wiring 40 and the emitter sense wiring 41 are flat metal. These are arranged so that the drive signal transmission wiring 40 overlaps the emitter sense wiring 41.

駆動信号伝送用配線４０は、前述した棒状中継導体４２、棒状中継導体４６と接続される。棒状中継導体４２は、駆動信号伝送用配線パターン２５と駆動信号伝送用配線４０とを接続するように図２紙面垂直方向に伸びる。一方棒状中継導体４６は駆動信号伝送用配線パターン３１と駆動信号伝送用配線４０とを接続するように図２紙面垂直方向に伸びる。駆動信号伝送用配線４０にはさらに、外部からゲート駆動信号が入力されるゲート駆動信号入力端子４５が配置される。   The drive signal transmission wiring 40 is connected to the rod-shaped relay conductor 42 and the rod-shaped relay conductor 46 described above. The rod-shaped relay conductor 42 extends in the direction perpendicular to the paper surface of FIG. 2 so as to connect the drive signal transmission wiring pattern 25 and the drive signal transmission wiring 40. On the other hand, the rod-shaped relay conductor 46 extends in the direction perpendicular to the paper surface of FIG. 2 so as to connect the drive signal transmission wiring pattern 31 and the drive signal transmission wiring 40. The drive signal transmission wiring 40 is further provided with a gate drive signal input terminal 45 to which a gate drive signal is input from the outside.

エミッタセンス配線４１は、前述した棒状中継導体２７、棒状中継導体３３と接続される。棒状中継導体２７は、配線パターン４８とエミッタセンス配線４１とを接続するように図２紙面垂直方向に伸びる。一方棒状中継導体３３は配線パターン４９とエミッタセンス配線４１とを接続するように図２紙面垂直方向に伸びる。エミッタセンス配線４１にはさらに、外部に接続されるエミッタセンス端子４４が配置される。   The emitter sense wiring 41 is connected to the aforementioned bar-shaped relay conductor 27 and bar-shaped relay conductor 33. The rod-shaped relay conductor 27 extends in the direction perpendicular to the paper surface of FIG. 2 so as to connect the wiring pattern 48 and the emitter sense wiring 41. On the other hand, the rod-shaped relay conductor 33 extends in the direction perpendicular to the paper surface of FIG. 2 so as to connect the wiring pattern 49 and the emitter sense wiring 41. The emitter sense wiring 41 is further provided with an emitter sense terminal 44 connected to the outside.

次いで、図３を参照して駆動信号伝送用配線４０とエミッタセンス配線４１について説明する。図３は駆動信号伝送用配線４０とエミッタセンス配線４１の断面図である。図３に記載の通り、駆動信号伝送用配線４０とエミッタセンス配線４１との間には両者に接触して平板状の絶縁体５０が配置される。絶縁体５０は駆動信号伝送用配線４０とエミッタセンス配線４１とが重なって配置される領域全体に配置されるものである。本実施形態における絶縁体５０はガラスエポキシであるが絶縁体である限り特に限定されない。また、本実施形態の絶縁体５０の厚さは１００μｍであり絶縁体全体にわたって一定の厚さを保つものである。なお、説明の便宜上図２では絶縁体５０の記載を省略している。   Next, the drive signal transmission wiring 40 and the emitter sense wiring 41 will be described with reference to FIG. FIG. 3 is a cross-sectional view of the drive signal transmission wiring 40 and the emitter sense wiring 41. As shown in FIG. 3, a flat insulator 50 is disposed between the drive signal transmission wiring 40 and the emitter sense wiring 41 in contact with both. The insulator 50 is disposed over the entire region where the drive signal transmission wiring 40 and the emitter sense wiring 41 overlap. The insulator 50 in this embodiment is glass epoxy, but is not particularly limited as long as it is an insulator. Moreover, the thickness of the insulator 50 of this embodiment is 100 μm, and maintains a constant thickness throughout the insulator. For convenience of explanation, the illustration of the insulator 50 is omitted in FIG.

本実施形態の構成では駆動信号伝送用配線４０とエミッタセンス配線４１とは電流の流れる方向が逆方向になる。すなわち駆動信号伝送用配線４０においてゲート駆動信号入力端子４５から棒状中継導体４２、４６へ向かう電流と、エミッタセンス配線４１において棒状中継導体２７、３３からエミッタセンス端子４４へ向かう電流とは互いに逆方向となるように接続、配線が構成されている。   In the configuration of the present embodiment, the drive signal transmission wiring 40 and the emitter sense wiring 41 have opposite directions of current flow. That is, the current from the gate drive signal input terminal 45 to the rod-shaped relay conductors 42 and 46 in the drive signal transmission wiring 40 and the current from the rod-shaped relay conductors 27 and 33 to the emitter sense terminal 44 in the emitter sense wiring 41 are opposite to each other. Connections and wiring are configured so that

このような構成により、駆動信号伝送用配線４０とエミッタセンス配線４１とに過渡電流が流れる場合、駆動信号伝送用配線４０周辺に発生する磁場とエミッタセンス配線４１周辺に発生する磁場とは打ち消しあう。よってこれらの磁場から駆動信号伝送用配線４０に生じる起電力を抑制できる。すなわち、駆動信号伝送用配線４０のインダクタンスを低減できる。したがって、主電流ｄＩ／ｄｔによる電磁誘導の影響を受けにくくなる。また、半導体装置内のゲート配線長が異なってもインダクタンスの差異が小さいため、従来と比較しより均一の動作が可能となり、本実施形態の構成によれば駆動信号伝送用配線４０を伝送するゲート駆動信号は過渡電流の影響を受けづらく安定的なゲート制御が可能となる。   With such a configuration, when a transient current flows through the drive signal transmission wiring 40 and the emitter sense wiring 41, the magnetic field generated around the drive signal transmission wiring 40 and the magnetic field generated around the emitter sense wiring 41 cancel each other. . Therefore, the electromotive force generated in the drive signal transmission wiring 40 from these magnetic fields can be suppressed. That is, the inductance of the drive signal transmission wiring 40 can be reduced. Therefore, it becomes difficult to be affected by electromagnetic induction due to the main current dI / dt. Further, since the difference in inductance is small even if the gate wiring length in the semiconductor device is different, a more uniform operation is possible as compared with the conventional one. According to the configuration of the present embodiment, the gate transmitting the drive signal transmission wiring 40 The drive signal is not easily affected by the transient current, and stable gate control is possible.

上述した駆動信号伝送用配線４０のインダクタンスを低減する効果は、駆動信号伝送用配線４０とエミッタセンス配線４１が重なる領域（重畳領域という）を設けることにより得られるものである。つまり、駆動信号伝送用配線４０とエミッタセンス配線４１が重畳領域を有し、当該重畳領域において駆動信号伝送用配線４０とエミッタセンス配線４１を流れる電流が逆方向である限りにおいて駆動信号伝送用配線４０のインダクタンスを低減できる。さらに、本実施形態では、駆動信号伝送用配線４０が全体に渡ってエミッタセンス配線４１と重なる構成であるため、より高いインダクタンス低減効果を得られる。   The effect of reducing the inductance of the drive signal transmission wiring 40 described above is obtained by providing a region where the drive signal transmission wiring 40 and the emitter sense wiring 41 overlap (referred to as an overlapping region). That is, as long as the drive signal transmission wiring 40 and the emitter sense wiring 41 have an overlapping region, and the current flowing through the drive signal transmission wiring 40 and the emitter sense wiring 41 in the overlapping region is in the reverse direction, the drive signal transmission wiring. The inductance of 40 can be reduced. Furthermore, in the present embodiment, since the drive signal transmission wiring 40 overlaps with the emitter sense wiring 41 throughout, a higher inductance reduction effect can be obtained.

さらに、本実施形態で駆動信号伝送用配線４０とエミッタセンス配線４１との間に配置される絶縁体５０は駆動信号伝送用配線４０とエミッタセンス配線４１とが接触（ショート）することを防止するとともに両者の間隔を一定に保つ。駆動信号伝送用配線４０とエミッタセンス配線４１との間隔を一定に保つことにより過渡電流などの電気的振動を相殺する効果が場所によらず一定に保つことができる。   Furthermore, the insulator 50 disposed between the drive signal transmission wiring 40 and the emitter sense wiring 41 in this embodiment prevents the drive signal transmission wiring 40 and the emitter sense wiring 41 from contacting (shorting). At the same time, the distance between the two is kept constant. By keeping the distance between the drive signal transmission wiring 40 and the emitter sense wiring 41 constant, the effect of canceling electrical vibration such as transient current can be kept constant regardless of the place.

絶縁体５０の厚さは駆動信号伝送用配線４０とエミッタセンス配線４１とのショート回避を保証できる限りにおいては「十分薄い」ほうがより駆動信号伝送用配線４０のインダクタンス低減効果が高まる。ここで、「十分薄い」とは標準的には１〜１０００μｍであることが好ましいが、これに限定されず適宜定められる。   As long as the thickness of the insulator 50 can assure short-circuit avoidance between the drive signal transmission wiring 40 and the emitter sense wiring 41, the inductance reduction effect of the drive signal transmission wiring 40 is further enhanced. Here, “sufficiently thin” is preferably 1 to 1000 μm as a standard, but is not limited thereto and is appropriately determined.

本実施形態は、重畳領域で駆動信号伝送用配線とエミッタセンス配線との電流の流れる向き、特に過渡電流の流れる方向が相互に逆向きであることによって駆動信号伝送用配線のインダクタンス低減効果を得るものである。したがってそれ以外の構成は本実施形態の必須構成要件ではなく様々な変形が可能である。例えば、パワーデバイスとしてＩＧＢＴを用いたがこれに限定される訳ではない。また駆動信号伝送用配線とエミッタセンス配線との間に配置される絶縁体は、両面に粘着性を有する絶縁テープあるいは粘着性接着性のあるシリコーンゴムのような樹脂であっても良い。   This embodiment obtains the inductance reduction effect of the drive signal transmission wiring by the direction in which the current flows between the drive signal transmission wiring and the emitter sense wiring in the overlapping region, in particular, the direction in which the transient current flows is opposite to each other. Is. Accordingly, other configurations are not essential components of the present embodiment, and various modifications are possible. For example, although IGBT was used as a power device, it is not necessarily limited to this. The insulator disposed between the drive signal transmission line and the emitter sense line may be an insulating tape having adhesiveness on both sides or a resin such as adhesive-adhesive silicone rubber.

実施の形態２
本実施形態は駆動信号伝送用配線とエミッタセンス配線とが同一プリント基板に形成される半導体装置に関する。本実施形態を説明する図は平面図４、５である。図４、５ともに図１〜３で説明した構成要素と同一の形状で現された部分については実施形態１と同様であるから説明を省略する。 Embodiment 2
The present embodiment relates to a semiconductor device in which a drive signal transmission wiring and an emitter sense wiring are formed on the same printed board. The drawings for explaining the present embodiment are plan views 4 and 5. 4 and 5 are the same as the components described in FIGS. 1 to 3 and are the same as those in the first embodiment, and thus the description thereof is omitted.

本実施形態ではＩＧＢＴが４枚の絶縁基板上にそれぞれ２個ずつ計８個搭載される。図４ではアルミワイヤの接続などを省略しているがこれは実施形態１と同様である。以後図５を参照して本実施形態の構成の特徴部分を説明する。   In the present embodiment, a total of eight IGBTs are mounted on each of four insulating substrates. In FIG. 4, the connection of the aluminum wire is omitted, but this is the same as in the first embodiment. Hereinafter, the characteristic part of the configuration of the present embodiment will be described with reference to FIG.

図５には、駆動信号伝送用配線とエミッタセンス配線とが形成されたプリント基板５７が示されている。プリント基板５７には駆動信号伝送用配線５８が配置される。駆動信号伝送用配線５８とはプリント基板５７に駆動信号伝送用配線用に形成されたパターンのことをいう。駆動信号伝送用配線５８は４本の棒状中継導体５５と接続される。棒状中継導体５５はゲートバランス抵抗を介してＩＧＢＴのゲートと接続されるものである。また、駆動信号伝送用配線５８はその一部に、ゲート駆動信号の入力が行われるゲート駆動信号入力端子５９を備える。   FIG. 5 shows a printed circuit board 57 on which drive signal transmission wiring and emitter sense wiring are formed. A drive signal transmission wiring 58 is disposed on the printed circuit board 57. The drive signal transmission wiring 58 is a pattern formed on the printed circuit board 57 for the drive signal transmission wiring. The drive signal transmission wiring 58 is connected to the four rod-shaped relay conductors 55. The rod-shaped relay conductor 55 is connected to the gate of the IGBT through a gate balance resistor. In addition, the drive signal transmission wiring 58 includes a gate drive signal input terminal 59 to which a gate drive signal is input.

プリント基板５７には駆動信号伝送用配線に加えてエミッタセンス配線６０が配置される。エミッタセンス配線６０はプリント基板５７の下すなわち駆動信号伝送用配線５８より下層に図５破線で示す形状で形成される。これは、多層プリント基板であるプリント基板５７の最上層以外のパターンは、平面図である図５では表せないが便宜的に示すものである。ここで、エミッタセンス配線６０とはプリント基板５７にエミッタセンス配線用に形成されたパターンのことをいう。エミッタセンス配線６０は棒状端子５６に接続されＩＧＢＴのエミッタと接続される。また、エミッタセンス配線６０はその一部に、エミッタセンス端子６１を備える。エミッタセンス端子６１は外部に接続されるべき端子である。   On the printed circuit board 57, an emitter sense wiring 60 is disposed in addition to the drive signal transmission wiring. The emitter sense wiring 60 is formed in a shape indicated by a broken line in FIG. 5 below the printed circuit board 57, that is, below the drive signal transmission wiring 58. This is for the sake of convenience, although patterns other than the uppermost layer of the printed circuit board 57 which is a multilayer printed circuit board cannot be represented in FIG. 5 which is a plan view. Here, the emitter sense wiring 60 refers to a pattern formed on the printed circuit board 57 for the emitter sense wiring. The emitter sense wiring 60 is connected to the rod-shaped terminal 56 and is connected to the emitter of the IGBT. Further, the emitter sense wiring 60 includes an emitter sense terminal 61 in a part thereof. The emitter sense terminal 61 is a terminal to be connected to the outside.

本実施形態によれば、実施形態１と同様に重畳領域において駆動信号伝送用配線とエミッタセンス配線とが電流の向きが逆になる構成を備えるため実施形態１で説明した効果が得られる。さらに、本実施形態のように搭載部品の比較的多い（ただし本実施形態の搭載部品数に限られない）半導体装置ではその製造工程において駆動信号伝送用配線とエミッタセンス配線を所望の位置に、相対位置精度よくしかも、両者の間隔を所定の値に保って配置することは困難である。しかしながら、本実施形態のように多層のプリント基板を用いることにより、半導体装置の製造工程において前述の位置調整を行う必要がなく半導体装置の製造容易化ができる。   According to the present embodiment, the effect described in the first embodiment can be obtained because the drive signal transmission wiring and the emitter sense wiring have a configuration in which the directions of currents are reversed in the overlapping region as in the first embodiment. Further, in a semiconductor device having a relatively large number of mounted components as in this embodiment (but not limited to the number of mounted components in this embodiment), the drive signal transmission wiring and the emitter sense wiring are placed in desired positions in the manufacturing process. It is difficult to arrange them with a high relative positional accuracy and with a predetermined distance between them. However, by using a multilayer printed board as in this embodiment, it is not necessary to perform the above-described position adjustment in the manufacturing process of the semiconductor device, and the manufacturing of the semiconductor device can be facilitated.

実施の形態３
本実施形態は駆動信号伝送用配線とエミッタセンス配線とが同一プリント基板に形成される半導体装置であって実施形態２と異なりエミッタセンス配線が２のパターンからなる半導体装置に関する。本実施形態を説明する図は平面図６、７、９、１０、１１と断面図８である。図６、７、９、１０、１１ともに図１〜３で説明した構成要素と同一の形状で現された部分については実施形態１と同様であるから説明を省略する。 Embodiment 3
The present embodiment relates to a semiconductor device in which a drive signal transmission wiring and an emitter sense wiring are formed on the same printed circuit board. Unlike the second embodiment, the present embodiment relates to a semiconductor device in which the emitter sense wiring has two patterns. The drawings for explaining this embodiment are plan views 6, 7, 9, 10, 11 and a sectional view 8. FIG. 6, 7, 9, 10, and 11 are the same as those of the first embodiment, and the description thereof will be omitted.

本実施形態ではＩＧＢＴが４枚の絶縁基板上にそれぞれ２個ずつ計８個搭載される。図６、７、９、１０、１１ではアルミワイヤの接続などを省略しているがこれは実施形態１と同様である。以後図６を参照して本実施形態の構成を説明する。ＩＧＢＴ６７、６８のゲートはゲートブリッジ抵抗６６、６９を介して、棒状中継導体７０と接続される。他のＩＧＢＴについても同様に棒状中継導体と接続される。ＩＧＢＴ６７、６８のエミッタはそれぞれダイオード８１、８０を介してエミッタ配線領域７７に接続される。エミッタ配線領域７７には棒状中継導体７１が配置される。   In the present embodiment, a total of eight IGBTs are mounted on each of four insulating substrates. 6, 7, 9, 10, and 11 omit connection of aluminum wires and the like, this is the same as in the first embodiment. Hereinafter, the configuration of the present embodiment will be described with reference to FIG. The gates of the IGBTs 67 and 68 are connected to the rod-shaped relay conductor 70 via the gate bridge resistors 66 and 69. The other IGBTs are similarly connected to the rod-shaped relay conductor. The emitters of the IGBTs 67 and 68 are connected to the emitter wiring region 77 via diodes 81 and 80, respectively. A rod-shaped relay conductor 71 is disposed in the emitter wiring region 77.

図７はプリント基板７２の平面図である。プリント基板７２はプリント基板７２の断面図である図８に示されるように多層パターンからなる。すなわち、プリント基板７２は、駆動信号伝送用配線７５と第一のエミッタセンス配線７４と第二のエミッタセンス配線７３を備える。なお、駆動信号伝送用配線７５と第一のエミッタセンス配線７４と第二のエミッタセンス配線７３とを形成する配線パターンは相互に接することのないように絶縁体で離隔されている。   FIG. 7 is a plan view of the printed circuit board 72. The printed circuit board 72 has a multilayer pattern as shown in FIG. That is, the printed circuit board 72 includes a drive signal transmission wiring 75, a first emitter sense wiring 74, and a second emitter sense wiring 73. Note that the wiring patterns forming the drive signal transmission wiring 75, the first emitter sense wiring 74, and the second emitter sense wiring 73 are separated by an insulator so as not to contact each other.

図９は駆動信号伝送用配線７５を説明するための平面図である。駆動信号伝送用配線７５には、ＩＧＢＴのゲートと接続される棒状端子７０が接続される。棒状端子７０は４本存在し、それぞれ駆動信号伝送用配線７５と接続されるものである。駆動信号伝送用配線７５にはさらに、ゲート駆動信号の入力が行われるゲート駆動信号入力端子７６が配置される。   FIG. 9 is a plan view for explaining the drive signal transmission wiring 75. A rod-shaped terminal 70 connected to the gate of the IGBT is connected to the drive signal transmission wiring 75. There are four rod-like terminals 70, which are connected to the drive signal transmission wiring 75, respectively. The drive signal transmission wiring 75 is further provided with a gate drive signal input terminal 76 for inputting a gate drive signal.

図１０は第一のエミッタセンス配線７４を説明する平面図である。第一のエミッタセンス配線７４には、後述の第二のエミッタセンス配線７３と接続するスルーホール７９が４箇所設けられている。さらに第一のエミッタセンス配線７４にはさらに外部と接続されるエミッタセンス端子７８が接続される。   FIG. 10 is a plan view for explaining the first emitter sense wiring 74. The first emitter sense wiring 74 is provided with four through holes 79 connected to a second emitter sense wiring 73 described later. Further, an emitter sense terminal 78 connected to the outside is further connected to the first emitter sense wiring 74.

図１１は第二のエミッタセンス配線７３を説明する平面図である。第二のエミッタセンス配線７３はスルーホール７９と接続される。このスルーホール７９は前述の通り第一のエミッタセンス配線にも接続されているため、第二のエミッタセンス配線７３と第一のエミッタセンス配線７４とはこのスルーホール７９で接続されている。第二のエミッタセンス配線７３はさらに棒状中継導体７１と接続される。棒状中継導体７１は前述の通り図６のエミッタ配線領域７７と接続されているため、第二のエミッタセンス配線７３は棒状中継導体７１を介してエミッタ配線領域７７と接続されている。   FIG. 11 is a plan view for explaining the second emitter sense wiring 73. The second emitter sense wiring 73 is connected to the through hole 79. Since the through hole 79 is also connected to the first emitter sense wiring as described above, the second emitter sense wiring 73 and the first emitter sense wiring 74 are connected by the through hole 79. The second emitter sense wiring 73 is further connected to the rod-shaped relay conductor 71. Since the rod-shaped relay conductor 71 is connected to the emitter wiring region 77 of FIG. 6 as described above, the second emitter sense wiring 73 is connected to the emitter wiring region 77 via the rod-shaped relay conductor 71.

本実施形態においては、絶縁体を介して隣接する駆動信号伝送用配線７５と第一のエミッタセンス配線７４とが実施形態１で説明した重畳領域を形成している。また、駆動信号伝送用配線７５ではゲート駆動信号入力端子７６から棒状中継導体７０へ過渡電流が流れるのに対し、第一のエミッタセンス配線７４ではスルーホール７９からエミッタセンス端子７８へ過渡電流が流れる。したがって駆動信号伝送用配線７５と第一のエミッタセンス配線７４との重畳領域では電流の向きが逆方向であるから駆動信号伝送用配線７５のインダクタンスを低減できる。   In the present embodiment, the drive signal transmission wiring 75 and the first emitter sense wiring 74 which are adjacent to each other through an insulator form the overlapping region described in the first embodiment. In the drive signal transmission wiring 75, a transient current flows from the gate drive signal input terminal 76 to the rod-shaped relay conductor 70, whereas in the first emitter sense wiring 74, a transient current flows from the through hole 79 to the emitter sense terminal 78. . Therefore, since the direction of the current is opposite in the overlapping region of the drive signal transmission wiring 75 and the first emitter sense wiring 74, the inductance of the drive signal transmission wiring 75 can be reduced.

上述したようにプリント基板を用いて、プリント基板７２が備える駆動信号伝送用配線とエミッタセンス配線とを近接させることによるインダクタンス低減の手法は実施形態２と同様である。しかしながら本実施形態の意義は、エミッタセンスのための配線が理由で、重畳領域を形成し重畳領域における電流の向きを相互に逆方向にすることが困難な場合であっても本発明の効果を得ることができる点にある。   As described above, the method of reducing the inductance by using the printed circuit board and bringing the drive signal transmission wiring and the emitter sense wiring included in the printed circuit board 72 close to each other is the same as in the second embodiment. However, the significance of the present embodiment is that the effect of the present invention is achieved even when it is difficult to form the overlapping region and to reverse the current directions in the overlapping region because of the emitter sensing wiring. It is in the point that can be obtained.

すなわち、図６におけるエミッタ配線領域７７に設置された棒状中継導体７１は第二のエミッタセンス配線７３と接続されるが、このような第二のエミッタセンス配線７３に直接にエミッタセンス端子を接続することも考えられる。ところが、第二のエミッタセンス配線７３を用いると、第二のエミッタセンス配線７３の如何なる位置にエミッタセンス端子を接続しようとも「駆動信号伝送用配線７５全体において重畳領域を形成ししかも電流の方向を反対にする」ことはできない。そこで、本実施形態のように第一のエミッタセンス配線７４を新規に設けることにより「駆動信号伝送用配線７５全体において重畳領域を形成ししかも電流の方向を反対にする」ことができる第一のエミッタセンス配線をプリント基板に配置できる。   That is, the rod-shaped relay conductor 71 installed in the emitter wiring region 77 in FIG. 6 is connected to the second emitter sense wiring 73, and the emitter sense terminal is directly connected to the second emitter sense wiring 73. It is also possible. However, when the second emitter sense wiring 73 is used, no matter what position of the second emitter sense wiring 73 is connected to the emitter sense terminal, “the overlap region is formed in the entire drive signal transmission wiring 75 and the direction of the current is changed. You can't do the opposite. Therefore, the first emitter sense wiring 74 can be newly provided as in the present embodiment, so that “the overlapping region can be formed in the entire drive signal transmission wiring 75 and the direction of the current can be reversed”. Emitter sense wiring can be arranged on the printed circuit board.

本実施形態による駆動信号伝送用配線７５のインダクタンスを低減する効果は実施形態１と同様である。なお、プリント基板７２には温度センス回路パターンや電流センス回路のパターン、コレクタセンス回路のパターンなどが加わっても良いが、駆動信号伝送用配線７５と第一のエミッタセンス配線７４とはプリント基板中最近接することにより本発明の効果が高まる。   The effect of reducing the inductance of the drive signal transmission wiring 75 according to the present embodiment is the same as that of the first embodiment. Note that a temperature sensing circuit pattern, a current sensing circuit pattern, a collector sensing circuit pattern, and the like may be added to the printed circuit board 72, but the drive signal transmission wiring 75 and the first emitter sensing wiring 74 are included in the printed circuit board. The effect of the present invention is enhanced by the closest contact.

実施の形態４
本実施形態は駆動信号伝送用配線とエミッタセンス配線とが同一プリント基板に形成される半導体装置であって実施形態２、３と異なり各ＩＧＢＴに伸びる配線長を統一できる半導体装置に関する。本実施形態を説明する図は平面図１２、１３、１４、１５である。図１２、１３、１４、１５ともに図１〜３で説明した構成要素と同一の形状で現された部分については実施形態１と同様であるから説明を省略する。 Embodiment 4
This embodiment relates to a semiconductor device in which a drive signal transmission wiring and an emitter sense wiring are formed on the same printed circuit board, and unlike the second and third embodiments, a semiconductor device capable of unifying the wiring length extending to each IGBT. The drawings for explaining this embodiment are plan views 12, 13, 14, and 15. 12, 13, 14, and 15 are the same as those of the first embodiment, and the description thereof will be omitted.

本実施形態ではＩＧＢＴが４枚の絶縁基板上にそれぞれ２個ずつ計８個搭載される。以後図１２を参照して本実施形態の構成を説明する。ＩＧＢＴ８６、８７のゲートはゲートブリッジ抵抗８８、８９を介して、棒状中継導体９０と接続される。他のＩＧＢＴについても同様に棒状中継導体９０と接続される。ＩＧＢＴ８７のエミッタはエミッタセンスのために棒状中継導体９１と接続される。他のＩＧＢＴのエミッタも同様に近接する棒状中継導体９１と接続される。   In the present embodiment, a total of eight IGBTs are mounted on each of four insulating substrates. Hereinafter, the configuration of the present embodiment will be described with reference to FIG. The gates of the IGBTs 86 and 87 are connected to the rod-shaped relay conductor 90 through gate bridge resistors 88 and 89. Other IGBTs are similarly connected to the rod-shaped relay conductor 90. The emitter of the IGBT 87 is connected to the rod-shaped relay conductor 91 for emitter sensing. Similarly, the emitters of other IGBTs are connected to the adjacent bar-shaped relay conductor 91.

図１３は本実施形態のプリント基板が備える駆動信号伝送用配線について説明する図である。図１３に示されるように本実施形態のプリント基板はそのパターンの一つとして２の駆動信号伝送用配線９２を備える。駆動信号伝送用配線９２は棒状中継導体９０によりＩＧＢＴのゲートと接続されている。駆動信号伝送用配線９２はさらにスルーホール９３を備える。スルーホール９３については後述する。   FIG. 13 is a diagram for explaining the drive signal transmission wiring provided in the printed circuit board of the present embodiment. As shown in FIG. 13, the printed circuit board according to this embodiment includes two drive signal transmission lines 92 as one of the patterns. The drive signal transmission wiring 92 is connected to the gate of the IGBT by a rod-shaped relay conductor 90. The drive signal transmission wiring 92 further includes a through hole 93. The through hole 93 will be described later.

図１４は本実施形態のプリント基板が備えるエミッタセンス配線について説明する図である。本実施形態では２のエミッタセンス配線９４を有しそれぞれ棒状中継導体９１と接続される。さらにエミッタセンス配線９４にはスルーホール９５が接続される。スルーホール９５については後述する。なお、同一のプリント基板において、上記駆動信号伝送用配線層とエミッタセンス配線層は、同一プリント基板中最も近接させることが望ましい。   FIG. 14 is a diagram illustrating the emitter sense wiring provided in the printed circuit board according to the present embodiment. In the present embodiment, there are two emitter sense wirings 94 and each is connected to a rod-shaped relay conductor 91. Further, a through hole 95 is connected to the emitter sense wiring 94. The through hole 95 will be described later. In the same printed circuit board, it is desirable that the drive signal transmission wiring layer and the emitter sense wiring layer be closest to each other in the same printed circuit board.

図１５は本実施形態のプリント基板が備える補助駆動信号伝送用配線と補助エミッタセンス配線について説明する図である。補助駆動信号伝送用配線９６は前述した２の駆動信号伝送用配線９２とスルーホール９３により接続される。補助駆動信号伝送用配線９６はさらに、外部からゲート駆動信号が入力されるゲート駆動信号入力端子９９を備える。そして補助駆動信号伝送用配線９６と同一平面上には補助エミッタセンス配線９７が配置される。補助エミッタセンス配線９７はエミッタセンス配線９４とスルーホール９５を介して接続される。補助エミッタセンス配線９７はさらに外部と接続されるエミッタセンス端子９８と接続される。   FIG. 15 is a diagram for explaining auxiliary drive signal transmission wiring and auxiliary emitter sense wiring included in the printed circuit board according to the present embodiment. The auxiliary driving signal transmission wiring 96 is connected to the two driving signal transmission wirings 92 described above by the through holes 93. The auxiliary drive signal transmission wiring 96 further includes a gate drive signal input terminal 99 to which a gate drive signal is input from the outside. An auxiliary emitter sense wiring 97 is arranged on the same plane as the auxiliary driving signal transmission wiring 96. The auxiliary emitter sense wiring 97 is connected to the emitter sense wiring 94 through the through hole 95. The auxiliary emitter sense wiring 97 is further connected to an emitter sense terminal 98 connected to the outside.

このような構成とすると、ゲート駆動信号入力端子９９からスルーホール９３を経由し、さらに、駆動信号伝送用配線９２に接続された棒状中継導体９０を経由してＩＧＢＴのゲートに至るまでの経路が、複数のＩＧＢＴ間で等しくなる。すなわち、ゲート駆動信号入力端子９９からＩＧＢＴ８６、８７、８、９のゲートへの配線経路長は等しくすることができる。また、エミッタセンス端子９８からＩＧＢＴ８６、８７、８、９への配線経路長もそれぞれ等しい。他のＩＧＢＴについても同様である。   With such a configuration, there is a path from the gate drive signal input terminal 99 via the through hole 93 to the IGBT relay gate via the rod-shaped relay conductor 90 connected to the drive signal transmission wiring 92. It becomes equal among a plurality of IGBTs. That is, the wiring path lengths from the gate drive signal input terminal 99 to the gates of the IGBTs 86, 87, 8, and 9 can be made equal. Further, the wiring path lengths from the emitter sense terminal 98 to the IGBTs 86, 87, 8, and 9 are also equal. The same applies to other IGBTs.

このように複数のＩＧＢＴ間で配線経路長を一致させることにより、異なるＩＧＢＴ間で配線抵抗やインダクタンスをほぼ統一できる。したがって、たとえば特定のＩＧＢＴに電流が集中することなどを回避でき、複数ＩＧＢＴ間で均一動作が可能となる。さらに、上述の通り複数ＩＧＢＴが同時にばらつきなく動作できることに加えて、本実施形態は、駆動信号伝送用配線とエミッタセンス配線との重畳領域における電流の流れる方向が反対方向となる構成であるから実施形態１などと同様に駆動信号伝送用配線のインダクタンス低減も可能である。   In this way, by matching the wiring path length between the plurality of IGBTs, the wiring resistance and inductance can be substantially unified among the different IGBTs. Therefore, for example, current concentration on a specific IGBT can be avoided, and uniform operation can be performed among a plurality of IGBTs. Furthermore, in addition to the fact that a plurality of IGBTs can operate simultaneously without variation as described above, this embodiment is implemented because the direction in which the current flows in the overlapping region of the drive signal transmission wiring and the emitter sense wiring is opposite. Similar to the first embodiment, the inductance of the drive signal transmission wiring can be reduced.

ゆえに、本実施形態の構成によれば一致するタイミングで動作するべき複数のＩＧＢＴが同時にばらつきなく動作を行い、しかも、電磁誘導による誘導起電力の影響を受けづらい半導体装置を得ることができる。上記実施形態では補助駆動信号伝送用配線９６と補助エミッタセンス配線９７がプリント基板内の同一の層に設置されている例を説明したが、異なる層に設置しても同様の効果を得ることができる。   Therefore, according to the configuration of the present embodiment, it is possible to obtain a semiconductor device in which a plurality of IGBTs that should operate at the same timing operate simultaneously without variation and are not easily influenced by the induced electromotive force due to electromagnetic induction. In the above embodiment, the example in which the auxiliary drive signal transmission wiring 96 and the auxiliary emitter sense wiring 97 are installed in the same layer in the printed circuit board has been described, but the same effect can be obtained even if they are installed in different layers. it can.

実施の形態１の半導体装置の絶縁基板および搭載される素子について説明する平面図である。3 is a plan view illustrating an insulating substrate and mounted elements of the semiconductor device of First Embodiment; FIG. 実施の形態１の半導体装置の配線について説明する平面図である。4 is a plan view illustrating wiring of the semiconductor device of First Embodiment; FIG. 実施の形態１の半導体装置が備える配線の断面図である。2 is a cross-sectional view of wirings provided in the semiconductor device of the first embodiment. FIG. 実施の形態２の半導体装置の構成を説明する平面図である。FIG. 10 is a plan view illustrating a configuration of a semiconductor device according to a second embodiment. 実施の形態２の半導体装置の配線について説明する平面図である。FIG. 10 is a plan view illustrating wiring of a semiconductor device according to a second embodiment. 実施の形態３の半導体装置の素子配置などについて説明する平面図である。FIG. 10 is a plan view for explaining element arrangement and the like of the semiconductor device of the third embodiment. 実施の形態３の半導体装置のプリント基板について説明する平面図である。FIG. 10 is a plan view illustrating a printed circuit board of a semiconductor device according to a third embodiment. 実施の形態３のプリント基板の断面図である。6 is a cross-sectional view of a printed circuit board according to Embodiment 3. FIG. 実施の形態３のプリント基板のうち駆動信号伝送用配線を説明する平面図である。FIG. 10 is a plan view for explaining drive signal transmission wiring in the printed circuit board according to the third embodiment. 実施の形態３のプリント基板のうち第一のエミッタセンス配線を説明する平面図である。FIG. 10 is a plan view for explaining a first emitter sense wiring in the printed circuit board according to the third embodiment. 実施の形態３のプリント基板のうち第二のエミッタセンス配線を説明する平面図である。FIG. 10 is a plan view for explaining a second emitter sense wiring in the printed circuit board according to the third embodiment. 実施の形態４の半導体装置の素子配置などについて説明する平面図である。FIG. 11 is a plan view for explaining element arrangement and the like of the semiconductor device of the fourth embodiment. 実施の形態４のプリント基板のうち駆動信号伝送用配線を説明する平面図である。FIG. 10 is a plan view for explaining drive signal transmission wiring in the printed circuit board according to the fourth embodiment. 実施の形態４のプリント基板のうちエミッタセンス配線を説明する平面図である。FIG. 10 is a plan view illustrating an emitter sense wiring in the printed circuit board according to the fourth embodiment. 実施の形態４のプリント基板のうち補助駆動信号伝送用配線などを説明する平面図である。FIG. 10 is a plan view for explaining auxiliary drive signal transmission wiring and the like in the printed circuit board according to Embodiment 4; 課題を説明する半導体装置の平面図である。It is a top view of the semiconductor device explaining a subject. 課題を説明する半導体装置の平面図である。It is a top view of the semiconductor device explaining a subject. 課題を説明する半導体装置の側面図である。It is a side view of a semiconductor device explaining a subject. 課題を説明する半導体装置の正面図である。It is a front view of the semiconductor device explaining a subject.

符号の説明Explanation of symbols

１６ ＩＧＢＴ
４０ 駆動信号伝送用配線
４１ エミッタセンス配線
４４ エミッタセンス端子
４５ ゲート駆動信号入力端子 16 IGBT
40 Drive signal transmission wiring 41 Emitter sense wiring 44 Emitter sense terminal 45 Gate drive signal input terminal

Claims (6)

ベース基板上の絶縁基板に配置されるパワーデバイスと、
外部からのゲート駆動信号が入力されるゲート駆動信号入力端子と、
外部に接続されるエミッタセンス端子と、
前記パワーデバイスのゲートと前記ゲート駆動信号入力端子とを接続する金属製の平板である駆動信号伝送用配線と、
前記パワーデバイスのエミッタと前記エミッタセンス端子とを接続する金属製の平板であるエミッタセンス配線とを備え、
前記駆動信号伝送用配線と前記エミッタセンス配線は前記ベース基板と平行に配置され、
前記駆動信号伝送用配線と前記エミッタセンス配線は互いに接触せずに重なる重畳領域を有し、
前記重畳領域では前記駆動信号伝送用配線を流れる電流と前記エミッタセンス配線を流れる電流の向きは逆方向であることを特徴とする半導体装置。 A power device disposed on an insulating substrate on the base substrate;
A gate drive signal input terminal to which an external gate drive signal is input;
An emitter sense terminal connected to the outside;
A drive signal transmission wiring that is a metal flat plate connecting the gate of the power device and the gate drive signal input terminal;
An emitter sense wiring that is a metal flat plate connecting the emitter of the power device and the emitter sense terminal;
The drive signal transmission wiring and the emitter sense wiring are arranged in parallel with the base substrate,
The drive signal transmission wiring and the emitter sense wiring have overlapping regions that do not contact each other,
The semiconductor device according to claim 1, wherein the direction of the current flowing through the drive signal transmission line and the direction of the current flowing through the emitter sense line is opposite in the overlap region. 第１の絶縁基板上に配置された第１のパワーデバイスと、
第２の絶縁基板上に配置された第２のパワーデバイスと、
外部からのゲート駆動信号が入力されるゲート駆動信号入力端子と、
外部に接続されるエミッタセンス端子と、
前記第１のパワーデバイスのゲートと前記ゲート駆動信号入力端子とを接続する金属製の第１の駆動信号伝送用配線と、
前記第２のパワーデバイスのゲートと前記ゲート駆動信号入力端子とを接続する金属製の第２の駆動信号伝送用配線と、
前記第１のパワーデバイスのエミッタと前記エミッタセンス端子とを接続する金属製の第１のエミッタセンス配線と、
前記第２のパワーデバイスのエミッタと前記エミッタセンス端子とを接続する金属製の第２のエミッタセンス配線とを備え、
前記第１の駆動信号伝送用配線と前記第１のエミッタセンス配線は、互いに接触せず重なる第１の重畳領域を有し、
前記第２の駆動信号伝送用配線と前記第２のエミッタセンス配線は、互いに接触せず重なる第２の重畳領域を有し、
前記第１の重畳領域では前記第１の駆動信号伝送用配線を流れる電流と前記第１のエミッタセンス配線を流れる電流の向きは逆方向であり、
前記第２の重畳領域では前記第２の駆動信号伝送用配線を流れる電流と前記第２のエミッタセンス配線を流れる電流の向きは逆方向であり、
前記第１の駆動信号伝送用配線の長さと前記第２の駆動信号伝送用配線の長さは等しく、
前記第１のエミッタセンス配線の長さと前記第２のエミッタセンス配線の長さは等しいことを特徴とする半導体装置。 A first power device disposed on a first insulating substrate;
A second power device disposed on a second insulating substrate;
A gate drive signal input terminal to which an external gate drive signal is input;
An emitter sense terminal connected to the outside;
A first drive signal transmission wiring made of metal that connects the gate of the first power device and the gate drive signal input terminal;
A second drive signal transmission wiring made of metal that connects the gate of the second power device and the gate drive signal input terminal;
A metal first emitter sense wiring connecting the emitter of the first power device and the emitter sense terminal;
A metal second emitter sense wiring connecting the emitter of the second power device and the emitter sense terminal;
The first drive signal transmission wiring and the first emitter sense wiring have a first overlapping region that overlaps without contacting each other,
The second drive signal transmission wiring and the second emitter sense wiring have a second overlapping region that overlaps without contacting each other,
In the first overlapping region, the direction of the current flowing through the first drive signal transmission line and the direction of the current flowing through the first emitter sense line are opposite to each other.
In the second overlapping region, the direction of the current flowing through the second drive signal transmission line and the direction of the current flowing through the second emitter sense line are opposite to each other.
The length of the first drive signal transmission line is equal to the length of the second drive signal transmission line,
The semiconductor device according to claim 1, wherein a length of the first emitter sense wiring is equal to a length of the second emitter sense wiring. 前記駆動信号伝送用配線は全体が前記重畳領域を形成することを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the drive signal transmission wiring forms the overlapping region as a whole. 前記重畳領域において、前記駆動信号伝送用配線と前記エミッタセンス配線との間に厚さが均一である絶縁体が配置され、
前記駆動信号伝送用配線と前記エミッタセンス配線はそれぞれ前記絶縁体と接することを特徴とする請求項１に記載の半導体装置。 In the overlapping region, an insulator having a uniform thickness is disposed between the drive signal transmission wiring and the emitter sense wiring,
2. The semiconductor device according to claim 1, wherein each of the drive signal transmission wiring and the emitter sense wiring is in contact with the insulator. 前記駆動信号伝送用配線と前記エミッタセンス配線は同一プリント基板に形成されることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the drive signal transmission wiring and the emitter sense wiring are formed on the same printed circuit board. 前記駆動信号伝送用配線および前記エミッタセンス配線、またはそのいずれかが複数の層を備えていることを特徴とする請求項５に記載の半導体装置。   The semiconductor device according to claim 5, wherein the drive signal transmission wiring and / or the emitter sense wiring each include a plurality of layers.
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