JP2010017452A - Processor for electronic endoscope and image processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To keep data rate constant after magnification changing process without providing a frame memory for changing the data rate. <P>SOLUTION: A frame memory 49 stores frame data which is input from an electronic endoscope 10 as still images in accordance with freeze signals. A CPU 45 outputs identical still images number of times corresponding to electronic zoom magnification from the frame memory 49 in response to electronic zoom operation signals. An image processing circuit 50 takes in still images when the still images are output from the frame memory 49 and performs image processing. A variable power circuit 54 performs variable power process in the number of output times according to the still images which are successively output several times from the frame memory 49 and creates partial data of images with variable power for each time of output. A memory 55 for still images stores the partial data created by the variable power circuit 54 in predetermined regions and makes one image with variable power. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic endoscope processor device and an image processing system having an electronic zoom function for electronically enlarging an image.

  In the medical field, medical diagnosis using an electronic endoscope apparatus is actively performed. An electronic endoscope apparatus includes an electronic endoscope (scope) having an insertion portion that is inserted into a body cavity, and a solid-state imaging device built in the electronic endoscope, in which the electronic endoscope is detachably connected. A processor device that receives an imaging signal, performs image processing, and displays an observation image on a monitor, and a light source device that generates light that illuminates the body cavity through a light guide in the electronic endoscope.

  In general, in such an electronic endoscope apparatus, an observation image is displayed as a moving image on a monitor, and a still image can be displayed by a freeze operation. Further, the electronic endoscope apparatus is provided with an electronic zoom function for partially enlarging the still image, so that the region of interest can be enlarged and displayed.

  The electronic zoom function is a function of cutting out a region (zoom region) having a size corresponding to the zoom magnification from an image picked up by a solid-state imaging device, and expanding the cut-out region to the size of one frame by scaling processing It is. For example, when an image for one frame is 640 × 480 pixels in size and the electronic zoom magnification is 2 times, a region of 320 × 240 pixels at an arbitrary position in the image is cut out, and the cut out region is The size is 640 × 480 pixels by the scaling process in the row direction and the column direction.

  The scaling process is a process for generating new pixel data by an interpolation process, and the ratio of the number of output pixel data to the number of input pixel data to the scaling circuit that performs this process varies according to the electronic zoom magnification. To do. For example, when the electronic zoom magnification is twice, the number of output pixel data is four times the number of input pixel data. Therefore, if the data rate of the pixel data input to the zoom circuit is constant, the data rate of the pixel data output from the zoom circuit changes according to the electronic zoom magnification. For example, when the electronic zoom magnification is 2 times, the number of output pixel data is 4 times the number of input pixel data, so the scaling circuit outputs at a data rate of 4 times.

  Specifically, the scaling circuit includes a horizontal scaling circuit that performs scaling in the row direction and a vertical scaling circuit that performs scaling in the column direction. FIG. 10A shows input pixel data (D1, D2, D3,...) And output pixel data (D1, D1) from the horizontal scaling circuit when the electronic zoom magnification is 2. H1, D2, H2, D3,. H1, H2,... Are interpolation data generated by interpolation processing based on input pixel data. As described above, since the horizontal scaling circuit generates interpolation data every time pixel data is input, the data rate of the pixel data after the interpolation processing is twice that at the time of input. By inputting the output pixel data from the horizontal scaling circuit to the vertical scaling circuit, the output pixel data from the vertical scaling circuit is further doubled. Therefore, when the electronic zoom magnification is 2, the data rate after the scaling process changes to 4 times before the scaling process.

As described above, when the data rate after the scaling process changes according to the electronic zoom magnification, the output data from the scaling circuit may not be received by the memory due to the processing speed of the memory. In order to solve such a problem, pixel data (frame data) for one frame output from the solid-state imaging device is temporarily written in the frame memory, and the frame data written in the frame memory is written according to the electronic zoom magnification. A technique is known in which a data rate after scaling processing is made constant regardless of the electronic zoom magnification by reading at a data rate lower than the current data rate and inputting it to the scaling circuit (see, for example, Patent Document 1). ).
JP 2004-64334 A (page 4-5)

  However, in the prior art as described above, in order to keep the data rate after scaling processing constant, it is necessary to provide a frame memory for changing the data rate before the scaling circuit, which increases power consumption and generates heat. There are problems such as increase, circuit scale expansion, device enlargement, and cost increase. In Patent Document 1, instead of a frame memory for changing a data rate, a register capable of writing pixel data for one row of frame data is provided in a preceding stage of a scaling circuit (resolution conversion unit), thereby Although it is described that the data rate of the processing is kept constant, the above-mentioned problem cannot be solved because the description about the scaling processing is insufficient.

  The present invention has been made in view of the above problems, and maintains a constant data rate after scaling processing by performing scaling processing in multiple steps without providing a frame memory for changing the data rate. An object of the present invention is to provide an electronic endoscope processor device and an image processing system.

  In order to achieve the above object, the processor device for an electronic endoscope of the present invention stores an image signal input from the electronic endoscope as a still image according to a freeze signal input from the electronic endoscope. Image storage means, control means for outputting the same still image from the image storage means more than the number of times corresponding to the electronic zoom magnification in response to an electronic zoom operation signal input from the electronic endoscope, and the electronic An image processing unit that captures an image signal input from an endoscope and performs image processing; and when a still image is output from the image storage unit, an image processing unit that captures the still image and performs image processing; and the image Based on each still image output from the storage means a plurality of times, scaling processing is performed for each of the output times, and scaling processing means for generating partial data of the scaled image for each output time; and the scaling Characterized by comprising a variable magnification image storage means to one of the scaled image by storing each partial data in a predetermined area generated by the management unit.

  The partial data is preferably divided in units of horizontal lines.

  Further, it is preferable that the image processing unit performs image processing on a still image taken from the image storage unit based on an image processing parameter different from that of an image signal input from the electronic endoscope.

  The image processing system according to the present invention includes an image storage unit that stores an image signal input from the imaging unit as a still image in response to a freeze signal input from the operation unit, and an electronic zoom input from the operation unit. In response to an operation signal, the same still image is output from the image storage unit a number of times corresponding to the electronic zoom magnification, and the image signal input from the imaging unit is captured and image processing is performed. When a still image is output from the image storage means, the output processing is divided based on the image processing means for capturing the still image and performing image processing, and each still image output a plurality of times from the image storage means. A scaling process means for performing a scaling process and generating partial data of the scaled image for each output time, and each partial data generated by the scaling process means for a predetermined area Characterized by comprising a variable magnification image storage means to one of the scaled image stored in.

  The partial data is preferably divided in units of horizontal lines.

  Further, it is preferable that the image processing unit performs image processing on the still image taken from the image storage unit based on an image processing parameter different from that of the image signal input from the imaging unit.

  The processor device for an electronic endoscope of the present invention performs a scaling process by dividing the number of outputs based on each still image output a plurality of times from the image processing means, and partial data of the scaled image at each output time Each is generated, and each generated partial data is stored in a predetermined area to form one scaled image. Therefore, the data rate after scaling processing is kept constant without providing a frame memory for changing the data rate. Can keep.

  In FIG. 1, the electronic endoscope apparatus 2 includes an electronic endoscope 10, a processor apparatus 11, a light source apparatus 12, and the like. The electronic endoscope 10 is connected to a flexible insertion portion 14 that is inserted into a body cavity, an operation portion 15 that is connected to a proximal end portion of the insertion portion 14, a processor device 11, and a light source device 12. And a universal cord 16.

  A distal end portion 17 having a built-in CCD type solid-state imaging device 40 (hereinafter simply referred to as a CCD 40) (see FIG. 3) is connected to the distal end of the insertion portion. Behind the distal end portion 17 is provided a bending portion 18 connecting a plurality of bending pieces. The bending portion 18 is bent in the vertical and horizontal directions when the angle knob 19 provided in the operation portion 15 is operated and the wire inserted in the insertion portion 14 is pushed and pulled. Thereby, the front-end | tip part 17 is orient | assigned to the desired direction in a body cavity.

  The base end of the universal cord 16 is connected to the connector 20. The connector 20 is of a composite type, and the light source device 12 is connected to the connector 20 in addition to the processor device 11.

  The processor device 11 receives an image signal output from the CCD 40 and performs various signal processing on the received image signal. The image signal processed by the processor device 11 is displayed as an observation image on a monitor 21 connected to the processor device 11 by a cable. The processor device 11 is electrically connected to the light source device 12 and comprehensively controls the operation of the electronic endoscope device 2.

  The operation unit 15 of the electronic endoscope 10 includes a forceps port 22 through which various treatment tools having an injection needle, a high-frequency knife and the like are inserted, and an air / water supply device (not shown) built in the light source device 12. ) Air supply / water supply button 23 for performing air supply / water supply using the air or cleaning water supplied from), a freeze button 24 for displaying a still image on the monitor 21, and a zoom button for partially enlarging the still image. 25 etc. are provided.

  On the front surface of the processor unit 11, an image enhancement execution button for performing enhancement processing such as contrast enhancement, contour enhancement, and color on a still image, a processing condition setting button for setting conditions for enhancement processing, and a light source device 12 A front panel 26 having a light amount adjustment button for adjusting the amount of illumination light is provided.

  In FIG. 2, an observation window 30, an illumination window 31, a forceps outlet 32, and an air / water supply nozzle 33 are provided on the end surface 17 a of the distal end portion 17. The observation window 30 is disposed at the center on one side of the tip portion 17. Two illumination windows 31 are arranged at symmetrical positions with respect to the observation window 30, and irradiate illumination light guided from the light source device 12 through the light guide 63 (see FIG. 3) to the site to be observed in the body cavity. The forceps outlet 32 is connected to a forceps channel (not shown) disposed in the insertion portion 14 and communicates with the forceps port 22 so that the distal end of the treatment tool inserted from the forceps port 22 is exposed. The air / water supply nozzle 33 injects cleaning water and air supplied from the air / water supply device toward the observation window 30 in accordance with the operation of the air / water supply button 23.

  In FIG. 3, a CCD 40 is built in the distal end portion 17 of the electronic endoscope 10, and the CCD 40 is disposed at an imaging position of an objective lens 41 provided to face the observation window 30. The CCD 40 is an interline transfer type CCD image sensor in which a plurality of light receiving elements (photodiodes) are two-dimensionally arranged. The CCD 40 employs a single-plate simultaneous method as a color imaging method, and a color filter composed of a plurality of color segments (for example, a primary color filter with a Bayer arrangement) is disposed on the light receiving surface.

  In addition to the CCD 40, the electronic endoscope 10 is provided with an analog signal processing circuit (AFE) 42, a timing generator (TG) 43, and a CPU 44. The AFE 42 includes a correlated double sampling (CDS) circuit, a programmable gain amplifier (PGA), and an A / D converter. The CDS circuit performs correlated double sampling processing on the image signal output from the CCD 40, and removes reset noise and amplifier noise generated in the CCD 40. The PGA amplifies the image signal from which noise has been removed by the CDS circuit at a predetermined amplification factor designated by the CPU 44. The A / D converter converts the image signal amplified by the PGA into a digital signal having a predetermined number of bits.

  The TG 43 generates a driving pulse (vertical / horizontal scanning pulse, reset pulse, etc.) for the CCD 40 and a synchronization pulse for the AFE 42 based on control from the CPU 44. The CCD 40 is driven by a sequential readout (progressive scan) system in response to a drive pulse input from the TG 43, sequentially reads out every row, and periodically outputs an image signal (frame data) for one frame. The frame data output from the AFE 42 is accompanied by a synchronization pulse and input to the processor unit 11.

  The freeze button 24 and the zoom button 25 described above are connected to the CPU 44. The CPU 44 inputs a freeze signal FR to the CPU 45 in the processor device 11 when the freeze button 24 is operated. Further, when the zoom button 25 is operated, the CPU 44 inputs an electronic zoom operation signal Z for designating an electronic zoom magnification to the CPU 45 in the processor device 11.

  In the processor device 11, an external terminal 46 to which frame data is input from the AFE 42 of the electronic endoscope 10 is connected to a first switch circuit 47 and a second switch circuit 48. The first switch circuit 47 is a switch element with two inputs and one output, and the external terminal 46 is connected to one input terminal, and the output terminal of the frame memory 49 is connected to the other input terminal. The output terminal of the first switch circuit 47 is connected to the input terminal of the image processing circuit 50.

  The second switch circuit 48 is a 1-input / 1-output on / off switch element, and is connected between the external terminal 46 and the frame memory 49. The frame memory 49 is a memory element that temporarily stores frame data input via the second switch circuit 48. The first switch circuit 47 selectively switches the input source of the frame data to the image processing circuit 50 to either the external terminal 46 or the frame memory 49.

  The second switch circuit 48 is turned on only for one frame period based on the control of the CPU 45, and causes the frame data input from the external terminal 46 to be input to the frame memory 49. The first switch circuit 47 switches the input source of frame data to the image processing circuit 50 based on the control of the CPU 45. In response to the input of the freeze signal FR from the electronic endoscope 10, the CPU 45 turns on the second switch circuit 48, inputs the frame data to the frame memory 49, and stores it as a still image. When the second switch circuit 48 is in the ON state, the input of the first switch circuit 47 is on the external terminal 46 side, and the frame data input from the external terminal 46 is the frame memory 49. At the same time, it is also input to the image processing circuit 50.

  In addition, after the freeze signal FR is input from the electronic endoscope 10, the CPU 45 switches the first switch circuit 47 to the frame memory 49 side in response to the input of the electronic zoom operation signal Z. The frame data is read out (output) continuously a plurality of times and input to the image processing circuit 50. Each frame data read continuously is used for a scaling process described later. Further, after the freeze signal FR is input from the electronic endoscope 10, the CPU 45 switches the first switch circuit 47 to the frame memory 49 side in response to the operation of the image enhancement execution button on the front panel 26. Frame data is read from the frame memory 49 and input to the image processing circuit 50.

  The image processing circuit 50 performs image processing such as color interpolation, white balance adjustment, gamma correction, and image enhancement on the input frame data, and is connected to a parameter register 51 that holds image processing parameters. ing. The image processing parameters can be rewritten by the CPU 45, and are used as moving image parameters during moving image processing and as still image parameters during still image processing. The image processing parameter is rewritten from a normal still image parameter to an image enhancement parameter when performing image enhancement in accordance with the operation of the image enhancement execution button described above. The contents of the image enhancement parameters (image enhancement conditions) are set by operating the processing condition setting button on the front panel 26. The image processing circuit 50 performs image processing based on the image processing parameters stored in the parameter register 51 on the input frame data.

  A third switch circuit 52 having one input and two outputs is connected to the output terminal of the image processing circuit 50. The frame data output from the image processing circuit 50 is input to the third switch circuit 52. A moving image memory 53 is connected to one of the output terminals of the third switch circuit 52, and a still image memory 55 is connected to the other via a scaling circuit 54. The third switch circuit 52 switches the output destination of the frame data from the image processing circuit 50 based on the control of the CPU 45. The CPU 45 treats the frame data output from the image processing circuit 50 as a still image (the frame data input to the image processing circuit 50 according to the freeze signal FR or the frame data read from the frame memory 49). In some cases, the output data of the third switch circuit 52 is set to the scaling circuit 54 side, and the frame data is input to the scaling circuit 54. In other cases, the CPU 45 treats the frame data output from the image processing circuit 50 as a moving image, and inputs the output destination of the third switch circuit 52 to the moving image memory 53 as the moving image memory 53 side.

  As will be described in detail later, the scaling circuit 54 is read from the frame memory 49 a plurality of times according to the electronic zoom magnification specified by the electronic zoom operation signal Z, and the first switch circuit 47, the image processing circuit 50, the third Based on each frame data input via the switch circuit 52, the scaling process is divided and generated to generate the scaled image data in which the central portion of the still image data is enlarged. The scaled image data is output from the scaler circuit 54 to the still image memory 55 at the same data rate as when input to the scaler circuit 54. Note that when the electronic zoom operation is not performed, the scaling circuit 54 outputs the input frame data as it is to the still image memory 55 as still image data without performing scaling processing.

  The display control circuit 56 displays the moving image data stored in the moving image memory 53, the still image data stored in the still image memory 55 (magnified image data at the time of electronic zoom), the screen according to the display form on the monitor 21. The mask data for masking the surroundings, character information such as date and patient information, etc. are mixed to generate a display image on the monitor 21. Further, the display control circuit 56 performs display using the parent screen mask 70 (see FIG. 4A) and the parent / child screen mask 71 (FIG. 4B) based on the freeze signal FR input via the CPU 45. Switch to display using (see).

  Specifically, before the freeze signal FR is input, the display control circuit 56 displays the moving image based on the moving image data in the moving image memory 53 using the parent screen mask 70 shown in FIG. Is performed in the main screen 72. When the freeze signal FR is input, a still image is displayed in the parent screen 72 based on the still image data in the still image memory 55 using the parent / child screen mask 71 shown in FIG. Based on the moving image data in the memory 53, the moving image is displayed in the sub-screen 73. When displaying the moving image on the child screen 73, the display control circuit 56 reduces the moving image data (decimation processing, pixel data averaging processing, etc.) according to the size of the child screen 73. Further, the display control circuit 56 performs the parent-child screen display of FIG. 4B in response to the input of the freeze signal FR, and then the predetermined time elapses or according to the operator's instruction, the display control circuit 56 of FIG. Return to the main screen display.

  The D / A converter 57 converts the display image generated by the display control circuit 56 into an analog signal and outputs it to the monitor 21. In this way, an observation image captured by the CCD 40 is displayed on the monitor 21.

  The light source device 12 includes a CPU 58, a light source 59, a light source driver 60, a diaphragm mechanism 61, a condenser lens 62, and the like. The CPU 58 communicates with the CPU 45 of the processor device 11 and controls the light source driver 60 and the diaphragm mechanism 61. The light source 59 includes a xenon lamp or a halogen lamp, and is driven and controlled by the light source driver 60. The diaphragm mechanism 61 is disposed on the light exit side of the light source 59 and increases or decreases the amount of light incident on the condenser lens 62. The condenser lens 62 condenses the light that has passed through the diaphragm mechanism 61 and guides it to the incident end of the light guide 63 of the electronic endoscope 10 connected to the light source device 12. The light guide 63 is inserted from the proximal end of the electronic endoscope 10 to the distal end portion 17, and the emission end is connected to each illumination window 31 described above.

  In FIG. 5, the zoom circuit 54 includes a first line buffer 80, a second line buffer 81, a read control circuit 82, a horizontal zoom circuit 83, a vertical zoom circuit 84, a write control circuit 85, and a write switch circuit. 86 and a read switch circuit 87. Frame data input from the image processing circuit 50 to the write switch circuit 86 via the third switch circuit 52 is input to the first line buffer 80 or the second line buffer 81 via the write switch circuit 86. The The write switch circuit 86 switches the output destination for each horizontal line, and switches the write destination to the first line buffer 80 or the second line buffer 81. The first and second line buffers 80 and 81 are composed of a FIFO memory or the like.

  As shown in FIG. 6, the frame data has a pixel size of, for example, 640 × 480, and the pixel data is scanned from the left to the right in order from the top as indicated by the arrows, and one row of pixel data (1 (Horizontal line data) is input to the first line buffer 80 or the second line buffer 81. In this case, as shown in FIG. 7A, one horizontal line data consists of pixel data of 640 pixels, and is input to the first line buffer 80 or the second line buffer 81 over one horizontal period. Is done.

  The zoom area shown in FIG. 6 is an area determined based on the electronic zoom magnification and a zoom position arbitrarily set in the frame data. When the electronic zoom magnification is M, the row direction and the column of the zoom area are shown. The number of pixels in the direction is 1 / M times the number of pixels in the row direction and the column direction of the frame data, respectively. When the zoom magnification is 2, the zoom area has a pixel size of 320 × 240. The zoom position can be arbitrarily set by changing the position of the horizontal line where the scaling process is started and the address positions of the first and second line buffers 80 and 81.

  The read switch circuit 87 selects a line buffer opposite to the line buffer selected by the write switch circuit 86 among the first and second line buffers 80 and 81. Specifically, when the write switch circuit 86 selects the first line buffer 80, the read switch circuit 87 selects the second line buffer 81. On the contrary, when the write switch circuit 86 selects the second line buffer 81, the read switch circuit 87 selects the first line buffer 80. In this way, the difference between the data rate of the image data input to the zoom circuit 54 and the read data rate of zoom area data in the line buffer in the zoom circuit 54 described later is absorbed. .

  The read control circuit 82 controls reading of zoom area data from the first line buffer 80 or the second line buffer 81. Specifically, the readout control circuit 82 changes the readout area and data rate of pixel data read from the first line buffer 80 or the second line buffer 81 in accordance with the electronic zoom magnification and the zoom area. It is. The read area is a range of memory addresses of the first line buffer 80 and the second line buffer 81 corresponding to the zoom area. The read control circuit 82 sets the data rate at the time of input to the first line buffer 80 or the second line buffer 81 to Ri and the data rate at the time of output from the first line buffer 80 or the second line buffer 81. If Ro and the electronic zoom magnification are M, control is performed so as to satisfy the relational expression of Ro = Ri / M.

  The zoom area data read from the first line buffer 80 or the second line buffer 81 by the read control circuit 82 is sequentially input to the horizontal scaling circuit 83 for each pixel data. For example, when the electronic zoom magnification is double, as shown in FIG. 7B, the zoom area is selected from one horizontal line data stored in the first line buffer 80 or the second line buffer 81. Corresponding data is read by the read control circuit 82 at a data rate that is ½ times that at the time of input.

  The horizontal scaling circuit 83 performs horizontal scaling processing on the zoom area data output from the first line buffer 80 or the second line buffer 81. Specifically, the horizontal scaling circuit 83 performs linear interpolation based on the pixel data, and generates interpolation data corresponding to the electronic zoom magnification specified by the CPU 45, thereby generating pixel data for one horizontal line. Is generated.

  In FIG. 11, a horizontal scaling circuit 83 is a two-point interpolation scaling circuit, and includes a horizontal scaling memory 90, a first horizontal scaling weighting circuit 91, a second horizontal scaling weighting circuit 92, a horizontal scaling circuit. A double adder circuit 93 is used.

  The flow of signals in the horizontal scaling circuit 83 when the electronic zoom magnification is 2 is shown in order in FIGS. In FIG. 12A, when pixel data D 1 is input to the horizontal scaling circuit 83, the pixel data D 1 is stored in the horizontal scaling memory 90. Next, in FIG. 12B, when the pixel data D2 is input to the horizontal scaling circuit 83, the pixel data D2 is input to the second horizontal scaling weighting circuit 92. At this time, in the second horizontal scaling weighting circuit 92, the weighting is set to “0” by a correction coefficient α described later, and the pixel data D2 is not input to the horizontal scaling addition circuit 93. At the same time, the pixel data D1 stored in the horizontal scaling memory 90 is read out and input to the first horizontal scaling weighting circuit 91. At this time, in the first horizontal scaling weighting circuit 91, the weighting is set to “1” by the correction coefficient α and input to the horizontal scaling addition circuit 93. The horizontal scaling addition circuit 93 outputs the pixel data D1 input via the first horizontal scaling weighting circuit 91.

  Next, in FIG. 12C, the value of the correction coefficient α is changed. The pixel data D1 is read from the horizontal scaling memory 90, weighted to “0.5” by the first horizontal scaling weighting circuit 91, and input to the horizontal scaling addition circuit 93. At this time, the pixel data D <b> 2 is input to the horizontal scaling addition circuit 93 with a weighting of “0.5” by the second horizontal scaling weighting circuit 92. The horizontal scaling addition circuit 93 adds the weighted pixel data D1 and D2 and outputs the interpolation data H1.

  Next, in FIG. 13A, the value of the correction coefficient α is changed to the same value as in FIG. The pixel data D2 is stored in the horizontal scaling memory 90, and the pixel data D3 is input to the horizontal scaling circuit 83. The pixel data D2 is input from the horizontal scaling memory 90 through the first horizontal scaling weighting circuit 91 to the horizontal scaling addition circuit 93 with a weight of “1”. At this time, the pixel data D3 is weighted to “0” by the second horizontal scaling weighting circuit 92 and is not input to the horizontal scaling addition circuit 93. The horizontal scaling addition circuit 93 outputs the pixel data D2 input via the first horizontal scaling weighting circuit 91.

  Next, in FIG. 13B, the value of the correction coefficient α is changed to the same value as in FIG. The pixel data D <b> 2 is input to the horizontal scaling addition circuit 93 with a weighting of “0.5” by the first horizontal scaling weighting circuit 91. The pixel data D3 is input to the horizontal scaling addition circuit 93 with a weighting of “0.5” by the second horizontal scaling weighting circuit 92. The horizontal scaling addition circuit 93 adds the weighted pixel data D2 and D3 and outputs the interpolation data H2. Thus, when the magnification of the electronic zoom is double, the relationship between the pixel data input to the horizontal scaling circuit 83 and the output of the horizontal scaling circuit 83 is as shown in FIG. .

  The flow of signals in the horizontal scaling circuit 83 when the magnification of the electronic zoom is 3 is shown in order in FIGS. The signal flow in FIGS. 14A to 14C is the same as the signal flow in FIGS. 12A to 12C, and thus description thereof is omitted. After the interpolation process shown in FIG. 14C, the interpolation process shown in FIG. 15A is performed. The case of FIG. 14C and the case of FIG. 15A differ only in the weighting to the signals performed by the first horizontal scaling weighting circuit 91 and the second horizontal scaling weighting circuit 92, In the case of FIG. 14C, the interpolation data H1a is output from the horizontal scaling addition circuit 93, and in the case of FIG. 15A, the interpolation data H1b is output from the horizontal scaling addition circuit 93. . When the electronic zoom is 3 ×, the relationship between the pixel data input to the horizontal scaling circuit 83 and the output of the horizontal scaling circuit 83 is as shown in FIG.

In the case of the two-point interpolation method, if the pixel data is D _i (= D1, D2,...), The data Dh output from the horizontal scaling addition circuit 93 is expressed by the following equation.
Dh = α × D _i + (1−α) × D _{i + 1} α is an interpolation coefficient, where the weighting coefficient by the first horizontal scaling weighting circuit 91 is “α”, and the weighting by the second horizontal scaling weighting circuit 92 is The coefficient is “1-α”. The interpolation coefficient α is designated by the CPU 45. The CPU 45 changes the interpolation coefficient α according to the magnification of the electronic zoom and the pixel data position after the scaling process. For example, when the electronic zoom magnification is 2 as described above, the CPU 45 sets α = 1 during pixel processing of odd rows and α = 0.5 during pixel processing of even rows. In the case of FIGS. 12 and 13 in which the electronic zoom magnification is 2 times, each data Dh output from the horizontal scaling addition circuit 93 is as follows. Since FIGS. 12C and 13B show the case of even-numbered pixel processing, α = 0.5, and data Dh is
Dh = 0.5 × D1 + 0.5 × D2 = H1
Dh = 0.5 × D2 + 0.5 × D3 = H2
It becomes. On the other hand, FIGS. 12 (B) and 13 (A) show the case of pixel processing on odd rows, and the data Dh is respectively
Dh = 1 × D1 + 0 × D2 = D1
Dh = 1 × D3 + 0 × D4 = D3
It becomes.

When the electronic zoom magnification is 3, the CPU 45 sets α = 1 during pixel data processing, α = 0.66 during the first interpolation processing, and α = 0.33 during the second interpolation processing. To do. In the case of FIGS. 14 and 15 in which the electronic zoom magnification is 3 times, each data Dh output from the horizontal scaling addition circuit 93 is as follows. In FIG. 14C, α = 0.66 because it is during the first interpolation process,
Dh = 0.66 × D1 + 0.34 × D2 = H1a
It becomes. In FIG. 15A, α = 0.33 because it is during the second interpolation process.
Dh = 0.33 × D1 + 0.67 × D2 = H1b
It becomes. Further, FIG. 14B and FIG. 15B are α = 1 because the pixel data is being processed,
Dh = 1 × D1 + 0 × D2 = D1
Dh = 1 × D2 + 0 × D3 = D2
It becomes.

  The horizontal scaling circuit 83 configured as described above sequentially generates interpolation data every time pixel data in the zoom area is input, and outputs pixel data that is electronic zoom magnification times (M times) the number of input pixel data. Since data is output, the data rate at the time of output is M times that at the time of input. For example, when the electronic zoom magnification is double, as shown in FIG. 7C, the data is output from the horizontal scaling circuit 83 at a data rate twice that at the time of input. Therefore, the data rate of the output data from the horizontal scaling circuit 83 is the same as the data rate of the input data to the first line buffer 80 or the second line buffer 81.

  One horizontal line data after horizontal scaling output from the horizontal scaling circuit 83 is input to the vertical scaling circuit 84 for each pixel data. Similarly to the horizontal scaling circuit 83, the vertical scaling circuit 84 is, for example, a two-point interpolation type scaling circuit, and as shown in FIG. 16, a vertical scaling line memory 96, a first vertical scaling weighting circuit, and the like. 97, a second vertical scaling weighting circuit 98, and a vertical scaling addition circuit 99. The vertical scaling line memory 96 is composed of a FIFO memory that stores image data for one row.

  The flow of signals in the vertical scaling circuit 84 when the electronic zoom magnification is 2 is shown in order in FIGS. In FIG. 17A, when horizontal line data L 1 after horizontal scaling is input to the vertical scaling circuit 84, the horizontal line data L 1 is stored in the vertical scaling line memory 96. Next, in FIG. 17B, when the horizontal line data L 2 is input to the vertical scaling circuit 84, the horizontal line data L 2 is input to the second vertical scaling weighting circuit 98. At this time, in the second vertical scaling weighting circuit 98, the weighting is set to “0” by a correction coefficient β described later, and the horizontal line data L2 is not input to the vertical scaling addition circuit 99. At the same time, the horizontal line data L 1 stored in the vertical scaling line memory 96 is read and input to the first vertical scaling weighting circuit 97. At this time, in the first vertical scaling weighting circuit 97, the weighting is set to “1” by the correction coefficient β and is input to the vertical scaling addition circuit 99. The vertical scaling addition circuit 99 outputs the horizontal line data L1 input via the first vertical scaling weighting circuit 97.

  Next, in FIG. 17C, the value of the correction coefficient β is changed. The horizontal line data L1 is read from the vertical scaling line memory 96, weighted to “0.5” by the first vertical scaling weighting circuit 97, and input to the vertical scaling addition circuit 99. At this time, the horizontal line data L2 is input to the vertical scaling addition circuit 99 with a weighting of “0.5” by the second vertical scaling weighting circuit 98. The vertical scaling addition circuit 99 adds weighted horizontal line data L1 and L2, and outputs interpolation data (L1, L2).

  Next, in FIG. 18, the value of the correction coefficient β is changed to the same value as in FIG. The horizontal line data L2 is stored in the vertical scaling line memory 96, and the horizontal line data L3 is input to the vertical scaling circuit 84. The processing in the case of FIG. 18 is the same as that in the case of FIG.

  The operation of the weighting circuits of the first vertical scaling weighting circuit 97 and the second vertical scaling weighting circuit 98 in the vertical scaling circuit 84 is basically the first horizontal scaling in the horizontal scaling circuit 83. This is equivalent to the weighting circuit 91 and the second horizontal scaling weighting circuit 92. However, although the vertical scaling circuit 84 creates the interpolation data of the line data, it does not change the data rate (processing for increasing the number of data) unlike the horizontal scaling circuit 83. The process of increasing the number of lines is performed by writing to the still image memory 55 by the write control circuit 85 in a plurality of times.

Similarly to the horizontal scaling circuit 83, in the case of the two-point interpolation method, if the horizontal line data is L _i (= L1, L2,...), The horizontal line data Lh output from the vertical scaling addition circuit 99 is It is expressed by the following formula.
Lh = β × L _i + (1−β) × L _{i + 1} β is an interpolation coefficient, where the weighting coefficient by the first vertical scaling weighting circuit 97 is “β” and the weighting by the second vertical scaling weighting circuit 98 The coefficient is “1-β”. The interpolation coefficient β is designated by the CPU 45. The CPU 45 changes the interpolation coefficient β according to the magnification of the electronic zoom and the number of times frame data is read from the frame memory 49. For example, when the electronic zoom magnification is double as described above, the CPU 45 reads β = 1 when the number of times frame data is read from the frame memory 49 is the first time, and the number of times frame data is read is the second time. In the inter-process, β = 0.5. In the case of FIGS. 17 and 18 where the electronic zoom magnification is 2 times, each data Lh output from the vertical scaling addition circuit 99 is as follows. In FIGS. 17B and 18, β = 1 because the number of times frame data is read is during the first processing, and the data Lh is
Lh = 1 × L1 + 0 × L2 = L1
Lh = 1 × L2 + 0 × L3 = L2
It becomes. On the other hand, in FIG. 17C, β = 0.5 because the number of times frame data is read is the second time, and the data Lh is Lh = 0.5 × L1 + 0.5 × L2 = interpolated data ( L1, L2)
It becomes.

When the electronic zoom magnification is 3 times, the CPU 45 reads β = 1 when the frame data is read from the frame memory 49 during the first process, and when the frame data is read during the second time. β = 0.66, and β = 0.33 during processing during the third frame data read. The output of the vertical scaling addition circuit 99 when the number of times frame data is read is the first time.
Lh = 1 × L1 + 0 × L2 = L1
Lh = 1 × L2 + 0 × L3 = L2
Lh = 1 × L3 + 0 × L4 = L3
It becomes. The output of the vertical scaling addition circuit 99 when the number of times frame data is read is the second time processing is
Lh = 0.66 × L1 + 0.34 × L2 = interpolation data (L1, L2)
Lh = 0.66 × L2 + 0.34 × L3 = interpolation data (L2, L3)
Lh = 0.66 × L3 + 0.34 × L4 = interpolation data (L3, L4)
It becomes. The output of the vertical scaling addition circuit 99 when the number of times frame data is read is the third time,
Lh = 0.33 × L1 + 0.67 × L2 = interpolation data (L1, L2)
Lh = 0.33 × L2 + 0.67 × L3 = interpolation data (L2, L3)
Lh = 0.33 × L3 + 0.67 × L4 = interpolation data (L3, L4)
It becomes.

  The number of times frame data is read from the frame memory 49 during the scaling process is changed according to the electronic zoom magnification, and is at least three when the electronic zoom magnification is three times and when the electronic zoom magnification is four times. At least 4 times.

  The write control circuit 85 divides the storage area of the still image memory 55 into a number of areas corresponding to the number of reading of the frame data based on the control of the CPU 45, and the horizontal line data output from the vertical scaling circuit 84. Are written in a predetermined area corresponding to the number of times of reading. For example, when the electronic zoom magnification is two times, the write control circuit 85 uses the storage area 55a of the still image memory 55 as the odd line area 55b and the even line area 55c, as shown in FIGS. Divided into two areas, horizontal line data output from the vertical scaling circuit 84 is written to the odd line area 55b in response to the first frame data read, and the second frame data is read out. The horizontal line data output from the vertical scaling circuit 84 is written in the even line area 55c. The storage area 55a is an area for one frame, of which an odd line corresponds to the odd line area 55b and an even line corresponds to the even line area 55c. Through the above processing, the pixel data after the scaling process is written in the storage area 55a at the same data rate as when input to the scaling circuit 54.

  When the electronic zoom magnification is 3, the frame data is read from the frame memory 49 three times or more. As shown in FIG. 20, the write control circuit 85 writes the output of the vertical scaling circuit 84 when reading from the frame memory 49 is the first time to the first processing line 55d. Next, the output of the vertical scaling circuit 84 when the reading from the frame memory 49 is the second time is written to the second processing line 55e. Then, the output of the vertical scaling circuit 84 when the reading from the frame memory 49 is the third time is written to the third processing line 55f.

  Next, the operation of the electronic endoscope apparatus 2 configured as described above will be described with reference to the timing chart shown in FIG. When observing the inside of a body cavity using the electronic endoscope device 2, the electronic endoscope 10, the processor device 11, the light source device 12, and the monitor 21 are turned on to insert the electronic endoscope 10. 14 is inserted into the body cavity, and the observation image inside the body cavity imaged by the CCD 40 is observed on the monitor 21 while illuminating the body cavity with the illumination light from the light source device 12. At this time, the CCD 40 repeats the imaging operation every frame period and periodically outputs the frame data.

  The frame data output from the CCD 40 is input from the external terminal 46 to the processor device 11 via the AFE 42. The frame data input from the external terminal 46 is input to the image processing circuit 50 via the first switch circuit 47 (first and second frame periods in FIG. 9). The frame data input to the image processing circuit 50 is subjected to image processing and written to the moving image memory 53 via the third switch circuit 52. At this time, the monitor 21 displays a moving image on the parent screen 72 using the parent screen mask 70.

  When the freeze button 24 is operated and the freeze signal FR is input to the CPU 45 (second frame period in FIG. 9), the second switch circuit 48 is turned on, and the frame data input from the external terminal 46 is received. It is stored as a still image in the frame memory 49 (third frame period in FIG. 9). At this time, the frame data stored in the frame memory 49 is also input to the image processing circuit 50 in parallel. After image processing is performed, the frame data is input to the scaling circuit 54 via the third switch circuit 52. . In the third frame period, the scaling circuit 54 does not perform a scaling operation, and frame data with an electronic zoom magnification of 1 is stored in the still image memory 55. On the monitor 21, a parent / child screen mask 71 is used, and a still image is displayed on the parent screen 72 and a moving image is displayed on the child screen 73.

  When the zoom button 25 is operated in this state and the electronic zoom operation signal Z is input to the CPU 45 (the 11th frame period in FIG. 9), the input destination of the first switch circuit 47 is switched to the frame memory 49 side. The frame data stored in the frame memory 49 is read out a number of times corresponding to the electronic zoom magnification, and is input to the image processing circuit 50 (the 12th and 13th frame periods in FIG. 9). FIG. 9 exemplifies a case where the electronic zoom magnification is 2 ×. In this case, the frame data (frame data in the third frame period) stored in the frame memory 49 is read at least twice continuously. . At this time, the frame data input from the external terminal 46 is not input to the image processing circuit 50, and so-called cycle stealing is performed by the frame data read from the frame memory 49. Further, at the time of cycle stealing, an identification flag may be attached to the image in advance in order to facilitate identification of the moving image and the still image.

  The frame data input to the image processing circuit 50 by cycle steal is input to the scaling circuit 54 via the third switch circuit 52 after image processing is performed. In the zoom circuit 54, first, frame data is alternately input to the first line buffer 80 and the second line buffer 81 one horizontal line at a time and stored in the first line buffer 80 or the second line buffer 81. The zoom area data in the one horizontal line data is read by the read control circuit 82 after changing the data rate to 1/2. The zoom area data read at the data rate of 1/2 is sequentially input to the horizontal scaling circuit 83. In the horizontal scaling circuit 83, the input zoom area data is expanded to double the data amount by interpolation processing, and as a result, pixel data for one horizontal line is generated.

  One horizontal line data after horizontal scaling output from the horizontal scaling circuit 83 is input to the vertical scaling circuit 84. In the vertical scaling circuit 84, there is a vertical scaling line memory 96, which stores the input horizontal line data after horizontal scaling. After one horizontal line data is stored in the vertical scaling line memory 96, the next one horizontal line data horizontally scaled by the horizontal scaling circuit 83 is input to the vertical scaling circuit 84. The data stored in the vertical scaling line memory 96 is input to the vertical scaling addition circuit 99 via the first vertical scaling weighting circuit 97. On the other hand, one horizontal line data after horizontal scaling output from the horizontal scaling circuit 83 is input to the vertical scaling addition circuit 99 via the second vertical scaling weighting circuit 98, and the vertical scaling addition circuit 99 99 is added.

  The vertical scaling circuit 84 calculates one interpolation data from the input pixel data of two horizontal lines by the above-described relational expression so as not to change the data rate. In the twelfth frame period, the interpolation coefficient β is set to 1 and interpolation processing is performed. The output data from the vertical scaling circuit 84 is output by the write control circuit 85 to the odd lines in the storage area 55a of the still image memory 55. It is written in the area 55b. In this case, since β = 1, the interpolation processing is not substantially performed, and the input data to the vertical scaling circuit 84 is written as it is in the odd line area 55b. In the following 13th frame period, the interpolation coefficient β is set to 0.5 and interpolation processing is performed, and the output data from the vertical scaling circuit 84 is written to the even line area 55c in the storage area 55a by the write control circuit 85. Written. In this case, since β = 0.5, interpolation data between pixel data adjacent in the column direction is generated and written into the even line region 55c.

  As described above, the vertical scaling process is performed in two steps of the twelfth and thirteenth frame periods based on the same frame data, and the partial data of the scaled image generated in each frame period is a still image. The data is written in the odd line area 55b and the even line area 55c of the memory 55, respectively. The still image memory 55 stores a single scaled image obtained by combining the partial data. After the 14th frame period, the scaled image is displayed as a still image on the main screen 72.

  Thereafter, when the image enhancement execution button on the front panel 26 is operated, the frame data stored in the frame memory 49 is read again and input to the image processing circuit 50 via the first switch circuit 47. . At this time, the image processing parameters in the parameter register 51 are rewritten to image enhancement parameters, and the image processing circuit 50 performs image enhancement. Similarly, frame data is read from the frame memory 49 a plurality of times, and after image enhancement is performed by the image processing circuit 50, the frame data is input to the scaling circuit 54 via the third switch circuit 52. The scaling circuit 54 performs the above scaling process and stores the scaled image subjected to image enhancement in the still image memory 55. Then, instead of the scaled image, the scaled image subjected to image enhancement is displayed as a still image on the main screen 72. Of course, it is also possible to operate the image enhancement button before performing the zoom operation. If the image enhancement button is operated before the zoom operation, the frame data subjected to the image enhancement is scaled. Without being stored in the still image memory 55.

  The case where the electronic zoom magnification is 2 has been described above as an example, but it is also possible to set the electronic zoom magnification to another magnification. When the electronic zoom magnification is N times (N: integer), the same frame data (still image) is output from the frame memory 49 at least N times, and the scaling circuit 54 outputs the number of times (N times). The scaling process is performed separately, and partial data of the scaled image is generated every output time. The storage area 55a of the still picture memory 55 is divided into N areas (in the above example, the odd line area 55b and the even line area 55c) in units of horizontal lines, and the partial data is written in each area. Thus, one zoomed image is synthesized.

  Next, another embodiment of the present invention is shown in FIG. In FIG. 21, the zoom circuit 100 of this embodiment includes a horizontal output switch circuit 101, a third line buffer 102, a fourth line buffer 103, and a vertical input switch between a horizontal zoom circuit 83 and a vertical zoom circuit 84. The only difference from the zoom circuit 54 of the above embodiment is that the circuit 104 is provided.

  When frame data is input to the scaling circuit 100, one horizontal line data is alternately input to the first line buffer 80 or the second line buffer 81 by the write switch circuit 86. The read switch circuit 87 selects a line buffer opposite to the line buffer selected by the write switch circuit 86, and the 1 horizontal line data stored in the first line buffer 80 or the second line buffer 81 is selected. Among them, the zoom area data is read by the read control circuit 82. At this time, reading is performed from the line buffer at the same data rate as the data rate at the time of input, and the read one horizontal line data is input to the horizontal scaling circuit 83. When the electronic zoom magnification is 2, the amount of data output from the horizontal scaling circuit 83 is twice the amount of data input to the horizontal scaling circuit 83, and after horizontal scaling during the zoom area readout period. Data is output, the data rate is doubled.

  The horizontal output switch circuit 101 alternately selects the third line buffer 102 or the fourth line buffer 103 for each horizontal line, and outputs one horizontal line data output from the horizontal scaling circuit 83 to the third line buffer. 102 or the fourth line buffer 103. The vertical input switch circuit 104 selects a line buffer opposite to the line buffer selected by the horizontal output switch circuit 100. The data stored in the third line buffer 102 or the fourth line buffer 103 is read out at the same data rate as the image data input to the scaling circuit 100 and input to the vertical scaling circuit 84. In this way, the difference between the data rates is absorbed by separating the write and read line buffers. The other operations are the same as those described with reference to FIG.

  As described above, the processor device of the present invention uses the frame memory 49 provided in the previous stage of the image processing circuit 50 for reprocessing still image data, and stores it in the frame memory 49 according to the electronic zoom magnification. The same frame data is input to the scaling circuit 54 (or the scaling circuit 100) a plurality of times, and the scaling process is performed according to the input number of times, so that the pixel data to be output to the still image memory 55 The data rate is constant regardless of the electronic zoom magnification. For this reason, unlike the prior art, it is not necessary to provide a frame memory for changing the data rate in front of the scaling circuit 54 (or the scaling circuit 100), reducing power consumption, reducing heat generation, preventing circuit scale expansion, The size of the apparatus can be reduced and the cost can be reduced.

  In the present invention, since all still images are always processed by the image processing circuit 50 and then input to the scaling circuits 54 and 100, a low-pass filter having a large kernel size is used for the image processing circuit 50. Therefore, even if the electronic zoom magnification is changed, the image quality is not affected.

  In the above embodiment, the first line buffer 80 and the second line buffer 81 are provided before the horizontal scaling circuit 83, and the data rate is changed by the read control circuit 82. However, the first line buffer 80, the second line buffer 81, and the read control circuit 82 are not provided, and the magnification change circuit 54 (from the image processing circuit 50 through the third switch circuit 52 is provided. Alternatively, the frame data input to the scaling circuit 100) may be directly input to the horizontal scaling circuit 83 for each pixel data. In this case, similarly to the vertical scaling circuit 84, the horizontal scaling circuit 83 also needs to perform scaling processing divided into a plurality of times. For example, when the electronic zoom magnification is 2, it is necessary to input the same frame data twice to each of the horizontal scaling circuit 83 and the vertical scaling circuit 84, and a total of 4 from the frame memory 49. Reading more than once is required.

  In the above embodiment, since all still images are always processed by the image processing circuit 50 and then input to the scaling circuit 54 (or the scaling circuit 100), the scaling circuit 54 (or the scaling circuit) is input. It is also possible to obtain images with different electronic zoom magnifications by using a plurality of magnification circuits 100).

  In the above embodiment, the write control circuit 85 divides the storage area 55a of the still image memory 55 in units of horizontal lines according to the electronic zoom magnification. However, the present invention is not limited to this. The storage area 55a may be divided so that the horizontal line is further divided.

  Further, in the above embodiment, the electronic zoom magnification is an integer for simplicity of explanation, but the present invention can also be applied when the electronic zoom magnification is not an integer. When the electronic zoom magnification is less than 1, the number of times of reading from the frame memory 49 is one. When the electronic zoom magnification is not less than 1 and less than 2, the number of times of reading from the frame memory 49 is 2. When the electronic zoom magnification is 2 times or more and less than 3 times, the number of times of reading from the frame memory 49 is three. As described above, by changing the number of times of reading from the frame memory 49, processing with an arbitrary zoom magnification is possible.

  In the above embodiment, as shown in FIG. 6, the zoom area is set at the center of the screen. However, the present invention is not limited to this, and as shown in FIG. It may be set at the bottom right of the screen. The horizontal scaling process in this case is as shown in FIG. The zoom position can be arbitrarily set by changing the position of the horizontal line where the scaling process is started and the address positions of the first and second line buffers 80 and 81.

  In the above embodiment, an example in which the horizontal scaling process and the vertical scaling process are performed by the two-point interpolation method is shown, but the present invention is not limited to this, and the horizontal scaling process is performed by the multipoint interpolation method. Alternatively, the vertical scaling process may be performed.

  In the above embodiment, an example in which the CCD solid-state imaging device 40 is used as the imaging unit is shown. However, the present invention is not limited to this, and a CMOS solid-state imaging device or the like is used as the imaging unit. May be.

  Furthermore, in the above embodiment, the present invention has been described by taking a medical endoscope apparatus as an example. However, the present invention is not limited to this, and an industrial endoscope apparatus, a digital still camera, and a video camera are described. The present invention is also applicable to systems, in-vehicle video cameras, surveillance cameras, and mobile phones with camera functions.

It is an external view which shows an electronic endoscope apparatus. It is a figure which shows the end surface of the front-end | tip part of an electronic endoscope. It is a figure which shows the structure of an electronic endoscope apparatus. It is a figure which shows the display mask to a monitor, (A) shows a parent screen mask and (B) shows a parent-child screen mask. It is a figure which shows the structure of a zoom circuit. It is a figure which shows an example of frame data and a zoom area | region. It is a figure explaining a horizontal scaling process, (A) is 1 horizontal line data input into a 1st line buffer, (B) is a zoom area | region output from a part in 1st line buffer Data, (C), shows one horizontal line data after horizontal scaling. It is a figure which shows the odd line area and the even line area which divided the storage area of the memory for still images. It is a timing chart explaining an effect | action of an electronic endoscope apparatus. It is a figure explaining the interpolation process by a horizontal scaling circuit. It is a figure which shows the structure of a horizontal scaling circuit. FIG. 5 is a diagram (part 1) illustrating a signal flow of a horizontal scaling circuit when an electronic zoom magnification is 2 times. FIG. 10 is a diagram (part 2) illustrating a signal flow of the horizontal scaling circuit when the electronic zoom magnification is 2 times. FIG. 5 is a diagram (part 1) illustrating a signal flow of a horizontal scaling circuit when the electronic zoom magnification is 3 times. FIG. 11 is a diagram (part 2) illustrating a signal flow of the horizontal scaling circuit when the electronic zoom magnification is 3 times. It is a figure which shows the structure of a vertical scaling circuit. FIG. 6 is a diagram (part 1) illustrating a signal flow of the vertical scaling circuit when the electronic zoom magnification is 2 times. FIG. 11 is a diagram (part 2) illustrating a signal flow of the vertical scaling circuit when the electronic zoom magnification is 2 times. It is a figure which shows the memory area of the scaling process and still picture memory in case an electronic zoom magnification is 2 times. It is a figure which shows the division of the storage area of the memory for still images in case an electronic zoom magnification is 3 times. It is a figure which shows the structure of the magnification changing circuit in another embodiment of this invention. It is a figure which shows the example which set the zoom area | region to the lower right of the screen. It is a figure explaining the horizontal scaling process in case a zoom area | region is set to the lower right of a screen, (A) is 1 horizontal line data input into a 1st line buffer, (B) is 1st horizontal line data. Zoom area data output from a part of the line buffer, (C), shows one horizontal line data after horizontal scaling.

Explanation of symbols

2 Electronic Endoscope 10 Electronic Endoscope 11 Processor Unit 24 Freeze Button 25 Zoom Button 40 CCD Type Solid-State Image Sensor (Imaging Means)
45 CPU (control means)
46 External terminal 47 First switch circuit 48 Second switch circuit 49 Frame memory (image storage means)
50 Image processing circuit (image processing means)
51 Parameter register 52 Third switch circuit 53 Memory for moving picture 54 Zoom circuit (magnification processing means)
55 Still image memory (magnified image storage means)
55a Storage area 55b Odd line area 55c Even line area 80 First line buffer 81 Second line buffer 82 Read control circuit 83 Horizontal zoom circuit 84 Vertical zoom circuit 85 Write control circuit 86 Write switch circuit 87 Read switch circuit 90 Horizontal scaling memory 91 First horizontal scaling weighting circuit 92 Second horizontal scaling weighting circuit 93 Horizontal scaling addition circuit 96 Vertical scaling line memory 97 First vertical scaling weighting circuit 98 Second vertical scaling Weighting circuit 99 Vertical scaling addition circuit 100 Scaling circuit (magnification processing means)
101 horizontal output switch circuit 102 third line buffer 103 fourth line buffer 104 vertical input switch circuit

Claims (6)

Image storage means for storing an image signal input from the electronic endoscope as a still image in response to a freeze signal input from the electronic endoscope;
In response to an electronic zoom operation signal input from the electronic endoscope, a control unit that outputs the same still image from the image storage unit a number of times corresponding to the electronic zoom magnification,
An image processing unit that captures an image signal input from the electronic endoscope and performs image processing; and when a still image is output from the image storage unit, an image processing unit that captures the still image and performs image processing;
Based on each still image that is output a plurality of times from the image storage means, performing a scaling process by dividing the number of outputs, and a scaling process means for generating partial data of the scaled image for each output time;
Magnified image storage means for storing each partial data generated by the magnifying processing means in a predetermined area and making it one magnifying image;
A processor device for an electronic endoscope, comprising:   The processor device for an electronic endoscope according to claim 1, wherein the partial data is divided in units of horizontal lines.   The image processing unit performs image processing on a still image captured from the image storage unit based on an image processing parameter different from that of an image signal input from the electronic endoscope. The processor apparatus for electronic endoscopes as described in 1 or 2. Image storage means for storing an image signal input from the imaging means as a still image in response to a freeze signal input from the operation unit;
Control means for outputting the same still image from the image storage means more than the number of times according to the electronic zoom magnification in response to the electronic zoom operation signal input from the operation unit;
An image processing unit that captures an image signal input from the imaging unit and performs image processing; and when a still image is output from the image storage unit, an image processing unit that captures the still image and performs image processing;
Based on each still image that is output a plurality of times from the image storage means, performing a scaling process by dividing the number of outputs, and a scaling process means for generating partial data of the scaled image for each output time;
Magnified image storage means for storing each partial data generated by the magnifying processing means in a predetermined area and making it one magnifying image;
An image processing system comprising:   The image processing system according to claim 4, wherein the partial data is divided in units of horizontal lines.   The image processing means performs image processing on a still image captured from the image storage means based on an image processing parameter different from that of an image signal input from the imaging means. 5. The image processing system according to 5.

Images