JP2010097050A - Panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve unevenness in luminance. <P>SOLUTION: In a flat self-luminous EL panel using an organic EL device, a mirroring inversion layout where the layout of a wiring pattern is reversed with respect to pixels adjacent to each other in a column direction is introduced as the wiring pattern layout of pixels 201. By providing an auxiliary capacitor 211 in a pixel 201R having a driver transistor 32R whose source (s) is irradiated earlier with laser on laser annealing, an increase ratio of the gate potential Vg to the source potential Vs of the driver transistor becomes different between the pixel 201R having the driver transistor whose source (s) is irradiated earlier with the laser and the pixel 201L having the driver transistor whose drain (s) is irradiated earlier with the laser. The present invention is applicable to an EL panel, for example. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a panel having a mirror inversion arrangement in which wiring patterns of pixel circuits arranged in a matrix are inverted between pixel circuits adjacent in the row direction, and in particular, can improve luminance unevenness. Regarding panels.

  In recent years, development of a planar self-luminous panel (EL panel) using an organic EL (Electro Luminescent) device as a light emitting element has become active. An organic EL device is a device having a diode characteristic and utilizing a phenomenon of emitting light when an electric field is applied to an organic thin film. Since the organic EL device is driven at an applied voltage of 10 V or less, it has low power consumption. In addition, since the organic EL device is a self-luminous element that emits light, it does not require an illumination member and can be easily reduced in weight and thickness. Furthermore, since the response speed of the organic EL device is as high as several μs, an afterimage does not occur when displaying a moving image.

  Among planar self-luminous panels using organic EL devices as pixels, active matrix panels in which thin film transistors are integrated and formed as driving elements are being actively developed. Active matrix type flat self-luminous panels are described in, for example, Patent Documents 1 to 5 below.

JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A Japanese Patent Laid-Open No. 2004-093682

  The display device is required to have no luminance unevenness in the entire display screen as display performance. However, in the predetermined pixel pattern layout of the EL panel, the characteristics of the thin film transistor are different depending on the pixel pattern layout, and the characteristic variation of the thin film transistor may be recognized as luminance unevenness.

  The present invention has been made in view of such a situation, and is intended to improve luminance unevenness.

  A panel according to an aspect of the present invention includes a light emitting element that has a diode characteristic and emits light according to a driving current, a sampling transistor that samples a video signal, and a driving transistor that supplies the driving current to the light emitting element. The pixel circuits connected to the anode side of the light emitting element and the gate of the driving transistor and having at least a storage capacitor for holding a predetermined potential are arranged in a matrix, and the wiring pattern of the pixel circuits in a matrix is arranged in a row. A mirror inversion arrangement in which the pixel circuits adjacent to each other in the direction are inverted, the pixel circuit in which the laser is first irradiated to the source during the laser annealing of the source and the drain of the driving transistor, and the drain to the first irradiation The pixel circuit is different.

  Of the source and drain of the driving transistor, the source for the amount of increase in the gate potential of the driving transistor during the writing of the video signal and the mobility correction period of the pixel circuit where the laser is first irradiated to the source during laser annealing The ratio of the potential increase amount can be made larger than that of the pixel circuit in which the laser is first irradiated onto the drain.

  The pixel circuit in which the laser is first irradiated to the source during the laser annealing may be further provided with an auxiliary capacitor that is connected to the anode and the cathode of the light emitting element and holds a predetermined potential.

  Of the source and drain of the driving transistor, the amount of increase in the source potential of the driving transistor after the writing of the video signal and the mobility correction period of the pixel circuit where the laser is first irradiated to the drain during laser annealing The ratio of the increase amount of the gate potential can be made smaller than that of the pixel circuit in which the laser is irradiated on the source first.

  In one aspect of the present invention, the ratio between the amount of increase in the gate potential of the driving transistor and the amount of increase in the source potential is such that the source is irradiated with the laser first during laser annealing of the source and drain of the driving transistor. The circuit is different from the pixel circuit previously irradiated on the drain.

  According to one aspect of the present invention, luminance unevenness can be improved.

<Basic form to which the present invention is applied>
First, in order to facilitate understanding of the present invention and clarify the background, refer to FIGS. 1 to 12 for the basic configuration and operation of a panel using an organic EL device (hereinafter referred to as an EL panel). To explain.

[Basic EL panel configuration]
FIG. 1 is a block diagram illustrating a configuration example of a basic EL panel.

  The EL panel 100 in FIG. 1 drives a pixel array unit 102 in which N × M pixels (pixel circuits) 101- (1,1) to 101- (N, M) are arranged in a matrix form. It comprises a horizontal selector (HSEL) 103, a write scanner (WSCN) 104, and a power supply scanner (DSCN) 105, which are driving units.

  The EL panel 100 also includes M scanning lines WSL10-1 to 10-M, M power supply lines DSL10-1 to 10-M, and N video signal lines DTL10-1 to 10-N.

  In the following description, scanning lines WSL10-1 to 10-M, video signal lines DTL10-1 to 10-N, pixels 101- (1,1) to 101- (N, M), or power supply lines DSL10-1 to DSL10-1 When there is no need to particularly distinguish each of 10-M, they are simply referred to as a scanning line WSL10, a video signal line DTL10, a pixel 101, or a power supply line DSL10.

  Among the pixels 101- (1,1) to 101- (N, M), the pixels 101- (1,1) to 101- (N, 1) in the first row are scanned by the scanning line WSL10-1. 104 and the power supply scanner 105 are connected to the power supply line DSL10-1. Among the pixels 101- (1,1) to 101- (N, M), the pixels 101- (1, M) to 101- (N, M) in the Mth row are the scanning lines WSL10-M. The light scanner 104 is connected to the power supply scanner 105 via the power supply line DSL10-M. The same applies to the other pixels 101 arranged in the row direction of the pixels 101- (1, 1) to 101- (N, M).

  Among the pixels 101- (1,1) to 101- (N, M), the pixels 101- (1,1) to 101- (1, M) in the first column are video signal lines DTL10-1. Is connected to the horizontal selector 103. Among the pixels 101- (1,1) to 101- (N, M), the pixels 101- (N, 1) to 101- (N, M) in the Nth column are horizontal by the video signal line DTL10-N. The selector 103 is connected. The same applies to the other pixels 101 arranged in the column direction of the pixels 101- (1, 1) to 101- (N, M).

  The write scanner 104 sequentially supplies control signals to the scanning lines WSL10-1 to 10-M in a horizontal cycle (1H) to scan the pixels 101 line by line. The power supply scanner 105 supplies a power supply voltage of the first potential (Vcc described later) or the second potential (Vss described later) to the power supply lines DSL10-1 to 10-M in accordance with the line sequential scanning. The horizontal selector 103 switches the signal potential Vsig that becomes a video signal and the reference potential Vofs within each horizontal period (1H) in accordance with the line sequential scanning, and supplies them to the columnar video signal lines DTLs 10-1 to 10-M. .

  A panel module is configured by adding a driver IC (Integrated Circuit) including a source driver and a gate driver to the EL panel 100 configured as shown in FIG. Furthermore, a display device is obtained by adding a power supply circuit, an image LSI (Large Scale Integration), and the like to the panel module. The display device including the EL panel 100 can be used as a display unit of, for example, a mobile phone, a digital still camera, a digital video camera, a television receiver, or a printer.

[Detailed Configuration of Pixel 101]
FIG. 2 is a block diagram showing a detailed configuration of the pixel 101 by enlarging one pixel 101 of the N × M pixels 101 included in the EL panel 100 shown in FIG.

  2, the scanning line WSL10, the video signal line DTL10, and the power supply line DSL10 connected to the pixel 101 are the pixel 101- (n, m) (n = 1, 2, .., N, m = 1, 2,..., M), the scanning line WSL10- (n, m), the video signal line DTL10- (n, m), and the power line DSL10- (n , M).

  The pixel 101 in FIG. 2 includes a sampling transistor 31, a driving transistor 32, a storage capacitor 33, and a light emitting element 34. The gate of the sampling transistor 31 is connected to the scanning line WSL10, the drain of the sampling transistor 31 is connected to the video signal line DTL10, and the source is connected to the gate g of the driving transistor 32.

  One of the source s and the drain d of the driving transistor 32 is connected to the anode of the light emitting element 34, and the other is connected to the power supply line DSL10. The storage capacitor 33 is connected to the gate g of the driving transistor 32 and the anode of the light emitting element 34. The cathode of the light emitting element 34 is connected to a wiring 35 set at a predetermined potential Vcat. The potential Vcat is at the GND level, and therefore the wiring 35 is a ground wiring. Hereinafter, the wiring 35 is referred to as a ground wiring 35.

  The sampling transistor 31 and the driving transistor 32 are both N-channel transistors, and can be made of amorphous silicon, which can be made at a lower cost than low-temperature polysilicon, thereby reducing the manufacturing cost of the pixel circuit. Can do.

  The organic EL element is a current light emitting element having a diode characteristic, and the light emitting element 34 emits light with a gradation corresponding to the supplied current value Ids.

  In the pixel 101 configured as described above, the sampling transistor 31 is turned on (conducted) in response to the control signal from the scanning line WSL10, and the video of the signal potential Vsig corresponding to the gradation is supplied via the video signal line DTL10. Sampling the signal. The storage capacitor 33 stores and holds charges supplied from the horizontal selector 103 via the video signal line DTL10. The driving transistor 32 receives supply of current from the power supply line DSL10 at the first potential Vcc, and flows (supply) the driving current Ids to the light emitting element 34 in accordance with the signal potential Vsig held in the storage capacitor 33. When a predetermined drive current Ids flows through the light emitting element 34, the pixel 101 emits light.

  The pixel 101 has a threshold correction function. The threshold value correction function is a function of holding a voltage corresponding to the threshold voltage Vth of the driving transistor 32 in the storage capacitor 33, thereby causing the threshold value of the driving transistor 32 to cause variation for each pixel of the EL panel 100. The influence of the voltage Vth can be canceled.

  Further, the pixel 101 has a mobility correction function in addition to the above-described threshold correction function. The mobility correction function is a function of adding correction for the mobility μ of the driving transistor 32 to the signal potential Vsig when the signal potential Vsig is held in the storage capacitor 33.

  Furthermore, the pixel 101 has a bootstrap function. The bootstrap function is a function of interlocking the gate potential Vg with the fluctuation of the source potential Vs of the driving transistor 32, and thereby maintaining the voltage Vgs between the gate g and the source s of the driving transistor 32 constant. I can do it.

  Note that the threshold value correction function, mobility correction function, and bootstrap function will also be described in FIG. 7, FIG. 11, FIG.

[Description of Operation of Pixel 101]
FIG. 3 is a timing chart for explaining the operation of the pixel 101.

  FIG. 3 shows potential changes of the scanning line WSL10, the power supply line DSL10, and the video signal line DTL10 with respect to the same time axis (horizontal direction in the drawing), and changes in the gate potential Vg and source potential Vs of the driving transistor 32 corresponding thereto. Show.

In FIG. 3, the period up to time t ₁ is the light emission period T ₁ during which light is emitted in the previous horizontal period (1H).

From time t ₁ to time t ₄ when the light emission period T ₁ ends, a threshold correction preparation period T _{2 in} which the gate potential Vg and the source potential Vs of the driving transistor 32 are initialized to prepare for the threshold voltage correction operation. is there.

In the threshold value correction preparation period T _2, at time t _1, the power supply scanner 105 switches the potential of the power supply line DSL10 from Vcc is a high potential Vss is low potential. At time t _2, the horizontal selector 103 switches the potential of the video signal line DTL10 from the signal potential Vsig to the reference potential Vofs. Next, at time t ₃ , the write scanner 104 switches the potential of the scanning line WSL10 to a high potential and turns on the sampling transistor 31. As a result, the gate potential Vg of the driving transistor 32 is reset to the reference potential Vofs, and the source potential Vs is reset to the low potential Vss of the video signal line DTL10.

From time t ₄ to time t ₅ is a threshold correction period T ₃ in which the threshold correction operation is performed. In the threshold correction period T ₃ , at time t ₄ , the power supply scanner 105 switches the potential of the power supply line DSL10 to the high potential Vcc, and the voltage corresponding to the threshold voltage Vth is the gate g and source s of the driving transistor 32. Is written in the storage capacitor 33 connected between the two.

In the writing + mobility correction preparation period T ₄ from time t ₅ to time t ₇ , the potential of the scanning line WSL 10 is temporarily switched from the high potential to the low potential. At time t ₆ before the time t _7, the horizontal selector 103 is switched to the signal potential Vsig corresponding to the gradation potential of the video signal line DTL10 from the reference potential Vofs.

Then, in the writing + mobility correction period T ₅ from time t ₇ to time t ₈ , video signal writing and mobility correction operation are performed. That is, between the time t ₇ to the time t _8, the potential of the scanning line WSL10 is set to a high potential, thereby written into the storage capacitor 33 in the form of the signal potential Vsig of the video signal is added up to the threshold voltage Vth . In addition, the mobility correction voltage ΔV _μ is subtracted from the voltage held in the storage capacitor 33.

Write + in the mobility correction period T ₅ after the end of the time t _8, the potential of the scanning line WSL10 is set to a low potential, thereafter, as a light-emitting period T _6, the light emitting element 34 in the light emitting luminance corresponding to the signal voltage Vsig is Emits light. Since the signal voltage Vsig is adjusted by the voltage corresponding to the threshold voltage Vth and the mobility correction voltage ΔV _μ , the light emission luminance of the light emitting element 34 varies in the threshold voltage Vth and mobility μ of the driving transistor 32. Will not be affected.

Note that a bootstrap operation is performed at the beginning of the light emission period T ₆ , and the gate potential Vg and the source potential of the driving transistor 32 are maintained while the gate-source voltage Vgs = Vsig + Vth−ΔV _μ of the driving transistor 32 is kept constant. Vs rises.

At time t ₉ after a predetermined time from the time t _8, the potential of the video signal line DTL10 is dropped from the signal potential Vsig to the reference potential Vofs. In FIG. 3, the period from time t ₂ to time t ₉ corresponds to a horizontal period (1H).

  As described above, in the EL panel 100, the light emitting element 34 can emit light without being affected by variations in the threshold voltage Vth and mobility μ of the driving transistor 32.

[Detailed Description of Operation of Pixel 101]
The operation of the pixel 101 will be described in more detail with reference to FIGS.

FIG. 4 shows the state of the pixel 101 in the light emission period T ₁ .

In the light emission period T ₁ , the sampling transistor 31 is off (the potential of the scanning line WSL10 is low), the potential of the power supply line DSL10 is the high potential Vcc, and the driving transistor 32 supplies the driving current Ids to the light emitting element 34. To supply. At this time, since the driving transistor 32 is set to operate in the saturation region, the driving current Ids flowing through the light emitting element 34 is expressed by the following equation (1) according to the gate-source voltage Vgs of the driving transistor 32. Takes a value that is

  In Expression (1), μ represents mobility, W represents gate width, L represents gate length, and Cox represents gate oxide film capacitance per unit area. Vgs is a voltage between the gate g and the source s of the driving transistor 32 (gate-source voltage), and Vth is a threshold voltage of the driving transistor 32. Note that the saturation region refers to a state where the condition of (Vgs−Vth <Vds) is satisfied (Vds is a voltage between the source s and the drain d of the driving transistor 32).

Then, at the first time t ₁ of the threshold correction preparation period T ₂ , as shown in FIG. 5, the power supply scanner 105 changes the potential of the power supply line DSL 10 from the high potential Vcc (first potential) to the low potential Vss (second potential). ). At this time, if the potential Vss of the power supply line DSL10 is smaller than the sum of the threshold voltage Vthel and the cathode potential Vcat of the light emitting element 34 (Vss <Vthel + Vcat), the light emitting element 34 is extinguished and connected to the power supply line DSL10 of the driving transistor 32. The side becomes the source s. The anode of the light emitting element 34 is charged to the potential Vss.

Next, as shown in FIG. 6, at time t _2, the after horizontal selector 103 has a potential of the video signal line DTL10 the reference potential Vofs, at time t _3, the write scanner 104, the high potential of the scanning line WSL10 Switching to the potential turns on the sampling transistor 31. As a result, the gate potential Vg of the driving transistor 32 becomes Vofs, and the gate-source voltage Vgs takes a value of Vofs−Vss. Here, the gate-source voltage Vgs of the driving transistor 32 (Vofs−Vss) is larger than the threshold voltage Vth (Vofs−Vss) because the threshold correction operation is performed in the next threshold correction period T _3. Vth) is necessary. In other words, the potentials Vofs and Vss are set so as to satisfy the condition of (Vofs−Vss> Vth).

Then, at the first time t ₄ of the threshold correction period T _3, as shown in FIG. 7, the power supply scanner 105 switches the potential of the power supply line DSL10 from the low potential Vss to the high potential Vcc. Then, the side connected to the anode of the light emitting element 34 of the driving transistor 32 becomes the source s, and a current flows as shown by a one-dot chain line in FIG.

  Here, the light emitting element 34 can be equivalently represented by a diode 34A and an organic EL capacitor 34B in which the parasitic capacitance is Cel. Under the condition that the leakage current of the light emitting element 34 is considerably smaller than the current flowing through the driving transistor 32 (Vel ≦ Vcat + Vthel is satisfied), the current flowing through the driving transistor 32 causes the storage capacitor 33 and the organic EL capacitor 34B to flow. Used to charge. The anode potential Vel of the light emitting element 34 (source potential Vs of the driving transistor 32) rises according to the current flowing through the driving transistor 32, as shown in FIG. After a predetermined time has elapsed, the gate-source voltage Vgs of the driving transistor 32 takes a value Vth. At this time, the anode potential Vel of the light emitting element 34 is (Vofs−Vth). Here, the anode potential Vel of the light emitting element 34 is equal to or less than the sum of the threshold voltage Vthel and the cathode potential Vcat of the light emitting element 34 (Vel = (Vofs−Vth) ≦ (Vcat + Vthel)).

Thereafter, at time t ₅ , as shown in FIG. 9, the potential of the scanning line WSL 10 is switched from the high potential to the low potential, the sampling transistor 31 is turned off, and the threshold correction operation (threshold correction period T ₃ ) is completed. To do.

At time t ₆ the subsequent write + mobility correction preparation period T _4, the horizontal selector 103, the potential of the video signal line DTL10 is, from the reference potential Vofs, is switched to the signal potential Vsig corresponding to the gradation (Fig. 9). Thereafter, the writing + mobility correction period T ₅ is entered, and as shown in FIG. 10, the sampling transistor 31 is turned on by setting the potential of the scanning line WSL 10 to a high potential at time t ₇ , and the video Signal writing and mobility correction operations are performed. The gate potential Vg of the driving transistor 32 becomes the signal potential Vsig because the sampling transistor 31 is on. However, since the current from the power supply line DSL10 flows through the sampling transistor 31, the source potential of the driving transistor 32 is reached. Vs increases with time.

The threshold correction operation of the driving transistor 32 has already been completed. Therefore, the term (Vgs−Vth) ^{2 on} the right side of Expression (1) is (Vgs−Vth) ² = {(Vsig− (Vofs−Vth)) − Vth} ² = (Vsig−Vofs) ² , Since the influence of the term of the voltage Vth disappears, the current Ids flowing through the driving transistor 32 reflects the mobility μ. Specifically, as shown in FIG. 11, when the mobility μ is large, the current Ids flowing through the driving transistor 32 increases and the source potential Vs rises quickly. On the other hand, when the mobility μ is small, the current Ids flowing through the driving transistor 32 is small, and the rise of the source potential Vs is delayed. In other words, when the mobility μ is large at a certain time, the amount of increase ΔV _μ (potential correction value) of the source potential Vs of the driving transistor 32 is large, and when the mobility μ is small, The increase amount ΔV _μ (potential correction value) of the source potential Vs of the driving transistor 32 becomes small. As a result, the variation in the gate-source voltage Vgs of the driving transistor 32 of each pixel 101 is reduced to reflect the mobility μ, and the gate-source voltage Vgs of each pixel 101 after a certain period of time is reduced by the mobility μ. This is a voltage that completely compensates for this variation.

At time t _8, the potential of the scanning line WSL10 the sampling transistor 31 by being set to the low potential is turned off, ends the writing + mobility correction period T _5, the light emission period T ₆ (FIG. 12) .

In the light emission period T ₆ , the gate-source voltage Vgs of the driving transistor 32 is constant, so that the driving transistor 32 supplies a constant current Ids ′ to the light emitting element 34. The anode potential Vel of the light emitting element 34 rises to a voltage Vx at which a constant current Ids ′ flows through the light emitting element 34, and the light emitting element 34 emits light. When the source potential Vs of the driving transistor 32 rises, the gate potential Vg of the driving transistor 32 also rises in conjunction with the bootstrap function of the storage capacitor 33.

  Due to the IV characteristics of the light-emitting element 34, as the light emission time becomes longer, the potential at the point B shown in FIG. 12 changes with time (deteriorates with time). However, since the gate-source voltage Vgs of the driving transistor 32 is maintained at a constant value, the current flowing through the light emitting element 34 does not change. Therefore, even if the light emitting element 34 deteriorates with time due to the IV characteristic, the constant current Ids' continues to flow, and thus the luminance of the light emitting element 34 does not change.

  As described above, in the EL panel 100 of FIG. 2 including the pixel 101, the difference between the threshold voltage Vth and the mobility μ for each pixel 101 can be corrected by the threshold correction function and the mobility correction function. In addition, the temporal variation (deterioration) of the light emitting element 34 can also be corrected.

  As a result, the display device using the EL panel 100 of FIG. 2 can obtain high-quality image quality.

[Wiring pattern layout of pixel 101]
FIG. 13 shows a layout of the wiring pattern of the pixel (pixel circuit) 101 in the portion related to the sampling transistor 31, the driving transistor 32, and the storage capacitor 33.

  The gate g of the sampling transistor 31 can be formed of the second metal layer, and the source s and drain d of the sampling transistor 31 can be formed of the first metal layer. The gate g of the driving transistor 32 can be formed of the second metal layer, and the source s and drain d of the driving transistor 32 can be formed of the first metal layer. The storage capacitor 33 can be formed of a first metal layer and a second metal layer.

  In the pixel 101 that performs the bootstrap operation, it is necessary to increase the capacity Cs of the storage capacitor 33, and thus it is necessary to secure a wide area for forming the storage capacitor 33. One method for ensuring a large area for the storage capacitor 33 is to invert the layout of the wiring pattern between the pixels 101 adjacent in the row direction.

[Wiring pattern layout of EL panel 100 in mirror inversion arrangement]
FIG. 14 shows a wiring pattern layout of the pixel array unit 102 (FIG. 1) of the EL panel 100 when a mirror inversion arrangement is employed in which the wiring pattern of the pixel 101 is inverted between adjacent pixels in the row direction.

  The pixel 101 described above corresponds to a so-called sub-pixel (sub-pixel) that emits light in one of red, green, and blue, and is in the row direction (the left-right direction in the drawing). One pixel as a display unit is configured by the three pixels 101 of red, green, and blue arranged side by side.

  One pixel as a display unit is called a display pixel, and when a column of display pixels is counted in order from the left end of the pixel array unit 102 (FIG. 1), an odd-numbered display pixel is an odd-numbered pixel (Odd pixel), and an even-numbered number is displayed. This display pixel is called an even pixel (Even pixel).

  If the display pixel composed of the three pixels 101 on the left side of FIG. 14 is an odd pixel, and the display pixel composed of the three pixels 101 on the right side is an even pixel, the EL panel 100 employing the mirror inversion arrangement has red and blue odd numbers and even numbers. The pixel 101 that emits green of the pixel has the wiring pattern layout shown in FIG. 13, and the pixel 101 that emits green of the odd pixel and red and blue of the even pixel has the wiring pattern layout shown in FIG. The wiring pattern layout is mirror-inverted.

  Hereinafter, the pixel 101 having the wiring pattern layout illustrated in FIG. 13 is referred to as a pixel 101R, and the pixel 101 having an arrangement reversed from the wiring pattern layout illustrated in FIG. 13 is referred to as a pixel 101L. In the pixel 101R and the pixel 101L, the positions of the drain d and the source s of the driving transistor 32 are inverted. The driving transistor 32 of the pixel 101R is referred to as a driving transistor 32R, and the driving transistor 32 of the inverted pixel 101L is referred to as the driving transistor 32. This is referred to as a driving transistor 32L.

  Here, consider the case where the channel semiconductor layer of the thin film transistor in the pixel 101 having the wiring pattern layout of the mirror inversion arrangement shown in FIG. 14 is annealed using a laser annealing apparatus.

  The laser annealing apparatus anneals the channel portion semiconductor layer (silicon) of the thin film transistor by repeatedly irradiating the laser in one direction along the row direction of the pixels 101. Therefore, even-numbered pixels and odd-numbered pixels have different ways of hitting the laser with respect to the driving transistor 32, which makes the ON characteristics (transistor characteristics) of the driving transistor 32 different.

  For example, as shown by the arrows in FIG. 14, when the laser irradiation direction (scanning direction) is from the left to the right in the drawing, in the pixel 101R, the laser is first emitted with respect to the source s of the driving transistor 32R. Irradiation is then performed on the drain d. On the other hand, in the pixel 101L, the laser is first irradiated to the drain d of the driving transistor 32L, and then the source s is irradiated. In the pixel 101 that performs the bootstrap operation, the storage capacitor 33 is provided on the source s side of the driving transistor 32, and the source s of the driving transistor 32 and one electrode of the storage capacitor 33 are the same first metal. Formed in layers. Therefore, before the laser is irradiated to the source s of the driving transistor 32R, the laser is irradiated to the storage capacitor 33 portion formed of the same metal layer (first metal layer), and the laser is first applied to the source s. The driving transistor 32 </ b> R irradiated to is affected by this. On the other hand, the driving transistor 32L is not affected by the storage capacitor 33 because there is no same metal layer before the drain d is irradiated with the laser. As a result, the ON characteristics of the driving transistor 32R are low, and the ON characteristics of the driving transistor 32L are high.

[On characteristics of driving transistor 32]
With reference to FIG. 15, the influence of the difference in ON characteristics will be described.

FIG. 15 is an enlarged view of the period from time t ₄ to time t _{8 in} the timing chart of the pixel 101 shown in FIG.

The ON characteristic of the driving transistor 32 represents an increase amount of the source potential Vs in accordance with the increase of the gate potential Vg of the driving transistor 32 in the writing + mobility correction period T ₅ from time t ₇ to time t ₈ . The higher the ON characteristic, the larger the increase amount of the source potential Vs, and the lower the ON characteristic, the smaller the increase amount of the source potential Vs.

  The gate potential Vg and the source potential Vs of the driving transistor 32 in FIG. 15 are solid lines when the ON characteristics are high, that is, when the laser is first irradiated to the drain d, and when the ON characteristics are low, that is, A dotted line indicates a case where the laser is irradiated to the source s first. Since the difference between the gate potential Vg and the source potential Vs of the driving transistor 32 is a difference in the driving current Ids flowing through the light emitting element 34, the difference in the ON characteristics of the driving transistor 32 eventually appears as a difference in luminance. When the mirror inversion arrangement is adopted, the pixel 101R that is irradiated with the laser first with respect to the source s and the pixel 101L that is irradiated with the laser first with respect to the drain d are alternately arranged. The entire EL panel 100 is visually recognized as luminance unevenness of fine vertical stripes, which is a cause of a decrease in the yield of panel production.

  Therefore, an EL panel will be described in which fine vertical stripe luminance unevenness caused by the difference in how the laser strikes the driving transistor 32 is improved.

<Embodiment of the present invention>
[Configuration of EL Panel 200 to which the Present Invention is Applied]
FIG. 16 is a block diagram showing a configuration example of an embodiment of an EL panel 200 to which the present invention is applied.

  In the following, portions corresponding to those of the above-described EL panel 100 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In the EL panel 200 of FIG. 16, in the pixel array unit 102, pixels 201- (1, 1) to 201- (N, M) having a partially different configuration from the pixel 101 described above are arranged in a matrix. However, it is different from the EL panel 100. Hereinafter, when it is not necessary to particularly distinguish each of the pixels 201-(1, 1) to 201-(N, M), similarly to the pixel 101, they are simply referred to as a pixel 201.

  Note that, in the wiring pattern layout of the pixel 201 in the pixel array unit 102 of the EL panel 200, a mirror inversion arrangement in which the arrangement of the wiring pattern is inverted between pixels adjacent in the row direction is adopted.

[First Embodiment of Pixel 201]
FIG. 17 shows a first embodiment of the wiring pattern layout of the pixels 201 in the pixel array unit 102 of the EL panel 200.

  In FIG. 17, as in the case of FIG. 14 described above, when annealing is performed using a laser annealing apparatus, the pixel 201R to which the laser is first applied to the source s of the driving transistor 32 is the pixel 201R. A pixel 201 that is first irradiated with a laser with respect to the drain d of the transistor 32 is indicated by a pixel 201L. In addition, the driving transistor 32 of the pixel 201R is indicated by a driving transistor 32R, and the driving transistor 32 of the pixel 201L is indicated by a driving transistor 32L.

  The first embodiment is different from the pixel 101R in FIG. 14 in that the auxiliary capacitor 211 is formed only for the pixel 201R where the laser is first irradiated to the source s of the driving transistor 32. The pixel 201L has the same configuration (wiring pattern) as the pixel 101L.

  The auxiliary capacitor 211 corresponds to a portion where the first metal layer and the second metal layer in the dotted line face each other. One electrode of the auxiliary capacitor 211 can be formed of a first metal layer and is connected to the cathode of the light emitting element 34 formed of a third metal layer (not shown). Further, the other electrode of the auxiliary capacitor 211 can be formed of the second metal layer and is connected to one electrode of the storage capacitor 33 formed of the first metal layer.

  As shown in FIG. 17, the auxiliary capacitor 211 is disposed at the lower part of the pixel 201R in the pixel 201R, and the first metal layer and the second metal layer constituting the storage capacitor 33 disposed at the substantially central portion of the pixel 201R. Can be arranged in a space between the first metal layer constituting the power line DSL10. Note that the location where the auxiliary capacitor 211 is disposed is not limited to the position shown in FIG.

  FIG. 18 shows an equivalent circuit of the pixel 201R.

  Compared to the equivalent circuit of the pixel 101 described with reference to FIG. 2, an auxiliary capacitor 211 having a capacitor Csub is newly added to the pixel 201 </ b> R. One electrode of the auxiliary capacitor 211 is connected to the anode of the light emitting element 34, and the other electrode of the auxiliary capacitor 211 is connected to the cathode of the light emitting element 34. The operation of the auxiliary capacitor 211 is the same as that of the organic EL capacitor 34B described with reference to FIG.

  In addition, the pixel 201R in FIG. 18 includes a parasitic capacitance (parasitic capacitance generated between the gate and the source of the sampling transistor 31) Cws and a parasitic capacitance Cgd generated between the gate and the drain of the driving transistor 32. A parasitic capacitance Cgs between the gate and the source of the driving transistor 32 is illustrated.

  In the pixel 201R, by adding the auxiliary capacitor 211 in this way, the input gain of the driving transistor 32R can be improved.

Input gain of the driving transistor 32R in the pixel 201R (Input_Gain) is the ratio of the amount of increase in the source potential Vs for the increased amount of the gate potential Vg of the driving transistor 32R in the write + mobility correction period T _5, the following equation ( 2).

  Note that Cel in Expression (2) is a parasitic capacitance of the light emitting element 34 as described with reference to FIG.

As is apparent from the equation (2), the input gain of the driving transistor 32R is improved by adding the auxiliary capacitor 211. Therefore, as shown by a dotted line in FIG. 15, the rise amount of the source potential Vs of the driving transistor 32R in writing + mobility correction period T ₅ of the driving transistor 32R which laser is irradiated to the earlier source s is indicated by a solid line The luminance of the pixel 201R and the pixel 201L can be made the same by adding the auxiliary capacitor 211 having the capacitor Csub that is the same as the increase amount of the source potential Vs of the driving transistor 32L. Accordingly, it is possible to improve luminance unevenness of fine vertical stripes.

That is, the pixel (pixel circuit) laser is irradiated before the source s to the time of laser annealing of the source s and drain d of the driving transistor 32 of the 201R, writing of the video signal and the driving transistor in the mobility correction period T ₅ Luminance unevenness can be improved by increasing the ratio of the increase amount of the source potential Vs to the increase amount of the gate potential Vg of 32 in comparison with the pixel (pixel circuit) 201L where the laser is first irradiated to the drain d. .

  Note that the point of improvement in luminance unevenness in the first embodiment is that the input gain of the driving transistor 32R is made higher than that of the driving transistor 32L by the capacitor Csub of the auxiliary capacitor 211. Therefore, for example, when an auxiliary capacitor is already provided for the purpose of supplementing the capacitance component of the organic light emitting material portion in the pixel 201L having the driving transistor 32L with originally high ON characteristics, the pixel 201L is provided with the pixel 201L. By providing the pixel 201 </ b> R with the auxiliary capacitor 211 having a different size (capacity) from the auxiliary capacitor that is larger in size, the luminance unevenness can be improved.

  In the above-described example, the case where the laser irradiation direction is from the left to the right in the drawing has been described. However, when the laser irradiation direction is from the right to the left in the drawing, the laser is subjected to the source s during laser annealing. The pixel that is irradiated first and the pixel that is irradiated first on the drain d are reversed. That is, the laser is first irradiated to the source s when the pixel 201L is laser-annealed, and the laser is first irradiated to the drain d when the pixel 201R is laser-annealed. In this case, the auxiliary capacitor 211 may be provided in the pixel 201L.

[Second Embodiment of Pixel 201]
FIG. 19 shows a second embodiment of the wiring pattern layout of the pixel 201 in the pixel array unit 102 of the EL panel 200.

  In FIG. 19, similarly to the case of FIG. 14, when annealing is performed using a laser annealing apparatus, the pixel 201R is the pixel 201 that is first irradiated with the laser to the source s of the driving transistor 32, and the driving transistor. A pixel 201L to which the laser is first irradiated to the 32 drains d is indicated by a pixel 201L. In addition, the driving transistor 32 of the pixel 201R is indicated by a driving transistor 32R, and the driving transistor 32 of the pixel 201L is indicated by a driving transistor 32L.

  The second embodiment differs from the pixel 101L only in that a pixel 201L is provided with a storage capacitor 221 having a smaller wiring pattern size than the storage capacitor 33 of the pixel 101L in FIG. The wiring pattern size is an area of a portion where the first metal layer and the second metal layer that constitute the storage capacitor 221 face each other, and the capacitor Cs of the storage capacitor 221 is smaller than the capacitor Cs of the storage capacitor 33. Note that the pixel 201R is similar to the pixel 101R.

The difference in the wiring pattern size of the storage capacitor 221 and the storage capacitor 33, the write + rise amount of the source potential Vs of the mobility correction period (writing and mobility correction period) T ₅ has elapsed after the emission period T ₆ the driving transistor 32 in The bootstrap gain (G _bst ), which is the ratio of the increase amount _ΔVg of the gate potential Vg to _ΔVs, is different. The bootstrap gain is expressed by the following equation (3).

  Since Cgs, Cws, and Cgd in Equation (3) are all parasitic capacitances, the bootstrap gain greatly depends on the capacitance Cs of the storage capacitor 221 or the storage capacitor 33. Therefore, the bootstrap gain is reduced by reducing the capacitance Cs of the storage capacitor 221.

  By reducing the capacitance Cs of the storage capacitor 221 of the pixel 201L, the source potential Vs of the driving transistor 32R after the bootstrap operation is indicated by the dotted line of the pixel 201R (pixel 101R) from the value indicated by the solid line of the pixel 101L. Can be close to

  In other words, the capacitance Cs of the storage capacitor 221 of the pixel 201L is set so that the source potential Vs of the driving transistor 32R after the bootstrap operation is the same as the source potential Vs of the driving transistor 32L (dotted line in FIG. 13). It is determined.

  In this manner, of the source s and drain d of the driving transistor 32, the bootstrap gain of the pixel (pixel circuit) 201L to which the laser is first irradiated to the drain d during laser annealing is irradiated, and the laser is first irradiated to the source s. By making the pixel smaller than the pixel (pixel circuit) 201R, it is possible to improve the luminance unevenness of fine vertical stripes.

  In the second embodiment, the capacity Cs of the storage capacitor 221 of the pixel 201L may be made larger than the capacity Cs of the storage capacitor 33 of the pixel 201R. Therefore, if there is an empty space in the pixel 201L, the pixel 201L is configured in the same manner as the pixel 101L in FIG. 14, and the wiring pattern size of the storage capacitor 33 of the pixel 201R is made larger than the wiring pattern size of the storage capacitor 33 of the pixel 201L. May be large.

  In the above-described example, the case where the laser irradiation direction is from the left to the right in the figure has been described. However, when the laser irradiation direction is from the right to the left in the figure, the laser precedes the source s during laser annealing. The pixel irradiated on the drain d and the pixel irradiated on the drain d first are reversed. That is, the laser is first irradiated to the source s when the pixel 201L is laser-annealed, and the laser is first irradiated to the drain d when the pixel 201R is laser-annealed. In this case, the storage capacitor 221 may be provided in the pixel 201R and the pixel 201L may have a configuration similar to that of the pixel 101L.

  As described above, in the first and second embodiments, the ratio of the increase amount of the gate potential Vg and the increase amount of the source potential Vs of the driving transistor 32 is the ratio of the source s and drain d of the driving transistor 32. By making the pixel 201R previously irradiated with laser to the source s different from the pixel 201L previously irradiated with the drain d at the time of laser annealing, it is possible to improve luminance unevenness of fine vertical stripes.

[Third Embodiment of Pixel 201]
FIG. 20 shows a third embodiment of the wiring pattern layout of the pixels 201 in the pixel array unit 102 of the EL panel 200.

  Also in FIG. 20, as in the case of FIG. 14, when annealing is performed using the laser annealing apparatus, the pixel 201R is the pixel 201 that is first irradiated with the laser to the source s of the driving transistor 32, and the driving transistor. A pixel 201L to which the laser is first irradiated to the 32 drains d is indicated by a pixel 201L.

  The third embodiment is different from the pixel 101L only in that the pixel 201L is provided with a driving transistor 231 having a different transistor size from the driving transistor 32L of the pixel 101L in FIG. That is, the gate width W of the driving transistor 231 of the pixel 201L is shorter than the gate width W of the driving transistor 32L of the pixel 101L. The pixel 201R is the same as the pixel 101R.

[Enlarged view of the driving transistor 231]
FIG. 21 is an enlarged view of the driving transistor 231 portion of the pixel 201L.

  The ON characteristic of the driving transistor 231 is also determined by the transistor size, that is, the gate width W and the gate length L of the channel region shown in FIG. The ON characteristics increase as the gate width W is increased, and the ON characteristics increase even when the gate length L is shortened. The same applies to the driving transistor 32.

  Therefore, in the third embodiment, the driving transistor is set so that the ON characteristic determined by the transistor size of the driving transistor 231 of the pixel 201L is lowered by the difference in the ON characteristic due to the difference in how the laser hits. The gate width W of 231 is made shorter than the gate width W of the driving transistor 32R of the pixel 201R.

  In other words, the gate width W of the driving transistor 231 is determined so that the ON characteristic of the driving transistor 231 of the pixel 201L after laser annealing is the same as the ON characteristic of the driving transistor 32R of the pixel 201R. Thereby, the brightness | luminance nonuniformity of a fine vertical stripe can be improved.

  Strictly speaking, when the gate width W of the driving transistor 231 is changed, the parasitic capacitance Cgd generated between the gate and the drain of the driving transistor 231 and the parasitic capacitance Cgs between the gate and the source are changed. The bootstrap gain in 3) also changes.

  As described in the second embodiment, since the luminance also changes by changing the bootstrap gain, in the third embodiment, the luminance change due to the change in the gate width W of the driving transistor 231 In consideration of both the luminance change of the bootstrap gain due to the change of the gate width W, it is necessary to determine the gate width W of the driving transistor 231 so that the luminance of the pixel 201L is the same as that of the pixel 201R.

  As described above, in the third embodiment, the gate width W of the driving transistor 231 of the pixel 201L to which the laser is first irradiated to the drain s at the time of laser annealing, and the pixel to which the laser is first irradiated to the source s. By making it shorter than the gate width W of the driving transistor 32R of 201R, it is possible to improve luminance unevenness of fine vertical stripes.

  Although the example of changing the gate width W has been described with reference to FIG. 20, as described above, the ON characteristics can be changed even if the gate length L is changed, so that the driving transistor 32 </ b> R and the driving transistor 231 can be changed. The luminance may be the same by changing the gate length L. In this case, the gate length L of the driving transistor 231 may be set longer than the gate length L of the driving transistor 32R.

  Therefore, in the third embodiment, by making the transistor sizes of the driving transistor 231 and the driving transistor 32R different between the adjacent pixels 201L and 201R, it is possible to improve luminance unevenness of fine vertical stripes. .

  In the above-described example, the case where the laser irradiation direction is from the left to the right in the drawing has been described. However, when the laser irradiation direction is from the right to the left in the drawing, the laser is subjected to the source s during laser annealing. The pixel that is irradiated first and the pixel that is irradiated first on the drain d are reversed. That is, the laser is first irradiated to the source s when the pixel 201L is laser-annealed, and the laser is first irradiated to the drain d when the pixel 201R is laser-annealed. In this case, the pixel 201L is configured in the same manner as the pixel 101L, and the gate width W of the driving transistor 32R of the pixel 201R may be shortened as in the driving transistor 231.

[Fourth Embodiment of Pixel 201]
FIG. 22 shows a fourth embodiment of the wiring pattern layout of the pixels 201 in the pixel array unit 102 of the EL panel 200.

  In FIG. 22, similarly to the case of FIG. 14, when annealing is performed using a laser annealing apparatus, the pixel 201R is the pixel 201 that is first irradiated with laser with respect to the source s of the driving transistor 32, and the driving transistor. A pixel 201L to which the laser is first irradiated to the 32 drains d is indicated by a pixel 201L.

  In the fourth embodiment, the pixel 201L is different from the pixel 101L only in that a sampling transistor 241 having a transistor size different from that of the sampling transistor 31 of the pixel 101L in FIG. 14 is provided. That is, the gate width W of the sampling transistor 241 of the pixel 201L is shorter than the gate width W of the sampling transistor 31 of the pixel 101L. The pixel 201R is the same as the pixel 101R.

The ON resistance of the sampling transistor 241 of the pixel 201L is higher than that of the sampling transistor 31 of the pixel 201R having a longer gate width W. When the ON resistance is high, the slope of the rise of the gate potential Vg of the driving transistor 32 in the writing + mobility correction period T ₅ in FIG. 15 becomes gentle. When the slope of the rise of the gate potential Vg of the driving transistor 32 becomes gentle, the rise of the source potential Vs of the driving transistor 32 also becomes gentle, and the amount of increase of the source potential Vs, that is, the ON characteristic becomes low. Therefore, the gate width W of the sampling transistor 241 in the pixel 201L is made shorter than the gate width W of the sampling transistor 31 in the pixel 201R so that the increase amount of the source potential Vs is the same in the pixel 201L and the pixel 201R. , Brightness unevenness of fine vertical stripes can be improved.

  As described above, in the fourth embodiment, the gate width W of the sampling transistor 241 of the pixel 201L to which the laser is first irradiated to the drain d at the time of laser annealing, and the pixel to which the laser is first irradiated to the source s. By making it shorter than the gate width W of the sampling transistor 31 of 201R, it is possible to improve luminance unevenness of fine vertical stripes.

  In the fourth embodiment, the luminance of the pixels 201L and 201R can be made equal by changing the gate length L instead of the gate width W. In this case, the gate length L of the sampling transistor 241 may be set longer than the gate length L of the sampling transistor 31.

  Therefore, in the fourth embodiment, by making the transistor sizes of the sampling transistor 241 and the sampling transistor 31 different between adjacent pixels 201L and 201R, it is possible to improve luminance unevenness of fine vertical stripes.

  In the above-described example, the case where the laser irradiation direction is from the left to the right in the drawing has been described. However, when the laser irradiation direction is from the right to the left in the drawing, the laser source s during laser annealing is used. The pixel that is irradiated first and the pixel that is irradiated first on the drain d are reversed. That is, when the pixel 201L is laser annealed, the laser is first irradiated to the source s, and when the pixel 201R is laser annealed, the laser is first irradiated to the drain d. In this case, the pixel 201L is configured in the same manner as the pixel 101L, and the gate width W of the sampling transistor 31 of the pixel 201R may be as short as the sampling transistor 241.

  As described above, in the third and fourth embodiments, among the source s and drain d of the driving transistor 32, the laser 201 is irradiated first with the laser during the laser annealing, and the pixel 201R and the drain d are irradiated first. By making the size of either the driving transistor or the sampling transistor different from that of the pixel 201L, it is possible to improve brightness unevenness of fine vertical stripes.

  The embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

It is a block diagram which shows the structural example of a basic EL panel. It is the block diagram which showed the detailed structural example of the pixel. It is a timing chart explaining operation | movement of a pixel. It is a figure explaining the operation | movement of a pixel in detail. It is a figure explaining the operation | movement of a pixel in detail. It is a figure explaining the operation | movement of a pixel in detail. It is a figure explaining the operation | movement of a pixel in detail. It is a figure explaining the operation | movement of a pixel in detail. It is a figure explaining the operation | movement of a pixel in detail. It is a figure explaining the operation | movement of a pixel in detail. It is a figure explaining the operation | movement of a pixel in detail. It is a figure explaining the operation | movement of a pixel in detail. It is a figure which shows the wiring pattern layout of the pixel in the EL panel of FIG. It is a figure which shows the wiring pattern layout at the time of employ | adopting mirror inversion arrangement | positioning. It is a figure explaining the influence by the difference in ON characteristic. It is a block diagram which shows the structural example of embodiment of EL panel to which this invention is applied. It is a figure which shows the 1st wiring pattern layout in the EL panel to which this invention is applied. It is a figure which shows the equivalent circuit of the pixel of FIG. It is a figure which shows the 2nd wiring pattern layout in the EL panel to which this invention is applied. It is a figure which shows the 3rd wiring pattern layout in the EL panel to which this invention is applied. It is an enlarged view of the transistor part for a drive. It is a figure which shows the 4th wiring pattern layout in the EL panel to which this invention is applied.

Explanation of symbols

    200 EL panel, 201L, 201R pixel (pixel circuit), 211 auxiliary capacitor, 221 storage capacitor, 231 driving transistor, 241 sampling transistor

Claims (4)

A light-emitting element having diode characteristics and emitting light according to a drive current;
A sampling transistor for sampling a video signal;
A driving transistor for supplying the driving current to the light emitting element;
Pixel circuits connected at least to the anode side of the light emitting element and the gate of the driving transistor and having at least a storage capacitor for holding a predetermined potential are arranged in a matrix, and the wiring pattern of the pixel circuits in the matrix is arranged in a row direction Is a mirror inversion arrangement inverted between the pixel circuits adjacent to each other,
The ratio of the amount of increase in the gate potential of the driving transistor to the amount of increase in the source potential is such that the source is first irradiated with a laser during laser annealing of the source and drain of the driving transistor, and the drain A panel different from the pixel circuit irradiated first. Of the source and drain of the driving transistor, the source for the amount of increase in the gate potential of the driving transistor during the writing of the video signal and the mobility correction period of the pixel circuit where the laser is first irradiated to the source during laser annealing The panel according to claim 1, wherein a ratio of a potential increase amount is larger than that of the pixel circuit in which the laser is first irradiated onto the drain. 3. The panel according to claim 2, wherein the pixel circuit in which a laser is first irradiated onto the source during the laser annealing further includes an auxiliary capacitor that is connected to an anode and a cathode of the light emitting element and holds a predetermined potential. Of the source and drain of the driving transistor, the amount of increase in the source potential of the driving transistor after the writing of the video signal and the mobility correction period of the pixel circuit where the laser is first irradiated to the drain during laser annealing The panel according to claim 1, wherein a ratio of an increase amount of a gate potential is smaller than that of the pixel circuit in which the laser is irradiated on the source first.

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