JP2010093318A - Semiconductor integrated circuit and lsi system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of operating a CMOS logic circuit at high speed by a small switch and capable of effectively reducing a sub-threshold leakage current, and to provide an LSI system. <P>SOLUTION: The semiconductor integrated circuit includes: the CMOS logic circuit; a switch circuit connected between the voltage supply source of the CMOS logic circuit and the power supply terminal of the CMOS circuit and includes a first MOSFET; and a digital-to-analog conversion circuit which includes a second MOSFET with a channel reverse to that of the first MOSFET, a first resistor connected to the drain of the second MOSFET and a second resistor connected to the first resistor and the source of the first MOSFET. A back gate of the first MOSFWT is connected to a node between the first resistor and the second resistor. A control signal to be supplied to the gate of the first MOSFWT is common to a control signal to be supplied to the gate of the second MOSFWT. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and an LSI system having a CMOS logic circuit.

  2. Description of the Related Art A semiconductor integrated logic circuit having a function of shutting off a power source of a CMOS logic circuit is widely used for high integration, high speed during operation, and low power consumption when stopped. FIG. 9 is a schematic diagram showing a configuration of a conventional semiconductor integrated circuit.

  As shown in FIG. 9A, in the semiconductor integrated circuit 9, a MOSFET (Mn11) is placed on a substrate of a switch (MOSFET (Mn11)) inserted for power shutoff of the CMOS logic circuit 91, and a forward diode configuration ( D11). Furthermore, the cathode side of the diode D11 is connected to the gate electrode of the MOSFET (Mn12). FIG. 9B and FIG. 9C are diagrams showing equivalent circuits when the MOSFET (Mn11) is turned on and off, respectively.

  As shown in FIG. 9B, when the supply voltage of the CMOS logic circuit 91 is applied to the gate of the MOSFET (Mn11) and turned on, the diode D11 is in the reverse direction, and the parasitic diode D12 between the substrate and the source of the MOSFET (Mn11). Is forward. At this time, the current flowing through the diodes D11 and D12 is determined by the dark current of the diode D11, the substrate potential Vb is near the threshold voltage of the diode D12, and the back gate electrode of the MOSFET (Mn11) is biased to a positive voltage. For this reason, the apparent threshold value of the MOSFET (Mn11) is lowered and the on-resistance is lowered. As a result, the CMOS logic circuit 91 can drive a large current.

  On the other hand, as shown in FIG. 9C, when the gate voltage Vg becomes 0V, forward current flows through the diodes D11 and D12 until the substrate voltage Vb converges to 0V. When the substrate voltage Vb converges to 0 V, the substrate bias effect on the MOSFET (Mn11) is lost, so the apparent threshold value of the MOSFET (Mn11) changes to the original high state, and the resistance as a switch increases. Thereby, the subthreshold leakage current flowing in the CMOS logic circuit 91 is suppressed.

  As described above, the semiconductor integrated circuit 9 shown in FIG. 9 can effectively suppress the subthreshold leakage current by adding a minimum number of elements (see, for example, Patent Document 1).

  Low power consumption design in LSI (Large Scale Integration) is to reduce the subthreshold leakage current by a switch that cuts off the power supply of the CMOS logic circuit, and to dynamically control the operating frequency and power supply voltage according to the operation mode of the circuit, etc. Power control technology is the mainstream.

  In LSI, it is most desirable to be able to set each power block separately for each functional block (hereinafter referred to as “power domain”), but it is practically impossible to prepare various power sources for each power domain. . In general, a single LSI has a plurality of power domains having a common power source. Thus, in a plurality of power domains having a common power source, when some of the power domains are in a low-speed operation or standby state, the resistance of the power shut-off switch of the power domain is increased, and the CMOS logic By reducing the apparent power supply voltage applied to the circuit to a minimum voltage at which the CMOS logic circuit operates, subthreshold leakage flowing in the CMOS logic circuit can be reduced.

  However, in the case of the semiconductor integrated circuit 9 shown in FIG. 9, the voltage biased to the substrate when the MOSFET (Mn11), which is a power cut-off switch, is turned on automatically applies the substrate bias, and the MOSFET (Mn11) is turned on. Resistance is forcibly lowered. Furthermore, since the voltage biased to the MOSFET (Mn11) is also fixed to the threshold value of the diode configuration D11, dynamic adjustment cannot be performed.

JP-A-9-121152

  An object of the present invention is to provide a semiconductor integrated circuit and an LSI system that can operate a CMOS logic circuit at high speed with a small switch and can effectively reduce a subthreshold leakage current.

  The present invention relates to a CMOS logic circuit, a switch circuit having a first MOSFET provided between a voltage supply source of the CMOS logic circuit and a power supply terminal of the CMOS logic circuit, and a reverse channel of the first MOSFET. A second resistor connected to the drain of the second MOSFET, and a second resistor connected to the source of the first resistor and the first MOSFET. An analog conversion circuit, a back gate of the first MOSFET, a connection point of the first resistor and the second resistor, and a control signal supplied to the gate of the first MOSFET; Provided is a semiconductor integrated circuit in which a control signal supplied to the gate of the second MOSFET is common.

  With this configuration, when the switch circuit is turned on, the substrate potential is biased in the forward direction to lower the on-resistance, and when the switch circuit is turned off, the bias is released to increase the resistance. Can be driven at a high speed. In addition, by dynamically controlling the resistance value of the digital-analog converter circuit according to the operating state of the CMOS logic circuit, the subthreshold leakage current of the CMOS logic circuit is effectively reduced, and the power consumption of the semiconductor integrated circuit is reduced. Can be achieved.

  In the semiconductor integrated circuit, the first MOSFET is an N-channel MOSFET, and the N-channel MOSFET is connected to a voltage supply source and a power supply terminal on the low voltage side of the CMOS logic circuit.

  With this configuration, when the N-channel MOSFET of the switch circuit is turned on, the substrate potential is biased in the forward direction to lower the on-resistance, and when the switch is turned off, the bias is released to increase the resistance, thereby speeding up the CMOS logic circuit. It can be operated. In addition, by dynamically controlling the resistance value of the digital-analog converter circuit according to the operating state of the CMOS logic circuit, the subthreshold leakage current can be effectively reduced and the power consumption can be reduced.

  In the semiconductor integrated circuit, the first MOSFET is a P-channel MOSFET, and the P-channel MOSFET is connected to a high-voltage side voltage supply source and a power supply terminal of the CMOS logic circuit.

  With this configuration, when the N-channel MOSFET of the switch circuit is turned on, the substrate potential is biased in the forward direction to lower the on-resistance, and when the switch is turned off, the bias is released to increase the resistance, thereby speeding up the CMOS logic circuit. It can be operated. In addition, by dynamically controlling the resistance value of the digital-analog converter circuit according to the operating state of the CMOS logic circuit, the subthreshold leakage current can be effectively reduced and the power consumption can be reduced.

  In the semiconductor integrated circuit, at least one of the first resistor and the second resistor is a variable resistor.

  With this configuration, the resistance value of the digital-to-analog converter circuit can be dynamically controlled according to the operating state of the CMOS logic circuit, and the subthreshold leakage current can be effectively reduced and the power consumption can be reduced. It becomes.

  In the semiconductor integrated circuit, the first resistor and the second resistor are MOSFETs of the same type as the first MOSFET.

  With this configuration, it is possible to eliminate the separation layer between the resistance element and the MOS region, and it is possible to design a layout with high density and to reduce the cost because a mask layer for creating the resistance element becomes unnecessary. Can do.

  In the semiconductor integrated circuit, the digital-analog converter circuit includes a band gap reference circuit.

  With this configuration, it is possible to obtain a stable bias voltage Vb that is not affected by dynamic power supply voltage fluctuations, and it is possible to effectively reduce the subthreshold leakage current and reduce power consumption.

  In the semiconductor integrated circuit, the second resistor is a MOSFET having a unit transistor configuration in which a ratio of a resistance value with the first MOSFET has an integer relationship.

  With this configuration, by replacing the resistance on the source electrode side of the switch circuit with a MOS resistor, it is possible to automatically correct the threshold variation, eliminating the need for trimming to correct the threshold variation, which has been required in the past, and reducing the cost. Reduction is possible.

  In the semiconductor integrated circuit, the digital-analog converter circuit is connected to a power source different from that of the CMOS logic circuit and the switch circuit.

  With this configuration, the CMOS logic circuit can be operated at a high speed with a smaller switch than the conventional one, and the subthreshold leakage current can be further reduced to further reduce power consumption.

  In the semiconductor integrated circuit, the switch circuit is composed of a plurality of MOSFETs, each gate of the plurality of MOSFETs is individually controlled, and the gate logic of the second MOSFET is the logic of the plurality of MOSFETs. It is common with the signal applied to each gate.

  With this configuration, it is possible to adjust a wider range of current capability for the CMOS logic circuit, reduce the subthreshold leakage current, and reduce the power consumption of the semiconductor integrated circuit.

  The present invention is an LSI system comprising the above semiconductor integrated circuit, based on a register group including a power cutoff control register, a frequency setting register, a power supply voltage setting register, and a temperature sensor determination result storage register, and an output of the register group There is provided an LSI system comprising: a decoder for adjusting on / off of the switch circuit and the digital-analog conversion circuit and a value of the second resistor.

  With this configuration, it is possible to adjust a wider range of current capability for the CMOS logic circuit, reduce the subthreshold leakage current of the semiconductor integrated circuit, and reduce the power consumption of the LSI system.

  According to the semiconductor integrated circuit and the LSI system of the present invention, the CMOS logic circuit can be operated at a high speed with a small switch, and the subthreshold leakage current can be effectively reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a schematic diagram showing the configuration of the semiconductor integrated circuit according to the first embodiment. As shown in FIG. 1, the semiconductor integrated circuit 1 according to the first embodiment includes a CMOS logic circuit 11, a power cutoff switch 12, and a resistance voltage-dividing digital-analog converter (hereinafter referred to as “DAC”) 13. .

  The power cutoff switch 12 is composed of two N-channel MOSFETs (Mn1, Mn2) connected to the Vss side power supply end of the CMOS logic circuit 11, and the output voltage Vb of the DAC 13 is applied to each back gate electrode.

  The DAC 13 includes a P-channel MOSFET (Mp1) connected to the Vdd-side power supply end of the CMOS logic circuit 11, a resistor R1 connected to the drain end thereof, and N-channel MOSFETs (Mn1, Mn2) of the resistor R1 and the power cut-off switch 12. ) And a variable resistor R2 connected to the source side. A back gate electrode of an N-channel MOSFET (Mn1, Mn2) is connected to a connection point between the resistor R1 and the variable resistor R2. Therefore, the voltage Vb divided by the resistor R1 and the variable resistor R2 is applied to the back gate electrode of the N-channel MOSFET (Mn1, Mn2).

  The gate electrodes of the N-channel MOSFETs (Mn1, Mn2) of the power cutoff switch 12 are connected in common, and are connected to the gate electrode of the P-channel MOSFET (Mp1) of the DAC 13 through an inverter. For this reason, when the power cut-off switch 12 is turned off according to the control signal Sa commonly applied to the gate electrodes of the N-channel MOSFETs (Mn1, Mn2), the DAC 13 is also turned off, and the voltage Vb becomes the Vss potential.

  Hereinafter, the operation of the semiconductor integrated circuit 1 of the present embodiment will be described. First, the operation when the power cutoff switch 12 is turned on will be described.

  In general, the operating current Ids of the MOSFET is expressed by the following formula (1). In Equation (1), k is a constant, W is a channel width, L is a channel length, Vgs is a gate-source voltage, and Vth is a threshold value.

Ids = k (W / L) (Vgs−Vth) ² (1)

  According to Expression (1), Ids increases as the threshold value Vth increases, and the driving capability as a MOSFET increases.

On the other hand, the threshold value Vth is expressed by the following equation (2). In the equation (2), Vth ₀ is the threshold voltage when a Vsb = 0, Vsb source - substrate junction potential (Vs-Vb), γ is a constant, [Phi _F are constants.

Vth = Vth ₀ + γ {√ (2Φ _F + Vsb) −√ (2Φ _F )} (2)

  Assuming that the MOSFET is an N-channel MOSFET, its source potential Vs = 0V. In this case, the threshold value Vth increases as the potential Vb increases in the negative direction. Conversely, when the potential Vb increases in the positive direction, the threshold value Vth decreases. Therefore, driving a large current with a small switch can be handled by increasing the voltage Vb in the positive direction and lowering the threshold value Vth.

  In the case of the semiconductor integrated circuit 1 shown in FIG. 1, since the DAC 13 is turned on at the same time when the power cutoff switch 12 is turned on, the voltage Vb divided by the resistor R1 and the variable resistor R2 is the source potential (Vss) of the power cutoff switch 12. Higher than. Accordingly, the threshold value Vth of the power cut-off switch 12 is lowered, and the CMOS logic circuit 11 can be driven with a large current. If the size of the power cutoff switch 12 is designed in consideration of this bias effect, the circuit area can be reduced.

  Next, an operation when the power cut-off switch 12 is turned off will be described. When the power cut-off switch 12 is turned off, the current driving capability of the CMOS logic circuit 11 is not necessary, but the subthreshold leakage current Ileak flows. Since the subthreshold leakage current Ileak flowing through the power cutoff switch 12 is sufficiently smaller than the subthreshold leakage current flowing through the CMOS logic circuit 11, the leakage current can be reduced as compared with the case where the power cutoff switch 12 is not provided. However, the leakage current itself of the power cut-off switch 12 determines the power consumption of the semiconductor integrated circuit 1.

  The subthreshold leakage current Ileak of the power cut-off switch 12 is expressed by the following equation (3). In Equation (3), Vth is a threshold value, S is a coefficient, λ is a constant of 0.1 to 1, W is a channel width, and L is a channel length.

Ileak = λ (W / L) 10 ^{((Vgs−Vth) / S)} (3)

  From equation (3), it can be seen that in order to reduce the subthreshold leakage current leak, the channel width W should be reduced and the threshold value Vth should be increased.

  In the case of the semiconductor integrated circuit 1 shown in FIG. 1, the DAC 13 is turned off at the same time as the power cut-off switch 12 is turned off, and the voltage Vb becomes the Vss potential. That is, since the voltage Vb becomes equal to the source potential (Vss) of the power cutoff switch 12, the threshold Vth becomes higher than when the power cutoff switch 12 is turned on, and the subthreshold leakage current leak can be reduced. Further, the subthreshold leakage current leak can be further reduced by determining the size of the power cutoff switch 12 in consideration of the shift of the threshold value Vth when the power cutoff switch 12 is turned on in advance, and designing the channel width W to be small.

  Next, in the semiconductor integrated circuit 1 according to the first embodiment, an operation in a case where the power cutoff switch 12 is on and the CMOS logic circuit 11 operates at a low speed or in a standby state will be described.

  When the CMOS logic circuit 11 operates at a low speed or in a standby state, the current drive capability of the CMOS logic circuit 11 is expressed by the above equation (1) indicating the operating current Ids of the power cutoff switch 12. However, if the operation speed of the CMOS logic circuit 11 is acceptable, “Vgs−Vt” in the expression (1) may be lowered to lower the current driving capability.

  In order to lower “Vgs−Vt”, it is only necessary to increase the ON resistance of the power cutoff switch 12 and increase the power supply end voltage Vssa of the CMOS logic circuit 11. When the power supply terminal voltage Vssa is increased, Vgs is reduced from the equation (3), and the subthreshold leakage current Ileak is reduced.

  The on resistance of the power cutoff switch 12 is biased in the direction in which the output voltage Vb of the DAC 13 increases. For this reason, the voltage Vb applied from the DAC 13 is lowered to release the bias, and the apparent threshold value Vth of the power cut-off switch 12 may be lowered.

  As described above, the power consumption of the semiconductor integrated circuit 1 can be reduced by dynamically controlling the on-resistance of the power cutoff switch 12 in consideration of the low-speed operation of the CMOS logic circuit 11.

  As described above, according to the semiconductor integrated circuit 1 of the first embodiment, the power cutoff switch 12 and the resistive voltage dividing DAC 13 for substrate bias are provided. In the semiconductor integrated circuit 1, when the power cutoff switch 12 is turned on, the potential Vb is biased in the forward direction to lower the on-resistance, and when the power cutoff switch 12 is turned off, the bias is released to increase the on-resistance. The CMOS logic circuit 11 can be driven with a large current and operated at a high speed with a small switch.

  In addition, by dynamically controlling the resistance value of the variable resistor R2 of the DAC 13 according to the operating state of the CMOS logic circuit 11, the subthreshold leakage current Ileak of the CMOS logic circuit 11 is effectively reduced, and the semiconductor integrated circuit 1 The power consumption can be reduced.

  In the semiconductor integrated circuit 1 shown in FIG. 1, the power cutoff switch 12 is composed of two N-channel MOSFETs (Mn1, Mn2). For example, as shown in the semiconductor integrated circuit 2 shown in FIG. The power cut-off switch 22 may be configured by two P-channel MOSFETs (Mp2, Mp3).

  In this case, the power cut-off switch 22 is connected to the Vdd side power supply end of the CMOS logic circuit 11, and the DAC 23 having the N-channel MOSFET (Mn3), the resistor R 1 and the variable resistor R 2 is connected to the power cut-off switch 22. When the DAC 23 is off, the voltage Vb becomes equal to the power supply voltage Vdd.

  FIG. 3 is a schematic diagram showing the configuration of the semiconductor integrated circuit 3 when the power cutoff switch is connected to both the Vdd side power supply terminal and the Vss side power supply terminal of the CMOS logic circuit 11.

  The power cutoff switch connected to the Vdd side power supply terminal is configured by a P channel MOSFET (Mp4), and the power cutoff switch connected to the Vss side power supply terminal is configured by an N channel MOSFET (Mn4).

  The DAC 33 includes N-channel MOSFETs (Mn5) and P-channel MOSFETs (Mp5) connected in a complementary manner, voltage dividing resistors R11 and R12 connected to power supply terminals on the Vdd side and Vss side of the CMOS logic circuit 11, respectively, It has pressure resistance R21, R22. According to this configuration, when the DAC 33 is off, the voltage Vb1 on the Vss side is Vb1 = Vss, and the voltage on the Vdd side is Vb2 = Vdd.

  Each operation of the semiconductor integrated circuit 2 shown in FIG. 2 and the semiconductor integrated circuit 3 shown in FIG. 3 is the same as the operation of the semiconductor integrated circuit 1 shown in FIG.

(Second Embodiment)
FIG. 4 is a schematic diagram showing the configuration of the semiconductor integrated circuit according to the second embodiment. The same components as those of the semiconductor integrated circuit 1 according to the first embodiment shown in FIG.

  As shown in FIG. 4, the semiconductor integrated circuit 4 of the second embodiment includes a CMOS logic circuit 11, a power cutoff switch 12, and a digital-analog converter (DAC) 43. The DAC 43 includes a P-channel MOSFET (Mp1) connected to the Vdd side power supply terminal of the CMOS logic circuit 11 and two N-channel MOSFETs (Mn6, Mn7). N-channel MOSFETs (Mn6 and Mn7) are provided in place of the resistors R1 and R2 included in the DAC 13 of the first embodiment.

  Since the resistive element of the DAC 43 is a MOS resistor, the isolation layer from the MOS region can be eliminated, so that the semiconductor integrated circuit 4 can be designed with a high density layout.

  In addition, when diffusing a resistance element in a semiconductor integrated circuit, a mask layer different from the creation of a MOSFET is generally required. Some LSIs use a process that does not include any analog circuit and does not include a mask layer of a resistive element. In an LSI for such applications, the present embodiment does not generate extra costs and can reduce power consumption.

  In this embodiment, the power cut-off switch 12 is composed of two N-channel MOSFETs (Mn1, Mn2). However, similarly to FIG. 2 described in the first embodiment, P-channel MOSFETs (Mp2, Mp3) You may comprise.

  As described above, according to the semiconductor integrated circuit 4 of the second embodiment, as in the first embodiment, the CMOS logic circuit 11 is driven with a large current and operated at a high speed with a smaller switch than the conventional one. Can do. Further, similarly to the first embodiment, the subthreshold leakage current Ileak can be effectively reduced, and the power consumption of the semiconductor integrated circuit 4 can be reduced. Further, in the present embodiment, since the resistive element of the DAC 43 is configured by a MOSFET, a mask layer for creating the resistive element is not necessary. Therefore, the cost can be reduced.

(Third embodiment)
FIG. 5 is a schematic diagram showing the configuration of the semiconductor integrated circuit according to the third embodiment. The same components as those of the semiconductor integrated circuit 1 according to the first embodiment shown in FIG.

  As shown in FIG. 5, the semiconductor integrated circuit 5 of the third embodiment includes a CMOS logic circuit 11, a power cutoff switch 12, and a DAC 53 including a bandgap reference circuit.

In the case of the semiconductor integrated circuit 1 of the first embodiment shown in FIG. 1, if the on-resistance of the power control MOSFET is ignored, the current I1 flowing through the resistors R1 and R2 of the DAC 13 is expressed by the following equation (4). Is done.
I1 = Vdd / (R1 + R2) (4)

The voltage Vb divided by the resistor R1 and the variable resistor R2 of the DAC 13 is expressed by the following equation (5).
Vb = I1 (R1 / (R1 + R2)) (5)

  From equations (4) and (5), when the DAC 13 is used as in the first embodiment, when the power supply voltage Vdd varies, the current I1 also varies and the voltage Vb also varies.

  On the other hand, in the case of the semiconductor integrated circuit 5 of this embodiment including the DAC 53 including the band gap reference circuit, the current I1 flowing through the resistors R1 and R2 is expressed by the following equations (6) and (7). The gate-source voltage Vgsa of the MOSFET (Ma) provided in the DAC 53 is expressed by the following formula (8). In the equations (7) and (8), α and k are constants, and I2 is a mirror current.

I1 = Vgsa / (R1 + R2) (6)
I1 = αI2 (7)
Vgsa = √ (I2 / k) + Vth (8)

  As shown in the equations (6) to (8), since the power supply voltage Vdd is not related to the factor that determines the current I1 flowing through the resistors R1 and R2, the current I1 and the voltage Vb are affected by fluctuations in the power supply voltage Vdd. Absent. As described above, by mounting the band gap reference circuit on the DAC, a stable voltage Vb that is not affected by the fluctuation of the power supply voltage Vdd can be applied to the back gate electrode of the N-channel MOSFET (Mn1, Mn2).

  In the semiconductor integrated circuit 5 shown in FIG. 5, the power cut-off switch 12 is composed of two N-channel MOSFETs (Mn1, Mn2). For example, as in the semiconductor integrated circuit 2 shown in FIG. The power cut-off switch 22 may be configured by two P-channel MOSFETs (Mp2, Mp3).

  As described above, according to the semiconductor integrated circuit 5 of the third embodiment, as in the first embodiment, the CMOS logic circuit 11 is driven with a large current and operated at a high speed with a smaller switch than the conventional one. Can do. Further, similarly to the first embodiment, the subthreshold leakage current Ileak can be effectively reduced, and the power consumption of the semiconductor integrated circuit 5 can be reduced. Further, in the present embodiment, a stable voltage Vb can be obtained without being subjected to fluctuations in the power supply voltage Vdd.

(Fourth embodiment)
FIG. 6 is a schematic diagram showing the configuration of the semiconductor integrated circuit according to the fourth embodiment. The same components as those of the semiconductor integrated circuit 1 according to the first embodiment shown in FIG.

  As shown in FIG. 6, the semiconductor integrated circuit 6 of the fourth embodiment includes a CMOS logic circuit 11, a power cutoff switch 12, and a DAC 63. In the DAC 63, the variable resistor R2 on the source electrode side of the power cut-off switch 12 shown in the first embodiment is replaced with a MOS resistor that is an N-channel MOSFET (Mn7), and the resistance values of the power cut-off switch 12 and the MOS resistor are changed. It is designed with a unit transistor configuration in which the ratio of is an integer.

The on-resistance Ron of the N-channel MOSFET (Mn7) is expressed by the following formula (9).
Ron = {k (W / L) (Vgs−Vth) ² } ⁻¹ (9)

  In the present embodiment, the N-channel MOSFET (Mn7) is the same type as the N-channel MOSFETs (Mn1, Mn2) of the power cutoff switch 12. For this reason, for example, when the threshold value Vth of the power cut-off switch 12 is shifted by ΔVth due to manufacturing variations, the N-channel MOSFET (Mn7) is similarly shifted by ΔVth.

  As shown in Expression (9), when the threshold value Vth is increased, the on-resistance Ron is also increased, so that the output voltage Vb of the DAC 63 is also increased so as to be corrected corresponding to ΔVth. Similarly, when ΔVth is shifted to the lower side, there is an effect of correcting the manufacturing variation of the threshold value. Thus, by replacing the resistance on the source electrode side of the power cutoff switch 12 provided in the DAC with the MOS resistance, the variation in the threshold value Vth can be automatically corrected. As a result, since trimming for correcting the threshold variation required conventionally is not required, the cost can be reduced.

  In the semiconductor integrated circuit 6 shown in FIG. 6, the power cutoff switch 12 is composed of two N-channel MOSFETs (Mn1, Mn2). For example, as shown in the semiconductor integrated circuit 2 shown in FIG. The power cut-off switch 22 may be configured by two P-channel MOSFETs (Mp2, Mp3).

  As described above, according to the semiconductor integrated circuit 6 of the fourth embodiment, the variation of the threshold value Vth can be automatically corrected by replacing the resistance on the source electrode side of the power cutoff switch 12 with the MOS resistance. it can. As a result, since trimming for correcting the threshold variation required conventionally is not required, the cost can be reduced.

(Fifth embodiment)
FIG. 7 is a schematic diagram showing the configuration of the semiconductor integrated circuit according to the fifth embodiment. The same components as those of the semiconductor integrated circuit 1 according to the first embodiment shown in FIG.

  As shown in FIG. 7, in the semiconductor integrated circuit 7 of the fifth embodiment, the power control for supplying power to the gate electrode of the P-channel MOSFET (Mp1) included in the resistance voltage dividing DAC 13 shown in the first embodiment. The power supply for deleting the signal and used for the DAC 73 is different from that of the CMOS logic circuit 11 and the power cut-off switch 12.

  As shown in Expression (2) described in the first embodiment, the threshold value Vth increases when the voltage Vb increases in the minus direction, and conversely, the threshold value Vth decreases when the voltage Vb increases in the plus direction. In the first embodiment, the drive capability of the power cut-off switch 12 is improved by biasing the voltage Vb in the positive direction and lowering the threshold value Vth. In the present embodiment, as the power source of the DAC 73, a voltage source that is lower by αV than the source potential (Vss) of the power cutoff switch 12 is used, so that the voltage Vb can be changed to be lower in the minus direction.

  According to this configuration, when the voltage Vb is shifted in the negative direction when the power cut-off switch 12 is turned off, the subthreshold leakage current Ileak can be further reduced as shown in Expression (3).

  In the semiconductor integrated circuit 7 shown in FIG. 7, the power cutoff switch 12 is composed of two N-channel MOSFETs (Mn1, Mn2). For example, as in the semiconductor integrated circuit 2 shown in FIG. The power cut-off switch 22 may be configured by two P-channel MOSFETs (Mp2, Mp3).

  As described above, according to the semiconductor integrated circuit 7 of the fifth embodiment, as in the first embodiment, the CMOS logic circuit 11 is driven with a large current and operated at a high speed with a smaller switch than the conventional one. Can do. Further, as in the first embodiment, the subthreshold leakage current Ileak can be further effectively reduced, and the power consumption of the semiconductor integrated circuit 7 can be reduced.

(Sixth embodiment)
FIG. 8 is a diagram showing a schematic configuration of an LSI system according to the sixth embodiment. The LSI system 8 shown in FIG. 8 includes a power supply control register 83, a temperature sensor determination result storage register 84, a frequency setting register 85, a power supply voltage setting register 86, and a decoder 87. According to the LSI system, each output of the registers 83 to 86 is decoded by the decoder 87, and is mounted on each power supply domain of the plurality of semiconductor integrated circuits D1 to D4 similar to the semiconductor integrated circuit 1 of the first embodiment. The output cut-off switch 82 and the output voltage Vb of the DAC 83 are dynamically controlled.

  As described in the first embodiment, the voltage Vb can be changed by changing the resistance value of the variable resistor R2 included in the DAC 13, and the power supply voltage Vssa of the CMOS logic circuit 11 can be changed. However, this variable range is limited to the amount of change in threshold value Vth in equation (1).

  On the other hand, when the control signals S1 to S4 of the power cut-off switch 82 are individually turned on / off, the same change as the channel width W shown in the equation (1) is possible. The channel width W can be divided at most by the number of mounted switches, and the accuracy is coarser than the change of the power supply end voltage Vssa by the threshold value Vth, but a wide range can be adjusted.

  As described above, in the LSI system 8, the adjustment of the power supply terminal voltage Vssa by the voltage Vb of the DAC 83 is fine adjustment, and the adjustment of the ON number of the power cut-off switch 82 is used as a rough adjustment of the power supply terminal voltage Vssa. It is possible to adjust the current capability.

  In the present embodiment, the power cutoff switch 82 is composed of an N-channel MOSFET, but may be composed of a P-channel MOSFET as shown in FIG. 2, for example.

  The semiconductor integrated circuit according to the present invention is useful for an LSI system or the like in which a CMOS logic circuit can be operated at high speed with a small switch to reduce a subthreshold leakage current.

Schematic diagram showing the configuration of the semiconductor integrated circuit of the first embodiment Schematic which shows the structure of the modification of the semiconductor integrated circuit of 1st Embodiment. Schematic which shows the structure of the other modification of the semiconductor integrated circuit of 1st Embodiment. Schematic which shows the structure of the semiconductor integrated circuit of 2nd Embodiment. Schematic which shows the structure of the semiconductor integrated circuit of 3rd Embodiment. Schematic which shows the structure of the semiconductor integrated circuit of 4th Embodiment. Schematic which shows the structure of the semiconductor integrated circuit of 5th Embodiment. Schematic which shows the structure of the system LSI of 6th Embodiment (A) Schematic diagram showing a configuration of a conventional semiconductor integrated circuit, (b) A diagram showing an equivalent circuit when Vg = Vdd in a conventional semiconductor integrated circuit, (c) Vg = The figure which shows the equivalent circuit when it is 0V

Explanation of symbols

1-7 Semiconductor integrated circuit 8 System LSI
11 CMOS logic circuit 12, 22, 82 Power shut-off switch 13, 23, 33, 43, 63, 73, 83 DAC
53 Band gap reference circuit 81 Power supply control register 82 Temperature sensor determination result storage register 83 Frequency setting register 84 Power supply voltage setting register 85 Decoder D1 to D4 Power supply domains R1, R3, R11, R21 Resistors R2, R12, R22 Variable resistors Mn1 to Mn8 N-channel MOSFET
Mp1-Mp5 P-channel MOSFET

Claims (10)

A CMOS logic circuit;
A switch circuit having a first MOSFET provided between a voltage supply source of the CMOS logic circuit and a power supply terminal of the CMOS logic circuit;
A first MOSFET connected to the drain of the second MOSFET; a first resistor connected to a drain of the second MOSFET; and a first resistor connected to a source of the first MOSFET. A digital-analog conversion circuit having two resistors,
A back gate of the first MOSFET is connected to a connection point of the first resistor and the second resistor;
A semiconductor integrated circuit in which a control signal supplied to the gate of the first MOSFET and a control signal supplied to the gate of the second MOSFET are common. The semiconductor integrated circuit according to claim 1,
The first MOSFET is an N-channel MOSFET;
The N-channel MOSFET is a semiconductor integrated circuit connected to a voltage supply source and a power supply terminal on the low voltage side of the CMOS logic circuit. The semiconductor integrated circuit according to claim 1,
The first MOSFET is a P-channel MOSFET;
The P-channel MOSFET is a semiconductor integrated circuit connected to a high voltage side voltage supply source and a power supply end of the CMOS logic circuit. A semiconductor integrated circuit according to any one of claims 1 to 3,
A semiconductor integrated circuit in which at least one of the first resistor and the second resistor is a variable resistor. A semiconductor integrated circuit according to any one of claims 1 to 3,
The semiconductor integrated circuit, wherein the first resistor and the second resistor are MOSFETs of the same type as the first MOSFET. A semiconductor integrated circuit according to any one of claims 1 to 5,
The digital-analog conversion circuit is a semiconductor integrated circuit including a band gap reference circuit. A semiconductor integrated circuit according to any one of claims 1 to 6,
The semiconductor integrated circuit, wherein the second resistor is a MOSFET having a unit transistor configuration in which a ratio of resistance values to the first MOSFET has an integer relationship. A semiconductor integrated circuit according to any one of claims 1 to 7,
The digital-analog converter circuit is a semiconductor integrated circuit connected to a power source different from the power source of the CMOS logic circuit and the switch circuit. A semiconductor integrated circuit according to any one of claims 1 to 8,
The switch circuit is composed of a plurality of MOSFETs,
A semiconductor integrated circuit in which the gates of the plurality of MOSFETs are individually controlled, and the logic of the gate of the second MOSFET is common to signals applied to the gates of the plurality of MOSFETs. An LSI system comprising the semiconductor integrated circuit according to any one of claims 1 to 9,
A group of registers including a power shutdown control register, a frequency setting register, a power supply voltage setting register, and a temperature sensor determination result storage register;
Based on the output of the register group, on / off of the switch circuit and the digital-analog converter circuit, and a decoder for adjusting the value of the second resistor,
LSI system with

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