JP2010093156A - Semiconductor optical element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that it is insufficient to suppress a leak current in high-temperature operation or large-current driving in a semiconductor optical element. <P>SOLUTION: A laminate structure in a mesa stripe shape is formed on a substrate made of InP. The laminate structure includes a lower clad layer, an active layer, and an upper clad layer. Buried layers containing In and P and having high resistance are disposed on a substrate on both sides of the laminate structure. A first coating layer made of a compound semiconductor containing Al as a group III element and P as a group V element is arranged between side surfaces of the laminate structure and the buried layers. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor optical device in which both sides of a mesa stripe-shaped laminated structure are embedded with embedded layers.

  With the increase in information traffic in recent years, demands on the characteristics of light sources used in optical transmission systems have become increasingly severe. For example, a semiconductor laser element used in a 10 Gb / s high-speed transmission system is required to have an uncooled operation that operates at a high temperature of 80 to 90 ° C. as well as high-speed direct modulation. In order to realize such an uncooled high-speed operation, it is preferable to employ a laser structure with low parasitic capacitance and low leakage current at high temperature. A so-called “high resistance embedded semiconductor laser element” in which both sides of a mesa stripe-shaped stacked structure including an active layer are embedded with a semi-insulating semiconductor material has a small parasitic capacitance and is suitable for high speed operation.

  Although the high resistance buried type semiconductor laser device has an advantage that the parasitic capacitance is small, the leakage current to the high resistance buried layer increases at the time of high temperature operation or large current driving. Due to the increase in the leakage current, the device characteristics are deteriorated such as a decrease in light output. Hereinafter, the reason why the leakage current increases will be described.

  The p-type InP cladding layer is usually doped with Zn as a p-type dopant. Further, Fe-doped InP is used for the semi-insulating buried layer. Since Fe and Zn have a property of easily diffusing each other, Zn is easily diffused into the semi-insulating buried layer. When Zn diffuses into the semi-insulating buried layer, the resistivity decreases and the leakage current to the buried layer increases.

  Fe forms a deep acceptor level in the band gap of InP and traps electrons but does not trap holes. When holes are injected from the p-type semiconductor layer into the semi-insulating buried layer, a leak current flows due to recombination of holes and electrons in the buried layer.

  When an AlGaInAs-based multiple quantum well structure of 1.3 μm band is used for the active layer, AlGaInAs having a composition wavelength of 1.0 to 1.1 μm is used for the barrier layer of the multiple quantum well structure. The lower end of the conduction band of AlGaInAs having a composition wavelength of 1.0 to 1.1 μm has substantially the same energy level as the lower end of the conduction band of InP. For this reason, electrons are likely to leak from the barrier layer to the buried layer. Electrons leaking into the buried layer cause a leakage current.

  By inserting a Ru-doped high-resistance InGaAlAs layer between the mesa stripe-shaped stacked structure and the buried layer, an increase in leakage current can be suppressed (Patent Document 1). Since Ru and Zn hardly diffuse each other, the diffusion of Zn into the Fe-doped semi-insulating buried layer is suppressed.

  By inserting a p-type InP layer and an InGaAlAs wide band gap layer between the mesa stripe-shaped stacked structure and the buried layer, carrier leakage to the buried layer can be suppressed ( Patent Document 2).

JP 2002-314196 A JP-A-8-255950

  In the prior art, the leakage current is not sufficiently suppressed during high-temperature operation or large current driving.

  An object of the present invention is to provide a semiconductor optical device suitable for suppressing leakage current.

A semiconductor optical device that solves the above problems is as follows.
A mesa stripe-shaped laminated structure formed on a substrate made of InP, in which a lower clad layer, an active layer, and an upper clad layer are laminated in this order;
A buried layer that is disposed on the substrate on both sides of the stacked structure, is lattice-matched to InP, and is formed of a compound semiconductor containing In and P;
A first covering layer disposed between a side surface of the stacked structure and the buried layer and made of a compound semiconductor containing Al as a group III element and P as a group V element;

  By disposing the first coating layer, carrier leakage from the stacked structure to the buried layer can be suppressed.

  Prior to describing the examples, the results of trial production performed by the present inventors will be described.

  FIG. 7A shows a cross-sectional view of the semiconductor laser device in the middle of the trial manufacture. A mesa stripe stacked structure 105 is formed on a substrate 100 made of n-type InP. The (100) plane of InP appears on the upper surface of the substrate 100, and the extending direction of the multilayer structure 105 is the [011] direction. The laminated structure 105 includes a lower cladding layer 101 made of n-type InP, an active layer 102 having a multiple quantum well structure made of an AlGaInAs-based compound semiconductor, and an upper cladding layer 103 made of p-type InP. A mask pattern 110 made of silicon oxide used as a mask during etching is formed on the upper cladding layer 103.

Using the mask pattern 110 as a selective growth mask, a coating layer 107 made of p-type In _0.52 Al _0.48 As is formed on the upper surface of the substrate 100 and on the side surface of the multilayer structure 105. The film was selectively grown to a thickness of 100 nm. In _0.52 Al _0.48 As lattice matches with InP. The film thickness and composition of the coating layer 107 formed on the upper surface of the substrate 100 and the side surface of the laminated structure 105 were evaluated by energy dispersive X-ray spectroscopy (TEM-EDX) using a transmission electron microscope.

  The thickness of the covering layer 107 formed on the side surface of the multilayer structure 105 was about 1/10 of the thickness of the covering layer 107 formed on the upper surface of the substrate 100. Further, the Al composition ratio of the coating layer 107 formed on the side surface of the laminated structure 105 was smaller than 0.48. That is, the band gap of the cover layer 107 on the side surface is smaller than the band gap of the cover layer 107 formed on the upper surface of the substrate. For this reason, a sufficient effect of suppressing the leakage current cannot be obtained.

  As shown in FIG. 7B, the coating layer 107 was selectively grown on the side surface so that the Al composition ratio was 0.48. At this time, on the upper surface of the substrate 100, the coating layer 107 was thicker and the Al composition ratio was larger than 0.48. Since the Al composition ratio is larger than 0.48, the covering layer 107 does not lattice match with the substrate 100 on the upper surface of the substrate 100. Since the coating layer 107 not lattice-matched grows thick, crystal defects are likely to occur.

  It was difficult to form the coating layer 107 having an Al composition with a large band gap on the side surface of the multilayer structure 105 without generating crystal defects on the upper surface of the substrate 100. In the embodiment described below, this problem is solved.

  With reference to FIG. 1A-FIG. 2F, the semiconductor optical element by Example 1 and its manufacturing method are demonstrated.

  As shown in FIG. 1A, on a semiconductor substrate 10 made of n-type InP having a (100) plane as a main surface, a lower cladding layer 11 made of n-type InP and having a thickness of 300 nm is formed by metal organic chemical vapor deposition (MOVPE). ) To grow. Note that MOCVD is applied to the growth of a compound semiconductor layer performed in a later step unless otherwise specified.

  As shown in FIG. 1B, a diffraction grating 11A is formed on the surface of the lower cladding layer 11 using photolithography and wet etching. The diffraction grating 11A has periodicity in the [011] direction, and its period is 200 nm. Further, the height difference of the unevenness constituting the diffraction grating 11A is 40 nm.

  An active layer 12 is formed on the lower cladding layer 11 on which the diffraction grating 11A is formed. The active layer 12 has a stacked structure in which a lower guide layer 12A, a multiple quantum well structure 12B, and an upper guide layer 12C are stacked in this order. The lower guide layer 12A and the upper guide layer 12C are made of non-doped AlGaInAs having a composition wavelength of 1.05 μm. The lower guide layer 12A has a thickness of 70 nm, and the upper guide layer 12C has a thickness of 50 nm.

  The multiple quantum well structure 12B includes barrier layers and well layers that are alternately stacked for 10 periods. The barrier layer is made of non-doped AlGaInAs having a composition wavelength of 1.05 μm, and the thickness of each is 10 nm. The well layer is made of non-doped AlGaInAs, each of which has a thickness of 5 nm and a photoluminescence (PL) wavelength of 1.3 μm.

  2A to 2F correspond to the cross section taken along one-dot chain line 2A-2A in FIG. 1B. That is, the direction perpendicular to the paper surface of FIGS. 2A to 2F corresponds to the [011] direction.

  As shown in FIG. 2A, a striped mesa mask pattern 25 having a width of 2 μm extending in the [011] direction is formed on the contact layer 14. For example, silicon oxide is used for the mesa mask pattern 25.

  As shown in FIG. 2B, etching is performed from the contact layer 14 to the surface layer portion of the semiconductor substrate 10 using the mesa mask pattern 25 as an etching mask. For this etching, dry etching is used. Thereby, the mesa stripe-shaped laminated structure 20 is formed. The height of the laminated structure 20 is 3 μm. The laminated structure 20 includes the lower cladding layer 11, the active layer 12, the upper cladding layer 13, and the contact layer 14.

  As shown in FIG. 2C, the coating layer 22 made of p-type InAlP is selectively grown on the upper surface of the semiconductor substrate 10 and on the side surfaces of the stacked structure 20 using the mesa mask pattern 25 as a mask for selective growth. Let The growth temperature is 600 ° C. The growth conditions are set so that the thickness is 15 nm on the side surface of the laminated structure 20 and the Al composition ratio is 20%. When grown under these conditions, crystal defects due to strain relaxation did not occur in the coating layer 22 on the side surface of the multilayer structure 20. In addition, no crystal defects occurred in the coating layer 22 on the upper surface of the semiconductor substrate 10.

  As shown in FIG. 2D, a buried layer 26 made of Fe-doped semi-insulating InP is selectively grown on the coating layer 22. As a material for the buried layer 26, another compound semiconductor that lattice matches with the semiconductor substrate 10 and contains In and P may be used. Further, instead of Fe, a dopant having a property of making the resistivity of the buried layer 26 higher than that of non-doped InP, for example, Ru, Ti, Co, Ni, etc., may be doped. The thickness of the buried layer 26 is about 3 μm. For this reason, the upper surface of the buried layer 26 has substantially the same height as the upper surface of the contact layer 14. The growth temperature is 600 ° C. After the buried layer 26 is formed, the mesa mask pattern 25 is removed as shown in FIG. 2E.

  As shown in FIG. 2F, the upper electrode 30 is formed on the contact layer 14 and the buried layer 26. Further, the lower electrode 31 is formed on the back surface of the semiconductor substrate 10. The upper electrode 30 has a three-layer structure of Au / Zn / Au, and the lower electrode 31 has a two-layer structure of AuGe / Au. By cleaving the semiconductor substrate 10 and performing end face coating or the like, a distributed feedback (DFB) laser element having a semi-insulating buried hetero (SIBH) structure is obtained.

FIG. 3A shows an energy band diagram of InP, In _0.8 Al _0.2 P, and AlGaInAs having a composition wavelength of 1.05 μm. InP corresponds to the buried layer 26, In _0.8 Al _0.2 P corresponds to the coating layer 22, and AlGaInAs corresponds to the barrier layer in the active layer 12. For reference, an energy band diagram in the case where In _0.8 Al _0.2 P is replaced with In _0.8 Ga _0.2 P is indicated by a broken line. Since the In _0.8 Al _0.2 P layer and the In _0.8 Ga _0.2 P layer on InP include strain, FIG. 3A considers energy shift due to strain.

  The lower ends of the conduction bands of InP and AlGaInAs are substantially equal energy levels. Therefore, when InP and AlGaInAs are brought into direct contact, that is, when the buried layer 26 is brought into direct contact with the laminated structure 20, electrons leak from the barrier layer in the active layer 12 to the buried layer 26. It's easy to do.

The energy level at the lower end of the conduction band of In _0.8 Al _0.2 P is higher than the energy level at the lower end of the conduction band of InP and AlGaInAs. For this reason, the coating layer 22 suppresses diffusion of electrons from the lower cladding layer 11 of n-type InP and diffusion of electrons from the barrier layer in the active layer 12. Furthermore, the energy level at the upper end of the valence band of In _0.8 Al _0.2 P is lower than the energy level at the upper end of the valence band of either InP or AlGaInAs. For this reason, the coating layer 22 suppresses the diffusion of holes from the upper clad layer 13 of p-type InP and the diffusion of holes from the barrier layer in the active layer 12.

When In _0.8 Al _0.2 P and In _0.8 Ga _0.2 P, which have the same Al composition and Ga composition and have almost the same magnitude of strain, are compared, In _0.8 Al _0.2 It can be seen that P forms a higher potential barrier. For this reason, in order to suppress the leakage current, it is preferable to use InAlP rather than InGaP for the coating layer 22. Thus, it is preferable to use a compound semiconductor containing In and Al as a group III element and P as a group V element for the coating layer 22. In addition, if AlP growth is difficult due to lattice constant mismatch, In may be included. Moreover, the effect which suppresses the leak of an electron and a hole becomes high by making the coating layer 22 contact the side surface of the laminated structure 20 directly.

The current-light output conversion efficiency η of the semiconductor optical device according to Example 1 was measured under the operating temperatures of 25 ° C. and 85 ° C. When the conversion efficiencies at the operating temperatures of 25 ° C. and 85 ° C. were η ₂₅ and η ₈₅ , respectively, η ₈₅ / η ₂₅ was about 65%. On the other hand, η ₈₅ / η ₂₅ of the semiconductor optical device having the structure in which the coating layer 22 is not disposed was about 55%. It was confirmed that the increase in leakage current during high temperature operation could be suppressed by inserting the covering layer 22.

  Since the InAlP coating layer 22 does not lattice match with InP, strain is inherent in the coating layer 22. If the coating layer 22 is too thick, the strain is relaxed and a large number of crystal defects are generated. Therefore, it is preferable that the thickness of the coating layer 22 be equal to or less than the maximum film thickness (critical film thickness) that allows growth without relaxing the strain in the coating layer 22.

As shown in FIG. 3B, when In _0.6 Al _0.4 P is used instead of In _0.8 Al _0.2 P, the potential barrier can be further increased. However, when the Al composition ratio is increased, the degree of lattice mismatch between InP and InAlP increases. For this reason, the critical film thickness becomes thin, and crystal defects such as misfit dislocations easily occur. It is preferable to set the Al composition ratio of the coating layer 22 in accordance with the desired height of the potential barrier and the allowable density of crystal defects.

  In Example 1, InAlP was selectively grown in the step shown in FIG. 2C under the conditions that the thickness of the coating layer 22 on the side surface of the multilayer structure 20 was 15 nm and the Al composition ratio was 20%. When grown under these conditions, the coating layer 22 was thinner than 15 nm and the Al composition ratio was lower than 20% on the upper surface of the semiconductor substrate 10.

  When InAlAs is used for the covering layer, as shown in FIGS. 7A and 7B, the film thickness of the covering layer 107 is relatively thick on the upper surface of the semiconductor substrate 100, and the Al composition ratio is relatively large. became. When InAlP is used for the coating layer 22, the film thickness relationship and the Al composition ratio relationship are completely reversed. On the upper surface of the semiconductor substrate 10, the Al composition ratio is reduced and the film thickness is reduced, so that crystal defects are less likely to occur. Therefore, when InAlP is used for the coating layer 22, crystal defects are less likely to occur in the entire region of the coating layer 22.

  FIG. 4 shows the distribution of the Al composition ratio of the coating layer 22 of the semiconductor optical device according to Example 2. A coating layer 22 made of InAlP is formed on the side surface of the mesa stripe-shaped laminated structure 20. The Al composition ratio of the covering layer 22 on the side surface decreases in a direction away from the laminated structure 20.

  The potential barrier at the interface between the barrier layer in the active layer 12 and the coating layer 22 can be increased by relatively increasing the Al composition ratio of the portion in contact with the laminated structure 20. Further, by reducing the Al composition ratio in the direction away from the laminated structure 20, the strain in the coating layer 22 can be reduced and the occurrence of crystal defects can be suppressed.

  With reference to FIG. 5A-FIG. 6F, the semiconductor optical element by Example 3 and its manufacturing method are demonstrated.

  As shown in FIG. 5A, on the semiconductor substrate 50 made of n-type InP having the (100) plane as the main surface, a lower cladding layer 51 made of n-type InP and having a thickness of 300 nm is grown by MOCVD. Note that MOCVD is applied to the growth of a compound semiconductor layer performed in a later step unless otherwise specified.

  On the lower clad layer 51, a diffraction grating formation layer 52 of n-type InGaAsP having a composition wavelength of 1.15 μm and having a thickness of 60 nm is formed.

  As shown in FIG. 5B, a groove having a depth of 80 nm that penetrates the diffraction grating formation layer 52 is formed by photolithography and dry etching. The remaining portion of the diffraction grating forming layer 52 becomes the diffraction grating 52A. The diffraction grating 52A has periodicity in the [011] direction, and the period is 200 nm.

  As shown in FIG. 5C, a spacer layer 53 made of n-type InP is formed on the lower cladding layer 51 so as to embed the diffraction grating 52A. The surface of the spacer layer 53 becomes flat. An active layer 54 is formed on the spacer layer 53. The active layer 54 includes a lower guide layer 54A, a multiple quantum well structure 54B, and an upper guide layer 54C. In Example 1 shown in FIG. 1B, the thickness of the lower guide layer 12A is set to 70 nm. However, in Example 3, since the base surface is flat, the thickness of the lower guide layer 54A is set to 50 nm. Other configurations are the same as those of the active layer 12 of the first embodiment.

  An upper cladding layer 55 made of p-type InP and having a thickness of 200 nm is formed on the active layer 54.

  The cross-sectional views in FIGS. 6A to 6F correspond to the cross section taken along the alternate long and short dash line 6A-6A in FIG. 5C. That is, the direction perpendicular to the paper surface of FIGS. 6A to 6F corresponds to the [011] direction.

  As shown in FIG. 6A, a striped mesa mask pattern 58 having a width of 2 μm extending in the [011] direction is formed on the upper cladding layer 55. For the mesa mask pattern 58, for example, silicon oxide is used.

  As shown in FIG. 6B, by using the mesa mask pattern 58 as an etching mask, dry etching is performed from the upper cladding layer 55 to the surface layer portion of the lower cladding layer 51, thereby forming a mesa stripe-shaped laminated structure 60. The etching depth is, for example, 1.5 μm. The laminated structure 60 includes a lower cladding layer 51, an active layer 54, and an upper cladding layer 55.

  As shown in FIG. 6C, by using the mesa mask pattern 58 as a selective growth mask, Ru-doped semi-insulating InAlP is selectively grown on the upper surface of the lower cladding layer 51 and the side surface of the laminated structure 60, The covering layer 62 is formed. A first buried layer 63 is formed on the covering layer 62 by selectively growing Fe-doped semi-insulating InP. The thickness of the first buried layer 63 is, for example, 1 μm. By selectively growing n-type InP on the first buried layer 63, the second buried layer 64 is formed. The thickness of the second buried layer 64 is, for example, 0.4 μm. The growth temperature of the covering layer 62, the first buried layer 63, and the second buried layer 64 is, for example, 600 ° C.

  The covering layer 62 is grown under the condition that the thickness is 30 nm on the side surface of the multilayer structure 60 and the Al composition ratio decreases from 30% to 0% in the direction away from the multilayer structure 60. When the Al composition ratio is changed in this way, the potential barrier can be increased without causing strain relaxation in the coating layer 62 as in the case of the second embodiment. As shown in FIG. 6D, the upper cladding layer 55 is exposed by removing the mesa mask pattern 58.

  As shown in FIG. 6E, an upper cladding layer 70 made of p-type InP and having a thickness of 3 μm is formed on the upper cladding layer 55 and the second buried layer 64. Further, a contact layer 71 made of p-type InGaAs is formed on the upper cladding layer 70.

  As shown in FIG. 6F, the upper electrode 75 is formed on the contact layer 71. A lower electrode 76 is formed on the back surface of the semiconductor substrate 50. By cleaving the semiconductor substrate 50 and performing end surface coating or the like, a DFB laser element having a semi-insulating planarization buried hetero (SIPBH) structure can be obtained. As in the case of the first embodiment, it is possible to suppress an increase in leakage current by inserting the covering layer 62.

When the temperature characteristic of the current-light output conversion efficiency η of the DFB laser device according to Example 3 was measured, η ₈₅ / η ₂₅ was about 70%. Η ₈₅ / η ₂₅ of the DFB laser element having the structure in which the coating layer 62 is not inserted was 55%. Thus, the effect of suppressing the increase in leakage current by inserting the coating layer 62 was confirmed.

  In the first to third embodiments, the active layer employs an AlGaInAs-based multiple quantum well structure. The active layer includes other materials that are lattice-matched to the InP substrate, such as InGaAsP-based and GaInNAs-based compound semiconductor bulks. A structure, a multiple quantum well structure, or the like may be adopted.

  In the first to third embodiments, the longitudinal direction of the mesa stripe laminated structure and the [011] direction are made parallel, but an oblique mesa structure inclined from the [011] direction may be adopted. When the oblique mesa structure is employed, the waveguide direction is disposed obliquely with respect to the cleavage plane.

  In the first to third embodiments, the covering layers 22 and 62 are brought into contact with the mesa stripe-shaped laminated structures 20 and 60, but a p-type InP layer may be inserted therebetween.

  In the first to third embodiments, the coating layers 22 and 62 are applied to the DFB laser element, but may be applied to other semiconductor optical elements. For example, the present invention may be applied to a semiconductor optical amplifier (SOA). Further, the present invention can be applied to an optical integrated element in which a semiconductor laser element and an optical modulator are integrated on the same substrate, an optical integrated element in which an SOA and an optical modulator are integrated on the same substrate, and the like.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

FIG. 6 is a cross-sectional view (part 1) of the semiconductor optical device according to the first embodiment when it is being manufactured; FIG. 6 is a cross-sectional view (part 2) of the semiconductor optical device according to the first embodiment when it is being manufactured; FIG. 6 is a cross-sectional view (part 3) of the semiconductor optical device according to Example 1 in the middle of manufacturing and a cross-sectional view when completed. FIG. 4 is an energy band diagram of a buried layer, a cover layer, and a barrier layer of the optical semiconductor element according to Example 1. 4 is a graph showing a distribution of Al composition ratio in a coating layer of a semiconductor optical device according to Example 2. FIG. 10 is a cross-sectional view (part 1) of the semiconductor optical device according to the third embodiment when it is being manufactured; FIG. 13 is a cross-sectional view (part 2) of the semiconductor optical device according to Example 3 in the middle of manufacture. FIG. 10 is a cross-sectional view (part 3) of the semiconductor optical device according to Example 3 in the middle of manufacturing and a cross-sectional view when completed. It is sectional drawing of the semiconductor optical element by a comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Lower clad layer 11A Diffraction grating 12 Active layer 12A Lower guide layer 12B Multiple quantum well structure 12C Upper guide layer 13 Upper clad layer 14 Contact layer 20 Mesa stripe laminated structure 22 Cover layer 25 Mesa mask pattern 26 Fill Embedded layer 50 Semiconductor substrate 51 Lower cladding layer 52 Diffraction grating forming layer 52A Diffraction grating 53 Spacer layer 54 Active layer 54A Lower guide layer 54B Quantum well structure 54C Upper guide layer 55 Upper cladding layer 58 Mesa mask pattern 60 Mesa stripe laminated structure Body 62 Covering layer 63 First buried layer 64 Second buried layer 70 Upper clad layer 71 Contact layer 75 Upper electrode 76 Lower electrode 100 Substrate 101 Lower clad layer 102 Active layer 103 Upper clad layer 105 Mesa stripe laminated structure Body 107 covering 110 mask pattern

Claims (5)

A mesa stripe-shaped laminated structure formed on a substrate made of InP, in which a lower clad layer, an active layer, and an upper clad layer are laminated in this order;
A buried layer that is disposed on the substrate on both sides of the stacked structure, is lattice-matched to InP, and is formed of a compound semiconductor containing In and P;
A semiconductor optical device having a first covering layer disposed between a side surface of the multilayer structure and the buried layer and made of a compound semiconductor containing Al as a group III element and P as a group V element.   2. The semiconductor optical device according to claim 1, wherein an Al composition ratio of the first coating layer is decreased in a direction away from the laminated structure. Further, a second coating layer that covers the upper surface of the substrate on both sides of the multilayer structure, is continuous with the first coating layer, includes Al as a group III element, and includes P as a group V element. Have
The first coating layer and the second coating layer are formed of a compound semiconductor having a composition that does not lattice match with InP, and the first coating layer and the second coating layer have a thickness that does not relax the inherent strain. The semiconductor optical device according to claim 1 or 2.   4. The semiconductor optical device according to claim 1, wherein the active layer has a quantum well structure made of an AlGaInAs-based compound semiconductor material. 5.   5. The semiconductor optical device according to claim 1, wherein the first covering layer is in contact with a side surface of the multilayer structure.

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