JP2010086628A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the conductance of a non-selective cell from degrading while preventing the occurrence of read disturbance phenomenon even when a coupling capacity between adjacent cells is increased in a NAND flash memory. <P>SOLUTION: A control circuit 5 controls so that, when a read-out is performed from a memory cell MCx connected to a word line WLxj, a read-out voltage Vgx corresponded to a value stored in the memory cell MCx is applied to the word line WLxj, and a pass voltage Vr for turning memory cells MC0 to MCx-2, MCx+2 to MCn to ON state is applied to word lines WL0j to WLx-2j, WLx+2j to WLnj, respectively, and a pass voltage Vr+α which is changed according to the read-out voltage Vgx so as to become higher than the pass voltage Vr, is applied to word lines WLx-1j, WLx1j, respectively. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and is particularly suitable for application to a read voltage application method in a NAND flash memory.

A NAND flash memory is composed of a NAND string in which a plurality of memory cells are connected in series, and it is known that higher integration is easier than a NOR type EEPROM (Patent Document 1).
On the other hand, as the capacity of the flash memory is increased, the memory cells are being miniaturized. As the memory cell is further miniaturized, the interval between the memory cells is narrowed, so that the coupling capacity between adjacent memory cells is increased. For this reason, the floating gate voltage of the memory cell is influenced not only by the influence of the control gate voltage of the own memory cell but also by the floating gate voltage of an adjacent cell adjacent to the own memory cell.

  Here, in the NAND flash memory, in order to read data from a selected cell, it is necessary to turn on an unselected cell included in the same NAND string as the selected cell. Therefore, even when the coupling capacitance between adjacent cells increases, the control gate voltage applied to the non-selected cells is increased in order to ensure that the non-selected cells are turned on when data is read from the selected cells. There is a need to.

  However, if the control gate voltage applied to the non-selected cell is increased when reading data from the selected cell, the tunnel current tends to flow through the tunnel oxide film of the non-selected cell. Rewrite phenomenon (read disturb phenomenon) occurs. Therefore, in the conventional NAND flash memory, when reading data from the selected cell, the control gate voltage applied to the non-selected cell cannot be increased, and the coupling capacitance between adjacent cells increases. Since the conductance of unselected cells adjacent to the selected cell is reduced, the cell current is reduced, and the read speed is deteriorated.

Japanese Patent Laid-Open No. 2005-100548

  Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory capable of suppressing a decrease in conductance of a non-selected cell while preventing the occurrence of a read disturb phenomenon even when the coupling capacitance between adjacent cells is increased. Is to provide a device.

  In order to solve the above-described problem, according to one aspect of the present invention, memory cells capable of storing multi-value information of three or more values are connected in series, and the series connection is performed at both ends of the series-connected memory cell group. A memory cell array in which NAND strings having select transistors capable of selecting the selected memory cell group are arranged in a matrix, bit lines connecting a plurality of NAND strings in the column direction, and memory cells in the NAND string; A word line connecting memory cells in the NAND string adjacent in the row direction orthogonal to the column direction, a column decoder circuit for selecting the bit line, a row decoder circuit for selecting the word line, and the bit And a control circuit that performs writing and reading of a selected memory cell selected by the line and the word line The control circuit applies a read voltage corresponding to a value stored in the selected memory cell to the first word line connected to the selected memory cell when reading the selected memory cell, and the NAND circuit A non-selected memory cell connected to the third word line is turned on for a third word line other than the first word line of the string and the second word line adjacent to the first word line. And a second pass voltage changed according to the read voltage so as to be higher than the first pass voltage is applied to the second word line. A nonvolatile semiconductor memory device is provided.

  Further, according to one aspect of the present invention, memory cells capable of storing multi-value information of three values or more are connected in series, and the memory cells connected in series are selected at both ends of the memory cells connected in series. A memory cell array in which NAND strings having possible selection transistors are arranged in a matrix, a bit line in which a plurality of NAND strings are connected in a column direction, a memory cell in the NAND string and a row orthogonal to the column direction. A word line connecting memory cells in the NAND string adjacent in the direction, a column decoder circuit for selecting the bit line, a row decoder circuit for selecting the word line, and the bit line and the word line. A control circuit for writing to and reading from the selected selected memory cell, and the control circuit includes the selection circuit. At the time of reading the memory cell, a read voltage corresponding to a value stored in the selected memory cell is applied to the first word line connected to the selected memory cell, and the first word line of the NAND string is applied. And a third word line other than the second word line adjacent to the first word line has a first pass voltage for turning on an unselected memory cell connected to the third word line. The conductance between the non-selected memory cell connected to the second word line and the non-selected memory cell connected to the third word line is mutually connected to the second word line. A non-volatile semiconductor memory device is provided, wherein a second pass voltage set so as to match is applied.

  According to one embodiment of the present invention, memory cells having floating gates and capable of storing multi-value information of three or more values are connected in series, and connected in series to both ends of the memory cells connected in series. A memory cell array in which NAND strings each having a selection transistor capable of selecting a memory cell group are arranged in a matrix, a bit line in which a plurality of NAND strings are connected in a column direction, a memory cell in the NAND string, and the column A word line connecting memory cells in the NAND string adjacent in the row direction orthogonal to the direction, a column decoder circuit for selecting the bit line, a row decoder circuit for selecting the word line, the bit line, and A control circuit for writing to and reading from the selected memory cell selected by the word line. When reading the selected memory cell, the circuit applies a read voltage corresponding to a value stored in the selected memory cell to the first word line connected to the selected memory cell, and In the third word line other than the first word line and the second word line adjacent to the first word line, the unselected memory cells connected to the third word line are turned on. A pass voltage of 1 is applied, and the second word line is connected between an unselected memory cell connected to the second word line and an unselected memory cell connected to the third word line. A non-volatile semiconductor memory device is provided in which a second pass voltage set so that the voltages of the floating gates coincide with each other is applied.

Further, according to one aspect of the present invention, memory cells capable of storing multi-value information of three values or more are connected in series, and the memory cells connected in series are selected at both ends of the memory cells connected in series. A memory cell array in which NAND strings having possible selection transistors are arranged in a matrix, a bit line in which a plurality of NAND strings are connected in a column direction, a memory cell in the NAND string and a row orthogonal to the column direction. A word line connecting memory cells in the NAND string adjacent in the direction, a column decoder circuit for selecting the bit line, a row decoder circuit for selecting the word line, and the bit line and the word line. A control circuit that performs writing and reading of the selected cell,
The control circuit applies a read voltage corresponding to a value stored in the selected memory cell to the first word line connected to the selected memory cell when reading the selected cell, and the NAND string In the third word line other than the first word line and the second word line adjacent to the first word line, the non-selected memory cells connected to the third word line are turned on. A first pass voltage is applied so that a decrease in conductance due to a coupling capacitance between the unselected memory cell connected to the second word line and the selected memory cell is canceled in the second word line. A non-volatile semiconductor memory device is provided in which a second pass voltage set to (1) is applied.

  According to one embodiment of the present invention, memory cells having floating gates and capable of storing multi-value information of three or more values are connected in series, and connected in series to both ends of the memory cells connected in series. A memory cell array in which NAND strings each having a selection transistor capable of selecting a memory cell group are arranged in a matrix, a bit line in which a plurality of NAND strings are connected in a column direction, a memory cell in the NAND string, and the column A word line connecting memory cells in the NAND string adjacent in the row direction orthogonal to the direction, a column decoder circuit for selecting the bit line, a row decoder circuit for selecting the word line, the bit line, and A control circuit for writing to and reading from the selected memory cell selected by the word line. When reading the selected memory cell, the circuit applies a read voltage corresponding to a value stored in the selected cell to the first word line connected to the selected memory cell, so that the first word line of the NAND string For a third word line other than one word line and a second word line adjacent to the first word line, a first non-selected memory cell connected to the third word line is turned on. Pass voltage is applied to the second word line, and the decrease in the floating gate voltage due to the coupling capacitance with the selected memory cell for the non-selected memory cell connected to the second word line is canceled out. A non-volatile semiconductor memory device characterized by applying a second pass voltage set as described above is provided.

  As described above, according to the present invention, even when the coupling capacity between adjacent cells increases, it is possible to suppress the decrease in the conductance of the non-selected cells while preventing the occurrence of the read disturb phenomenon. Become.

  Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. In the following embodiments, a NAND flash memory will be described as an example of a nonvolatile semiconductor memory device.
In FIG. 1, a NAND flash memory is provided with a memory cell array 1, a sense amplifier circuit 2, a column decoder circuit 3, a row decoder circuit 4, and a control circuit 5. In the memory cell array 1, a plurality of bit lines BL are arranged in the column direction (up and down direction in FIG. 1), and a plurality of word lines WL are arranged in the row direction (left and right direction in FIG. 1). The sense amplifier circuit 2 is connected to the bit line BL of the memory cell array 1, and the column decoder circuit 3 is connected to the sense amplifier circuit 2. The row decoder circuit 4 is connected to the word line WL of the memory cell array 1. Further, a control circuit 5 is connected to the sense amplifier circuit 2, the column decoder circuit 3, and the row decoder circuit 4.

  Here, in the memory cell array 1, memory cells that store multi-value information of three or more values based on the amount of charge accumulated in the floating gate electrode are arranged in a matrix. In the NAND flash memory, a NAND string having a memory cell group in which a plurality of memory cells are connected in series in the column direction and selection transistors that are arranged at both ends of the memory cell group and can select the memory cell group is a matrix. Arranged in a shape. A plurality of NAND strings are connected to the bit line BL in the column direction, and each NAND string is connected to the active region of the memory cell, so that the NAND string can be selected for each column. The word line WL connects the memory cell in the NAND string and the memory cell in the NAND string adjacent to the NAND string in the row direction, and is connected to the control gate electrode of the memory cell. Can be selected. The sense amplifier circuit 2 can amplify the voltage applied to the bit line BL during writing and reading for each bit line BL. The column decoder circuit 3 can select the bit line BL connected to the NAND string including the memory cell selected at the time of writing and reading. The row decoder circuit 4 can select the bit line BL connected to the selected memory cell at the time of writing and reading. The control circuit 5 can write, read and erase selected cells selected by the bit line BL and the word line WL.

FIG. 2 is a block diagram showing a schematic configuration of the memory cell array 1 of FIG.
2, m + 1 (m is an integer of 2 or more) bit lines BL0 to BLm are provided as the bit lines BL in FIG. 1, and the bit lines BL0 to BLm are arranged in parallel to each other. The sense amplifier circuit 2 in FIG. 1 is provided with m + 1 sense amplifiers SA0 to SAm corresponding to the bit lines BL0 to BLm, respectively. In the example of FIG. 2, the method of providing the sense amplifiers SA0 to SAm for each of the bit lines BL0 to BLm has been described. However, a column selection switch is provided between the memory cell array 1 and the sense amplifier circuit 2 of FIG. A sense amplifier may be shared between adjacent odd-numbered and even-numbered bit lines BL0 to BLm.

  1 includes k + 1 (k is an integer of 2 or more) memory blocks MB0 to MBk, and the memory blocks MB0 to MBk are arranged in the column direction along the bit lines BL0 to BLm. Has been placed. Here, in each of the memory blocks MB0 to MBk, a NAND string MS is provided for each of the bit lines BL0 to BLm. The NAND string MS includes a memory cell group including n + 1 (n is an integer of 2 or more) memory cells MC0 to MCn, and select gate transistors SG1 and SG2 provided at both ends of the memory cell group. The memory cells MC0 to MCn are connected in series with each other, and a select gate transistor SG1 is connected in series to the memory cell MC0 at one end, and a select gate transistor SG2 is connected in series to the memory cell MCn at the other end.

  One end of the NAND string MS provided for each of the bit lines BL0 to BLm is commonly connected to the cell source line CSL via the selection gate transistor SG1, and the other end of the NAND string MS is connected to the bit line BL0 via the selection gate transistor SG2. To BLm, respectively.

  In the memory cell array 1, word lines WL0j to WLnj and select gate lines SGSj and SGDj are arranged so as to be orthogonal to the bit lines BL0 to BLm. Here, the word lines WL0j to WLnj are respectively connected to the control gate electrodes of the memory cells MC0 to MCn, and the selection gate lines SGSj and SGDj are respectively connected to the selection gate electrodes of the selection gate transistors SG1 and SG2.

FIG. 3 is a cross-sectional view showing a schematic configuration when the NAND string MS is cut along the direction of the bit line BLy.
In FIG. 3, an N well 12 is formed in a P-type semiconductor substrate 11, and a P well 13 is formed in the N well 12. A stacked structure in which a tunnel oxide film 15, a floating gate electrode 16, an intergate insulating film 17 and a control gate electrode 18 are sequentially stacked is disposed on the P well 13 at a predetermined interval. The memory cells MC0 to MCn shown in FIG. 2 are configured by forming the N-type impurity diffusion layer 14 disposed between the P-type well 13 as the source / drain.

  Further, selection gate electrodes 20 stacked on the gate insulating film 19 are formed next to the control gate electrodes 18 constituting the memory cells MC0 and MCn, respectively, and N arranged on both sides of the selection gate electrode 20 are formed. The selection impurity transistors SG1 and SG2 of FIG. 2 are configured by forming the type impurity diffusion layer 14 as the source / drain in the P well 13.

Then, word lines WL0j to WLnj are respectively connected to the control gate electrodes 18 constituting the memory cells MC0 to MCn of FIG. 2, and the selection gate electrodes 20 constituting the selection gate transistors SG1 and SG2 of FIG. The select gate lines SGSj and SGDj are connected to each other.
Here, a coupling capacitor C1 is formed between the floating gate electrode 16 of the memory cell MCx (x is an integer not smaller than 0 and not larger than n) connected to the word line WLxj, and the P well 13. A coupling capacitance C2 is formed between them. Further, the floating gate electrode 16 of the memory cell MCx has a coupling capacitance with the floating gate electrode 16 of the memory cells MCx−1 and MCx + 1 respectively connected to the word lines WLx−1j and WLx + 1j adjacent to the word line WLxj. C3 and C4 are respectively formed, and coupling capacitors C5 and C6 are respectively formed between the control gate electrodes 18 of the memory cells MCx−1 and MCx + 1.

  When the memory cells MC0 to MCn are miniaturized as the capacity of the flash memory is increased, the distance between the memory cells MC0 to MCn is reduced, and the coupling capacitors C3 and C4 are increased. For this reason, the voltage of the floating gate electrode 16 of the memory cell MCx is not only influenced by the voltage of the floating gate electrode 16 of its own memory cell MCx, but also the floating of the memory cells MCx−1 and MCx + 1 adjacent to its own memory cell MCx. It is also affected by the voltage of the gate electrode 16.

  When reading from the memory cell MCx connected to the word line WLxj, in the NAND flash memory, all the memory cells MC0 to MCx−1 and MCx + 1 to MCn in the NAND string MS including the memory cell MCx are turned on. Therefore, the pass voltages applied to the word lines WL0j to WLx-1j and WLx + 1j to WLnj are set so as to be higher than the read voltage applied to the word line WLxj.

Therefore, the voltages of the floating gate electrodes 16 of the memory cells MCx−1 and MCx + 1 connected to the word lines WLx−1j and WLx + 1j are affected by the coupling capacitances C3 and C4 between the floating gate electrodes 16 of the memory cells MCx. Is lowered to lower.
As a result, when reading is performed from the memory cell MCx connected to the word line WLxj, if all the pass voltages applied to the word lines WL0j to WLx-1j and WLx + 1j to WLnj are set to the same value, the word lines WLx-1j, Conductances of the memory cells MCx-1 and MCx + 1 connected to WLx + 1j are smaller than conductances of the memory cells MC0 to MCx-2 and MCx + 2 to MCn connected to the word lines WL0j to WLx-2j and WLx + 2j to WLnj, respectively. .

  Here, when reading data from the memory cell MCx connected to the word line WLxj, the control circuit 5 of FIG. 1 is affected by the coupling capacitances C3 and C4 with the floating gate electrode 16 of the memory cell MCx. In order to compensate for a decrease in conductance of the memory cells MCx−1 and MCx + 1 connected to WLx−1j and WLx + 1j, respectively, a read voltage Vgx corresponding to a value stored in the memory cell MCx is applied to the word line WLxj. A pass voltage Vr for turning on the memory cells MC0 to MCx-2 and MCx + 2 to MCn is applied to the word lines WL0j to WLx-2j and WLx + 2j to WLnj, and a pass is applied to the word lines WLx-1j and WLx + 1j. The pass voltage Vr + α changed according to the read voltage Vgx so as to be higher than the voltage Vr. α is able to apply a positive value).

FIG. 4 is a diagram showing the relationship between the voltage Vgx applied to the word line WLxj in FIG. 2 and the voltage Vr + α applied to the word lines WLx−1j and WLx + 1j adjacent to the word line WLxj.
In FIG. 4, as the read voltage Vgx applied to the word line WLxj decreases due to the coupling capacitors C3 and C4 between the memory cell MCx and the floating gate electrode 16, the floating of the memory cells MCx−1 and MCx + 1. The voltage of the gate electrode 16 decreases, and the conductance of the memory cells MCx−1 and MCx + 1 decreases.
Therefore, the decrease in conductance of the memory cells MCx−1 and MCx + 1 can be compensated by increasing the value of α as the read voltage Vgx applied to the word line WLxj decreases.

That is, when reading from the memory cell MCx connected to the word line WLxj, the control circuit 5 conducts the memory cells MCx−1 and MCx + 1 by the coupling capacitors C3 and C4 with the floating gate electrode 16 of the memory cell MCx. The pass voltage Vr + α can be set so as to cancel out the decrease in.
For example, when the control circuit 5 performs reading from the memory cell MCx connected to the word line WLxj, the memory cells MC0 to MCx-2 and MCx + 2 to MCn connected to the word lines WL0j to WLx-2j and WLx + 2j to WLnj, respectively. In addition, the pass voltage Vr + α can be set so that the conductances coincide with each other between the memory cells MCx−1 and MCx + 1 connected to the word lines WLx−1j and WLx + 1j, respectively.

Alternatively, when reading data from the memory cell MCx connected to the word line WLxj, the control circuit 5 floats the memory cells MCx−1 and MCx + 1 by the coupling capacitors C3 and C4 with the floating gate electrode 16 of the memory cell MCx. The pass voltage Vr + α can be set so that the decrease in the voltage of the gate electrode 16 is canceled out.
For example, when the control circuit 5 performs reading from the memory cell MCx connected to the word line WLxj, the memory cells MC0 to MCx-2 and MCx + 2 to MCn connected to the word lines WL0 to WLx-2j and WLx + 2j to WLn, respectively. And the pass voltage Vr + α can be set so that the voltages of the floating gate electrodes 16 match each other between the memory cells MCx−1 and MCx + 1 connected to the word lines WLx−1j and WLx + 1j, respectively.

Specifically, for example, four values can be stored in the memory cells MC0 to MCn, and the threshold value at this time is set to E level, A level, B level, C level from the lowest. And
In this case, the read voltage Vgx and the pass voltages Vr, Vr + α can be set for each level as follows.
E level: Vgx = 0.0V, Vr = 6.0V, Vr + α = 7.3V
A level: Vgx = 0.5V, Vr = 6.0V, Vr + α = 6.9V
B level: Vgx = 1.5V, Vr = 6.0V, Vr + α = 6.7V
C level: Vgx = 2.8V, Vr = 6.0V, Vr + α = 6.5V

1 and 2, during the erase operation, the control circuit 5 applies a high voltage of about 20 V to the P well 13 via the row decoder circuit 4, for example. In the erase target block, 0 V is applied to the control gate electrode 18 via the word lines WL0j to WLnj. In the erase prohibition block, the word lines WL00 to WLn0,..., WL0j-1 to WLnj-1, WL0j + 1 to WLnj + 1,..., WL0k to WLnk are brought into a floating state.
Then, a high voltage is prevented from being applied to the tunnel oxide film 15 of the erase-inhibited block, while a high voltage is applied to the tunnel oxide film 15 of the block to be erased, and a tunnel current is applied to the tunnel oxide film 15 of the erase-inhibited block. While the flow is prohibited, a tunnel current flows through the tunnel oxide film 15 of the block to be erased. As a result, electrons are selectively extracted from the floating gate electrode 16 of the block to be erased, so that the threshold voltage of the block to be erased is shifted from positive to negative. Data can be erased.

Further, when writing to a selected cell selected by the word line WLxj and the bit line BLy (y is an integer not smaller than 0 and not larger than m) at the time of the write operation, the control circuit 5 passes, for example, the column decoder circuit 3 Then, 0 V is applied to the bit line BLy, and a voltage of about Vcc (power supply voltage) is applied to the bit lines BL0 to BLy−1 and BLy + 1 to BLm. Vcc can be set to 3.5 V, for example.
For example, the control circuit 5 applies a voltage Vd of about Vcc to the selection gate line SGDj of the memory block MBj including the selected cell via the row decoder circuit 4, and applies to the selection gate line SGSj of the memory block MBj. A voltage Vs of 0V is applied.
Further, for example, the control circuit 5 applies a high voltage of about 20 V to the word line WLxj via the row decoder circuit 4, and applies a voltage of about 10 V to the word lines WL0j to WLx-1j and WLx + 1j to WLnj.

  Then, the select gate transistor SG1 is turned off, and the memory block MBj including the selected cell is disconnected from the cell source line CSL. Further, the select gate transistor SG2 included in the NAND string MS including the selected cell is turned on, and the source / drain of the NAND string MS including the selected cell is connected to the bit line BLy.

On the other hand, in the NAND string MS that does not include the selected cell, the voltage Vd of the selection gate line SGDj is set to Vcc, and then Vcc is applied to the bit lines BL0 to BLy−1 and BLy + 1 to BLm connected to the NAND string MS. Is applied. Therefore, when the source / drain potential of the NAND string MS not including the selected cell becomes Vcc−Vth, the selection gate transistor SG2 included in the NAND string MS is cut off. However, Vth is the threshold voltage of the select gate transistor SG2.
As a result, the channel potential of the NAND string MS including the selected cell becomes 0 V, and the channel of the NAND string not including the selected cell is in a floating state, and the channel potential of the NAND string has the capacitance with the word lines WL0j to WLnj. It rises from Vcc-Vth by coupling.

  Therefore, a high voltage is prevented from being applied to the tunnel oxide film 15 of the non-selected cell, while a high voltage is applied to the tunnel oxide film 15 of the selected cell, and a tunnel current is applied to the tunnel oxide film 15 of the non-selected cell. While the flow is prohibited, a tunnel current flows through the tunnel oxide film 15 of the selected cell. As a result, electrons are selectively injected into the floating gate electrode 16 of the selected cell, whereby the threshold voltage of the selected cell is shifted from negative to positive, and writing to the selected cell is performed. Here, by adjusting the amount of electrons injected into the floating gate electrode 16 of the selected cell, the threshold voltage of the selected cell can be set to any level of E, A, B, and C. Four values can be written to the cell.

In the read operation, when reading from the selected cell selected by the word line WLxj and the bit line BLy, the control circuit 5 uses, for example, the cell source voltage Vc of the cell source line CSL via the row decoder circuit 4. Is set to 0 V, and voltages Vd and Vs of about Vcc are respectively applied to the selection gate lines SGDj and SGSj of the memory block MBj including the selected cell, thereby turning on the selection gate transistors SG1 and SG2.
Then, the NAND string MS of the memory block MBj is connected to the bit lines BL0 to BLm, and is also connected to the cell source line CSL, and the bit lines BL0 to BLm and the cell source are respectively connected via the NAND strings of the memory block MBj. A conduction path between the line CSL is secured.

  The control circuit 5 applies, for example, a pass voltage Vr of 6V to the word lines WL0j to WLx-2j and WLx + 2j to WLnj via the row decoder circuit 4, while 0V, 0.5V, 1.. Read voltage Vgx of 5V and 2.8V is sequentially applied. When the read voltage Vgx of 0V is applied to the word line WLxj, the control circuit 5 applies the pass voltage Vr + α of 7.3V to the word lines WLx-1j and WLx + 1j, and 0.5V to the word line WLxj. When the read voltage Vgx is applied, the pass voltage Vr + α of 6.9 V is applied to the word lines WLx-1j and WLx + 1j, and the read voltage Vgx of 1.5 V is applied to the word line WLxj. When a pass voltage Vr + α of 6.7 V is applied to the word lines WLx-1j and WLx + 1j and a read voltage Vgx of 2.8 V is applied to the word line WLxj, the word lines WWLx-1j and WLx + 1j are 6.5 V. A pass voltage Vr + α is applied.

  Then, when the memory cells MC0 to MCx-1 and MCx + 1 to MCn are turned on and data corresponding to the E level is stored in the memory cell MCx, a read voltage Vgx of 0 V is applied to the word line WLxj. Current flows through the memory cell MCx. When data corresponding to the A level is stored in the memory cell MCx, a current flows through the memory cell MCx when the read voltage Vgx of 0.5 V is applied to the word line WLxj. When data corresponding to the B level is stored in the memory cell MCx, a current flows through the memory cell MCx when the read voltage Vgx of 1.5 V is applied to the word line WLxj. When data corresponding to the C level is stored in the memory cell MCx, a current flows through the memory cell MCx when the read voltage Vgx of 2.8 V is applied to the word line WLxj.

  Then, when the read voltage Vgx of 0V, 0.5V, 1.5V, and 2.8V is sequentially applied to the word line WLxj, the sense amplifier SAy detects whether or not a current flows through the memory cell MCx. Data stored in the memory cell MCx can be read.

  Here, by changing the pass voltage Vr + α applied to the word lines WLx−1j and WLx + 1j in accordance with the read voltage Vgx applied to the word line WLxj, the floating gate electrodes 16 of the memory cells MCx−1, MCx and MCx + 1. Even when the coupling capacitances C3 and C4 in the meantime increase, it is possible to suppress the decrease in conductance of the memory cells MCx−1 and MCx + 1 while preventing the occurrence of the read disturb phenomenon. For this reason, it is possible to suppress a decrease in the cell current at the time of reading from the memory cell MCx, and even when the miniaturization of the memory cell advances, the deterioration of the reading speed due to the coupling capacitors C3 and C4 is suppressed. can do.

(Second Embodiment)
FIG. 5 is a block diagram showing a schematic configuration of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.
In FIG. 5, the NAND flash memory is provided with a memory cell array 101, sense amplifier circuits 102a and 102b, a column decoder circuit 103, row decoder circuits 104a and 104b, and a control circuit 105. Here, the memory cell array 101 is divided into planes 101a and 101b, and the same configuration as that in FIG. 2 can be used for each of the planes 101a and 101b.

The plane 101a is connected to the column decoder circuit 103 via the bit line BLa and is connected to the row decoder circuit 104a via the word line WLa. The plane 101b is connected to the column decoder circuit 103 via the bit line BLb and to the row decoder circuit 104b via the word line WLb.
The control circuit 105 can change the pass voltage Vr + α applied to the word lines WLx−1j and WLx + 1j in accordance with the read voltage Vgx applied to the word line WLxj in FIG.

As a result, even when the memory cell array 101 is divided for each of the planes 101a and 101b, it is possible to suppress the decrease in conductance of the non-selected cell adjacent to the selected cell while preventing the occurrence of the read disturb phenomenon. Become.
In the above-described embodiment, the method of storing four values in the memory cells MC0 to MCn has been described. However, the value stored in the memory cells MC0 to MCn is not limited to four values, and any number of three values or more can be used. Good.

1 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration of a memory cell array 1 in FIG. 1. Sectional drawing which shows schematic structure when NAND string MS is cut | disconnected along the direction of the bit line BLy. The figure which shows the relationship between the voltage Vgx applied to the word line WLxj of FIG. 2, and the voltage Vr + α applied to the word lines WLx-1j and WLx + 1j adjacent to the word line WLxj. The block diagram which shows schematic structure of the non-volatile semiconductor memory device which concerns on 2nd Embodiment of this invention.

Explanation of symbols

  1, 101 memory cell array, 2, 102a, 102b sense amplifier circuit, 3, 103 column decoder circuit, 4, 104a, 104b row decoder circuit, 5, 105 control circuit, 101a, 101b plane, MB0 to MBk memory block, MS NAND String, MC0 to MCn memory cell, SG1, SG2 select gate transistor, SA0 to SAm sense amplifier, BL0 to BLm bit line, WL0j to WLnj word line, SGSj, SGDj select gate line, CSL cell source line, 11 P type semiconductor substrate , 12 N well, 13 P well, 14 N-type impurity diffusion layer, 15 tunnel oxide film, 16 floating gate electrode, 17 intergate insulating film, 18 control gate electrode, 19 gate insulating film, 20 selection gate electrode, C1 to C Coupling capacitance

Claims (5)

A NAND string in which memory cells capable of storing multi-value information of three values or more are connected in series, and selection transistors capable of selecting the memory cells connected in series are arranged at both ends of the memory cells connected in series. Memory cell arrays arranged in a shape;
A bit line in which a plurality of NAND strings are connected in the column direction;
A word line connecting memory cells in the NAND string and memory cells in the NAND string adjacent in the row direction orthogonal to the column direction;
A column decoder circuit for selecting the bit line;
A row decoder circuit for selecting the word line;
A control circuit for performing writing and reading of a selected memory cell selected by the bit line and the word line,
The control circuit applies a read voltage corresponding to a value stored in the selected memory cell to the first word line connected to the selected memory cell when reading the selected memory cell, and the NAND circuit A non-selected memory cell connected to the third word line is turned on for a third word line other than the first word line of the string and the second word line adjacent to the first word line. And a second pass voltage changed according to the read voltage so as to be higher than the first pass voltage is applied to the second word line. A nonvolatile semiconductor memory device. A NAND string in which memory cells capable of storing multi-value information of three values or more are connected in series, and selection transistors capable of selecting the memory cells connected in series are arranged at both ends of the memory cells connected in series. Memory cell arrays arranged in a shape;
A bit line in which a plurality of NAND strings are connected in the column direction;
A word line connecting memory cells in the NAND string and memory cells in the NAND string adjacent in the row direction orthogonal to the column direction;
A column decoder circuit for selecting the bit line;
A row decoder circuit for selecting the word line;
A control circuit for performing writing and reading of a selected memory cell selected by the bit line and the word line,
The control circuit applies a read voltage corresponding to a value stored in the selected memory cell to the first word line connected to the selected memory cell when reading the selected memory cell, and the NAND circuit A non-selected memory cell connected to the third word line is turned on for a third word line other than the first word line of the string and the second word line adjacent to the first word line. A first pass voltage is applied, and the second word line includes: an unselected memory cell connected to the second word line; and an unselected memory cell connected to the third word line; A non-volatile semiconductor memory device, wherein a second pass voltage set so that conductances coincide with each other is applied. Memory cells having floating gates and capable of storing multi-value information of three or more values are connected in series, and selection transistors capable of selecting the memory cells connected in series are provided at both ends of the memory cells connected in series. A memory cell array in which NAND strings are arranged in a matrix;
A bit line in which a plurality of NAND strings are connected in the column direction;
A word line connecting memory cells in the NAND string and memory cells in the NAND string adjacent in the row direction orthogonal to the column direction;
A column decoder circuit for selecting the bit line;
A row decoder circuit for selecting the word line;
A control circuit for performing writing and reading of a selected memory cell selected by the bit line and the word line,
The control circuit applies a read voltage corresponding to a value stored in the selected memory cell to the first word line connected to the selected memory cell when reading the selected memory cell, and the NAND circuit A non-selected memory cell connected to the third word line is turned on for a third word line other than the first word line of the string and the second word line adjacent to the first word line. A first pass voltage is applied, and the second word line includes: an unselected memory cell connected to the second word line; and an unselected memory cell connected to the third word line; A non-volatile semiconductor memory device characterized by applying a second pass voltage set so that the voltages of the floating gates coincide with each other. A NAND string in which memory cells capable of storing multi-value information of three values or more are connected in series, and selection transistors capable of selecting the memory cells connected in series are arranged at both ends of the memory cells connected in series. Memory cell arrays arranged in a shape;
A bit line in which a plurality of NAND strings are connected in the column direction;
A word line connecting memory cells in the NAND string and memory cells in the NAND string adjacent in the row direction orthogonal to the column direction;
A column decoder circuit for selecting the bit line;
A row decoder circuit for selecting the word line;
A control circuit that performs writing and reading of a selected cell selected by the bit line and the word line,
The control circuit applies a read voltage corresponding to a value stored in the selected memory cell to the first word line connected to the selected memory cell when reading the selected cell, and the NAND string In the third word line other than the first word line and the second word line adjacent to the first word line, the non-selected memory cells connected to the third word line are turned on. A first pass voltage is applied so that a decrease in conductance due to a coupling capacitance between the unselected memory cell connected to the second word line and the selected memory cell is canceled in the second word line. A non-volatile semiconductor memory device characterized by applying a second pass voltage set to (1). Memory cells having floating gates and capable of storing multi-value information of three or more values are connected in series, and selection transistors capable of selecting the memory cells connected in series are provided at both ends of the memory cells connected in series. A memory cell array in which NAND strings are arranged in a matrix;
A bit line in which a plurality of NAND strings are connected in the column direction;
A word line connecting memory cells in the NAND string and memory cells in the NAND string adjacent in the row direction orthogonal to the column direction;
A column decoder circuit for selecting the bit line;
A row decoder circuit for selecting the word line;
A control circuit for performing writing and reading of a selected memory cell selected by the bit line and the word line,
The control circuit applies a read voltage corresponding to a value stored in the selected cell to the first word line connected to the selected memory cell when reading the selected memory cell, and the NAND string In the third word line other than the first word line and the second word line adjacent to the first word line, the non-selected memory cells connected to the third word line are turned on. The first pass voltage is applied, and the second word line has a decrease in the floating gate voltage due to the coupling capacitance with the selected memory cell with respect to the non-selected memory cell connected to the second word line. A non-volatile semiconductor memory device, wherein a second pass voltage set so as to cancel is applied.

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