JP2010074282A - Power amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control an idling current of a FET, which is difficult to keep the temperature variations to be constant, and which keeps the output of a power amplifier to be constant. <P>SOLUTION: The power amplifier using the FET has a drain current value measuring means for measuring the drain current value of the FET and an idling current correction means for correcting an idling current of the FET, and the idling current correction means corrects the idling current, according to the drain current value measured by the drain current value measuring means. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power amplifier using an FET, and more particularly to correction of an output level of the power amplifier.

Conventionally, the idling current of an FET used in a power amplifier is temperature-corrected by a diode. Also, when no input is detected, the drain current of the MOS-FET can be detected as an idling current, so the idling current value is compared with a specified value, and the gate voltage of the MOS-FET is controlled so that they match. The change in idling current over time is removed (for example, see Patent Document 1).
JP 2001-148615 A

  Since it is difficult to completely match the temperature characteristics of the FET and the diode in the conventional technique of correcting the idling current of the FET using the diode, it is difficult to keep the idling current of the FET constant.

  An object of the present invention is to control the idling current of the FET, which has been difficult to keep constant due to temperature changes, and to keep the output of the power amplifier constant.

  The power amplifier using the FET of the present invention has drain current value measuring means for measuring the drain current value of the FET and idling current correcting means for correcting the idling current of the FET, and the idling current correcting means measures the drain current value. Correction is performed according to the drain current value measured by the means.

  According to the present invention, the idling current can be stabilized in the same circuit regardless of the difference in individual thermal characteristics of the FET. Further, by adopting digital processing, it is possible to stabilize the idling current accurately in real time faster than the conventional diode method, and it is possible to simplify the circuit.

  The power amplifier using the FET of the present invention corrects the idling current Ia of the FET 11 from the drain current Id of the FET. An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram for explaining a power amplifier 1 according to an embodiment of the present invention.

  In FIG. 1, an RF (Radio Frequency) signal input from the input terminal 2 of the power amplifier 1 is amplified by the FET 11 and output from the output terminal 3 via the capacitor 14.

  The drain current Id of the FET 11 is supplied from the power supply VDD via the coil 13. The drain current Id of the FET 11 is converted into a voltage by the current sensor unit 15, averaged by the LPF (Low Pass Filter) unit 16, converted into a digital signal by the A / D (Analog / Digital) conversion unit 17, The processing unit 18 outputs an H signal 26 or an L signal 27 that is a control signal in comparison with a threshold value set in advance. The digital potentiometer unit 20 can change the resistance value stepwise by the pulse signal of the H signal 26 or the L signal 27.

The voltage variable regulator unit 19 supplies power from the power supply VCC, and the output voltage value is determined from the ratio of the resistor 21 and the variable resistor 23.
The idling current Ia of the FET 11 is adjusted by adjusting the output voltage of the voltage variable regulator unit 19 with the variable resistor 23, thereby changing the voltage dividing ratio according to the resistance values of the resistor 22, the variable resistor 23, the resistor 24, and the resistor 25. Is possible.

  Next, the detailed operation of one embodiment of the present invention will be described with reference to FIG. FIG. 2 is a flowchart for explaining the operation of the power amplifier according to the embodiment of the present invention.

  The signal processing unit 18 starts processing from the start. In step S1, the upper and lower thresholds of the drain current Id of the FET 11 are set. The value between the upper threshold and the lower threshold is the specification value of the drain current Id of the FET 11. The current value of the drain current Id converted into the digital voltage value in the process of step S2 is captured. The current value of the drain current Id converted into the digital voltage value in the process of step S3 is compared with the upper limit threshold value. If the current value of the drain current Id converted into the digital voltage value is larger than the upper limit threshold value, the process of step S4 is performed. If the current value of the drain current Id converted to the digital voltage value is less than or equal to the upper threshold value, the process proceeds to step S5.

  When the signal processing unit 18 outputs one pulse signal to the digital potentiometer unit 20 as the L signal 27 in the process of step S4, the resistance value of the digital potentiometer unit 20 becomes smaller by one pulse signal. As the resistance value of the digital potentiometer unit 20 decreases by one pulse signal, the voltage output from the voltage variable regulator unit 19 decreases. When the voltage output from the voltage variable regulator unit 19 decreases, the idling current Ia of the FET 11 decreases, and as a result, the drain current Id of the FET 11 decreases. Next, the process proceeds to step S7.

  The signal processing unit 18 compares the current value of the drain current Id converted into the digital voltage value in the process of step S5 with the lower limit threshold value, and the current value of the drain current Id converted into the digital voltage value is smaller than the lower limit threshold value. Advances to the process of step S6, and if the current value of the drain current Id converted into the digital voltage value is equal to or greater than the lower limit threshold value, the process advances to the process of step S7.

  When the signal processing unit 18 outputs one pulse signal to the digital potentiometer unit 20 as the H signal 26 in the process of step S6, the resistance value of the digital potentiometer unit 20 increases by one pulse signal. As the resistance value of the digital potentiometer unit 20 increases by one pulse signal, the voltage output from the voltage variable regulator unit 19 increases. When the voltage output from the voltage variable regulator unit 19 increases, the idling current Ia of the FET 11 increases, and as a result, the drain current Id of the FET 11 increases. Next, the process proceeds to step S7.

  The signal processor 18 stops the process for a predetermined interval time in the process of step S7, and returns to the process of step S2 after the elapse of the predetermined interval time. This predetermined interval time is a time until the operation of the FET 11 is stabilized, or an interval for operating the feedback loop of one embodiment of the present invention.

  In the present invention, since the FET idling current is corrected from the average value of the drain current of the FET, there is a carrier whose average output changes due to the modulation such as amplitude modulation or a carrier such as SSB (Single Side Band) modulation. Not suitable for non-existing modulation schemes. The present invention is suitable for a modulation system in which the carrier is constant and the average output is not changed by the modulation, such as digital modulation.

  Although the present invention has been described in detail above, it is needless to say that the present invention is not limited to the high-frequency power amplifier described herein, and can be widely applied to power amplifiers other than those described above.

It is a block diagram for demonstrating the power amplifier which is one Example of this invention. It is a flowchart for demonstrating operation | movement of the power amplifier which is one Example of this invention.

Explanation of symbols

  1: power amplifier, 2: input terminal, 3: output terminal, 11: FET, 12, 14: capacitor, 13: coil, 15: current sensor unit, 16: LPF, 17: A / D, 18: signal processing unit , 19: voltage variable regulator section, 20: digital potentiometer, 21, 22, 24, 25: resistance, 23: variable resistance, 26: H signal, 27: L signal.

Claims (1)

In power amplifiers using FETs,
A drain current value measuring means for measuring the drain current value of the FET, and an idling current correcting means for correcting the idling current of the FET;
The power amplifier according to claim 1, wherein the idling current correcting means corrects according to the drain current value measured by the drain current value measuring means.

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