JP2009302647A - Carrier frequency reproduction circuit and method of ofdm signal demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect a frequency error in a range smaller than carrier wave intervals, to heighten precision of correction of frequency errors accurately and to improve reception performance of a receiver. <P>SOLUTION: A carrier frequency reproduction circuit is provided with: a circuit 43 for outputting a phase angle corresponding to a differential demodulation result (PRNp and PJNp) about a pilot signal component; a shift direction determining means 45 for determining the direction of shift of a frequency on the basis of the differential demodulation result about a signal component above one carrier wave and a differential modulation result about a signal component under one carrier wave; and a code determining means 46 for determining the code of a phase angle on the basis of a code of a phase angle output by the phase angle output circuit 43 and the shift direction by the shift direction determining means 45. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a carrier frequency recovery circuit and method for an OFDM signal demodulator.

  In Japan, as a terrestrial digital broadcasting system, a modulation system called orthogonal frequency division multiplexing (OFDM) that uses a large number of carriers and distributes and transmits information is adopted. One of the important functions for the OFDM receiver to correctly receive a signal is a carrier frequency synchronization function.

  As a carrier frequency synchronization method, for example, the carrier component of the current symbol of the frequency domain signal is differentially demodulated with the carrier component of the previous symbol, and the phase of the signal falls within a predetermined range set in advance on the complex plane. Judgment is made whether or not it is distributed, the correlation value of the arrangement of each carrier component on the frequency axis is calculated from the determined result, the absolute value of the calculation result is calculated, and the position of the maximum value on the frequency axis of the absolute value is detected Then, there is a method of outputting as a frequency error that is an integral multiple of the carrier interval for correcting the frequency error of the carrier (for example, Patent Document 1).

JP 2004-135037 A

  In the carrier frequency synchronization method of the conventional OFDM signal demodulator described above, the frequency error detection range is limited to an integral multiple of the distance between the carriers.

  The present invention has been made to solve the above-described problems, and an object thereof is to extend the frequency error detection range to 0 to 1/2 of the inter-carrier distance within the inter-carrier distance.

The carrier frequency recovery circuit of the OFDM signal demodulator of the present invention is
The input orthogonal frequency division multiplexing (OFDM) complex digital signal is orthogonally demodulated, converted to a baseband frequency, removed the guard interval (GI), and Fourier transformed to convert the frequency domain signal. An OFDM signal demodulating device that detects the carrier frequency, and then recovers the carrier frequency used in the quadrature demodulation based on the signal obtained by the quadrature demodulation and the frequency domain signal obtained by the Fourier transform. In the circuit
A correlation value between an I signal component or Q signal component obtained by the orthogonal demodulation and a signal delayed by one effective symbol time is calculated, and a first frequency error is calculated based on the calculated value A frequency error detection circuit;
A second frequency error detection circuit for detecting a second frequency error based on the TMCC pilot signal component in the Fourier transformed frequency domain and the data signal component on and under the one carrier;
An adder circuit for adding the first frequency error and the second frequency error;
A numerical control transmission circuit whose oscillation frequency is controlled by the output of the addition circuit,
The second frequency error detection circuit includes:
The TMCC pilot signal component in the frequency domain subjected to Fourier transform and the data signal component on one carrier and one carrier thereof are delayed by one effective symbol time, and the TMCC pilot signal component delayed by one effective symbol time and the current TMCC Differentially demodulated using a pilot signal component, differentially demodulated using a signal component on one carrier delayed by one effective symbol time and a signal component on one current carrier, and delayed by one effective symbol time A differential demodulation circuit that differentially demodulates using the lower signal component and the signal component under one current carrier wave;
A phase angle output circuit for outputting a phase angle corresponding to an I component and a Q component on a complex plane of a differential demodulation result by the differential demodulation circuit for the TMCC pilot signal component;
Based on the I component and Q component in the differential demodulation result by the differential demodulation circuit for the signal component on the one carrier wave, and the I component and Q component in the differential demodulation result on the signal component on the one carrier wave A deviation direction determination circuit for determining a direction of frequency deviation;
A code determination circuit that determines a code of the phase angle based on a code of the phase angle output by the phase angle output circuit and a direction of shift by the shift direction determination circuit;
The phase angle whose code is determined by the code determination circuit is output as the second frequency error.

  Since the present invention is configured as described above, it is possible to detect a frequency error in a range smaller than the carrier interval, and to correct the frequency error with higher accuracy than the conventional method. It becomes possible to improve the reception performance of the receiver.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Prior to that, the orthogonal frequency division multiplexing (OFDM) transmission technology used in the present invention is necessary to understand the present invention. Briefly described.

  Orthogonal frequency division multiplexing (OFDM) transmission (transmission / reception) technology is a transmission / reception method in which information is modulated and multiplexed by a plurality of carriers whose frequencies are orthogonal to each other, and the reception side performs reverse processing to demodulate. In particular, practical application is progressing in the field of broadcasting and communication.

  In transmission in the OFDM scheme, data to be transmitted is allocated to a plurality of carriers at the time of transmission, and Quadrature Phase Shift Keying (QPSK), Quadrature Amplitude Modulation (QAM), or Differential Quadrature PPS Modulated, additional information on transmission parameters and transmission control, and the continuous pilot carrier component modulated with known data are always digitally modulated using a specific carrier wave in the DBPSK or BPSK system, and then multiplexed. Thereafter, the OFDM signal is frequency-converted to a desired transmission frequency and transmitted.

  Specifically, transmission data to be transmitted at the time of transmission is mapped to signal points on the complex plane according to the modulation scheme of each carrier wave (subcarrier), and these are subjected to inverse discrete Fourier transform to be converted into a time domain signal. The The same signal as the last part of the signal (effective symbol period (SI) signal) after the inverse discrete Fourier transform generated thereby is added to the head of the effective period signal as a guard period (GI: guard interval) signal (FIG. 1). (A)). The baseband OFDM signal generated in this manner is converted into an intermediate frequency (IF) band signal by orthogonal modulation, further converted into a radio frequency (RF) band signal, and transmitted.

  By adding the GI period signal as described above, even if there is a delay wave having a delay time equal to or shorter than the GI length, the signal can be reproduced without intersymbol interference on the receiving side.

  In the OFDM method, all the carrier waves are orthogonal to each other. Therefore, when the carrier frequency is correctly reproduced on the receiving side, the transmission data can be correctly reproduced. However, when the carrier frequency on the receiving side includes an error with respect to the actual frequency, interference (ICI: inter-carrier interference) occurs between the carriers, and the probability that transmission data is erroneously reproduced increases and transmission characteristics increase. Deteriorates. Therefore, in the OFDM method, how to correctly reproduce the carrier frequency on the receiving side is an important issue.

  In a demodulator that receives an OFDM signal, for example, as in the conventional OFDM receiver, the OFDM demodulated digital signal is generally orthogonally demodulated and frequency-converted to a baseband band. The time domain signal is removed by removing the GI, and the time domain signal is demodulated by performing a Fourier transform to detect the frequency domain signal.

  In addition, in a demodulator that receives an OFDM signal, in order to reproduce the carrier frequency, it is necessary to perform processing to reduce the frequency error and achieve synchronization. In the carrier frequency synchronization circuit of a general OFDM signal demodulator, the frequency error Are separated into components that are integral multiples of the carrier interval and other components, and frequency errors are detected and corrected for each component to achieve synchronization. For example, the OFDM receiving apparatus shown in the above prior art detects a frequency error that is an integral multiple of the carrier interval.

Embodiment 1 FIG.
FIG. 2 is a block diagram showing an OFDM receiver according to Embodiment 1 of the present invention, particularly a carrier frequency recovery circuit of the OFDM signal demodulator.

As shown in FIG. 2, the OFDM receiver 150 includes a receiving antenna 101, a tuner 102, a band pass filter (BPF) 104, an analog / digital (A / D) conversion circuit 105,
A subcarrier frequency signal demodulating circuit 120, a detecting circuit 125, a clock signal oscillator 131,
And a clock signal reproduction circuit 130.

The receiving antenna 101 receives an OFDM-modulated radio signal (OFDM modulated signal).
The tuner 102 includes a multiplication circuit 102a and a main carrier oscillation circuit 102b as a local oscillator used for channel selection. The oscillation frequency of the main carrier oscillation circuit 102b is switched according to a channel selection signal supplied from a channel selection circuit (not shown), and the multiplication circuit 102a receives a predetermined main carrier frequency signal output from the main carrier oscillation circuit 102b. Multiply by radio signal.

The band pass filter (BPF) 104 extracts an intermediate frequency (IF) signal that becomes a subcarrier frequency band from the output of the multiplication circuit 102a.
The A / D conversion circuit 105 converts the analog IF signal extracted by the BPF 104 into a digital signal using a clock signal having a predetermined frequency supplied from the clock signal oscillator 131.

The clock signal oscillator 131 reproduces a clock used when a received signal is modulated by the modulator on the transmission side on the receiver side. For example, the voltage controlled crystal oscillator (Voltage Controlled Crystal Oscillator) is used. ) Etc.
In this case, the phase rotation amount in the same symbol is obtained from the phase information of the subcarrier frequency signal.
The clock signal oscillator 131 is controlled by a control signal output from the clock signal regeneration circuit 130.

  The digital signal output from the A / D conversion circuit 105 is supplied to the subcarrier frequency signal demodulation circuit 120.

  The subcarrier frequency signal demodulation circuit 120 includes a demultiplexer 106, low band pass filters (LPF) 107 and 108, a complex multiplication circuit 109, a guard removal circuit 110, a fast Fourier transform circuit (FFT circuit) 111, a carrier wave Frequency reproduction circuit 112.

  The demultiplexer 106 separates the I channel IF data and the Q channel IF data from the digitized IF signal and outputs demodulated data for each channel.

  The LPF 107 removes unnecessary high frequency components (for example, adjacent channel signals and noise) included in the I channel IF data, and the LPF 108 removes unnecessary high frequency components included in the Q channel IF data.

  The complex multiplication circuit (digital quadrature demodulation circuit) 109 multiplies the input I-channel IF data and Q-channel IF data by the subcarrier frequency signal supplied from the numerically controlled oscillation circuit 116, thereby removing the frequency error. While performing orthogonal demodulation, baseband I-channel demodulated data and Q-channel demodulated data are generated.

  The guard removal circuit 110 removes a guard interval (GI) from the baseband I-channel demodulated data and Q-channel demodulated data output from the complex multiplier circuit 109.

The FFT circuit 111 performs an FFT operation (discrete Fourier transform) on the I-channel demodulated data and the Q-channel demodulated data output from the guard removal circuit 110 and converts them into frequency components. Thus, I-channel demodulated data IR and Q-channel demodulated data QR that have been subjected to discrete Fourier transform are generated.
As a result, a signal that is orthogonally modulated on each subcarrier is extracted and output.

  The detection circuit 125 recovers the data signal by demapping after detecting each subcarrier output from the FFT circuit 111 according to the modulation method.

  The carrier frequency reproduction circuit 112 is a carrier wave used in the orthogonal demodulation in the complex multiplication circuit 109 based on the signal obtained by the orthogonal demodulation by the complex multiplication circuit 109 and the frequency domain signal obtained by the Fourier transform by the FFT circuit 111. The frequency reproduction circuit includes a first carrier frequency error detection circuit 113, a second carrier frequency error detection circuit 114, an adder circuit 115, and a numerically controlled oscillation circuit 116.

  The first carrier frequency error detection circuit 113 calculates a correlation value between the I signal component or the Q signal component obtained by the orthogonal demodulation by the complex multiplication circuit 109 and a signal delayed by one effective symbol time, and the calculation The first frequency error is calculated based on the value, and includes a correlation value calculation circuit 113a and a frequency error calculation circuit 113b.

The correlation value calculation circuit 113a receives the I-channel demodulated data and the Q-channel demodulated data of the time domain signal as input, and calculates a correlation value between these and data obtained by delaying them by one effective symbol period. Further, the detection result in the correlation value calculation circuit 113 a is also used for controlling the FFT timing in the FFT circuit 111.
The carrier frequency error calculation circuit 113b calculates a frequency error exceeding the carrier frequency interval based on the timing at which the correlation value becomes maximum, and outputs an error correction value (first frequency error) in units of carriers.

  The second carrier frequency error detection circuit 114 is based on the TMCC pilot signal component in the frequency domain Fourier-transformed by the FFT circuit 111 and the data signal component on one carrier and one carrier below, and the output bias for each frequency. Is detected to detect the frequency error of the demodulated data IR and QR subjected to the FFT, and this is detected as the second frequency error. The second carrier frequency error detection circuit 114 detects a frequency error within a range not exceeding the carrier interval, and outputs a correction value for the error.

The adder circuit 115 includes a first frequency error (correction value for the error) output from the first carrier frequency error detection circuit 113 and a second frequency error output from the second carrier frequency error detection circuit 114. (Correction value for the error) is added.
The oscillation frequency of the numerically controlled oscillation circuit 116 is controlled by the output of the addition circuit 115.

The GI period in the OFDM signal is configured by adding a signal having the same content as a part near the end of the effective symbol, and this GI period appears in a period of a symbol period (sum of the effective symbol period and the GI period). become.
Since a signal having the same content as that of a part near the end of the effective symbol is added to the signal in the GI period, the correlation between the effective symbol and the signal in the GI period is maximized.

  FIG. 1 illustrates the relationship between signals and correlation values. When comparing the current signal (FIG. 1 (a)) with the signal delayed by only one symbol period Ts (FIG. 1 (b)), the signals in the GI period Tg are exactly the same, so the correlation between the two is Maximum.

Therefore, by finding a place where the correlation between the effective symbol and the signal in the GI period is maximized, it is possible to specify the GI period in the effective symbol, and it is also possible to specify the effective symbol period. Become.
That is, by specifying the effective symbol period, it is possible to perform FFT in the FFT circuit 111 according to the length of the effective symbol period.

  In the subcarrier frequency signal demodulating circuit 120, as described above, the complex multiplier circuit 109 causes the subsequent FFT circuit 111 to start computation at the timing when the correlation value becomes maximum, so that the converted data IR and the output data from the FFT circuit 111 and QR frequency error can be minimized.

  The second carrier frequency error detection circuit 114 uses the pilot component extracted from the I-channel demodulated data IR and the Q-channel demodulated data QR, the signal component on the one carrier, and the signal component on the one carrier. Then, the second frequency error signal CS for controlling the numerically controlled oscillation circuit 116 is generated and output.

  The numerical control signal oscillator 116 corresponds to the addition result of the first frequency error detected by the first frequency error detection circuit 113 and the second frequency error detected by the second carrier frequency error calculation circuit 114. Oscillates at a frequency.

  The complex multiplication circuit 109, the FFT circuit 111, the second carrier frequency error detection circuit 114, the addition circuit 115, and the numerically controlled oscillation circuit 116 shown in FIG. 2 constitute a PLL circuit for controlling the subcarrier frequency.

FIG. 3 is a block diagram showing a configuration of the second carrier frequency error detection circuit 114 according to the first embodiment of the present invention.
The illustrated carrier wave frequency error calculation circuit 114 includes a signal component extraction circuit 20, a differential demodulation circuit 30, switches 41 and 42, a ROM 43, a loop filter 44, a deviation direction determination circuit 45, and a code determination circuit 46. Have

The signal component extraction circuit 20 includes switches 21 and 22.
In the switch 21, the data PIRp corresponding to the pilot signal and the signals PIRa and PIRb corresponding to the positions of the TMCC pilot signals in the upper and lower one carrier waves are selected from the demodulated I channel data IR converted into the frequency domain by the FFT circuit 111. .
Similarly, the switch 22 selects data PQRp corresponding to the TMCC pilot signal and signals PQRa and PQRb corresponding to the positions of the TMCC pilot signals in the upper and lower one carrier waves from the Q channel demodulated data QR.
Here, “upper and lower one carrier wave” means a carrier wave having a frequency higher than that of the pilot signal and closest to a carrier wave having a frequency lower than that of the pilot signal.

The differential demodulation circuit 30 includes RAMs 31 and 32, a sign inverting circuit 33, and a complex multiplication circuit 34.
The RAMs 31 and 32 function as delay circuits, and data PIRp, PIRa, PIRb, PQRp, PQRa, PQRb corresponding to pilot signals in the I channel demodulated data IR and Q channel demodulated data QR and their TMCC pilot signals in one upper and lower carrier waves. And delay-demodulated data dPIRp, dPIRa by delaying the time until the arrival of the next pilot signal and the signal corresponding to the pilot signal in the upper and lower carrier waves, that is, the time corresponding to one pilot signal generation interval. , DPIRb and dPQRp, dPQRa, dPQRb are output.

  The sign inverting circuit 33 inverts the sign of the delayed demodulated data dPQRp, dPQRa, dPQRb output from the RAM 32 and outputs the result.

  Note that one symbol (period) in the OFDM signal includes several hundred to several thousand subcarrier frequency signals, and a plurality of pilot signals are included therein. The time corresponding to one pilot signal generation interval described above means a period between one pilot signal and the next pilot signal.

  Also, the time until the arrival of the signal corresponding to the pilot signal in one carrier above and below the pilot signal means the period between the signal corresponding to the pilot signal and the signal corresponding to the next pilot signal, and the delay time is the same. It will be time.

  The complex multiplication circuit 34 receives the pilot signal which is not delayed from the signal component extraction circuit 20 and demodulated data PIRp, PIRa, PIRb and PQRp, PQRa, PQRb, and pilots delayed by the RAMs 31 and 32. Complex multiplication is performed on the signal and the delayed demodulated data dPIRp, dPIRa, dPIRb and dPQRp, dPQRa, dPQRb for one carrier above and below. By this multiplication, differential demodulation is performed on the pilot signal and the complex signal corresponding to one carrier wave above and below it.

  The result of the complex operation by the complex multiplication circuit 34 (result of differential demodulation) is the pilot signal and its real component data PRNp, PRNa, PRNb for the upper and lower carrier waves, the pilot signal and the imaginary component data PJNp for the upper and lower carrier waves, The output is divided into PJNa and PJNb.

  The switches 41 and 42 output only the signals PRNp and PJNp corresponding to pilot signals among the PRNp, PRNa, PRNb, and PJNp, PJNa, and PJNb to the ROM 43.

  The ROM 43 functions as a circuit that outputs a phase angle corresponding to the I component (I coordinate) and the Q component (Q coordinate) on the complex plane of the real component data PRNp and imaginary component data PJNp of the input pilot signal. The real number component data PRNp and the imaginary number component data PJNp are input, and arc tangent (inverse tangent function) data (Arctan (PJN / PRN)) corresponding thereto is read, and the phase variation data PS of the pilot signal Output as. However, the range is −π / 2 to π / 2.

The loop filter 44 performs phase compensation.
The shift direction determination circuit 45 includes an I component and a Q component PRNp, PJNp in the differential demodulation result for the pilot signal, and an I component and a Q component PRNa, PJNa in the differential demodulation result for the signal component on one carrier wave of the pilot signal. Then, based on the I component and the Q components PRNb and PJNb in the differential demodulation result for the signal component under one carrier wave of the pilot signal, the direction of frequency shift is determined, and a signal DR indicating the determination result is output.
The shift direction determination circuit 45 detects the frequency shift direction of the pilot signal and outputs a signal indicating the shift direction. For example, “0” is output when it is shifted downward by one carrier wave, and “1” is output when it is shifted downward by one carrier wave.

The sign determination circuit 46 determines the sign of the phase angle based on the sign of the phase angle output from the ROM 43 and the direction of the shift by the shift direction determination circuit 45 (the sign is reversed if necessary), and the sign is determined. The obtained phase angle is output as a second frequency error.
The phase angle determined by the code determination circuit 46 is supplied to the adder circuit 115 as a second frequency error.

  The sign determination circuit 46 includes a sign bit extraction circuit 47, a mismatch detection circuit 48, and a multiplication circuit 49.

The sign bit extraction circuit 47 extracts a bit (sign bit) representing the sign of the output of the ROM 43. The sign bit represents, for example, negative when “1” and positive when “0”.
The mismatch detection circuit 48 detects a mismatch between the output of the sign bit extraction circuit 47 and the output of the shift direction determination circuit 45, and outputs a signal indicating “−1” when there is a mismatch, A signal indicating “+1” is output.

Through the above processing, the mismatch detection circuit 48
(A) The frequency of the pilot signal is shifted upward, and when the sign of Arctan (PJNp / PRNp) output from the ROM 43 is positive, and the frequency of the pilot signal is shifted downward, and is output from the ROM 43. Arctan (PJNp / PRNp) has a negative sign,
(B) When the pilot signal frequency is shifted downward and the sign of Arctan (PJNp / PRNp) output from the ROM 43 is negative, and when the pilot signal frequency is shifted upward, it is output from the ROM 43. A different signal is output when the sign of Arctan (PJNp / PRNp) is positive.
For example, in the case of the former (a), “+1” is output, and in the case of the latter (b), “−1” is output.

  The relationship between the output of the sign bit extraction circuit 47, the output of the determination circuit 45, and the output of the mismatch detection circuit 48 is as shown in Table 1 described later.

  The multiplication circuit 49 multiplies the output of the loop filter 44 by the output of the mismatch detection circuit 48 and outputs the multiplication result as a frequency error signal CS.

Here, the relationship between the TMCC pilot signal and the carrier frequency deviation will be described. The data obtained by differentially demodulating the TMCC pilot signal on the complex plane is shown in FIGS. 4 (c) and 4 (d).
FIG. 4C shows a TMCC demodulation result when there is no error in the carrier frequency, and FIG. 4D shows a TMCC demodulation result when there is an error in the carrier frequency.
4C and 4D, “CNR = 30 dB” means that a CNR (carrier to noise ratio) is assumed to be 30 dB. Δf represents a carrier frequency error. The same applies to FIGS. 5, 6, and 11 described later.
The TMCC pilot signal is modulated by DBPSK and arranged on subcarriers defined in the standard. Therefore, when the differential demodulation result when there is no error in the carrier frequency is displayed on the complex plane, it is displayed at two points on the I axis as shown in FIG. In this case, a phase error when extracting a signal in a predetermined section on the time axis appears in the FFT result.

  The frequency error for one carrier is approximately 2π when this phase error is taken. Thus, when there is a frequency error of ½ of the interval between carriers, the phase shift is approximately π, and when there is a frequency error of ¼ of the interval between carriers, the phase shift is approximately π / 2.

  However, it is assumed that there is an error in the carrier frequency as shown in FIG. The TMCC pilot signal has a binary value transmitted by DBPSK. In such a case, it is impossible to determine whether the phase rotation amount of the TMCC demodulated signal is, for example, −π / 8 or 7π / 8.

  Therefore, the phase rotation direction is determined using the shift direction determination circuit 45, and when the rotation direction is different from the output PS of the ROM 43, the polarity of the output PS of the ROM 43 is inverted using the multiplier 49.

  Here, the magnitude of the frequency error and its influence on the adjacent carrier will be described. As the frequency error increases, the phase error also increases, but at the same time, the influence ICI (inter-carrier interference) received from adjacent carriers also increases. For this reason, the signal point of the demodulation result has a spread. This is conceptually illustrated in FIG. When there is no error in the carrier frequency, for example, no phase shift occurs in the FFT period A and the FFT period B in FIG. 4A, but when there is an error in the carrier frequency, the FFT periods A and FFT in FIG. In period B, a phase difference occurs.

  As the frequency error value increases, the influence of ICI on adjacent carriers increases, and the differential demodulation result of adjacent carriers of pilot carriers that are not originally DPSK modulated exhibits a DPSK aspect (FIG. 6). . 6A shows the differential demodulation result of the signal component under one carrier wave of the pilot signal, FIG. 6B shows the differential demodulation result of the pilot signal, and FIG. 6C shows the pilot signal. The differential demodulation result of the signal component on one carrier wave is shown. In FIGS. 6A to 6C, “TMCC-1” means a signal component one carrier below the pilot signal, and “TMCC + 1” means a signal component one carrier above the pilot signal. . The same applies to FIG. 11 described later.

Next, the deviation direction determination circuit 45 will be described.
FIG. 7 shows details of the deviation direction determination circuit 45 in the first embodiment.
The illustrated deviation direction determination circuit 45 includes a power calculation circuit 50,
A distribution switch 60 and a comparison determination circuit 65 are included.
The comparison determination circuit 65 includes a difference calculation circuit 70 and a sign bit extraction circuit 80.

The outputs PRNp, PRNa, PRNb, PJNp, PJNa, and PJNb of the complex multiplication circuit 34 are squared in the multiplication circuits 51 and 52 of the power calculation circuit 50, delayed in the delay circuits 53 and 54 for timing adjustment, and added in the addition circuit 55. The power values PWp, PWa, and PWb are calculated by addition. That is,
PWp = PRN ² + PJN ²
Is used to calculate the power value PWp of the pilot signal component,
PWa = PRNa ² + PJNa ²
The power value PWa of the signal component on one carrier wave of the pilot signal component is calculated by
PWb = PRNb ² + PJNb ²
Thus, the power value PWb of the signal component under one carrier wave of the pilot signal component is calculated.

  The calculated power values PWp, PWa, and PWb are supplied to the comparison determination circuit 65 via the distribution switch 60.

The comparison / determination circuit 65 includes a difference (first difference) between the power value PWp of the pilot signal component and the power value PWa of the signal component on one carrier, and the power value PWp of the pilot signal component and the power of the signal component on one carrier. The difference (second difference) between the values PWb is compared, and a signal indicating the comparison result is output.
The comparison determination circuit 65 includes a difference calculation circuit 70 and a sign bit extraction circuit 80.

The difference calculation circuit 70 determines the difference (first difference) between the power value PWp of the pilot signal component and the power value PWa of the signal component on one carrier, the power value PWp of the pilot signal component and the power of the signal component on one carrier. The difference between the values PWb (second difference) is calculated.
The sign bit extraction circuit 80 outputs a signal DR representing the sign of the output of the difference calculation circuit 70.

  The comparison determination circuit 65 includes delay circuits 71, 72, 73, subtraction circuits 74, 75, absolute value circuits 76, 77, and a subtraction circuit 78.

  The calculated power values PWp, PWa, PWb are distributed by the distribution switch 60 and supplied to the delay elements 72, 71, 73 of the difference calculation circuit 60. The power value PWp of the pilot signal component is supplied to the delay element 72, the power value PWa of the signal component on one carrier wave is supplied to the delay element 71, and the power value PWb of the signal component on one carrier wave is supplied to the delay element 73.

Each of the delay circuits 71, 72, 73 delays the power value.
The subtraction circuit 74 obtains a difference (ΔWa = PWp−PWa) between the power value PWp of the pilot signal supplied from the delay circuit 72 and the power value PWa of the signal on one carrier wave supplied from the delay circuit 71.
The subtraction circuit 75 obtains a difference (ΔWb = PWp−PWb) between the power value PWp of the pilot signal supplied from the delay circuit 72 and the power value PWb of the signal under one carrier wave supplied from the delay circuit 73.

The absolute value circuit 76 obtains the absolute value | ΔWa | of the output ΔWa of the subtraction circuit 74.
The absolute value circuit 77 obtains the absolute value | ΔWb | of the output ΔWb of the subtraction circuit 75.
The subtraction circuit 78 subtracts the output | ΔWa | of the absolute value circuit 76 from the output | ΔWb | of the absolute value circuit 77 to obtain a difference (| ΔWb | − | ΔWa |).
The sign bit extracting circuit 80 extracts and outputs a bit (sign bit) representing the sign of the output of the subtracting circuit 78. The sign bit represents, for example, negative when “1” and positive when “0”.
The output of the sign bit extraction circuit 80 is supplied as an output of the determination circuit 45 to the mismatch detection circuit 48 (shown in FIG. 1).
The mismatch detection circuit 48 outputs “−1” or “+1” by the logical operation as described above.

As described above, the difference ΔWa between the pilot signal power value PWp and the signal power value PWa on one carrier using the subtracting circuits 74 and 75, and the pilot signal power value PWp and the signal power value PWb on one carrier wave. The difference ΔWb is obtained.
In this calculation result, it can be determined that the frequency is shifted in the direction of the carrier having the smaller value. This is because, for example, when the frequency of the pilot signal shifts downward, the signal component under one carrier wave has a great influence, and the power (at the sampling point SP) becomes larger, and the power of the pilot signal If the difference becomes small and the frequency of the pilot signal shifts upward as well, the signal component on one carrier wave has a great influence, and the power (at the sampling point SP) becomes larger, and the power of the pilot signal This is because the difference between and becomes smaller.

  Accordingly, the difference is calculated by the subtraction circuit 78 to compare the magnitudes. Specifically, in the subtraction circuit 78, the output | ΔWa | of the absolute value circuit 76 for obtaining the absolute value of the output of the subtraction circuit 74 is used, and the output | ΔWb of the absolute value circuit 77 for obtaining the absolute value of the output of the subtraction circuit 75. | Is subtracted from |, and as a result, | ΔWb | − | ΔWa | is output.

  For example, when the output of the subtraction circuit 78 is a positive value (when the absolute value of the output of the subtraction circuit 74 is smaller than the absolute value of the output of the subtraction circuit 75), the frequency of the pilot signal is shifted upward. Judge that If the value of the arc tangent (ROM 43 output) obtained from the differential demodulation result of the TMCC pilot is positive, the output of the mismatch detection circuit 48 becomes +1 and the sign of the output of the loop filter 44 is inverted. do not do. Conversely, if the output of the ROM 43 is negative, the output of the mismatch detection circuit 48 becomes −1 and the sign of the output of the loop filter 44 is inverted.

  Conversely, when the output of the subtraction circuit 78 is negative (when the absolute value of the output of the subtraction circuit 74 is larger than the absolute value of the output of the subtraction circuit 75), the frequency of the pilot signal is shifted downward. Judge. If the value of the arc tangent (output of ROM 43) obtained from the differential demodulation result of the TMCC pilot is positive, the output of the mismatch detection circuit 48 becomes −1, and the sign of the output of the loop filter 44 is changed. Invert. Conversely, when the output of the ROM 43 is negative, the output of the mismatch detection circuit 48 becomes +1, and the sign of the output of the loop filter 44 is not inverted.

  The operation of the code determination circuit 46 as described above is shown together with the operation of the comparison determination circuit 65 as shown in Table 1 below.

  The output CS of the multiplier circuit 49 is supplied to the adder circuit 115 in FIG. 2 as a signal representing a frequency error.

  Thus, in the receiving apparatus according to the first embodiment, it is possible to detect a frequency error exceeding the range of ± π / 2, that is, exceeding a quarter frequency between subcarriers. Therefore, it is possible to detect / correct a frequency error with a small value and improve the reception performance of the receiver.

Embodiment 2. FIG.
Next, the second embodiment will be described. In Embodiment 1 above, derivation of the arc tangent and determination of the rotation direction (frequency error direction) are performed for each differential demodulation result. In Embodiment 2, however, before the arc tangent is derived and the rotation direction is determined. In addition, the average calculation circuit 36 calculates an average value for a pilot signal in one symbol section and a signal corresponding to a pilot signal for one upper and lower carrier wave, and uses the result to derive an arc tangent and determine a rotation direction. FIG. 8 shows a second carrier frequency error detection circuit 114 used in the carrier frequency recovery circuit according to the second embodiment.

The carrier frequency error detection circuit 114 shown in FIG. 8 is generally the same as the circuit shown in FIG. 3, but includes an average calculation circuit 36 that calculates the average of one symbol of the differential demodulation result by the differential demodulation circuit 30. The output of the average calculation circuit 36 is supplied to the ROM 43 via the switches 41 and 42 and also supplied to the deviation direction determination circuit 45.
The ROM 43 obtains the arc tangent based on the output of the average arithmetic circuit 35.
The deviation direction determination circuit 45 determines the deviation direction based on the output of the average calculation circuit 36.

  As shown in FIG. 8, the white noise component superimposed on the transmission path can be suppressed by averaging the output of the complex arithmetic circuit 11 by the average arithmetic circuit 36.

  As described above, the receiving apparatus according to the second embodiment suppresses the white noise component by averaging the differential demodulation results over one symbol interval, and exceeds the range of ± π / 2, that is, 1 between subcarriers. Since it is possible to detect a frequency error exceeding a frequency of / 4, a frequency error larger than that of the conventional method can be corrected with high accuracy, and reception performance of the receiver can be improved.

Embodiment 3 FIG.
Next, the third embodiment will be described. The carrier frequency recovery circuit of the third embodiment is generally the same as that of the first embodiment, but the configuration of the deviation direction determination circuit 45 in the second carrier frequency error detection circuit 114 is different.

The deviation direction determination circuit 45 used in the third embodiment is configured as shown in FIG.
The shift direction determination circuit shown in FIG. 9 is generally the same as the shift direction determination circuit of FIG. 7, but differs in that a power integration circuit 90 is added.

The power integration circuit 90 includes integration circuits 90p, 90a, and 90c.
The power value calculated by the power calculation circuit 50 is distributed by the distribution switch 60 to the integrating circuits 90a, 90b, 90p. Specifically, the power value PWp of the pilot signal component is supplied to the integrating circuit 90p, and the power value PWa of the signal component on one carrier wave of the pilot signal component is supplied to the integrating circuit 90a, and one carrier wave of the pilot signal component The power value PWb of the lower signal component is supplied to the integrating circuit 90b.
The integrating circuit 90p includes an adding circuit 92 and a delay circuit 95, the integrating circuit 90a includes an adding circuit 91 and a delay circuit 94, and the integrating circuit 90b includes an adding circuit 93 and a delay circuit 96.
Delay circuits 94, 95, and 96 each have a delay time of one symbol period.
The adder circuits 91, 92, 93 perform integration by adding the outputs of the delay circuits 94, 95, 96 to the inputs.

  Each of the integrating circuits 90p, 90a, 90b integrates the input for a predetermined number of symbols. The outputs (integrated values) of the integrating circuits 90p, 90a, 90b are supplied to delay circuits 72, 71, 73, respectively.

  As described above, in the third embodiment, the white noise component is suppressed by integrating the signal to be compared and determined a predetermined number of times, and the frequency exceeding the range of ± π / 2, that is, a quarter frequency between subcarriers is set. It is possible to detect an excess frequency error, and it is possible to detect / correct a frequency error having a value smaller than the carrier wave interval, thereby improving the reception performance of the receiver.

Embodiment 4 FIG.
Next, the fourth embodiment will be described. The fourth embodiment is generally the same as the third embodiment, but the shift direction determination circuit 45 is different. FIG. 10 shows the deviation direction determination circuit 45 of the fourth embodiment.

The shift direction determination circuit 45 shown in FIG. 10 is generally the same as the shift direction determination circuit 45 of FIG. 9 except that an absolute value circuit 81, a subtraction circuit 82, a sign bit extraction circuit 83, and a logical product circuit 84 are added. Yes.
The absolute value circuit 81 obtains the absolute value of the output of the subtraction circuit 78 (the output of the difference calculation circuit 70).
The subtraction circuit 82 subtracts the output of the absolute value circuit 81 from a predetermined threshold value TH.
The sign bit extraction circuit 83 extracts the sign bit output from the subtraction circuit 82. The output of the sign bit extraction circuit 83 indicates negative when “1” and positive when “0”.

If the output of the absolute value circuit 81 is larger than the threshold value TH, the output of the subtraction circuit 82 becomes negative, and the output of the sign bit extraction circuit 83 indicates negative.
The AND circuit 84 outputs “−1” when the output of the sign bit extraction circuit 80 represents negative and the output of the sign bit extraction circuit 83 represents negative, and otherwise. "+1" is output.

  The sign bit extraction circuit 80, the absolute value circuit 81, the subtraction circuit 82, the sign bit extraction circuit 83, and the AND circuit 84 indicate the direction of the frequency error based on the difference obtained by the difference calculation circuit 70. A code signal output circuit for outputting a signal is configured. On the other hand, in the case of the deviation direction determination circuit 45 of FIG. 7, only the sign bit extraction circuit 80 constitutes a sign signal output circuit.

By such processing, it is more probable by comparing the comparison result of the power value of the differential demodulation result calculated from the pilot signal and the signal corresponding to the pilot signal for one carrier above and below it with a predetermined threshold value. Only the calculated value is used to invert the loop filter signal.
The operations of the comparison determination circuit 65 are summarized as shown in Table 2 below.

  The differential demodulation results of the pilot signal and the signals above and below one carrier when the frequency error does not exceed the 1/4 carrier frequency interval are shown in FIGS. 11A shows the differential demodulation result of the signal component under one carrier wave of the pilot signal, FIG. 11B shows the differential demodulation result of the pilot signal, and FIG. 11C shows the pilot signal. The differential demodulation result of the signal component on one carrier wave is shown.

  When the frequency error does not exceed the 1/4 carrier frequency interval, the influence of ICI is not so great, so the differential demodulation result of the signal above and below one carrier wave of the pilot signal is very different from the differential demodulation result of the pilot signal. The calculation result of the subtraction circuit 78 is a relatively small value, and the possibility of a detection error is large. On the other hand, the phase rotation amount in this case is ± π / 2, and no detection error occurs even if the rotation angle is obtained from the demodulation result of a normal TMCC pilot.

  On the other hand, when the frequency error exceeds the 1/4 carrier frequency interval, the adjacent carrier is affected by the pilot signal as shown in FIGS. 5C and 5D, so that the calculation result of the subtraction circuit 78 is somewhat large. It has a value, and it is difficult to cause a detection error. Further, in this case, the phase rotation amount is a value exceeding ± π / 2, and when a detection result of the TMCC pilot is used as usual, a detection error occurs.

  Therefore, in the fourth embodiment, by comparing the output result of the subtraction circuit 78 with a threshold value, the direction of frequency deviation is determined using the more probable result.

  As described above, in the fourth embodiment, the comparison result of the power value of the differential demodulation result calculated from the pilot signal and the signal corresponding to the pilot signal corresponding to one upper and lower carrier wave is compared with a predetermined threshold value. Only the more probable operation value can be used for inversion of the loop filter signal.

Embodiment 5 FIG.
Next, the fifth embodiment will be described. The fifth embodiment is generally the same as the first embodiment, but the second carrier frequency error detection circuit 114 is different. FIG. 12 shows an example of the second carrier frequency error detection circuit 114 used in the fifth embodiment.

The carrier frequency error detection circuit shown in FIG. 12 is generally the same as that shown in FIG. 3 except that the loop filter 44 is provided on the output side of the multiplication circuit 49.
In the configuration of FIG. 12, the output of the multiplication circuit 49 is input to the loop filter 44 to perform phase compensation. Even if it changes in this way, the same effect as the case of FIG. 3 is acquired.

Embodiment 6 FIG.
Next, the sixth embodiment will be described. The carrier frequency error detection circuit 114 of the sixth embodiment is generally the same as that of the first embodiment, but the configuration of the determination circuit 45 is different. The deviation direction determination circuit 45 in the sixth embodiment is configured as shown in FIG. The deviation direction determination circuit 45 shown in FIG. 13 is generally the same as the determination circuit of FIG. 7, but differs in the following points.

As in the first embodiment, the power calculation circuit 50 calculates the power value PWa of the signal component on one carrier wave of the pilot signal component and the power value PWb of the signal component on one carrier wave of the pilot signal component. The power value PWp of the signal component is not calculated.
The power values PWa and PWb are supplied to the delay circuits 71 and 73 of the difference calculation circuit 70 by the distribution switch 60. That is, the power value PWa is supplied to the delay circuit 71 and the power value PWb is supplied to the delay circuit 73.
The subtracting circuit 78 subtracts the output PWb of the delay circuit 73 from the output PWa of the delay circuit 71, and outputs a difference (PWa−PWb).
The sign bit extraction circuit 80 outputs a signal representing the sign of the output of the subtraction circuit 78.

  As the frequency error increases as shown in FIG. 5, the difference between the differential demodulation result of the signal component on one carrier wave of the pilot signal and the differential demodulation result of the signal component on one carrier wave of the pilot signal becomes significant. Therefore, the error direction can be determined from the sign of the calculation result of the subtraction circuit 78.

  As described in the first embodiment, when the frequency of the pilot signal is shifted upward, the signal component on one carrier wave has a larger influence, and the power (at the sampling point SP) becomes larger. The output of the subtraction circuit 78 becomes positive. When the frequency of the pilot signal shifts downward, the signal component under one carrier wave has a greater influence, and the power (at the sampling point SP) becomes larger, so that the output of the subtraction circuit 78 becomes negative. Therefore, the direction in which the frequency of the pilot signal is shifted can be determined based on the sign of the output of the subtraction circuit 78.

Therefore, as in the first embodiment, the output of the sign bit extracting circuit 80 that extracts the sign bit of the output of the subtracting circuit 78 can be used, for example, for determining the sign in the sign determining circuit 46 of FIG.
The operations of the comparison determination circuit 65 and the sign determination circuit 46 in this case are as shown in Table 3 below.

  As described above, in the sixth embodiment, the difference between the power values of the differential demodulation results of the upper and lower one carrier waves of the pilot signal is determined, so that the range of ± π / 2 is exceeded, that is, ¼ between the subcarriers. Since it is possible to detect a frequency error exceeding the frequency, the frequency error can be detected or corrected in a range smaller than the carrier interval, and the reception performance of the receiver can be improved.

Embodiment 7 FIG.
Next, a seventh embodiment will be described. The seventh embodiment is generally the same as the sixth embodiment, but the configuration of the deviation direction determination circuit 45 in the second carrier frequency error detection circuit 114 is different.
The deviation direction determination circuit 45 used in the seventh embodiment is configured as shown in FIG.

  The shift direction determination circuit shown in FIG. 14 is generally the same as the shift direction determination circuit of FIG. 13, but differs in that a power integration circuit 90 is added.

The power integration circuit 90 includes integration circuits 90a and 90b.
The power value calculated by the power calculation circuit 50 is distributed by the distribution switch 60 to the integrating circuits 90a and 90b. Specifically, the power value PWa of the signal component on one carrier wave of the pilot signal component is supplied to the integrating circuit 90a, and the power value PWb of the signal component on one carrier wave of the pilot signal component is supplied to the integrating circuit 90b. The
The integration circuits 90a and 90b are the same as the integration circuits 90a and 90b in FIG. 9, respectively.
The outputs (integrated values) of the integrating circuits 90a and 90b are supplied to the delay circuits 71 and 73, respectively, and the subtracting circuit 78 obtains the difference between the outputs of the integrating circuits 90a and 90b supplied via the delay circuits 71 and 73. .

  As described above, in the seventh embodiment, the white noise component is suppressed by determining the difference between the power values of the differential demodulation results of the upper and lower one carrier waves of the pilot signal a predetermined number of times, and ± π / 2 is suppressed. The frequency error can be detected / corrected in a range that exceeds the range and smaller than the carrier interval, and the frequency error that is larger than the conventional method can be corrected with high accuracy, thereby improving the reception performance of the receiver. Is possible.

Embodiment 8 FIG.
Next, an eighth embodiment will be described. The eighth embodiment is generally the same as the seventh embodiment. An example of the deviation direction determination circuit 45 used in the eighth embodiment is shown in FIG.

  The shift direction determination circuit 45 shown in FIG. 15 is generally the same as the shift direction determination circuit of FIG. 14, but is similar to the absolute value circuit 81, the subtraction circuit 82, and the sign bit described with reference to FIG. A take-out circuit 83 and a logical product circuit 84 are added.

  As shown in FIG. 6 and FIG. 11, only when the frequency error exceeds the 1/4 carrier frequency interval, the differential demodulation results of the upper and lower one carrier waves of the pilot signal produce a large difference. In other words, when the value of this calculation result is small, the rotation angle is within ± π / 2, and no detection error occurs in the direction determination method using the normal TMCC pilot signal.

  In the eighth embodiment, a more reliable calculation is performed by comparing the comparison result of the power value of the differential demodulation result calculated from the signal corresponding to the pilot signal for one carrier above and below the pilot signal with a predetermined threshold value. Only the value can be used to invert the loop filter signal.

(A)-(c) is a figure explaining the correlation of an OFDM signal. It is a block diagram which shows the OFDM receiver in which the carrier wave signal reproduction | regeneration circuit of Embodiment 1 of this invention is used. It is a block diagram which shows the 2nd carrier frequency error detection circuit 114 of Embodiment 1 of this invention. (A)-(d) is a figure which shows the influence which a frequency shift has on a demodulation signal. (A)-(d) is a figure which shows the influence which a frequency shift has on a demodulation signal. (A)-(c) is a figure which shows the influence which it gives to the signal of 1 carrier wave of a pilot signal when the frequency shift exceeds 1/4 of a carrier wave interval. It is a block diagram which shows the shift | offset | difference direction determination circuit used in Embodiment 1 of this invention. It is a block diagram which shows the structure of the 2nd carrier frequency error detection circuit 114 used in Embodiment 2 of this invention. It is a block diagram which shows the shift | offset | difference direction determination circuit used in Embodiment 3 of this invention. It is a block diagram which shows the shift | offset | difference direction determination circuit used in Embodiment 4 of this invention. It is a figure which shows the influence which it has on the signal above and below one carrier wave of a pilot signal when a frequency shift does not exceed 1/4 of a carrier wave interval. It is a block diagram which shows the structure of the 2nd carrier frequency error detection circuit 114 used in Embodiment 5 of this invention. It is a block diagram which shows the shift | offset | difference direction determination circuit used in Embodiment 6 of this invention. It is a block diagram which shows the shift | offset | difference direction determination circuit used in Embodiment 7 of this invention. It is a block diagram which shows the shift | offset | difference direction determination circuit used in Embodiment 8 of this invention.

Explanation of symbols

  20 signal component extraction circuit, 30 differential demodulation circuit, 31, 32 RAM, 33 sign inversion circuit, 34 complex multiplication circuit, 36 one-symbol interval average calculation circuit, 43 ROM, 44 loop filter, 45 deviation direction determination circuit, 46 code Decision circuit, 48 mismatch detection circuit, 49 multiplication circuit, 50 power operation circuit, 60 distribution circuit, 65 comparison determination circuit, 70 difference operation circuit, 80 code bit extraction circuit, 101 antenna, 102 tuner, 104 band pass filter, 105 A / D conversion circuit, 106 demultiplexer, 107, 108 low-pass filter, 109 complex multiplication circuit, 110 guard removal circuit, 111 fast Fourier transform (FFT) circuit, 112 carrier recovery circuit, 113 carrier frequency error detection Road, 113a correlation value calculation circuit, 113b frequency error calculating circuit, 114 a carrier frequency error detection circuit, 115 adder circuits, 116 numerically controlled oscillator, 130 carrier frequency reproducing circuit, 131 a clock oscillator.

Claims (17)

The input orthogonal frequency division multiplexing (OFDM) complex digital signal is orthogonally demodulated, converted to a baseband frequency, removed the guard interval (GI), and Fourier transformed to convert the frequency domain signal. An OFDM signal demodulating device that detects the carrier frequency, and then recovers the carrier frequency used in the quadrature demodulation based on the signal obtained by the quadrature demodulation and the frequency domain signal obtained by the Fourier transform. In the circuit
A correlation value between an I signal component or Q signal component obtained by the orthogonal demodulation and a signal delayed by one effective symbol time is calculated, and a first frequency error is calculated based on the calculated value A frequency error detection circuit;
A second frequency error detection circuit for detecting a second frequency error based on the TMCC pilot signal component in the Fourier transformed frequency domain and the data signal component on and under the one carrier;
An adder circuit for adding the first frequency error and the second frequency error;
A numerical control transmission circuit whose oscillation frequency is controlled by the output of the addition circuit,
The second frequency error detection circuit includes:
The TMCC pilot signal component in the frequency domain subjected to Fourier transform and the data signal component on one carrier and one carrier thereof are delayed by one effective symbol time, and the TMCC pilot signal component delayed by one effective symbol time and the current TMCC Differentially demodulated using a pilot signal component, differentially demodulated using a signal component on one carrier delayed by one effective symbol time and a signal component on one current carrier, and delayed by one effective symbol time A differential demodulation circuit that differentially demodulates using the lower signal component and the signal component under one current carrier wave;
A phase angle output circuit for outputting a phase angle corresponding to an I component and a Q component on a complex plane of a differential demodulation result by the differential demodulation circuit for the TMCC pilot signal component;
Based on the I component and Q component in the differential demodulation result by the differential demodulation circuit for the signal component on the one carrier wave, and the I component and Q component in the differential demodulation result on the signal component on the one carrier wave A deviation direction determination circuit for determining a direction of frequency deviation;
A code determination circuit that determines a code of the phase angle based on a code of the phase angle output by the phase angle output circuit and a direction of shift by the shift direction determination circuit;
A carrier frequency recovery circuit of an OFDM signal demodulator, wherein the phase angle whose code is determined by the code determination circuit is output as the second frequency error. The code determination circuit includes:
When the shift direction determination circuit detects a shift in the upward direction and the phase angle output circuit outputs a negative phase angle, the sign of the phase angle output by the phase angle output circuit is inverted,
When the shift direction determination circuit detects a shift in the downward direction and the phase angle output circuit outputs a positive phase angle, the sign of the phase angle output by the phase angle output circuit is inverted. A carrier frequency recovery circuit for an OFDM signal demodulator according to claim 1. The comparison judgment circuit
A difference calculation circuit that calculates a difference between a value according to an upward shift of the carrier frequency of the pilot signal component and a value according to a downward shift of the carrier frequency of the pilot signal component;
The carrier frequency recovery circuit of the OFDM signal demodulator according to claim 2, further comprising: a code signal output circuit that outputs a signal indicating a frequency shift direction based on an output of the difference calculation circuit.   4. The OFDM signal according to claim 3, wherein the code determination circuit performs the inversion of the code on condition that a difference obtained by the difference calculation circuit of the shift direction determination circuit is larger than a predetermined value. A carrier frequency recovery circuit of a demodulator. The deviation direction determination circuit includes:
First signal power is obtained from the I and Q components in the differential demodulation result for the signal component on the one carrier wave, and from the I and Q components in the differential demodulation result for the signal component on the one carrier wave. A signal power calculation circuit for obtaining a second signal power;
The carrier frequency of the OFDM signal demodulator according to claim 1, further comprising a comparison / determination circuit that determines a direction of frequency deviation based on the first signal power and the second signal power. Reproduction circuit.   The comparison determination circuit determines that the frequency of the pilot signal is shifted upward when the first signal power is larger than the second signal power, and the first signal power is the second signal power. 6. The carrier frequency recovery circuit of an OFDM signal demodulator according to claim 5, wherein it is determined that the frequency of the pilot signal is shifted downward when the signal power is smaller than the signal power of the OFDM signal demodulator. The comparison determination circuit includes:
A difference calculation circuit for obtaining a difference between the first signal power and the second signal power;
7. A carrier frequency recovery of an OFDM signal demodulator according to claim 5, further comprising: a code signal output circuit that outputs a signal indicating a direction of a frequency error based on the difference obtained by the difference calculation circuit. circuit. The signal power calculation circuit further includes:
A third signal power is obtained from the I component and the Q component in the differential demodulation result for the pilot signal component,
The comparison / determination circuit may determine the frequency based on which of a difference between the first signal power and the third signal power and a difference between the second signal power and the third signal power is greater. The carrier frequency recovery circuit of the OFDM signal demodulating device according to claim 5, wherein the direction of deviation is determined. When the absolute value of the difference between the first signal power and the third signal power is larger than the absolute value of the difference between the second signal power and the third signal power, the comparison determination circuit It is determined that the frequency of the pilot signal is shifted downward, and the absolute value of the difference between the first signal power and the third signal power is the second signal power and the third signal. The carrier frequency recovery circuit of the OFDM signal demodulator according to claim 8, wherein it is determined that the frequency of the pilot signal is shifted upward when it is smaller than an absolute value of a difference from power. The comparison determination circuit calculates a difference between an absolute value of a difference between the first signal power and the third signal power and an absolute value of a difference between the second signal power and the third signal power. A difference calculation circuit to be obtained;
The carrier frequency recovery of the OFDM signal demodulator according to claim 5 or 9, further comprising: a code signal output circuit that outputs a signal indicating a direction of a frequency error based on the difference obtained by the difference calculation circuit. circuit. The code signal output circuit comprises:
When the output of the difference calculation circuit indicates a downward shift and the absolute value of the output of the difference calculation circuit is larger than a predetermined threshold, a signal indicating that the frequency error is in the downward direction is output. The carrier wave frequency recovery circuit of the OFDM signal demodulator according to claim 7 or 10. The deviation direction determination circuit includes:
An integration circuit for adding a predetermined number of symbols to the signal power value calculated by the signal power calculation circuit;
6. The carrier frequency recovery circuit of the OFDM signal demodulator according to claim 5, wherein the comparison / determination circuit determines the direction of the deviation based on an addition result by the integration circuit. The second frequency error detection circuit includes:
An average calculation circuit for calculating an average of one symbol of the differential demodulation result;
The carrier frequency recovery circuit of the OFDM signal demodulator according to claim 1, wherein the shift direction determination circuit determines the shift direction based on an output of the average arithmetic circuit. The carrier frequency recovery circuit of the OFDM signal demodulator according to claim 13, wherein the phase angle output circuit outputs a phase angle corresponding to the output of the average arithmetic circuit. The second frequency error detection circuit comprises:
A loop filter having the output of the phase angle output circuit as an input;
The carrier frequency recovery circuit of the OFDM signal demodulator according to claim 1, wherein the code determination circuit receives an output of the loop filter as an input. The second frequency error detection circuit comprises:
A loop filter having the output of the code determination circuit as an input;
The carrier frequency recovery circuit of the OFDM signal demodulator according to claim 1, wherein the adding circuit adds the output of the loop filter and the output of the first frequency error detection circuit. The input orthogonal frequency division multiplexing (OFDM) complex digital signal is orthogonally demodulated, converted to the baseband frequency, removed the guard interval (GI), and Fourier transformed to obtain the frequency domain signal. Carrier wave frequency recovery method for recovering the carrier frequency used in the quadrature demodulation based on the signal obtained by the quadrature demodulation and the signal in the frequency domain obtained by the Fourier transform In
A correlation value between an I signal component or Q signal component obtained by the orthogonal demodulation and a signal delayed by one effective symbol time is calculated, and a first frequency error is calculated based on the calculated value A frequency error detection step;
A second frequency error detecting step for detecting a second frequency error based on the TMCC pilot signal component in the Fourier transformed frequency domain and the data signal component on one carrier and one carrier;
An adding step of adding the first frequency error and the second frequency error;
A numerical control transmission step in which the oscillation frequency is controlled by the output of the addition step,
The second frequency error detection step includes:
The TMCC pilot signal component in the frequency domain subjected to Fourier transform and the data signal component on one carrier and one carrier thereof are delayed by one effective symbol time, and the TMCC pilot signal component delayed by one effective symbol time and the current TMCC Differentially demodulated using a pilot signal component, differentially demodulated using a signal component on one carrier delayed by one effective symbol time and a signal component on one current carrier, and delayed by one effective symbol time A differential demodulation step for differential demodulation using the lower signal component and the signal component under the current carrier;
A phase angle output step of outputting a phase angle corresponding to an I component and a Q component on a complex plane of a differential demodulation result by the differential demodulation step for the TMCC pilot signal component;
Based on the I and Q components in the differential demodulation result of the differential demodulation step for the signal component on the one carrier wave, and the I and Q components in the differential demodulation result on the signal component on the one carrier wave A deviation direction determination step for determining a direction of frequency deviation;
A code determination step for determining a code of the phase angle based on a code of the phase angle output by the phase angle output step and a shift direction by the shift direction determination step;
A phase frequency whose code is determined in the code determination step is output as the second frequency error. A carrier frequency recovery method of an OFDM signal demodulator.

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