JP2009302200A - Film for cof, semiconductor device, and production method of film for cof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for reducing a stress caused by bending an inner lead joined to a semiconductor chip. <P>SOLUTION: This film for COF comprises a chip mounting region set in a semiconductor device forming region of a base film, a plurality of inner leads formed in the chip mounting region, an outer lead for connecting between the inner leads and a terminal, a solder resist layer covering the outer lead, and also has a thick wall portion of enlarged thickness in a chip mounting region side of the solder resist layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a COF film, a semiconductor device, and a method for producing a COF film used when continuously manufacturing a COF (Chip On Film) type semiconductor device.

  In the conventional tape carrier, a plurality of sprocket holes are arranged at a predetermined pitch in the edge regions on both sides of a long base film made of polyimide, and device holes are formed in the chip mounting region of the semiconductor device formation region of the base film. An inner lead is formed at the same time, an outer lead that connects the inner lead and the terminal is formed, a bump electrode of a semiconductor chip is bonded to the inner lead, and a sealing layer made of an epoxy resin is formed around the device hole. Semiconductor devices are manufactured continuously.

In addition, a plurality of notches are provided in the direction perpendicular to the winding direction of the tape carrier, and a protective resin such as silicone resin is applied to both sides of the outer lead that straddles the notches to facilitate bending of the tape carrier. The size of the apparatus is reduced (for example, refer to Patent Document 1).
Japanese Patent Laid-Open No. 2-132418 (mainly gazette page 2 lower right column-page 3 upper right column, Fig. 1)

The above-described conventional technique is a technique for improving the bendability of a TCP (Tape Carrier Package) type semiconductor device. In recent years, a semiconductor device for a driver of a liquid crystal display device is a COF type semiconductor device. In order to increase the number of semiconductor devices manufactured from one roll of COF film, the product pitch is becoming smaller.
The COF film for forming this COF type semiconductor device is thinner (50 μm) than the thickness of a tape carrier for a TCP type semiconductor device (usually about 75 μm) in order to improve bendability. The following is formed.

In addition, with the increasing number of functions of semiconductor chips for drivers, assuming that no device holes or notches are provided, the thickness of the wiring pattern formed by the inner leads and outer leads is reduced and the width is reduced to be finer. We are trying to make it.
Such a conventional COF type semiconductor device will be described with reference to FIGS.
FIG. 9 is an explanatory view showing the upper surface of a film for COF in which a conventional semiconductor device is formed, and FIG. 10 is an explanatory view showing a cross section taken along the line XX of FIG.

In FIG. 9, the upper drawing shows the semiconductor chip and the solder resist layer as transparent with the sealing layer removed for the sake of explanation, and the lower drawing shows the sealing layer, the semiconductor chip and The state excluding the solder resist layer is shown.
9 and 10, reference numeral 1 denotes a COF film.
Reference numeral 2 denotes a base film of the COF film 1, which is a long thin tape-like member (50 μm or less) made of a resin material such as polyimide having a relatively high heat resistance, and its winding direction ( Sprocket holes 3 that are fitted to sprocket teeth (not shown) are formed in one row at a regular regular pitch in edge regions 2a on both sides along the base film 2).

A semiconductor chip 5 has a bump electrode 6 as an electrode terminal electrically connected to a circuit element (not shown) as shown in FIG. 10, and a semiconductor device between the edge regions 2a of the base film 2 The chip is mounted on the chip mounting area 8 set at a predetermined pitch along the winding direction in the forming area 2b.
The chip mounting area 8 is an area that is slightly larger than the semiconductor chip 5 mounted on the base film 2 at the center of the semiconductor device forming area 2b of the base film 2 (in the lower diagram of FIG. A rectangular region shown), that is, a region in which a gap for injecting the sealing resin is added around the side surface of the outer diameter shape of the semiconductor chip 5 after the semiconductor chip 5 is joined.

As shown in FIG. 9, a plurality of inner leads 10 are formed on the base film 2 in the chip mounting area 8, and the bump electrodes 6 of the semiconductor chip 5 are joined by soldering or the like.
Reference numeral 11 denotes an outer lead, which connects between a terminal 12 used for signal input / output with an external wiring (not shown) and an inner lead 10 to which the bump electrode 6 is bonded.

The inner lead 10, the outer lead 11, and the terminal 12 are integrally formed by patterning a thin film (for example, 2 to 12 μm in thickness) of a conductive material such as copper (Cu), thereby wiring on the base film 2. A pattern is formed.
Reference numeral 14 denotes a solder resist layer, which is a solder resist formation region 15 set in the semiconductor device formation region 2b of the base film 2 (between a rectangle indicated by a thick two-dot chain line in the lower diagram of FIG. 9 and the chip mounting region 8). Of the wiring pattern covering the base film 2 on which the outer lead 11 is formed, that is, the base film 2 on which the wiring pattern excluding the chip mounting region 8 on which the inner lead 10 is formed and the terminals 12 are formed. , And a protective layer for securing the strength thereof, which is formed to a thickness of 5 to 40 μm by applying a resist material such as polyimide.

Reference numeral 16 denotes a sealing layer, which has a relatively high viscosity for improving and protecting the strength of the joint between the inner lead 10 and the bump electrode 6 between the base film 2 in the chip mounting region 8 and the lower surface of the semiconductor chip 5. A low epoxy resin or the like is injected to form the chip mounting region 8 and the solder resist layer 14 therearound.
The conventional COF film 1 is formed by the base film 2 in which the sprocket hole 3 is formed, the wiring pattern formed on the inner lead 10, the outer lead 11 and the terminal 12, and the solder resist layer 14. Is done.

Reference numeral 18 denotes a cut area, which is a rectangular area indicated by a rough broken line in the lower diagram of FIG. 9, that is, a rectangular area including the solder resist forming area 15 of the semiconductor device forming area 2 b of the base film 2 and all the terminals 12. This cut area 18 is punched out of the COF film 1 to form one COF type semiconductor device 20.
Reference numeral 22 denotes a defective product cut area, which is set as a rectangular area indicated by a fine broken line in the lower diagram of FIG. 9, that is, a rectangular area including the semiconductor chip 5 mounted in the chip mounting area 8. In order to distinguish the semiconductor device 20 determined to be defective during the inspection of the semiconductor device 20 formed on the semiconductor device 20, the defective product cut area 22 is set as an area from which the semiconductor chip 5 is extracted.

As shown in FIG. 11, a plurality of such semiconductor devices 20 are formed on the COF film 1 at a predetermined pitch, and then the electrical characteristics and the like of the semiconductor device 20 are inspected in an inspection process.
At this time, in the semiconductor device 20 determined to be defective, the defective product cut area 22 is punched using a punch or the like.

  At the time of this punching operation, the worker picks and lifts the side edge portion of the base film 2 where the semiconductor device 20 determined to be defective is formed, but the base film 2 of the COF film 1 is lifted. Is formed thin in order to improve bendability, the side edge of the base film 2 is bent as shown in FIG. 12, and the effect thereof is that the product pitch is reduced as shown in FIG. The stress is also caused by the difference in elongation at the bending portion between the COF film 1 made of polyimide and the wiring pattern made of a metal such as copper, that is, the difference in elastic modulus. When the generated stress exceeds the strength of the wiring pattern, the wiring pattern is broken, and there is a problem that the semiconductor device 20 determined to be non-defective is defective.

As shown in FIG. 14 in which the Y portion of FIG. 10 is enlarged, the inner lead 10 (A portion shown in FIG. 9) formed in the direction orthogonal to the winding direction of the base film 2 Since a bending force acts in a state of being bonded to the bump electrode 6, the stress at the Z portion of the inner lead 10 shown in FIG.
Further, when the amount of lifting of the base film 2 becomes excessive, the stress of the inner lead 10 (B portion shown in FIG. 9) formed in the winding direction of the base film 2 becomes excessive, and the same problem occurs.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide means for reducing stress due to bending of an inner lead bonded to a semiconductor chip.

  In order to solve the above problems, the present invention provides a chip mounting region set in a semiconductor device forming region of a base film, a plurality of inner leads formed in the chip mounting region, and a space between the inner leads and the terminals. In the COF film comprising an outer lead for connecting the outer lead and a solder resist layer covering the outer lead, a thick film portion having a thicker thickness is formed on the chip mounting region side of the solder resist layer. To do.

  As a result, the present invention can increase the bending of the thin film portion of the solder resist layer and suppress the bending on the chip mounting region side which is a thick film portion, and in the direction perpendicular to the winding direction of the base film. The stress generated in the formed inner lead can be reduced to prevent breakage of the inner lead, and the stress generated in the inner lead formed in the winding direction of the base film can be reduced to reduce the inner lead. The effect that a fracture | rupture can be prevented is acquired.

  Examples of the film for COF according to the present invention will be described below with reference to the drawings.

1 is an explanatory view showing the upper surface of the film for COF on which the semiconductor device of the embodiment is formed, FIG. 2 is an explanatory view showing a cross section taken along the line CC of FIG. 1, and FIG. FIG. 4 is a partial enlarged view, FIG. 4 is an explanatory view showing a cross section taken along the DD cross section line of FIG.
In addition, the same part as the said FIG. 9, FIG. 10 attaches | subjects the same code | symbol, and abbreviate | omits the description.

Further, in FIG. 1, the upper diagram shows the semiconductor chip and the solder resist layer as transparent with the sealing layer removed for the sake of explanation, and the lower diagram shows the sealing layer, the semiconductor chip and The state excluding the solder resist layer is shown. FIG. 5 shows a cross section similar to FIG.
1 to 4, reference numeral 30 denotes a second solder resist layer, which is the solder resist layer 14 described with reference to FIGS. 9 and 10 (in this description, for the sake of distinction, it is referred to as the first solder resist layer 14). ) The same material as that of the first solder resist layer 14 is laminated in the same thickness around the upper chip mounting region 8.

  Thus, in the COF film 1 of the present embodiment, the first solder resist layer 14 and the second solder resist layer 30 are laminated on the chip mounting region 8 side of the first solder resist layer 14. A thicker film portion having a larger thickness is formed, and a stepped portion 32 made of a plane formed in the vertical direction on the upper surface of the first solder resist layer 14 is formed at the outer end of the second solder resist layer 30. .

Note that a region where only the first solder resist layer 14 is formed is also referred to as a thin film portion.
In this case, the second solder resist layer 30 in the direction orthogonal to the winding direction of the base film 2 is an inner formed in the direction orthogonal to the winding direction to which the pad electrode 6 is bonded, as shown in FIG. The lead 10 is formed in a region including all portions of the outer lead 11 (A portion shown in FIG. 1) extending in the direction perpendicular to the winding direction.

Below, according to the process shown by P in FIG. 5, the manufacturing method of the film for COF of a present Example and a semiconductor device is demonstrated.
A sprocket hole 3 is formed in the edge region 2a on both sides of the base film 2 made of polyimide having a thickness of about P1 and a thickness of about 38 μm, and a copper foil having a thickness of about 6 μm is pasted on one surface thereof to conduct the conductive material The body layer 35 is formed.

The conductor layer 35 is patterned by P2, photolithography, and etching to form a wiring pattern including the plurality of inner leads 10 in the chip mounting region 8, the terminals 12, and the outer leads 11 that connect them.
P3, a base on which the outer lead 11 is formed by applying a resist material on the base film 2 on which the wiring pattern excluding the chip mounting area 8 and the terminal 12 is formed, that is, on the solder resist forming area 15 by screen printing. A first solder resist layer 14 having a thickness of about 20 μm is formed on the film 2.

P4, again, by a screen printing method, a resist material is applied to the chip mounting region 8 side on the first solder resist layer 14, and a second solder resist layer having a thickness of about 20 μm is formed around the chip mounting region 8. 30 is formed.
In this way, the second solder resist layer 30 is laminated on the chip mounting region 8 side on the first solder resist layer 14, and the thick film portion is formed on the chip mounting region 8 side. The film for COF 1 of this embodiment in which the wiring pattern terminals 12 and the inner leads 10 formed on the film 2 are exposed is formed.

P5, the semiconductor chip 5 formed in another process is prepared, and the bump electrode 6 of the semiconductor chip 5 is soldered or gold (Au) on the inner lead 10 exposed in the chip mounting region 8 of the COF film 1 Join with etc.
After the bonding of P6 and the semiconductor chip 5, the chip mounting region is formed from the gap between the end surface of the first and second solder resist layers 14 and 30 on the chip mounting region 8 side and the side surface forming the outer diameter shape of the semiconductor chip 5. The sealing resin is injected between the base film 2 of FIG. 8 and the semiconductor chip 5 to form the sealing layer 16 on the chip mounting region 8 and the second solder resist layer 30 around the chip mounting region 8, and the film for COF A semiconductor chip 5 is mounted on one chip mounting area 8.

In this way, the semiconductor chips 5 are sequentially mounted in each chip mounting area 8 of the COF film 1, and the COF film 1 in which a plurality of semiconductor devices 20 are formed at a predetermined pitch as shown in FIG. 6 is manufactured. Then, the semiconductor device 20 determined to be a non-defective product in the inspection process is punched in the cut area 18 to form one COF type semiconductor device 20.
Further, in the semiconductor device 20 in the inspection process of the semiconductor device 20, the defective product cut area 22 is punched using a punch or the like.

  Even if the worker picks up and lifts the side edge portion of the portion where the semiconductor device 20 determined to be defective in the base film 2 is picked up with a finger during the punching operation, the COF film 1 of this embodiment is used. Since the second solder resist layer 30 is laminated on the first solder resist layer 14 and the thick film portion is formed on the chip mounting region 8 side, as shown in FIG. The bending of the thin film portion where only the resist layer 14 is formed can be increased to suppress the bending of the thick film portion on the chip mounting area 8 side, and the bump film 6 is bonded to the base film 2. It is possible to reduce the stress generated in the inner lead 10 of part A shown in FIG. 1 formed in the direction perpendicular to the winding direction, thereby preventing the inner lead 10 from being broken, and the yield in the manufacture of the COF type semiconductor device 20. To improve It can be.

  Further, since the second solder resist layer 30 of the present embodiment is formed around the chip formation region 8, even if the lifting amount of the base film 2 becomes excessive, the base film 2 is the same as above. The inner lead 10 in the portion B shown in FIG. 1 formed in the winding direction is not excessively stressed, and the inner lead 10 formed in the winding direction to which the bump electrode 6 is bonded is prevented from breaking. can do.

  Furthermore, the first and second solder resist layers 14 and 30 each having a thickness of about 20 μm are laminated on the base film 2 formed to a thickness of 50 μm or less (38 μm in this embodiment), and the thickness is 40 μm. Since the film thickness portion is formed to the extent, the combined thickness of the base film 2 and the first and second solder resist layers 14 and 30 is about the same as the thickness of the tape carrier forming the TCP type semiconductor device. The strength in the vicinity of the inner lead 10 can be made extremely high.

Furthermore, since a film thickness portion in which the first and second solder resist layers 14 and 30 are laminated is formed around the chip mounting region 8 of the present embodiment, the film thickness portion is made of a sealing material. It can also function as a dam when injecting.
In the present embodiment, the step portion 32 of the second solder resist layer 30 has been described as being formed in a plane formed in the vertical direction on the upper surface of the first solder resist layer 14, but is shown in FIG. As described above, a stepped portion 32 formed of an arc surface or a slope that expands toward the upper surface of the first solder resist layer 14 may be formed at the outer end of the second solder resist layer 30.

In this way, it is possible to increase the curvature radius of the bending of the thin film portion where only the first solder resist layer 14 is formed, and to further reduce the stress of the outer lead 11 formed in the thin film portion.
In the present embodiment, the second solder resist layer 30 is formed around the chip formation region 8 and is formed with the first solder resist layer 14 left outside the stepped portion 32. The second solder resist layer 30 may be formed over the entire length in the direction perpendicular to the winding direction of the base film 2 of the first solder resist layer 14.

By doing so, it is possible to further reduce the stress of the inner lead 10 in the above-described A portion and the outer lead 11 formed under the second solder resist layer 30 formed over the entire length.
As described above, in this embodiment, the thick resist film is formed on the chip mounting region side of the solder resist layer that covers the outer leads of the wiring pattern formed on the COF film. The bending of the thin film portion of the layer can be increased to suppress the bending on the chip mounting area side which is a thick film portion, and the stress generated in the inner lead formed in the direction perpendicular to the winding direction of the base film can be reduced. Thus, the inner lead can be prevented from being broken, and the stress generated in the inner lead formed in the winding direction of the base film can be reduced to prevent the inner lead from being broken.

Explanatory drawing which shows the upper surface of the film for COF which formed the semiconductor device of the Example Explanatory drawing which shows the cross section along CC sectional line of FIG. Partial enlarged view of the semiconductor device of FIG. Explanatory drawing which shows the cross section along the DD cross section line of FIG. Explanatory drawing which shows the manufacturing method of the semiconductor device of an Example Explanatory drawing which shows the upper surface of the film for COF which formed the semiconductor device of an Example continuously Explanatory drawing which shows the bending state in the E section of FIG. Explanatory drawing which shows the other form of the soldering resist layer of an Example Explanatory drawing which shows the upper surface of the film for COF which formed the conventional semiconductor device Explanatory drawing which shows the cross section along the XX cross section line of the conventional semiconductor device. Explanatory drawing which shows the upper surface of the film for COF which formed the conventional semiconductor device continuously Explanatory drawing which shows the side of the state which picked up the film for conventional COF Explanatory drawing which shows the upper surface of the state which picked up the film for conventional COF Explanatory drawing which shows the bending state in the Y section of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 COF film 2 Base film 2a Edge area 2b Semiconductor device formation area 3 Sprocket hole 5 Semiconductor chip 6 Bump electrode 8 Chip mounting area 10 Inner lead 11 Outer lead 12 Terminal 14 Solder resist layer (first solder resist layer)
DESCRIPTION OF SYMBOLS 15 Solder resist formation area 16 Sealing layer 18 Cut area 20 Semiconductor device 22 Defective product cut area 30 2nd solder resist layer 32 Step part 35 Conductor layer

Claims (9)

A chip mounting area set in the semiconductor device forming area of the base film;
A plurality of inner leads formed in the chip mounting region;
An outer lead connecting between the inner lead and the terminal;
A film for COF comprising a solder resist layer covering the outer lead,
A COF film, wherein a thick film portion having a large thickness is formed on the chip mounting region side of the solder resist layer. In claim 1,
The COF film, wherein the thick film portion is formed around the chip mounting region. In claim 1,
The film for COF, wherein the thick film portion is formed over the entire length of the solder resist layer having a small thickness in the direction perpendicular to the winding direction of the base film. In any one of Claims 1 to 3,
The film for COF, wherein the base film has a thickness of 50 μm or less.   5. A semiconductor device comprising a COF film according to claim 1, wherein a semiconductor chip having an electrode terminal bonded to the inner lead is mounted in the chip mounting region. Preparing a base film in which a chip mounting area is set in a semiconductor device forming area;
Forming a conductive layer made of a conductive material on the base film;
Patterning the conductor layer, forming a plurality of inner leads in the chip mounting region, and forming an outer lead connecting between the inner lead and the terminal;
Forming a first solder resist layer covering the outer leads;
And a step of forming a second solder resist layer on the chip mounting region side on the first solder resist layer. In claim 6,
A method for producing a film for COF, wherein the second solder resist layer is formed around the chip mounting region. In claim 6,
The second solder resist layer is formed over the entire length of the first solder resist layer in the direction perpendicular to the winding direction of the base film. In any one of Claims 6 thru | or 8,
The method for producing a film for COF, wherein the base film has a thickness of 50 μm or less.

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