JP2009239436A - Hysteresis comparator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a hysteresis comparator wherein a hysteresis voltage is not changed and influence of temperature characteristics is not received even when the threshold of an input voltage changes. <P>SOLUTION: Resistors 2 and 3 connected between an input terminal IN and the ground generate a voltage corresponding to an input voltage Vin and supply it to the input terminal of a comparator 1. While the comparator 1 outputs "H", the drain current of a PMOS 6 flows to the resistor 8. The drain current of a PMOS 4 equivalent to the drain current of a PMOS 6 is given to the connection point of the resistor 2 and the resistor 3, and thus the hysteresis voltage is set. Even when the temperature changes and the resistance values of the resistors 2, 3 and 8 change, the value of the hysteresis voltage set by supplying the drain current of the PMOS 4 to the connection point of the resistor 2 and the resistor 3 is not changed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a hysteresis comparator.

  The comparator compares the reference voltage with the input voltage, outputs “H” (high level) when the input voltage is higher than the reference voltage, and “L” (low level) when the input voltage is lower than the reference voltage. Is output. However, when the input voltage rises and exceeds the reference voltage in the presence of noise, the output of the comparator is disturbed and “H” and “L” are repeated in a short period.

In order to mitigate the influence of such noise, the hysteresis comparator has hysteresis in the threshold value of the input voltage. In other words, a voltage difference (hysteresis voltage) is provided between the threshold of the input voltage when the output voltage of the hysteresis comparator transitions to “H” and the threshold of the input voltage when the output voltage of the hysteresis comparator transitions to “L”. ing.
FIG. 2 is a diagram showing a conventional hysteresis comparator circuit, which is described in Patent Document 1 below.
JP 2001-174337 A

  The hysteresis comparator circuit of FIG. 2 is a circuit that compares the reference voltage generated by the first reference voltage circuit with the voltage generated by the second reference voltage circuit as an input signal. A comparator 24, an inverter circuit 25, and a transistor 26. In accordance with the output of the comparator 24, the transistor 26 is turned on and off, and both ends of the resistor 23 are short-circuited or opened to provide a hysteresis voltage.

  In the hysteresis comparator circuit of Patent Document 1, when the reference voltage varies, the threshold value of the comparator 24 changes, and an appropriate hysteresis width cannot be maintained.

  It is an object of the present invention to provide a hysteresis comparator that ensures an appropriate hysteresis width and is not affected by temperature characteristics even when there is a threshold fluctuation of the input voltage.

In order to achieve the above object, a hysteresis comparator according to an aspect of the present invention includes:
A first resistor having one end connected to a fixed potential and the other end connected to a signal input terminal, and generating a voltage corresponding to the input signal;
When the reference voltage is input to one input terminal, the other input terminal is connected to the other end of the first resistor, and the voltage at the other end of the first resistor is lower than the reference voltage, the first voltage A comparator that outputs a logic level and outputs a second logic level when the voltage at the other end of the first resistor is greater than or equal to the reference voltage;
A second resistor provided between the power source and the fixed potential;
Period detecting means for detecting a period during which the comparator outputs the second logic level;
Current supply means for supplying current from the power source to the second resistor during the period detected by the period detection means, and generating a correction current corresponding to the current to be applied to the other end of the first resistor;
It is characterized by providing.

  Note that a third resistor connected between the other end of the first resistor and the signal input terminal may be provided.

  The first resistor and the second resistor may have negative temperature characteristics.

  A hysteresis comparator may be formed on the semiconductor substrate.

  According to the present invention, it is possible to realize a hysteresis comparator that can secure an appropriate hysteresis width even when the threshold value of the input voltage varies, and that is not affected by temperature characteristics.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit diagram showing a hysteresis comparator according to an embodiment of the present invention.

  This hysteresis comparator is formed on a semiconductor substrate, and outputs a first logic level “L” or a second logic level “H”, and a comparator (CMP) 1 and a signal input terminal input terminal IN. And a resistor 2 that is a third resistor and a resistor 3 that is a first resistor, and a P-channel MOS transistor (hereinafter referred to as PMOS) 4 connected in series between the resistor and the ground that is a fixed potential. Yes.

  The connection point of the resistors 2 and 3 and the drain of the PMOS 4 are connected to the non-inverting input terminal (+) of the comparator 1. The reference voltage Vref1 is input to the inverting input terminal (−) of the comparator 1, and the output terminal of the comparator 1 is connected to the output terminal OUT. The source of the PMOS 4 is connected to the power supply VDD.

  The source of the PMOS 5 and the source of the PMOS 6 are connected to the power supply VDD. The drain of the PMOS 5 is commonly connected to the gates of the PMOS 4 and 6. The gate of the PMOS 5 is connected to the output terminal of the comparator 1.

The drain of the PMOS 6 is connected to the gates of the PMOSs 4 and 6 and is connected to the drain of an N-channel MOS transistor (hereinafter referred to as NMOS) 7. The source of the NMOS 7 is connected to one end of a resistor 8 as a second resistor, and the other end of the resistor 8 is connected to the ground.
The PMOS 5 is a period detection means for detecting the period during which the comparator 1 outputs “H”. The PMOSs 4 and 6 flow current from the power source to the resistor 8 and flow to the resistor 8 during the period detected by the PMOS 5. The current supply means generates a current corresponding to the current and applies the current to the connection point of the resistors 2 and 3.

  The connection point between the source of the NMOS 7 and the resistor 8 is connected to the non-inverting input terminal (+) of the amplifier (AMP) 9. A reference voltage Vref2 is divided by resistors 10 and 11 and input to the inverting input terminal (−) of the amplifier 9. The output terminal of the amplifier 9 is connected to the gate of the NMOS 7.

Next, the operation of the hysteresis comparator of FIG. 1 will be described.
The input voltage Vin input from the input terminal IN is divided by the resistors 2 and 3 and applied to the non-inverting input terminal (+) of the comparator 1. When the input voltage Vin is low, the voltage V0 of the non-inverting input terminal (+) of the comparator 1 is also low, and the comparator 1 outputs “L”.

While the output of the comparator 1 is “L”, the PMOS 5 is turned on and the PMOSs 4 and 6 are turned off. When the PMOS 5 is turned on, the drain current I ₅ of the PMOS ₅ flows through the resistor 8. Amplifier 9 and NMOS7, even power supply VDD fluctuates, acts to flow a drain current _{I 5} a stable.

  At this time, the voltage V 0 of the non-inverting input terminal (+) of the comparator 1 is a voltage obtained by dividing the input voltage Vin by the resistors 2 and 3.

  When the input voltage Vin rises and the voltage V0 of the non-inverting input terminal (+) of the comparator 1 rises accordingly, and the voltage V0 exceeds the reference voltage Vref1, the output of the comparator 1 transitions to “H”. That is, the threshold value when the output of the comparator 1 transitions to “H” is a voltage value obtained by dividing the input voltage Vin by the resistors 2 and 3.

When the output of the comparator 1 becomes “H”, the PMOSs 4 and 6 are turned on and the PMOS 5 is turned off. When the PMOSs ₄ and 6 are turned on, the drain current I ₄ of the PMOS ₄ and the drain current I _{6 of the} PMOS ₆ flow. Since the PMOS 4 and the PMOS 6 constitute a current mirror circuit, when the sizes of the PMOS 4 and the PMOS 6 are equal, the PMOS ₄ flows a drain current I ₄ corresponding to the drain current I _{6 of the} PMOS 6. By drain current I ₄ flows, the voltage V0 of the non-inverting input terminal of the comparator 1 (+) becomes higher.

When the voltage Vin of the input terminal IN decreases again and the voltage V0 of the non-inverting input terminal (+) of the comparator 1 becomes lower than the reference voltage Vref1, the output of the comparator 1 transitions to “L”. That is, the threshold value when the output of the comparator 1 transitions to “L” is lower than the threshold value when the output of the comparator 1 changes to “H”.
As described above, the hysteresis comparator of FIG. 1 has a hysteresis voltage.

When the resistor 2 has the resistance value R ₂ and the resistor 3 has the resistance value R ₃ , the voltage V0 ′ that the resistor 2 and the resistor 3 divides the input voltage Vin and gives to the non-inverting input terminal (+) of the comparator 1 is
V0 ′ = Vin · R ₃ / (R ₂ + R ₃ )
It becomes.

Since the drain current I ₄ flows through the resistor 2 and the resistor 3 during the period when the comparator 1 is outputting “H”, the voltage V 0 ″ applied to the non-inverting input terminal (+) of the comparator 1 is from the drain of the PMOS 4. Since the combined resistance value of the resistor 2 and the resistor 3 seen is R ₂ · R ₃ / (R ₂ + R ₃ ),
_{V0 "= I 4 · R 2} · R 3 / (R 2 + R 3)
It becomes.

Therefore, the voltage V0 of the non-inverting input terminal (+) of the comparator 1 during the period in which the comparator 1 outputs “H” is
V0 = V0 '+ V0 "
It becomes.

On the other hand, the voltage V0 of the non-inverting input terminal (+) of the comparator 1 during the period when the comparator 1 outputs “L” is
V0 = V0 '
It becomes.
That is, the voltage V0 ″ (= I ₄ · R ₂ · R ₃ / (R ₂ + R ₃ )) is the hysteresis voltage.

If the sizes of the PMOS 4 and the PMOS 6 are equal, the drain current I ₄ has the same current value as the drain current I _{6 of the} PMOS 6. Assuming that the resistance values of the resistors ₈ , ₁₀ , and ₁₁ are R ₈ , R ₁₀ , and R ₁₁ and the voltage Vdd of the power supply VDD, the drain current I ₆ is I ₆ = Vref2 · R ₁₁ / {R ₈ (R ₁₀ + R ₁₁ )}
It becomes. Therefore, the hysteresis voltage V0 "
_{V0 "= Vref2 · R 11 ·} R 2 · R 3 / {R 8 (R 10 + R 11) (R 2 + R 3)}
It can be expressed as.

Here, when the temperature of the semiconductor substrate changes, the resistance values R ₂ and R ₃ of the resistors ₂ and ₃ and the resistance value R ₈ of the resistor ₈ also change. When the resistors 2 and 3 and the resistor 8 are made of the same material, when the resistance values R ₂ and R _{3 of the} resistors ₂ and ₃ change by α%, the resistance value R8 of the resistor ₈ also changes by α%. The hysteresis voltage V0 ″ when the resistance values R ₂ and R ₃ of the resistors ₂ and ₃ and the resistance value R ₈ of the resistor ₈ change by α% is
_{V0 "= Vref2 · R 11 ·} R 2 · R 3 · α 2 / {R 8 · α (R 10 + R 11) (R 2 · α + R 3 · α)}
_{= Vref2 · R 11 · R 2} · R 3 / {R 8 (R 10 + R 11) (R 2 + R 3)}
Thus, even if the temperature changes, the hysteresis voltage V0 ″ does not change. That is, an appropriate hysteresis voltage is ensured. Also, an appropriate hysteresis width can be ensured even if the reference voltage Vref1 varies.

  As described above, according to the hysteresis comparator of the present embodiment, the hysteresis voltage is stabilized by the fluctuation of the reference voltage Vref1 and does not change with temperature, and an appropriate hysteresis voltage can always be ensured.

In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible.
For example, the input terminal IN may be directly connected to the non-inverting input terminal (+) of the comparator 1 without using the resistor 2.

  Further, the hysteresis comparator does not have to be formed on the semiconductor substrate. When the resistors 2, 3, and 8 are subjected to the same temperature change, the same effect as that of the present embodiment is obtained.

It is a block diagram which shows the hysteresis comparator which concerns on embodiment of this invention. It is a figure which shows the conventional hysteresis comparator circuit.

Explanation of symbols

1 Comparator 2, 3, 8, 10, 11 Resistor 4, 5, 6 PMOS
7 NMOS
9 Amplifier IN input terminal OUT output terminal

Claims (4)

A first resistor having one end connected to a fixed potential and the other end connected to a signal input terminal, and generating a voltage corresponding to the input signal;
When the reference voltage is input to one input terminal, the other input terminal is connected to the other end of the first resistor, and the voltage at the other end of the first resistor is lower than the reference voltage, the first voltage A comparator that outputs a logic level and outputs a second logic level when the voltage at the other end of the first resistor is greater than or equal to the reference voltage;
A second resistor provided between the power source and the fixed potential;
Period detecting means for detecting a period during which the comparator outputs the second logic level;
Current supply means for supplying current from the power source to the second resistor during the period detected by the period detection means, and generating a correction current corresponding to the current to be applied to the other end of the first resistor;
A hysteresis comparator comprising:   The hysteresis comparator according to claim 1, further comprising a third resistor connected between the other end of the first resistor and the signal input terminal.   The hysteresis comparator according to claim 1, wherein the first resistor and the second resistor have negative temperature characteristics.   The hysteresis comparator according to claim 1, wherein the hysteresis comparator is formed on a semiconductor substrate.

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