JP2009238957A - Via forming method on board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a via forming method of a board can reduce warpage of the board. <P>SOLUTION: After forming a metal thin film 26 on one surface side of a board 20a after a through-hole formation process to prevent the respective through-holes 22 from being closed, a resist layer 61 having a plurality of openings 61a exposing the respective through-holes 22 and the metal thin film 26 in circumferential parts of the respective through-holes 22 are formed on the one surface side of the board 20a; thereafter a plurality of island-like conductor parts 27 closing the respective through-holes 22 are formed on the one surface side of the board 20a by electric plating; thereafter a current is carried between positive electrodes oppositely arranged on the other surface side of the board 20a and negative electrodes composed of the conductor parts 27 closing the respective through-holes 22 on the one surface side of the board 20a to deposit a plurality of metal parts respectively used as vias 24 along the thickness direction of the board 20a from exposed surfaces of the through-hole 22 sides in the respective conductor parts 27; and thereafter the resist layer 61 and the metal thin film 26 under the resist layer 61 are removed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for forming a via in a substrate.

  Conventionally, as application fields of devices and packages having vias, for example, light emitting devices using LED chips, physical quantity sensors (acceleration sensors, pressure sensors, gyro sensors, etc.), infrared sensors, high frequency devices (RF-MEMS, micro relays) Etc.), microvalves, acoustic sensors, chemical sensors, semiconductor devices (eg, integrated circuit devices), etc., and methods for forming vias on substrates such as semiconductor substrates and insulating substrates (eg, glass substrates) Are being researched and developed in various places (for example, see Patent Documents 1 to 3).

  Here, Patent Document 1 describes that a molten metal backfill method is employed as a method of filling a conductive material to be a via (through hole wiring) into a plurality of through holes formed in a substrate. Patent Documents 3 and 4 describe an electroplating method.

  Here, an example of a method of forming a via (through-hole wiring) in the substrate described in Patent Document 2 will be described with reference to FIG.

  First, a through-hole recess 240a is formed by etching or the like at a through-hole formation scheduled portion on one surface of the substrate 240 made of a semiconductor substrate (the upper surface of FIG. 11 (a)). Get the structure.

  Thereafter, an insulating layer 243a is formed on the one surface of the substrate 240 and the inner surface of the recess 240a by CVD or thermal oxidation, and an insulating layer 243b is formed on the other surface of the substrate 240 (the lower surface in FIG. 11A). Subsequently, a metal thin film 244 made of a metal material (for example, copper, nickel, etc.) is laminated on the insulating layer 243a formed on the one surface of the substrate 240 and the inner surface of the recess 240a by a CVD method, a sputtering method, or the like. Thus, the structure shown in FIG.

  Thereafter, a metal portion 245 made of a metal material (for example, copper, nickel, etc.) is deposited (deposited) by electroplating using the metal thin film 244 as a seed layer, thereby obtaining the structure shown in FIG.

  Thereafter, the other surface side of the substrate 240 is polished by a CMP technique or the like to complete the through hole 242, and then unnecessary portions on the one surface side of the substrate 240 of the metal portion 245 are removed, whereby FIG. The structure shown in (d) is obtained. Here, in FIG. 11D, the portion embedded in the through hole 242 in the metal portion 245 constitutes the through wiring 246.

  Next, an example of a method for forming a via (through-hole wiring) in the substrate described in Patent Document 3 will be described with reference to FIG.

  First, the structure shown in FIG. 12A is obtained by forming a plurality of through holes 342 penetrating in the thickness direction by etching or the like on a substrate 340 made of an insulating substrate.

  Thereafter, a metal thin film 344 is formed on one surface side of the substrate 340 by a sputtering method or the like, thereby obtaining the structure shown in FIG. Subsequently, a metal portion is deposited by electroplating using the metal thin film 344 as a seed layer to form a conductor portion 345 that closes each through-hole 342 on the one surface side of the substrate 340, whereby FIG. Get the structure shown.

  Thereafter, a current is applied between an anode (not shown) disposed opposite to the other surface side of the substrate 340 and a cathode formed of a conductor portion 345 blocking each through-hole 342 on the one surface side of the substrate 340. The portion 346 is deposited along the thickness direction of the substrate 340 from the exposed surface of each conductor portion 345 on the through hole 342 side, and then, unnecessary portions protruding from the other surface side of the substrate 340 are removed from each metal portion 346. By performing CMP, the structure shown in FIG. 12D is obtained.

Thereafter, CMP is performed to remove the conductor portion 345 on the one surface side of the substrate 340, thereby obtaining a structure shown in FIG. 12E in which a via made of the metal portion 346 is completed.
JP 2002-237468 A JP 2003-328180 A JP 2006-111896 A

  However, in the method of forming a via on a substrate that forms a via using the molten metal backfill method described in Patent Document 1, the substrate is immersed in a molten metal (molten tin) at 300 ° C. in a reduced pressure atmosphere. After that, the atmosphere is returned to atmospheric pressure, but stress is generated due to shrinkage when the molten metal is cured, and the substrate is warped.

  Further, in the method for forming a via on the substrate described in Patent Document 2, the metal portion 245 is formed on the substrate 240 as shown in FIG. 11C by performing electroplating to form the metal portion 245. Since it is formed on the entire surface side, the substrate 240 warps due to the plating stress, and the warp of the substrate 240 remains even after the unnecessary portion of the metal portion 245 on the one surface side of the substrate 240 is removed. End up.

  Further, in the method for forming a via in the substrate described in Patent Document 3, a conductor portion 345 that closes each through-hole 342 is formed on the one surface side of the substrate 340, as shown in FIG. Thus, since the conductor portion 345 is formed on the entire surface of the one surface of the substrate 340, the substrate 340 is warped by the plating stress, and after that, even if unnecessary portions of the conductor portion 345 are removed, the warpage of the substrate 340 is caused. It will remain.

  By the way, if a substrate is warped during the manufacture of a device having a substrate having vias, the substrate cannot be transported by a robot arm in the subsequent process, or the processing accuracy is lowered (especially photolithography technology and etching technology). Patterning using a metal or reduction in processing accuracy such as flattening using a polishing technique), a decrease in yield, or a decrease in device characteristics (for example, sensor characteristics of a physical quantity sensor). Can be considered.

  The present invention has been made in view of the above-described reasons, and an object thereof is to provide a method for forming a via in a substrate that can reduce the warpage of the substrate.

  The invention according to claim 1 is a method for forming a via in a substrate, wherein a through hole forming step of forming a plurality of through holes penetrating in the thickness direction in the substrate, and one surface side of the substrate after the through hole forming step A metal thin film forming step for forming a metal thin film so that each through hole is not blocked at the same time, and after the metal thin film forming step, each through hole and the metal thin film around each through hole are exposed on the one surface side of the substrate A resist layer forming step for forming a resist layer having a plurality of openings, and a plurality of island-shaped conductor portions for closing each through hole on the one surface side of the substrate after the resist layer forming step are formed by electroplating A first electroplating step, an anode disposed opposite to the other surface side of the substrate after the first electroplating step, and a cathode comprising a conductor portion closing each through hole on the one surface side of the substrate Multiple energizing each to become a via A second electroplating step of depositing the genus portion along the thickness direction of the substrate from the exposed surface on the through hole side in each conductor portion; and an unnecessary portion removing step of removing the resist layer after the second electroplating step; It is characterized by providing.

  According to this invention, after forming the metal thin film so that each through hole is not blocked on one surface side of the substrate after the through hole forming step, each through hole and the periphery of each through hole are formed on the one surface side of the substrate. Forming a resist layer having a plurality of openings exposing the metal thin film, and then forming a plurality of island-shaped conductor portions for closing each through hole on the one surface side of the substrate by electroplating, A plurality of metal portions each serving as a via by energizing between an anode arranged opposite to the other surface side of the substrate and a cathode composed of a conductor portion blocking each through hole on the one surface side of the substrate, each conductor portion Since the resist layer is removed from the exposed surface on the through hole side in the substrate, and then the resist layer is removed, a plurality of conductor portions for closing each through hole on the one surface side of the substrate are formed in an island shape. And the whole of the one surface side of the substrate As compared with the case where continuous conductor part is formed, the plating stress can be reduced, thereby reducing the warp of the substrate.

  The invention of claim 2 is the invention of claim 1, wherein the substrate is a semiconductor substrate, and the one surface and the other surface of the substrate and the surface between the through hole forming step and the metal thin film forming step. An insulating film forming step of forming an insulating film on the inner peripheral surface of each through hole is provided.

  According to this invention, when a semiconductor substrate is used as the substrate, an insulating film is formed on the one surface and the other surface of the substrate and the inner peripheral surface of each through-hole before forming the metal thin film. Therefore, the via and the substrate can be prevented from being electrically connected.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, each of the conductor portions also serves as a conductor pattern on the one surface side of the substrate. In the resist layer forming step, The opening shape is set according to the conductor pattern.

  According to this invention, each said conductor part remaining after the said unnecessary part removal process can be utilized as a conductor pattern.

  In the invention of claim 1, there is an effect that the warpage of the substrate can be reduced.

  Hereinafter, in the present embodiment, a light emitting device as an example of a device formed using a method for forming a via on a substrate will be described with reference to FIGS. 8 to 10 and then a method for forming a via on a substrate. This will be described with reference to FIGS.

  As shown in FIGS. 8 and 9, the light-emitting device includes a light-emitting element 1 made of an LED chip, a mounting substrate 2 in which a housing recess 2 a for storing the light-emitting element 1 is formed on one surface, and the above-described mounting board 2. A translucent member 3 fixed to the mounting substrate 2 so as to close the housing recess 2a on one surface side, and a light detecting element (light receiving element) provided on the mounting substrate 2 for detecting light emitted from the light emitting element 1 ) 4 and a light-transmitting material (for example, silicone resin, acrylic resin, epoxy resin, polycarbonate resin, glass, etc.) filled in the housing recess 2a of the mounting substrate 2, the light emitting element 1 and the light emitting element 1 are electrically And the sealing part 5 which sealed the bonding wire 14 connected in general. Here, the mounting substrate 2 has a hook-like protrusion 2c protruding inward from the peripheral portion of the housing recess 2a on the one surface side, and the light detection element 4 is provided on the protrusion 2c. ing.

  The mounting substrate 2 includes a rectangular plate-like base substrate 20 on which the light-emitting element 1 is mounted on one surface side, and a circular light extraction window 41 formed on the one surface side of the base substrate 20 so as to face the light. A light detection element forming substrate 40 on which the detection element 4 is formed, and an intermediate layer in which a rectangular opening window 31 that is interposed between the base substrate 20 and the light detection element formation substrate 40 and communicates with the light extraction window 41 is formed. A space surrounded by the base substrate 20, the intermediate layer substrate 30, and the photodetecting element forming substrate 40 constitutes the housing recess 2a. Here, the outer peripheral shapes of the base substrate 20, the intermediate layer substrate 30, and the light detection element formation substrate 40 are rectangular, and the intermediate layer substrate 30 and the light detection element formation substrate 40 are formed to have the same outer dimensions as the base substrate 20. Yes. Further, the thickness dimension of the light detection element forming substrate 40 is set smaller than the thickness dimension of the base substrate 20 and the intermediate layer substrate 30. In the present embodiment, a portion of the light detection element forming substrate 40 that protrudes over the opening window 31 of the intermediate layer substrate 30 constitutes the above-described protruding portion 2c. In the present embodiment, the package is constituted by the mounting substrate 2 and the translucent member 3, but the translucent member 3 is not necessarily provided, and may be appropriately provided as necessary. Further, the light detection element forming substrate 40 in the mounting substrate 2 is not necessarily provided.

  The base substrate 20, the intermediate layer substrate 30, and the light detection element formation substrate 40 described above are formed using silicon substrates (semiconductor substrates) 20a, 30a, and 40a having an n-type conductivity and a (100) principal surface, respectively. It is. Here, in the intermediate layer substrate 30, the inner surface of the opening window 31 is constituted by a (111) surface formed by anisotropic etching using an alkaline solution (for example, TMAH solution, KOH solution, etc.). (That is, the intermediate layer substrate 30 gradually increases as the opening area of the opening window 31 increases from the base substrate 20), and constitutes a mirror that reflects light emitted from the light emitting element 1 forward.

  In the base substrate 20, two conductor patterns 25a and 25a electrically connected to both electrodes of the light emitting element 1 are formed on one surface side (the upper surface side in FIG. 8) of the silicon substrate 20a, and an intermediate layer is formed. Two conductor patterns 25b and 25b are formed which are electrically connected to the photodetecting element 4 through two vias 34 and 34 (hereinafter also referred to as through-hole wirings 34 and 34) formed on the substrate 30. Each of the conductor patterns 25a, 25a, 25b, and 25b and the four external connection electrodes 27a, 27a, 27b, and 27b formed on the other surface side (right side in FIG. 8) of the silicon substrate 20a are used for wiring. The vias 24 (hereinafter also referred to as through-hole wiring 24a) are electrically connected. The base substrate 20 is also formed with a bonding metal layer 29 for bonding to the intermediate layer substrate 30 on the one surface side of the silicon substrate 20a.

  The light-emitting element 1 in this embodiment is a visible light LED chip in which a conductive substrate is used as a crystal growth substrate and electrodes (not shown) are formed on both surfaces in the thickness direction. Therefore, the base substrate 20 has one of the two conductor patterns 25a and 25a to which the light emitting element 1 is electrically connected, a rectangular die pad portion 25aa to which the light emitting element 1 is die-bonded, and The lead-out wiring part 25ab is formed integrally with the die pad part 25aa and is connected to the through-hole wiring 24a. In short, the light emitting element 1 is die-bonded to the die pad portion 25aa of the one conductor pattern 25a, the electrode on the die pad portion 25aa side is joined and electrically connected to the die pad portion 25aa, and the electrode on the light extraction surface side. Is electrically connected to the other conductor pattern 25 a via the bonding wire 14. In addition, as the light emitting element 1, you may use the thing in which both electrodes were formed in the light extraction surface side.

  The base substrate 20 has a rectangular heat radiation pad portion 28 made of a metal material having a higher thermal conductivity than the silicon substrate 20a on the other surface side of the silicon substrate 20a. A plurality of (in this embodiment, nine) cylindrical vias 24 (hereinafter also referred to as thermal vias 24b) made of a metal material (for example, Cu) having a thermal conductivity higher than that of the silicon substrate 20a. The heat generated in the light emitting element 1 is dissipated through the thermal vias 24b and the heat dissipating pad portion 28.

  By the way, the base substrate 20 has a plurality of through-holes 22 formed in the thickness direction in the silicon substrate 20a, in which each of the above-described vias 24 is formed. An insulating film 23 made of a thermal oxide film (silicon oxide film) is formed across the inner surface of the through hole 22, and each conductor pattern 25 a, 25 a, 25 b, 25 b, the bonding metal layer 29, each external connection electrode 27a, 27a, 27b, 27b, the heat radiation pad portion 28, and each via 24 are electrically insulated from the silicon substrate 20a.

  Here, each conductor pattern 25a, 25a, 25b, 25b, bonding metal layer 29, each external connection electrode 27a, 27a, 27b, 27b, and heat radiation pad portion 28 are formed on the insulating film 23. And the Au film formed on the Ti film, the conductor patterns 25a, 25a, 25b, 25b on the one surface side of the silicon substrate 20a and the bonding metal layer 29 are simultaneously formed. The external connection electrodes 27a, 27a, 27b, 27b on the other surface side of the silicon substrate 20a and the heat dissipation pad portion 28 are formed at the same time. In this embodiment, the thickness of the Ti film on the insulating film 23 is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Further, the material of each Au film is not limited to pure gold, and may be one added with impurities. In addition, although a Ti film is interposed as an adhesion layer for improving adhesion between each Au film and the insulating film 23, the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used. Moreover, although Cu is adopted as the material of the via 24, it is not limited to Cu, and for example, Ni, Al, etc. may be adopted.

  The intermediate layer substrate 30 is bonded to two connection metal layers (hereinafter referred to as first connection metal layers) 25b and 25b of the base substrate 20 on one surface side (the lower surface side in FIG. 8) of the silicon substrate 30a. Then, two second connection metal layers (not shown) 35 and 35 that are electrically connected to each other are formed, and the bonding metal layer 36 bonded to the bonding metal layer 29 of the base substrate 20 is formed. Is formed. Further, the intermediate layer substrate 30 is electrically connected to the second connection metal layers 35 and 35 via the through-hole wirings 34 and 34 on the other surface side (the upper surface side in FIG. 8) of the silicon substrate 30a. Two third connection metal layers 37, 37 are formed, and a bonding metal layer 38 (see FIG. 9) for bonding to the photodetecting element forming substrate 40 is formed.

  Further, the intermediate layer substrate 30 has two through holes 32 formed therein in the thickness direction of the silicon substrate 30a, and the one surface of the silicon substrate 30a and the other. An insulating film 33 made of a thermal oxide film (silicon oxide film) is formed across the surface and the inner surface of each through hole 32, and the second connection metal layers 35, 35 and the third connection metal layer 37 are formed. , 37 and the bonding metal layers 36, 38 are electrically insulated from the silicon substrate 30a. Here, the second connecting metal layers 35, 35, the third connecting metal layers 37, 37, and the joining metal layers 36, 38 are formed on the Ti film formed on the insulating film 33 and the Ti film. The second connecting metal layers 35, 35 and the bonding metal layer 36 on the one surface side of the silicon substrate 30a are formed at the same time to form the silicon substrate 30a. The third connecting metal layers 37 and 37 on the other surface side and the joining metal layer 38 are formed simultaneously. In this embodiment, the thickness of the Ti film on the insulating film 33 is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Here, the material of each Au film is not limited to pure gold, and may be added with impurities. Further, although a Ti film is interposed as an adhesion improving layer for adhesion between each Au film and the insulating film 33, the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used. Further, although Cu is adopted as the material of the through-hole wiring 34, it is not limited to Cu, and for example, Ni, Al or the like may be adopted.

  The photodetecting element forming substrate 40 is bonded to and electrically connected to two connecting metal layers 37, 37 of the intermediate layer substrate 30 on one surface side (the lower surface side in FIG. 8) of the silicon substrate 40a. The fourth connection metal layers 47 and 47 are formed, and a bonding metal layer (not shown) to be bonded to the bonding metal layer 38 of the intermediate layer substrate 30 is formed. Here, the photodetecting element 4 is constituted by a photodiode, and one of the four fourth connecting metal layers 47, 47 formed on the photodetecting element forming substrate 40 is the fourth connecting metal layer 47. Is electrically connected to the p-type region 4a of the photodiode constituting the photodetecting element 4, and the other fourth connecting metal layer 47 is formed on the silicon substrate 40a constituting the n-type region 4b of the photodiode. Electrically connected.

  Further, in the photodetecting element forming substrate 40, an insulating film 43 made of a silicon oxide film is formed on the one surface side of the silicon substrate 40a, and the insulating film 43 also serves as an antireflection film of the photodiode. In the photodetecting element forming substrate 40, the one fourth connecting metal layer 47 is electrically connected to the p-type region 4a through a contact hole 43a formed in the insulating film 43, and the other fourth connecting metal layer 47 is connected. The connecting metal layer 47 is electrically connected to the n-type region 4 b through a contact hole 43 b formed in the insulating film 43. Here, the two fourth connecting metal layers 47, 47 and the bonding metal layer are constituted by a laminated film of a Ti film formed on the insulating film 43 and an Au film formed on the Ti film. Are formed at the same time. In this embodiment, the thickness of the Ti film on the insulating film 43 is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Here, the material of each Au film is not limited to pure gold, and may be added with impurities. Further, although a Ti film is interposed as an adhesion improving layer for adhesion between each Au film and the insulating film 43, the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used.

  In forming the mounting substrate 2 described above, for example, the photodetector 4, the insulating film 43, the fourth connection metal layers 47 and 47, and the silicon substrate 40 a and the intermediate layer substrate on which the bonding metal layer is formed. After performing the first bonding step for bonding to the substrate 30, a polishing step for polishing the silicon substrate 40a to a desired thickness is performed, and then a light extraction window 41 is formed on the silicon substrate 40a using an ICP type dry etching apparatus or the like. The light detection element forming substrate 40 is completed by performing the light extraction window forming step of forming the base substrate 20 on which the light emitting element 1 is mounted (the light emitting element 1 is mounted and the bonding wire 14 is connected). A second bonding step for bonding the base substrate 20) and the intermediate layer substrate 30 may be performed. Here, in the first bonding step and the second bonding step, each bonding surface is cleaned and activated by irradiating each bonding surface with argon plasma, ion beam or atomic beam in vacuum before bonding. After performing the normal temperature bonding method of contacting the bonding surfaces together and directly bonding at normal temperature, but not limited to the normal temperature bonding method, after normalizing and activating each of the above-mentioned bonding surfaces, The bonding surfaces may be brought into contact and directly bonded at a specified temperature higher than room temperature (for example, 80 ° C.).

  In the first bonding step, the bonding metal layer on the one surface side of the silicon substrate 40a and the bonding metal layer 38 of the intermediate layer substrate 30 are bonded, and the one surface side of the silicon substrate 40a is bonded. The fourth connection metal layers 47 and 47 and the third connection metal layers 37 and 37 of the intermediate layer substrate 30 are joined and electrically connected. Here, if the pattern design is made so that the joint portion between the fourth connection metal layers 47 and 47 and the third connection metal layers 37 and 37 is shifted from the region overlapping the through-hole wiring 34, The flatness of the bonding surfaces of the connecting metal layers 47 and 47 and the third connecting metal layers 37 and 37 can be increased, and in particular, the bonding yield when bonded by the room temperature bonding method can be increased. At the same time, the bonding reliability can be improved. Further, in the second bonding step, the bonding metal layer 29 of the base substrate 20 and the bonding metal layer 36 of the intermediate layer substrate 30 are bonded, and the first connection metal layers 25b and 25b of the base substrate 20 are bonded. And the second connecting metal layers 35 of the intermediate layer substrate 30 are joined and electrically connected. Here, in the present embodiment, the joint portions of the first connection metal layers 25b and 25b and the second connection metal layers 35 and 35 are regions overlapping the through-hole wiring 24a and regions overlapping the through-hole wiring 34. Therefore, the flatness of the joint surfaces of the first connection metal layers 25b and 25b and the second connection metal layers 35 and 35 can be increased. The bonding yield can be increased and the bonding reliability can be increased.

  Further, the above-described translucent member 3 is formed using a translucent substrate made of a translucent material (for example, silicone resin, acrylic resin, epoxy resin, polycarbonate resin, glass, or the like). Here, the translucent member 3 is formed in a rectangular plate shape having the same outer peripheral shape as the mounting substrate 2, and all of the light emitted from the light emitting element 1 is formed on the light extraction surface opposite to the mounting substrate 2 side. A fine concavo-convex structure that suppresses reflection is formed. Here, the fine concavo-convex structure formed on the light extraction surface of the translucent member 3 is formed such that many fine concave portions have a two-dimensional periodic structure. The fine concavo-convex structure described above may be formed using, for example, a laser processing technique, an etching technique, an imprint lithography technique, or the like. Further, the period of the fine concavo-convex structure may be appropriately set within a range of about ¼ to 100 times the emission peak wavelength of the light emitting element 1.

  In manufacturing the light emitting device of the present embodiment, as each of the silicon substrates 20a, 30a, and 40a described above, a silicon wafer capable of forming a large number of the base substrate 20, the intermediate layer substrate 30, and the light detection element forming substrate 40 is used. A wafer-like one (translucent wafer) capable of forming a large number of translucent members 3 is used as the above-described translucent substrate, and the above-described first bonding step, polishing step, light extraction window forming step, second step The mounting substrate 2 and the translucent member 3 after the joining step, the sealing portion forming step of forming the sealing portion 5 by filling the housing recess 2a of the mounting substrate 2 with the translucent material, and the sealing portion forming step. The wafer level package structure is formed by performing each process such as a third bonding process for bonding the two at the wafer level, and then divided into the size of the mounting substrate 2 by the dicing process. Therefore, the base substrate 20, the intermediate layer substrate 30, the light detection element formation substrate 40, and the translucent member 3 have the same outer size, so that a small package can be realized and manufacturing is facilitated. Further, the relative positional accuracy between the mirror in the intermediate layer substrate 30 and the light detection element 4 in the light detection element formation substrate 40 can be improved, and the light emitted from the light emitting element 1 to the side is reflected by the mirror. It is guided to the light detection element 4.

In the light emitting device described above, a visible light LED chip is used as the light emitting element 1, but the light emitting element 1 is not limited to the visible light LED chip, but is stacked on the ultraviolet light LED chip or the LED chip and the LED chip. It may be composed of a phosphor layer formed of a phosphor that is excited by light emitted from the LED chip and emits light having a longer wavelength than the LED chip, or may be an organic EL element. In addition, as the light emitting element 1, for example, after a light emitting portion or the like is epitaxially grown on the main surface side of the crystal growth substrate, a conductive substrate (for example, a Si substrate) that supports the light emitting portion is fixed to the light emitting portion. You may use what removed the board | substrate for crystal growth. The number of the light emitting elements 1 is not limited to one, and a plurality of light emitting elements having the same or different emission colors may be used. The light detecting element 4 is not limited to a photodiode, and may be, for example, a photodiode and a color. A color sensor combined with a filter, or a combination of a photodiode and a wavelength selection filter may be used. Further, the light detection element 4 is not necessarily provided.

  Hereinafter, a method for forming the via 24 in the above-described silicon substrate 20a (hereinafter referred to as the substrate 20a) will be described with reference to FIGS.

  First, an oxidation for forming a silicon oxide film on one surface side of the substrate 20a (here, the other surface side of the silicon substrate 20a) and the other surface side (here, the one surface side of the silicon substrate 20a) by thermal oxidation. In order to form a mask for forming the through hole 22 for forming the via 24 in the substrate 20a after performing the film forming step, silicon on the other surface side of the substrate 20a is used by using a photolithography technique and an etching technique. Patterning the oxide film, and using the patterned silicon oxide film as a mask, the substrate 20a is dry etched by the inductively coupled plasma (ICP) type etching apparatus until it reaches the silicon oxide film on the other surface side from the one surface side. As a result, a through hole forming step for forming a plurality of through holes 22 penetrating in the thickness direction of the substrate 20a is performed. Subsequently, after performing an oxide film removing step for removing each silicon oxide film by etching, the one surface side and the other surface side of the substrate 20a and the inner surface (inner peripheral surface) of each through hole 22 are thermally oxidized. An insulating film forming step of forming an insulating film 23 made of a silicon oxide film is performed, and then a metal thin film 26 made of a metal material is formed by sputtering or the like so that each through hole 22 is not blocked on the one surface side of the substrate 20a. The structure shown in FIG. 1A is obtained by performing the metal thin film forming step to be formed. A part of the metal thin film 26 formed in the metal thin film forming step is also formed inside each through hole 22 on the one surface side of the substrate 20a. In the present embodiment, the metal thin film 26 is composed of a laminated film of a Cr film formed on the insulating film 23 and a Cu film formed on the Cr film. In this embodiment, a silicon wafer (silicon substrate) having a thickness of 300 μm is used as the substrate 20 a, the inner diameter of the through hole 22 is set to 20 μm, and the film thickness of the Cr film on the insulating film 23 is set to 0. Although the film thickness of the Cu film on the Cr film is set to 03 μm and 0.4 μm, these numerical values are merely examples and are not particularly limited. However, the inner diameter of the through hole 22 is preferably set in the range of 5 μm to 50 μm from the viewpoint of device miniaturization. The film thickness of the Cu film is preferably set to 0.2 μm or more in consideration of the oxidation of the surface in the resist layer forming step described later.

  After the above-described metal thin film forming step, a resist for forming a resist layer 61 having a plurality of openings 61a that expose each through hole 22 and the metal thin film 26 around the through hole 22 on the one surface side of the substrate 20a. By performing the layer forming step, the structure shown in FIG. 1B is obtained. In forming the resist layer 61, a photosensitive photoresist may be applied by spin coating or the like, and then exposed and developed.

  By performing a first electroplating step of forming a plurality of island-like conductor portions 27 for closing each through-hole 22 on the one surface side of the substrate 20a by the electroplating after the resist layer forming step described above, FIG. The structure shown in 1 (c) is obtained. In the first electroplating step, a copper sulfate plating solution is used as a plating solution, and an anode (not shown) made of a copper plate disposed opposite to the one surface side of the substrate 20a via the plating solution and the one surface of the substrate 20a. The conductor portion 27 is formed by energizing the cathode made of the metal thin film 26 on the side.

  After the first electroplating step, a copper sulfate plating solution is used as a plating solution, and an anode (not shown) made of a copper plate disposed opposite to the other surface side of the substrate 20a and the one surface side of the substrate 20a A plurality of metal parts made of a metal material (here, Cu) that becomes the vias 24 when energized between the cathodes made of the conductor parts 27 closing the through-holes 22 are connected to the through-holes 22 in the conductor parts 27. A second electroplating step for depositing along the thickness direction of the substrate 20a from the exposed surface on the side (that is, in the second electroplating step, the metal portion to be the via 24 is grown bottom-up), and then Then, by performing a polishing process for removing unnecessary portions formed on the other surface side of the silicon substrate 20a in the metal portion by CMP or the like, the structure shown in FIG. 1D is obtained. The metal material is not limited to Cu, and may be Ni, for example.

  A structure shown in FIG. 1E is obtained by performing an unnecessary portion removing step of removing the resist layer 61 and the metal thin film 26 under the resist layer 61 after the above-described polishing step. Here, in the unnecessary portion removing step, the resist layer 61 is removed using an organic solvent or the like, and then the metal thin film 26 is removed using an etching solution. In the present embodiment, the external connection electrodes 27a and 27b and the heat dissipating pad portion 28 are configured by leaving the conductor portions 27 on the one surface side of the substrate 20a. The external connection electrodes 27a and 27b and the heat radiation pad portion 28 may be formed after removal by CMP or the like (in this case, the metal thin film 26 is removed when each conductor portion 27 is removed by CMP or the like). May also be removed by CMP or the like). In order to complete the above-described base substrate 20, the conductive patterns 25a, 25a, 25b, and 25b and the bonding metal layer 29 are formed on the other surface side of the substrate 20a after the unnecessary portion removing step. It may be formed simultaneously using a technique, a photolithography technique, and an etching technique.

  By the way, in the formation method of the via | veer 24 of the board | substrate 20a of this embodiment, the plating accelerator 71 and the plating inhibitor 72 are added to a plating solution (copper sulfate plating solution) in the above-mentioned 1st electroplating process. Here, as shown in FIG. 2A, the plating accelerator 71 has a function of adhering to the surface of the metal thin film 26 inside the through hole 22 to promote plating, and a plating inhibitor 72. Has a function of suppressing the plating by adhering to the surface of the metal thin film 26 on the one surface side of the substrate 20a. Therefore, by adding the plating accelerator 71 and the plating inhibitor 72 as additives in the plating solution, the through holes 22 can be easily blocked by the action of these additives, so that the plating accelerator 71 and the plating inhibitor 72 are added. As shown in FIG. 2B, the thickness of the conductor 27 can be reduced as compared with the conductor 27 (see FIG. 3) formed when a plating solution to which no is added is used. As the plating accelerator 71, for example, bis (3-sulfopropyl) disulfide (SPS) is used, and as the plating inhibitor 72, polyethylene glycol (PEG) having a molecular weight of 3000 to 8000 is used. Is not particularly limited.

  Further, in the second electroplating step, electroplating may be performed under a constant current or constant voltage condition, and the plating inside the through hole 22 is finished and the plating is further continued, so that the metal portion 24 is formed as shown in FIG. Since it is formed in a mushroom shape, when electroplating is performed under the condition of a constant current, the plating voltage changes as shown in FIG. 5 as the plating time elapses. If the energization is terminated with the time when the value becomes larger than the value as the time when the plating is completed (the time when filling is completed), the plating can be performed without excess or deficiency. In addition, when electroplating was performed under the condition of a constant voltage, the plating current changed as shown in FIG. 6 with the lapse of the plating time, so the rate of change of the plating current was larger than the second specified value. If energization is terminated with the point in time as the end of plating (the point of completion of filling), plating can be performed without excess or deficiency. However, when judging the end point of plating from the rate of change of the plating voltage or plating current, if the plating current wraps around the conductor portion 27 on the one surface side of the substrate 20a, the rate of change of the plating voltage or plating current is small. Since it is difficult to determine the end point of plating by a control device including a computer equipped with an appropriate program, it is preferable to perform masking so that the back side of the conductor portion 27 is not plated.

  According to the method of forming a via on the substrate 20a of the present embodiment described above, after the metal thin film 26 is formed so that each through hole 22 is not blocked on the one surface side of the substrate 20a after the through hole forming step. The resist layer 61 having a plurality of openings 61a exposing the through holes 22 and the metal thin film 26 around the through holes 22 is formed on the one surface side of the substrate 20a, and then the one surface of the substrate 20a is formed. A plurality of island-shaped conductor portions 27 for closing each through-hole 22 on the side are formed by electroplating, and then each through-hole is formed on the one surface side of the substrate 20a and the anode disposed opposite to the other surface side of the substrate 20a. A plurality of metal portions each serving as a via 24 are energized between the cathode made of the conductor portion 27 closing the hole 22 and are exposed from the exposed surface of each conductor portion 27 on the through hole 22 side along the thickness direction of the substrate 20a. Then, since the resist layer 61 and the metal thin film 26 under the resist layer 61 are removed, a plurality of conductor portions 27 that close the through holes 22 are formed in an island shape on the one surface side of the substrate 20a. And compared with the case where the continuous conductor part is formed in the whole said one surface side of the board | substrate 20a, a plating stress can be reduced and the curvature of the board | substrate 20a can be reduced.

  Here, in general, when the plating film is formed on the entire surface of the wafer, the wafer warp h [μm] is the wafer thickness T [μm], the wafer Young's modulus E [Pa], When the Poisson's ratio is ν, the plating film thickness is t [μm], the plating diameter (wafer diameter) is D [μm], and the plating stress is σ [Pa], it is expressed by the following equation (1).

Warp h of the wafer as can be seen from Equation 1, if the plating stress σ are the same, whereas increases in proportion to the plating area (≒ πD ^2/4), to the substrate 20a of the present embodiment According to the method for forming the via 24, the area of the region in which the conductor portion 27 is formed in the plane parallel to the one surface of the substrate 20a is formed by forming the resist layer 61 before the first electroplating step. The warpage of the substrate 20a can be reduced. In addition, according to the method for forming the via 24 on the substrate 20a of the present embodiment, the plating accelerator 71 and the plating inhibitor 72 are added to the plating solution used in the first electroplating step described above. Since the thickness of the conductor portion 27 on the one surface side can be reduced, the warp of the substrate 20a can be further reduced.

  Thus, when manufacturing a device including the substrate 20a having the vias 24, the substrate 20a can be stably transported by the robot arm in the process after the vias 24 are formed, and the processing accuracy is lowered (particularly, photo processing). It is possible to prevent a reduction in processing accuracy such as patterning using a lithography technique and an etching technique and flattening using a polishing technique) and a reduction in yield, and a deterioration in device characteristics can be prevented.

  Here, if the method for forming the via 24 in the substrate 20a of the present embodiment is applied to the method for forming the base substrate 20 described above and applied to the method for forming the intermediate layer substrate 30, the base substrate 20 and the intermediate layer substrate 30 can be formed. Since warpage can be reduced, the yield of the first bonding step and the second bonding step described above can be improved, and the cost of the light-emitting device can be reduced.

  Further, in the above-described method for forming the via 24 on the substrate 20a, a semiconductor substrate such as a silicon substrate is used as the substrate 20a. However, the above-described method of forming the via 20 between the through hole forming step and the metal thin film forming step. Since the insulating film forming step of forming the insulating film 23 on the one surface, the other surface, and the inner peripheral surface of each through hole 22 is performed, the one surface, the other surface, and each of the substrate 20a are formed before the metal thin film 26 is formed. An insulating film 23 is formed on the inner peripheral surface of the through hole 22, and it is possible to prevent the via 24 and the substrate 20 a from being electrically connected. In this embodiment, an example in which a semiconductor substrate is used as the substrate 20a has been described. However, the substrate 20a is not limited to a semiconductor substrate, and may be a metal plate or an insulating substrate (for example, a glass substrate). When using, the above-described insulating film forming step is not necessary.

  Further, in the method of forming the via 24 on the substrate 20a of the present embodiment, each conductor portion 27 is a conductor pattern on the one surface side of the substrate 20a (in FIG. 7, the external connection electrodes 27a and 27a are used as the conductor pattern, and for heat dissipation. If the opening portion 61a is set in accordance with these conductor patterns in the resist layer forming step, each remaining after the unnecessary portion removing step is also provided. The conductor part 27 can be used as a conductor pattern. In the unnecessary portion removing step, the metal thin film 26 under the resist layer 61 is also removed. However, the entire metal thin film 26 under the resist layer 61 is not necessarily removed. The metal thin film 26 around the via 24 constituting the through-hole wiring 24 a may be removed, and the metal thin film 26 around the via 24 constituting the thermal via 24 b of the via 24 may be left.

  Further, according to the method for forming the via 24 of the substrate 20a, the metal thin film 26 is formed by the sputtering method in the metal thin film forming step of forming the metal thin film 26. Compared with the case of forming by the CVD method, the metal thin film 23 is less likely to be deposited inside the through hole 22, and as a result, the embedding property of the via 24 is improved.

  By the way, in the above-mentioned embodiment, although the light-emitting device was illustrated as a device which has the via 24, the device which has the via 24 is not restricted to a light-emitting device, A physical quantity sensor, an infrared sensor, a high frequency device, a microvalve, an acoustic sensor, chemical A sensor, a semiconductor device, etc. may be sufficient.

It is main process sectional drawing for demonstrating the formation method of the via | veer to the board | substrate in embodiment. It is explanatory drawing of the formation method of the via to a board | substrate same as the above. It is explanatory drawing of the formation method of the via to a board | substrate same as the above. It is explanatory drawing of the formation method of the via to a board | substrate same as the above. It is explanatory drawing of the formation method of the via to a board | substrate same as the above. It is explanatory drawing of the formation method of the via to a board | substrate same as the above. It is explanatory drawing of the formation method of the via to a board | substrate same as the above. It is a schematic sectional drawing of the light-emitting device in the same as the above. It is a general | schematic disassembled perspective view of the light-emitting device same as the above. The base board | substrate in the same as the above is shown, (a) is a schematic plan view, (b) is an A-A 'schematic sectional view of (a), and (c) is a B-B' schematic sectional view of (a). It is main process sectional drawing for demonstrating the formation method of the via | veer to the board | substrate which shows a prior art example. It is main process sectional drawing for demonstrating the formation method of the via to the board | substrate which shows another prior art example.

Explanation of symbols

20a Substrate 22 Through-hole 23 Insulating film 24 Via (metal part)
26 Metal thin film 27 Conductor (conductor pattern)
61 resist layer 61a opening

Claims (3)

  A method of forming a via in a substrate, wherein a through hole forming step for forming a plurality of through holes penetrating in the thickness direction in the substrate and each through hole is not blocked on one surface side of the substrate after the through hole forming step A metal thin film forming step of forming a metal thin film, and a resist having a plurality of openings exposing the through holes and the metal thin film around the through holes on the one surface side of the substrate after the metal thin film forming step A resist layer forming step of forming a layer, and a first electroplating step of forming, by electroplating, a plurality of island-shaped conductor portions that close each through hole on the one surface side of the substrate after the resist layer forming step Via each of the vias between the anode disposed opposite to the other surface side of the substrate after the first electroplating step and the cathode formed of a conductor portion closing each through hole on the one surface side of the substrate. Multiple metal parts to each conductor part And a second electroplating step of depositing along the thickness direction of the substrate from the exposed surface on the through hole side, and an unnecessary portion removing step of removing the resist layer after the second electroplating step. A method of forming a via on a substrate.   The substrate is a semiconductor substrate, and an insulating film is formed on the one surface and the other surface of the substrate and an inner peripheral surface of each through hole between the through hole forming step and the metal thin film forming step. The method for forming a via in a substrate according to claim 1, further comprising a film forming step.   Each of the conductor portions also serves as a conductor pattern on the one surface side of the substrate, and in the resist layer forming step, an opening shape of the opening portion is set in accordance with the conductor pattern. A method for forming a via in a substrate according to claim 1.

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