JP2009231602A - Producing method of semiconductor optical element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of producing a semiconductor optical element which can enhance crystallinity. <P>SOLUTION: This invention is a method of producing a semiconductor optical element. The method includes a first step of growing a first III-V compound semiconductor layer, which contains Ga as group III and As as group V, in a MOVPE method; a second step of growing a second III-V compound semiconductor layer, which contains Ga and In as group III and As and N as group V, in the MOVPE method; a third step of growing III-V compound semiconductor layer, which contains Ga as group III and As as group V, in the MOVPE method; and a fourth step of subjecting the grown first to third III-V compound semiconductor layers to heat annealing after growing up the first to third III-V compound semiconductor layers; a fifth step of lowering the temperature of the first to third III-V compound semiconductor layers after heat annealing at 2°C/second or lower after the heat annealing is completed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for fabricating a semiconductor optical device.

  Non-Patent Document 1 describes a method of growing a GaInNAs crystal by a molecular beam epitaxy (MBE) method. In Non-Patent Document 1, N radical is used as a nitrogen raw material for GaInNAs crystal growth.

  Non-Patent Document 2 describes a method of growing a GaInNAs crystal by metal organic vapor phase epitaxy (MOVPE). In Non-Patent Document 2, dimethylhydrazine (UDMHy: 1,1-dimethylhydrazine) is used as a nitrogen raw material at the time of GaInNAs crystal growth.

Patent Document 1 describes a heat treatment method for obtaining good crystal characteristics in GaInNAs crystal growth.
Jpn. J. Appl. Phys. (1996) 35, pp. 1273-1275 Jpn. J. Appl. Phys. (1997) 36, pp.2671-2675 JP 2002-319548 A

A semiconductor optical device (for example, a laser diode) having an active layer of Ga _0.66 In _0.34 N _0.01 As _0.99 has been developed. A GaInNAs crystal having this composition can emit light at a wavelength of 1.3 micrometers. However, it is not easy to obtain a GaInNAs crystal that realizes good laser characteristics. In addition, it is not easy to obtain sufficient emission intensity, the laser diode has a high oscillation threshold current density, and a long life of the laser diode is often not obtained with respect to long-term reliability. One of these factors is the difficulty of crystallization of nitrogen as GaInNAs.

  In order to improve the crystallinity of the semiconductor optical device, heat treatment (thermal annealing) is performed after the GaInNAs layer is grown. However, even after the heat treatment, the crystallinity of the semiconductor optical device does not reach a level applicable to a product, and further improvement in crystallinity has been desired. For example, Patent Document 1 discloses the processing temperature range and temperature change conditions when performing thermal annealing. As a result of the inventors confirming these conditions and the like through experiments, the product can be commercialized. The characteristic improvement was not obtained.

  Therefore, the present invention has been made in view of such circumstances, and an object thereof is to provide a method for manufacturing a semiconductor optical device capable of improving the crystallinity of the semiconductor optical device.

  One aspect of the present invention is a method for fabricating a semiconductor optical device. This method includes a first step of growing a first III-V compound semiconductor layer containing gallium as a group III and arsenic as a group V by metal organic chemical vapor deposition, and gallium and indium as a group III. And a second step of growing a second III-V compound semiconductor layer containing arsenic and nitrogen as a group V by metal organic vapor phase epitaxy, and a third step including gallium as a group III and arsenic as a group V A third step of growing the III-V compound semiconductor layer by metal organic vapor phase epitaxy; and, after growing the first to third III-V compound semiconductor layers, the grown first to third III- A fourth step of performing thermal annealing on the V compound semiconductor layer; and after the thermal annealing, the first to third III-V compound semiconductor layers after the thermal annealing at a rate of 2 degrees / second or less And a fifth step of lowering the temperature of And butterflies.

  According to this method, after the thermal annealing, the temperature of the first to third III-V compound semiconductor layers after the thermal annealing is decreased at a low speed of 2 degrees / second or less, thereby providing a semiconductor optical device. The crystallinity of can be improved.

  In the method according to the present invention, in the fifth step, after the thermal annealing, the temperature of the first to third III-V compound semiconductor layers after the thermal annealing at a rate of 0.5 degrees / second or less. Is preferably reduced. According to this method, the crystallinity of the semiconductor optical device is further improved by lowering the temperature of the first to third III-V compound semiconductor layers after the thermal annealing at a low speed of 0.5 degrees / second or less. Can be improved.

  In the method according to the present invention, the second III-V compound semiconductor layer can be made of any one of GaInNAs, GaInNAsP, and GaInNAsSb. This method is suitable for the growth of the III-V compound semiconductor layer.

  In the method according to the present invention, the first and third III-V compound semiconductor layers can be made of either GaAs or GaNAs. This method is suitable for the growth of the first and third III-V compound semiconductor layers used together with the second III-V compound semiconductor layer.

  In the method according to the present invention, the second III-V compound semiconductor layer may be a well layer in a quantum well structure. According to the present invention, an active layer in a single quantum well structure or a multiple quantum well structure with improved crystallinity can be produced using the second III-V compound semiconductor layer.

  In the method according to the present invention, the first and third III-V compound semiconductor layers may be barrier layers or light confinement layers in a quantum well structure. According to this invention, a multiple quantum well structure with improved crystallinity using the second III-V compound semiconductor layer and the first and third III-V compound semiconductor layers used in combination therewith. Can be realized.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, a method for producing a semiconductor optical device capable of improving the crystallinity of the semiconductor optical device is provided.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, an embodiment relating to a method for producing a semiconductor optical device of the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

[Method of Fabricating Single Quantum Well Semiconductor Optical Device]
First, a method for manufacturing a semiconductor optical device having a single quantum well structure (SQW) according to an embodiment of the present invention will be described. 1 to 4 show the main steps of this method. The semiconductor optical device fabricated by this method is made of a III-V compound semiconductor, and the crystal growth of the III-V compound semiconductor is performed using a metal organic vapor phase epitaxy method. Further, this semiconductor optical device includes a III-V compound semiconductor layer (first and third III-V compound semiconductor layers) containing gallium as a group III and arsenic as a group V, and gallium and indium as a group III. And a III-V compound semiconductor layer (second III-V compound semiconductor layer) containing arsenic and nitrogen as a group V. The second III-V compound semiconductor layer is a well layer in a single quantum well structure of the semiconductor optical device, and the first and third III-V compound semiconductor layers are light confinement layers. In the following description, a method for manufacturing an edge-emitting laser diode as an example of a semiconductor optical device will be described.

  A semiconductor substrate 113 is set in the growth furnace 111. Examples of gallium source, indium source, aluminum source, nitrogen source, phosphorus source and arsenic source are triethylgallium (TEGa), trimethylindium (TMIn), trimethylaluminum (TMAl), dimethylhydrazine (DMHy) and tertiary butyl, respectively. Phosphine (TBP) and tertiary butylarsine (TBAs) can be used.

  The semiconductor substrate 113 is made of a first conductivity type III-V compound semiconductor, and is, for example, a Si-doped n-type GaAs substrate. As shown in FIG. 1A, a buffer layer 115, a cladding layer 117, and an optical confinement layer 119 are formed on the main surface 113a of the semiconductor substrate 113. The buffer layer 115 and the cladding layer 117 are made of a first conductivity type III-V compound semiconductor, and the optical confinement layer 119 is made of a III-V compound semiconductor containing gallium as a group III and arsenic as a group V. An n-type GaAs buffer layer, an n-type AlGaAs cladding layer, and an undoped GaAs optical confinement layer are grown in this order on an example n-type GaAs substrate. The growth temperature of the GaAs buffer layer is, for example, 550 degrees Celsius, the growth temperature of the AlGaAs cladding layer is, for example, 650 degrees Celsius, and the growth temperature of the GaAs optical confinement layer is, for example, 550 degrees Celsius. The material of the optical confinement layer 119 is not limited to GaAs, and can be made of either GaNAs or GaAsP.

  Next, as shown in FIG. 1B, a well layer 121 for the active layer is formed on the optical confinement layer 119 at the growth temperature T11. The well layer 121 is made of a III-V compound semiconductor containing gallium and indium as a group III and arsenic and nitrogen as a group V. The well layer 121 can be made of, for example, an undoped GaInNAs layer, and the growth temperature T11 is, for example, not less than 490 degrees Celsius and not more than 540 degrees Celsius.

  In the subsequent step, after the well layer 121 for the active layer is grown, the optical confinement layer 123 is formed on the well layer 121 at the growth temperature T12 as shown in FIG. The optical confinement layer 123 is made of a III-V compound semiconductor containing gallium as a group III and arsenic as a group V. The example optical confinement layer 123 can be, for example, undoped GaAs, and the growth temperature T12 is, for example, not less than 490 degrees Celsius and not more than 550 degrees Celsius. The material of the optical confinement layer 123 is not limited to GaAs, and can be made of either GaNAs or GaAsP.

  Next, as shown in FIG. 2B, a clad layer 125 made of a second conductivity type III-V compound semiconductor is formed on the optical confinement layer 123 at a growth temperature T13. For example, the clad layer 125 may be p-type AlGaAs, and the growth temperature T13 is, for example, 550 degrees Celsius or higher and 650 degrees Celsius or lower.

  Next, as shown in FIG. 3A, a contact layer 127 made of a second conductivity type III-V compound semiconductor is formed on the cladding layer 125 at a growth temperature T14. For example, the contact layer 127 may be p-type GaAs, and the growth temperature T14 is, for example, 500 degrees Celsius or more and 550 degrees Celsius or less. Through these steps, an epitaxial substrate E11 was formed.

  Next, as shown in FIG. 3B, annealing 129 of the epitaxial substrate E11 is performed at a temperature T15 using the growth furnace 111. The annealing temperature T15 is, for example, not less than 550 degrees Celsius and not more than 750 degrees Celsius. The annealing 129 is performed in an atmosphere such as tertiary butyl arsine (TBAs). By this heat treatment, an epitaxial substrate E12 was formed.

  After the annealing 129 is performed, the temperature of the epitaxial substrate E12 after the thermal annealing 129 is decreased at a rate of 2 degrees / second or less. Preferably, the temperature of epitaxial substrate E12 after thermal annealing 129 is reduced at a rate of 0.5 degrees / second or less.

  Thereafter, as shown in FIG. 4A, an insulating film 131 is formed on the contact layer 127 of the epitaxial substrate E12 after the temperature decrease by using the CVD film forming apparatus 133, and an opening is formed in the insulating film 131. Then, the protective layer 131a is formed. The opening of the insulating film 131 is formed by photolithography.

  Next, as shown in FIG. 4B, electrodes 135 and 137 are formed on the epitaxial substrate. In one example, the p electrode of the electrodes 135 and 137 is formed on the contact layer 127 and the n electrode of the electrodes 135 and 137 is formed on the back surface 113 b of the substrate 213.

After forming the electrodes, a semiconductor laser was fabricated by opening the wafer wall. The cavity length of this semiconductor laser is, for example, 600 μm. An example of a semiconductor laser manufactured by these processes is
Semiconductor substrate 113: Si-doped n-type GaAs
Buffer layer 115: Si-doped n-type GaAs, thickness 200 nm
Cladding layer 117: Si-doped n-type AlGaAs, thickness 1.5 μm
Optical confinement layer 119: undoped GaAs, thickness 140 nm
Well layer 121: undoped GaInNAs, thickness 7 nm
Optical confinement layer 123: undoped GaAs, thickness 140 nm
Cladding layer 125: Zn-doped p-type AlGaAs, thickness 1.5 μm
Contact layer 127: Zn-doped p-type GaAs, thickness 200 nm
Insulating film 131: silicon oxide, thickness 100 nm
It is.

The active layer has a single quantum well structure, and can include, for example, an optical confinement layer 119, a well layer 121, and an optical confinement layer 123. With this growth of the well layer, the flow rates of the organic metal raw materials TEGa, TMIn, DMHy, and TBAs are 5 × 10 ⁻⁵ mol / min, 2 × 10 ⁻⁵ mol / min, and 3 × 10 ⁻² mol / min, respectively. It was 3 × 10 ⁻⁴ mol / min. In this growth, the molar ratio of DMHy and TBAs supplied to the same group V atom is [DMHy]: [TBAs] = 100: 1.
Met. The In composition and the N composition were about 34% and about 1%, respectively, and the laser emission wavelength was 1.29 μm.

[Method of Fabricating Semiconductor Optical Device with Multiple Quantum Well Structure]
Next, a method for manufacturing a semiconductor optical device having a multiple quantum well structure (MQW) according to an embodiment of the present invention will be described. 5 to 9 are drawings showing the main steps of this method. The semiconductor optical device fabricated by this method is made of a III-V compound semiconductor, and the crystal growth of the III-V compound semiconductor is performed using a metal organic vapor phase epitaxy method. Further, this semiconductor optical device includes a III-V compound semiconductor layer (first and third III-V compound semiconductor layers) containing gallium as a group III and arsenic as a group V, and gallium and indium as a group III. And a III-V compound semiconductor layer (second III-V compound semiconductor layer) containing arsenic and nitrogen as a group V. The second III-V compound semiconductor layer is a well layer in the multiple quantum well structure of the semiconductor optical device, and the first and third III-V compound semiconductor layers are barrier layers or light confinement layers. In the following description, a method for manufacturing an edge-emitting laser diode as an example of a semiconductor optical device will be described.

  A semiconductor substrate 213 is set in the growth furnace 211. Examples of gallium source, indium source, aluminum source, nitrogen source, phosphorus source and arsenic source are triethylgallium (TEGa), trimethylindium (TMIn), trimethylaluminum (TMAl), dimethylhydrazine (DMHy) and tertiary butyl, respectively. Phosphine (TBP) and tertiary butylarsine (TBAs) can be used.

  The semiconductor substrate 213 is made of a first conductivity type III-V compound semiconductor, and is, for example, a Si-doped n-type GaAs substrate. As shown in FIG. 5A, the buffer layer 215, the cladding layer 217, and the light confinement layer 219 are formed on the main surface 213 a of the semiconductor substrate 213. The buffer layer 215 and the cladding layer 217 are made of a first conductivity type III-V compound semiconductor, and the optical confinement layer 219 is made of a III-V compound semiconductor containing gallium as a group III and arsenic as a group V. An n-type GaAs buffer layer, an n-type AlGaAs cladding layer, and an undoped GaAs optical confinement layer are grown in this order on an example n-type GaAs substrate. The growth temperature of the GaAs buffer layer is, for example, 550 degrees Celsius, the growth temperature of the AlGaAs cladding layer is, for example, 650 degrees Celsius, and the growth temperature of the GaAs optical confinement layer is, for example, 550 degrees Celsius. The material of the optical confinement layer 219 is not limited to GaAs, and can be made of either GaNAs or GaAsP.

  Next, as shown in FIG. 5B, a well layer 221a for the active layer is formed on the optical confinement layer 219 at the growth temperature T21. The well layer 221a is made of a III-V compound semiconductor containing gallium and indium as a group III and arsenic and nitrogen as a group V. The well layer 221a can be made of, for example, an undoped GaInNAs layer, and the growth temperature T21 is, for example, not less than 490 degrees Celsius and not more than 540 degrees Celsius.

  In the subsequent process, after the well layer 221a for the active layer is grown, the remaining plurality of III-V compound semiconductor layers for the semiconductor optical device are grown at respective growth temperatures to form an epitaxial substrate. After the formation of the well layer 221a, as shown in FIG. 6A, a barrier layer 223 is formed on the well layer 221a at the growth temperature T22. The barrier layer 223 is made of a III-V compound semiconductor containing gallium as a group III and arsenic as a group V. The barrier layer 223 can be made of, for example, an undoped GaAs layer, and the growth temperature T22 is, for example, not less than 490 degrees Celsius and not more than 540 degrees Celsius. If necessary, a desired dopant is added to the barrier layer 223. The material of the barrier layer 223 is not limited to GaAs, and can be made of either GaNAs or GaAsP.

  Next, as shown in FIG. 6B, the well layer 221b is formed on the barrier layer 223 at the growth temperature T21 in the same manner as the well layer 221a. The well layer 221b can be composed of, for example, an undoped GaInNAs layer, like the well layer 221a. The material of the well layers 221a and 21b is not limited to GaInNAs, but can be made of either GaInNAsP or GaInNAsSb.

  Next, as shown in FIG. 7A, the optical confinement layer 225 is formed on the well layer 221b at the growth temperature T23. The optical confinement layer 225 is made of a III-V compound semiconductor containing gallium as a group III and arsenic as a group V. The example optical confinement layer 225 can be, for example, undoped GaAs, and the growth temperature T23 is, for example, not less than 490 degrees Celsius and not more than 550 degrees Celsius. The material of the optical confinement layer 225 is not limited to GaAs, and can be made of either GaNAs or GaAsP.

  Next, as shown in FIG. 7B, a cladding layer 227 made of the second conductivity type III-V compound semiconductor is formed on the optical confinement layer 225 at a growth temperature T24. For example, the clad layer 227 can be p-type AlGaAs, and the growth temperature T24 is, for example, 550 degrees Celsius or higher and 650 degrees Celsius or lower.

  Next, as shown in FIG. 8A, a contact layer 229 made of a second conductivity type III-V compound semiconductor is formed on the cladding layer 227 at a growth temperature T25. For example, the contact layer 229 may be p-type GaAs, and the growth temperature T25 is, for example, 500 degrees Celsius or more and 550 degrees Celsius or less. Through these steps, an epitaxial substrate E21 was formed.

  Next, as shown in FIG. 8B, annealing 231 of the epitaxial substrate E21 is performed at a temperature T26 using the growth furnace 211. The annealing temperature T26 is, for example, not less than 550 degrees Celsius and not more than 750 degrees Celsius. The annealing 231 is performed in an atmosphere such as tertiary butyl arsine (TBAs). By this heat treatment, an epitaxial substrate E22 was formed.

  After the annealing 231 is performed, the temperature of the epitaxial substrate E22 after the thermal annealing 231 is decreased at a rate of 2 degrees / second or less. Preferably, the temperature of the epitaxial substrate E22 after the thermal annealing 231 is lowered at a rate of 0.5 degrees / second or less.

  Thereafter, as shown in FIG. 9A, an insulating film 233 is formed on the contact layer 229 of the epitaxial substrate E22 after the temperature decrease by using the CVD film forming apparatus 235, and an opening is formed in the insulating film 233. Then, the protective layer 233a is formed. The opening of the insulating film 233 is formed by photolithography.

  Next, as shown in FIG. 9B, electrodes 237 and 239 are formed on the epitaxial substrate. In one example, the p electrode of the electrodes 237 and 239 is formed on the contact layer 229, and the n electrode of the electrodes 237 and 239 is formed on the back surface 213b of the substrate 213.

After forming the electrodes, a semiconductor laser was fabricated by opening the wafer wall. The cavity length of this semiconductor laser is, for example, 600 μm. An example of a semiconductor laser manufactured by these processes is
Semiconductor substrate 213: Si-doped n-type GaAs
Buffer layer 215: Si-doped n-type GaAs, thickness 200 nm
Clad layer 217: Si-doped n-type AlGaAs, thickness 1.5 μm
Optical confinement layer 219: undoped GaAs, thickness 140 nm
Well layer 221a: undoped GaInNAs, thickness 7 nm
Barrier layer 223: undoped GaAs, thickness 8 nm
Well layer 221b: undoped GaInNAs, thickness 7 nm
Optical confinement layer 225: undoped GaAs, thickness 140 nm
Cladding layer 227: Zn-doped p-type AlGaAs, thickness 1.5 μm
Contact layer 229: Zn-doped p-type GaAs, thickness 200 nm
Insulating film 233: silicon oxide, thickness 100 nm
It is.

The active layer has a multiple quantum well structure, and can include, for example, an optical confinement layer 219, a well layer 221a, a barrier layer 223, a well layer 221b, and an optical confinement layer 225. With this growth of the well layer, the flow rates of the organic metal raw materials TEGa, TMIn, DMHy, and TBAs are 5 × 10 ⁻⁵ mol / min, 2 × 10 ⁻⁵ mol / min, and 3 × 10 ⁻² mol / min, respectively. It was 3 × 10 ⁻⁴ mol / min. In this growth, the molar ratio of DMHy and TBAs supplied to the same group V atom is [DMHy]: [TBAs] = 100: 1.
Met. The In composition and the N composition were about 34% and about 1%, respectively, and the laser emission wavelength was 1.29 μm.

[Experimental result]
The method for manufacturing a semiconductor optical device having a single or multiple quantum well structure has been described above. Below, the result of the experiment which confirmed the crystallinity of the semiconductor optical element produced by said method is demonstrated.

  The inventor manufactured four types of edge-emitting light emitting diodes (LEDs) having a GaInNAs / GaAs quantum well structure by the above-described [Method of manufacturing a semiconductor optical device having a single quantum well structure]. TEGa, TMIn, DMHy, and TBAs were used as Ga, In, N, and As raw materials, respectively. The substrate is a 2 ° off substrate of Si-doped GaAs (100). An undoped GaAs buffer layer was grown to 200 nm on the GaAs substrate, an undoped GaInNAs quantum well layer was grown to 7 nm thereon, and an undoped GaAs cap layer was grown to 100 nm thereon. The growth temperature of the GaInNAs quantum well layer was 510 ° C., the growth rate was 1 micron / hrs, the DMHy / (DMHy + TBAs) ratio was 0.97, and the growth pressure was 76 torr. The composition of the GaInNAs quantum well layer was 66% Ga and 34% In.

After the epitaxial growth, the epitaxial wafer was subjected to thermal annealing and temperature cooling after the thermal annealing under different conditions. The conditions for thermal annealing and temperature cooling after the thermal annealing are as follows. The thermal annealing time is about several minutes.
Condition 1: Temperature at the time of thermal annealing = 650 degrees, temperature decrease rate after thermal annealing = 2 degrees / second Condition 2: Temperature at the time of thermal annealing = 700 degrees, temperature decrease speed after thermal annealing = 2 degrees / second Condition 3: Temperature during thermal annealing = 620 ° C., rate of temperature decrease after thermal annealing = 0.5 ° C./second Condition 4: Temperature during thermal annealing = 670 ° C., rate of temperature decrease after thermal annealing = 0. 5 degrees / second

  The optical properties of these four GaInNAs / GaAs quantum well structure crystals were evaluated by PL (Photoluminescence) at room temperature. FIG. 10 shows the results of the PL peak wavelength, the PL intensity, and the half width of the PL peak. In the experimental results shown in FIG. 10, in the correlation between the PL peak wavelength and the PL peak intensity in the GaInNAs / GaAs quantum well structure crystal, the PL emission intensity tends to increase as the PL peak wavelength becomes shorter. Should be considered. Therefore, when comparing the PL emission characteristics of GaInNAs / GaAs quantum well structure crystals using the experimental results shown in FIG. 10, it is necessary to compare the PL emission intensity for the same PL peak wavelength. That is, condition 1 and condition 3 should be compared, and condition 2 and condition 4 should be compared.

  Comparing Condition 1 and Condition 3, the PL peak wavelength is close, but the PL intensity is significantly greater in Condition 3. As shown in FIG. 10, the PL intensity is 4.5 under condition 1, while the PL intensity is 13 under condition 3. In condition 1, the half-width of the PL peak is 52 meV, whereas in condition 3, the half-width of the PL peak is 49 meV. Further, when the conditions 2 and 4 are compared, the PL peak wavelength is close, but the PL intensity is significantly higher in the condition 4. As shown in FIG. 10, the PL intensity is 4.8 under condition 2, but the PL intensity is 14 under condition 4. In condition 2, the half width of the PL peak is 49 meV, whereas in condition 4, the half width of the PL peak is 47 meV.

  Considering these results, it can be seen that the crystallinity of the finally obtained GaInNAs / GaAs quantum well structure crystal depends on the rate of decrease when the temperature is lowered after thermal annealing. Although not shown in the figure, when the rate of decrease is faster than 2 degrees / second, a PL intensity lower than that of Condition 1 or 2 appears. Therefore, in order to achieve good crystallinity, the temperature is low at 2 degrees / second or less. Is preferably lowered. Although not shown, when the rate of decrease is slower than 0.5 degrees / second, a PL intensity higher than that of Condition 3 or 4 appears, and in order to achieve better crystallinity, 0.5 degrees It is preferable to lower the temperature at a rate of less than / sec.

  Here, the above experimental results will be further discussed. In general, GaInNAs / GaAs quantum well structure crystals can be used not only for simple single quantum well structure epi-wafers, but also for epi-wafers such as multiple quantum well structures for use in laser active layers and structures with cladding layers. It is necessary to thermally anneal the GaInNAs / GaAs quantum well layer at a temperature higher than the growth temperature at which the crystal is grown. By heat annealing, the crystallinity can be made good enough to be commercialized. In this thermal annealing, the temperature of the GaInNAs / GaAs quantum well layer is higher than the growth temperature of the crystal growth, so changes in the crystal structure occur, such as the arrangement of the atoms of the GaInNAs once crystallized by thermal annealing. It is thought that. On the other hand, the temperature decreases immediately after the thermal annealing is completed, but it is considered that there is a change in the structure inside the crystal even during the time when the temperature is decreasing.

  At this time, when the rate of temperature decrease is small, it is considered that the structural change inside the crystal is small in the time zone when the temperature is decreasing, and it is easy to maintain good crystallinity obtained by thermal annealing. it is conceivable that. On the other hand, if this temperature decrease rate is large, it is considered that the structural change inside the crystal is large in the time zone when the temperature is decreasing, and the good crystallinity obtained by thermal annealing cannot be maintained. Furthermore, it is considered that the crystallinity is deteriorated.

  Therefore, in the present invention, the crystallinity of the semiconductor optical device can be improved by reducing the temperature of the semiconductor layer after the thermal annealing at a low speed after the thermal annealing.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

It is drawing which shows the main processes of [the method of manufacturing the semiconductor optical element of a single quantum well structure] concerning an embodiment of the invention. It is drawing which shows the main processes of [the method of manufacturing the semiconductor optical element of a single quantum well structure] concerning an embodiment of the invention. It is drawing which shows the main processes of [the method of manufacturing the semiconductor optical element of a single quantum well structure] concerning an embodiment of the invention. It is drawing which shows the main processes of [the method of manufacturing the semiconductor optical element of a single quantum well structure] concerning an embodiment of the invention. It is drawing which shows the main processes of [the method of manufacturing the semiconductor optical element of a multiple quantum well structure] concerning an embodiment of the invention. It is drawing which shows the main processes of [the method of manufacturing the semiconductor optical element of a multiple quantum well structure] concerning an embodiment of the invention. It is drawing which shows the main processes of [the method of manufacturing the semiconductor optical element of a multiple quantum well structure] concerning an embodiment of the invention. It is drawing which shows the main processes of [the method of manufacturing the semiconductor optical element of a multiple quantum well structure] concerning an embodiment of the invention. It is drawing which shows the main processes of [the method of manufacturing the semiconductor optical element of a multiple quantum well structure] concerning an embodiment of the invention. It is drawing which shows the result of the experiment which confirmed the crystallinity of the semiconductor optical element produced by [The method of producing the semiconductor optical element of a single quantum well structure].

Explanation of symbols

113, 213 ... Semiconductor substrate, 115, 215 ... Buffer layer, 117, 125, 217, 227 ... Cladding layer, 119, 123, 219, 225 ... Optical confinement layer, 121, 221a, 221b ... Well layer, 223 ... Barrier layer 127, 229, contact layers, 131, 233, insulating films.

Claims (6)

A method for producing a semiconductor optical device, comprising:
A first step of growing a first III-V compound semiconductor layer containing gallium as a group III and arsenic as a group V by metal organic chemical vapor deposition;
A second step of growing a second III-V compound semiconductor layer containing gallium and indium as a group III and arsenic and nitrogen as a group V by metal organic chemical vapor deposition;
A third step of growing a third III-V compound semiconductor layer containing gallium as a group III and arsenic as a group V by metal organic chemical vapor deposition;
A fourth step of performing thermal annealing on the grown first to third III-V compound semiconductor layers after growing the first to third III-V compound semiconductor layers;
A fifth step of lowering the temperature of the first to third III-V compound semiconductor layers after the thermal annealing at a rate of 2 degrees / second or less after the thermal annealing;
A method comprising the steps of:   In the fifth step, after the thermal annealing, the temperature of the first to third III-V compound semiconductor layers after the thermal annealing is decreased at a rate of 0.5 degrees / second or less. The method of claim 1, wherein:   3. The method according to claim 1, wherein the second III-V compound semiconductor layer is made of any one of GaInNAs, GaInNAsP, and GaInNAsSb. The first III-V compound semiconductor layer is made of either GaAs or GaNAs,
4. The method according to claim 3, wherein the third III-V compound semiconductor layer is made of either GaAs or GaNAs.   The method according to claim 1, wherein the second III-V compound semiconductor layer is a well layer in a quantum well structure.   6. The method according to claim 5, wherein the first and third III-V compound semiconductor layers are barrier layers or optical confinement layers in a quantum well structure.

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