JP2009231308A - Method of manufacturing semiconductor device having super junction structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having a super junction structure wherein a dislocation defect does not easily occur in a filled epitaxial layer of a second conductivity type for the purpose of further improving the quality of the region of the second conductivity type formed inside a trench. <P>SOLUTION: In the method, the growth time by an epitaxial growth method is made longer than the time until the region of the second conductivity type is filled to the opening of the trench, and is made shorter than the time needed until the over-deposition layer of the region of the second conductivity type grown on an oxide film or on the surface of a silicon substrate from the opening of the trench contacts the over-deposition layer from the opening of the other adjacent trench on the oxide film or on the surface of the silicon substrate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  In particular, the present invention has a pn junction structure in which a p-type semiconductor is epitaxially grown in a trench formed in an n-type semiconductor substrate so that the n-type semiconductor region and the p-type semiconductor region are repeatedly joined in stripes. The present invention relates to a method of manufacturing a semiconductor having a parallel structure, for example, a super junction MOS transistor.

In a normal vertical power MOSFET (insulated gate field effect transistor: planar type), the lower limit value of the on-resistance is theoretically determined according to the breakdown voltage. That is, when the breakdown voltage of the element is increased, the lower limit value of the on-resistance is increased, and it is inevitable that the switching loss increases. This is because the direction of the drift current flowing in the on state is the same as the direction in which the depletion layer spreads in the off state (reverse bias state). In other words, in order to increase the breakdown voltage of the element, it is necessary to increase the resistance of the drift layer.
The same situation applies to IGBTs (insulated gate bipolar transistors) and diodes.

  To solve these problems, a vertical power MOSFET (super junction MOSFET) having a pn junction structure in which an n-type drift layer region with an increased impurity concentration and a p-type partition region is alternately and repeatedly arranged has been proposed and put into practical use. (For example, refer to Patent Document 1). In a power MOSFET with such a structure, pn junctions are repeatedly formed in parallel, so that a depletion region can be formed in both the horizontal and vertical directions in the off state, so that the entire drift layer can be widely depleted and high breakdown voltage is ensured. it can. Further, with this structure, the impurity concentration of the drift layer can be increased, so that the on-resistance can be reduced.

  In order to obtain a semiconductor substrate in which pn junction structures are repeated in parallel and alternately, there is a method in which an ion implantation process and an epitaxial layer growth process are repeatedly performed on the semiconductor substrate (see, for example, Patent Document 2). However, it is difficult to make it easier, and there is a limit to the improvement of characteristics, and the number of processes is likely to increase. On the other hand, a trench (groove) is formed by etching on the surface of the first conductivity type silicon single crystal substrate, and the trench is filled with a second conductivity type filling epitaxial layer, thereby repeating the structure in parallel and alternately. Techniques for forming a pn junction structure have been disclosed (see, for example, Patent Document 3 and Patent Document 4).

When the trench is filled with a filled epitaxial layer by an epitaxial growth method, it is necessary to increase the aspect ratio of the trench depth to the width of the opening of the trench in order to further reduce the on-resistance. However, when the aspect ratio is increased, the shape of the trench becomes a rectangle that is elongated in the normal direction to the surface of the substrate. Therefore, the trench opening is easily blocked while the trench is filled with an epitaxial film by the epitaxial growth method, and a void ( It has been pointed out that voids tend to remain (see, for example, Patent Document 3).
On the other hand, in an epitaxial growth reaction when filling the inside of the trench, there is a method capable of filling a complete epitaxial layer in which no void is generated inside the trench by flowing an etching gas such as HCl gas simultaneously with the silicon source gas. It is disclosed (see Patent Document 5).

  However, when epitaxial growth is performed using such a method, dislocations may occur near the surface of the filled epitaxial layer, although imperfect filling such as voids formed in the trench can be prevented. there were.

European Patent Application No. 0053854 JP 2001-139399 A JP 2001-196573 A JP 2002-141407 A Japanese Patent No. 3915984 D. Kishimoto et al., The Journal of Crystal Growth, 240 (2002) 52. Ichiro Mizushima et al., Applied Physics, 69 (2000) 1187 H. Kuribayashiet.al., AVS49th International Symposium, SS-TuP12, Nov. 3-8, (2002)

  The present invention has been made in view of the above-described problems. For the purpose of further improving the quality of the second conductivity type region formed in the trench, dislocation defects are present in the second conductivity type filled epitaxial layer. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a super junction structure that is unlikely to occur.

  In order to achieve the above object, according to the present invention, a stripe-shaped trench is formed on a first conductivity type silicon substrate, and a second conductivity type region is formed in the trench by an epitaxial growth method. In the method of manufacturing a semiconductor device having a super junction structure in which a pn junction structure is formed at an interface between a silicon substrate of one conductivity type and a region of the second conductivity type formed in the trench, Forming a trench by etching using an oxide film as a mask on a silicon substrate; and growing the second conductivity type region on the first conductivity type silicon substrate having the trench formed by an epitaxial growth method; A step of filling the trench, and spending the growth time by the epitaxial growth method up to the opening of the trench in the second conductivity type region. The over-deposited layer of the second conductivity type region grown on the oxide film or the silicon substrate from the opening of the trench is longer than the time until it is formed. There is provided a method for manufacturing a semiconductor device having a super junction structure, characterized in that the time required for contacting the deposition layer with the oxide film or the silicon substrate is shorter.

  As described above, the method includes the above-described steps, and the growth time by the epitaxial growth method is longer than the time until the second conductivity type region is filled up to the opening of the trench, The overdeposition layer of the second conductivity type region grown on the oxide film or the silicon substrate is in contact with the overdeposition layer from the opening of another adjacent trench on the oxide film or the silicon substrate. If the manufacturing method of the semiconductor device having a super junction structure that is shorter than the time required for the above-mentioned process, the formed trench can be reliably filled with the epitaxial layer, and the over-deposition layer in the second conductivity type region is adjacent Contact with an over-deposition layer from the opening of another trench on the oxide film or on the surface of the silicon substrate Further, since it is possible to prevent stress from being generated in the second conductivity type region, a semiconductor device having a super junction structure in which the second conductivity type filled epitaxial layer formed in the trench has no dislocation defect is manufactured. Can do.

At this time, in the step of forming the second conductivity type region by the epitaxial growth method, it is preferable to form the second conductivity type region while supplying dichlorosilane or trichlorosilane and HCl gas.
As described above, in the step of forming the second conductivity type region by the epitaxial growth method, if the second conductivity type region is formed while supplying dichlorosilane or trichlorosilane and HCl gas, it may occur in the process of filling the trench. It is possible to make it difficult for voids to be generated. As a result, it is possible to manufacture a semiconductor element having a super junction structure in which there is no void in the trench and the second conductivity type filled epitaxial layer formed in the trench has no dislocation defect.

  In the present invention, a stripe-shaped trench is formed on a first conductivity type silicon substrate, a second conductivity type region is formed in the trench by an epitaxial growth method, and the first conductivity type silicon substrate and the trench are formed. In the manufacture of a semiconductor device having a super junction structure in which a pn junction structure is formed at the interface with the region of the second conductivity type formed in the substrate, it is grown from the opening of the trench on the oxide film or on the surface of the silicon substrate. The over-depot layer in the second conductivity type region is prevented from contacting the over-deposition layer from the opening of another adjacent trench on the oxide film or the surface of the silicon substrate. A super junction having no dislocation defect in the second conductivity type filled epitaxial layer formed in the trench can be prevented. It is possible to manufacture a semiconductor device having the structure.

Hereinafter, although an embodiment is described about the present invention, the present invention is not limited to this.
The super junction MOSFET has a parallel pn junction structure in which p-type partition regions having a low resistance are arranged in parallel and alternately on an n-type silicon substrate having a high impurity concentration and a low resistance. As described above, with this configuration, the on-resistance and the breakdown voltage that are in a trade-off relationship can be significantly improved. That is, the on-resistance can be reduced and a high breakdown voltage can be secured.

In order to fabricate the parallel pn junction structure on, for example, an n-type silicon substrate, a method of forming a striped trench on the silicon substrate and filling the trench with an epitaxial layer of p-type silicon single crystal by an epitaxial growth method. Is common.
In the epitaxial growth reaction when filling the trench, it is possible to fill a complete epitaxial layer in which no voids are generated inside the trench by flowing an etching gas such as HCl gas simultaneously with the silicon source gas.
However, when a semiconductor device is manufactured using such a method, dislocation defects may occur in the second conductivity type filled epitaxial layer in the trench.

  Therefore, the present inventor investigated and examined the cause of the occurrence of such dislocation defects. As a result, dislocation defects are caused by the occurrence of an overdeposit layer that is an unnecessary raised portion grown on the oxide film or the surface of the silicon substrate from the trench opening. It was found that there is a stress generated when contacting the layer. That is, after the silicon is filled up to the opening of the trench and further epitaxial growth is continued, the silicon rises above the opening and further spreads on the oxide film or the silicon substrate. At this time, if the overdeposit layers formed by the same phenomenon in adjacent trenches come into contact with each other, epitaxial growth which has been performed freely so far is hindered, and a large stress is generated. It was found that due to the stress, dislocation defects occurred and the dislocation defects extended into the trench.

  Therefore, in order to prevent the occurrence of dislocation to the second conductivity type filled epitaxial layer in the trench, the inventor contacts the overdeposit layer from the opening of the adjacent trench with each other on the oxide film or the silicon substrate. The present invention was completed by conceiving that it should be avoided. That is, conventionally, it is common knowledge that the trench is filled with the second conductivity type epitaxial layer to ensure the epitaxial growth until the overdeposition layer is formed. Until the overdeposition layer is formed on the entire surface of the wafer. The epitaxial growth of was continued. On the other hand, in the method for manufacturing a semiconductor device having a super junction structure according to the present invention, the growth time by the epitaxial growth method is longer than the time until the second conductivity type region is filled to the opening of the trench, An overdeposition layer of the second conductivity type region grown on the oxide film or on the surface of the silicon substrate from the opening is overlaid on the oxide film or the silicon substrate from the opening of another adjacent trench. The growth time was shorter than the time required for contact on the surface.

FIG. 1 is a flowchart of a manufacturing process of a semiconductor device having a super junction structure according to the present invention.
FIG. 2A is a schematic cross-sectional view showing an example of a silicon epitaxial wafer manufactured by the method for manufacturing a semiconductor device having a super junction structure according to the present invention.
As shown in FIG. 2A, the silicon epitaxial wafer 1 is formed such that the longitudinal direction of the surface MP of the n-type silicon single crystal substrate 2 doped with P, As or Sb coincides with a predetermined direction. A plurality of trenches 5 are formed at regular intervals, and the inside of the trenches 5 is filled with a filled epitaxial layer 3 made of p-type silicon single crystal doped with B. An n-type layer region 4 derived from the substrate 2 is formed between the adjacent filled epitaxial layers 3. As shown in FIG. 3, a p-type silicon single crystal substrate 2 may be used and the filled epitaxial layer 3 may be formed as an n-type layer region.
FIG. 2B is an enlarged schematic cross-sectional view showing the trench of FIG.
As shown in FIG. 2B, the trench 5 has an inner surface WP, and is formed of a groove having a depth d, a width w1 of the opening, and a width w2 at the bottom.

As shown in FIG. 4, a silicon single crystal substrate 2 that can be used in the method of manufacturing a semiconductor device of the present invention has an epitaxial layer 2b having a resistivity of about 1 Ωcm on an n-type silicon single crystal substrate 2a by an epitaxial growth method. It can be set as the grown n / n + type | mold silicon epitaxial substrate. Here, the surface index of the surface of the substrate 2 can be (100). The orientation flat direction or notch direction is not particularly limited, but can be (100).
The surface index of the inner surface WP of the trench 5 can be (010), and the width w1 of the opening of the trench 5 is substantially equal to the width w2 at the bottom, or w1 is set wider than w2. In this case, the surface index of the inner surface WP becomes a higher index surface than (010).
Moreover, the depth d of the trench 5 can be 5-100 micrometers, for example, and the width w1 of the trench 5 can be 0.5-6 micrometers, for example.

In the method of manufacturing a semiconductor device having a super junction structure according to the present invention, first, a silicon single crystal substrate 2 as shown in FIG. 4 is prepared (see FIG. 1A).
Next, a pattern of a silicon oxide film 6 made of a thermal oxide film is formed on the surface of the substrate 2 by a known photolithography technique (see FIG. 1B). Then, using these films as a mask, trenches 5 having a predetermined depth for forming parallel pn junction structures in stripes are formed by, for example, dry etching such as reactive ion etching (FIG. 5). 1C, see FIG. 5).
Thus, the use of dry etching is preferable because the steepness of the inner surface of the trench can be increased, but a wet etching method may be used.
A p-type silicon single crystal substrate as shown in FIG. 3 can also be used.

Further, when RIE or the like is performed, reaction products and damage remain on the inner wall of the trench 5, so that the trench is cleaned and removed if necessary. These can be cleaned by performing sufficient hydrogen baking or performing a minimum amount of gas etching.
Here, the oxide film used as a mask in the trench formation step may be removed by wet etching after the trench formation, but it is not necessary to remove the oxide film and is not particularly limited in the present invention.

Next, the p-type filled epitaxial layer 3 is vapor-phase grown on the silicon single crystal substrate 2 in which the trench 5 is formed (see FIGS. 1D and 6). In this example, the mask oxide film 6 is left.
When the p-type is used for the silicon single crystal substrate, the filled epitaxial layer is an n-type layer region.
Specifically, the silicon single crystal substrate 2 is disposed in a vapor phase growth apparatus, the substrate 2 is heat-treated at a predetermined temperature (for example, 1130 ° C. in a hydrogen atmosphere), and then the filled epitaxial layer 3 is vapor-phase grown.

FIG. 8 is a schematic side sectional view showing an example of a vapor phase growth apparatus 121 that can be used in the present invention.
As shown in FIG. 8, the vapor phase growth apparatus 121 includes a reaction vessel 122 formed in a flat box shape, and a source gas SG from a gas inlet 171 formed at one end thereof passes through a flow adjustment unit 124. It is supplied horizontally and in one direction to the internal space of the container body 123. In the container main body 123, only one silicon single crystal substrate 2 is disposed substantially horizontally on the susceptor 112 disposed in the susceptor housing recess 110. In addition, a gas discharge port 128 is formed in the reaction vessel 122 through a venturi-shaped throttle 129 at the end opposite to where the source gas introduction port 171 is formed.
The introduced source gas SG is exhausted from the gas outlet 128 after passing over the surface of the silicon single crystal substrate 2.

Here, for example, trichlorosilane gas can be used as the source gas SG. This trichlorosilane gas is bubbled with hydrogen gas in liquid trichlorosilane (SiHCl ₃ ) to form a mixed gas having a constant concentration, and is introduced into the pipe 107 while the flow rate is adjusted by the valve 109.
Further, the diluting hydrogen gas is guided to the pipe 108 through the valve 105, and finally flows into the reaction vessel 122 from the raw material gas inlet 171 in a form in which both are further mixed and the trichlorosilane concentration is adjusted. .
Alternatively, dichlorosilane can be used as the source gas SG.
Further, the dopant gas is diluted in advance with hydrogen gas or the like, and supplied to the reaction vessel 122 from the pipe 106 while the flow rate is adjusted by the mass flow controller 104.
Here, when the p-type filled epitaxial layer 3 is vapor-phase grown, the dopant gas can be, for example, diborane (B ₂ H ₆ ).

The silicon single crystal substrate 2 is rotationally driven by the motor M together with the susceptor 112, and further supplied with the source gas SG while being heated by the infrared heating lamp 111, whereby an epitaxial layer is formed in the trench. The pressure in the reaction vessel is a normal pressure, but it is preferable to set the pressure so that the pressure is slightly higher than the atmospheric pressure in order to prevent the intake of outside air.
Here, the growth temperature can be 850 to 1100 ° C.

At this time, it is preferable to vapor-phase grow the filled epitaxial layer 3 while supplying hydrogen chloride as an etching gas together with the source gas SG. Specifically, hydrogen chloride is supplied into the reaction vessel 122 from the pipe 102 while the flow rate is adjusted by the valve 103.
Thus, if the filled epitaxial layer 3 is vapor-phase grown while supplying hydrogen chloride as an etching gas together with the source gas SG, it is possible to make it difficult to generate voids that may occur in the process of filling the trench.
Here, for example, when the growth temperature is 1000 ° C., the supply amount of hydrogen chloride can be 1.0 liter / min.

Thus, when the growth of the epitaxial layer proceeds (see step 2 and step 3 in FIG. 6), the inside of the trench 5 is filled with the epitaxial layer, and finally becomes the filled epitaxial layer 3 (see step 4 in FIG. 6). .
As shown in FIG. 6, when the epitaxial growth is continued after filling with the epitaxial layer, silicon rises above the opening and further spreads over the oxide film. In this way, the overdeposit layer 7 is formed on the oxide film. Thus, in order to completely fill the trench with the epitaxial layer, it is necessary to form the over deposition layer 7.

At this time, in the method for manufacturing a semiconductor device of the present invention, the growth time of the epitaxial layer is longer than the time until the second conductivity type region (filled epitaxial layer) is filled up to the opening of the trench 5. In the case where the oxide film or the mask oxide film is removed from the opening, the over-deposit layer 7 of the second conductivity type region grown on the surface of the silicon substrate 2 is exposed from the opening of another adjacent trench. The epitaxial growth is stopped before the overdepot layers 7 come into contact with each other by making the time shorter than the time required to contact the overdeposit layer 7 on the oxide film or on the surface of the silicon substrate 2.
Here, when the oxide film 6 is removed in the previous step, the overdepot layer 7 is formed on the silicon substrate 2. Even in such a case, adjacent overdeposit layers 7 are in contact with each other. As a result, dislocation defects may occur in the filled epitaxial layer 3, and thus the epitaxial growth is stopped before the overdepot layers 7 contact each other in the same manner as described above.
Here, in order to stop the epitaxial growth before the overdeposition layers 7 come into contact with each other, the epitaxial growth time for the width and depth of the trench is experimentally determined in advance, and the epitaxial growth is performed up to the growth time. Can do.

  Next, as shown in FIG. 7, the overdeposition layer formed above the opening of the trench 5 is removed by polishing (FIG. 1E). Thereby, a flat surface can be obtained.

  As described above, according to the method of manufacturing a semiconductor device having a super junction structure according to the present invention, the overdepot layer in the second conductivity type region is an overdeposit layer from the opening of another adjacent trench. Can be prevented from being generated in the region of the second conductivity type by contact with the oxide film or the surface of the silicon substrate, so that the second conductivity type filled epitaxial layer formed in the trench can be prevented. A semiconductor element having a super junction structure free from dislocation defects without causing so-called slipback can be manufactured.

  EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples and comparative examples of the present invention, but the present invention is not limited to these.

(Example)
First, an epitaxial layer 2b having a resistivity of about 1 Ωcm was grown on an n-type silicon single crystal substrate 2a as shown in FIG. 4 by an epitaxial growth method to prepare an n / n + type silicon epitaxial substrate 2. The substrate 2 has an orientation flat orientation or notch orientation of (100). Next, after forming an oxide film on the surface of the substrate 2 and forming a mask pattern by photolithography, a trench 5 having a crystal orientation of (100) on the side wall and the bottom is formed to a depth of 50 μm by RIE. (See FIG. 5). The line width of the trench 5 was 4 μm.

  Next, cleaning and damage removal in the trench 5 were performed by sacrificial oxidation. Thereafter, HCl gas is simultaneously supplied using trichlorosilane as a source gas, and epitaxial growth of p-type silicon having substantially the same resistivity as that of the n-type epitaxial layer 1b is performed. To fill the trench 5 (see FIG. 6).

  Here, the epitaxial growth is performed at a low growth rate of about 0.5 μm / min by using a vapor phase growth apparatus as shown in FIG. 8, setting the growth temperature to about 1010 ° C., and increasing the supply amount of trichlorosilane. Then, an epitaxial layer was formed.

  The epitaxial growth is performed for a minimum time during which the trench 5 is completely filled, and then an overdeposit layer is formed above the trench 5, and the overdepot layer is formed in each adjacent trench 5. Stopped before contact.

Next, the overdevo layer formed on the oxide film 6 was removed by polishing (see FIG. 7).
The epitaxial wafer thus produced was cleaved and the cross section was examined for the presence of dislocation defects from an optical micrograph (see FIG. 9) after selective etching with a mixed acid solution of fluorine, nitric acid and acetic acid.
As a result, as shown in FIG. 9, no etch pits were seen, and it was confirmed that the generation of dislocation defects could be prevented.

(Comparative example)
An epitaxial wafer is manufactured in the same process as the embodiment, and as shown in FIG. 10, the overdeposit layer 7 from the trench 5 is epitaxially grown, and the overdeposit layer 7 and the oxide film from the opening of the other adjacent trench 5 are used. 6 until contact was made, and the presence or absence of dislocation defects was examined from a micrograph (see FIG. 11) obtained by the same method as in the example.
As a result, as shown in FIG. 11, it was confirmed that many etch pits were generated due to dislocations.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

It is a flowchart which shows an example of the manufacturing process of the semiconductor element which has a super junction structure in this invention. It is the schematic which shows an example of the silicon epitaxial wafer manufactured with the manufacturing method of the semiconductor element which has a super junction structure of this invention. (A) Schematic sectional view of a silicon epitaxial wafer. (B) The schematic sectional drawing which expanded and showed the trench. It is a schematic sectional drawing which shows another example of the silicon epitaxial wafer manufactured by the manufacturing method of the semiconductor element which has a super junction structure of this invention. It is a schematic sectional drawing which shows an example of the silicon substrate which can be used with the manufacturing method of the semiconductor element which has a super junction structure of this invention. It is a schematic sectional drawing of the wafer in B process and C process of the manufacturing method of the semiconductor element which has a super junction structure in this invention. It is a schematic sectional drawing of the wafer in D process of the manufacturing method of the semiconductor element which has a super junction structure in this invention. It is a schematic sectional drawing of the wafer in E process of the manufacturing method of the semiconductor element which has a super junction structure in this invention. It is a schematic sectional drawing which shows an example of the vapor phase growth apparatus which can be used in this invention. The optical microscope photograph after selectively etching the silicon epitaxial wafer manufactured in the Example. It is the schematic sectional drawing which showed the mode of the trench of the silicon epitaxial wafer manufactured in the comparative example. The optical microscope photograph after selectively etching the silicon epitaxial wafer manufactured in the comparative example.

Explanation of symbols

1 ... silicon epitaxial wafer, 2 ... silicon substrate,
3 ... filling epitaxial layer, 4 ... n-type region, 5 ... trench, 6 ... oxide film,
7: Over deposition layer, 121 ... Vapor growth apparatus.

Claims (2)

  A stripe-shaped trench is formed on the first conductivity type silicon substrate, a second conductivity type region is formed in the trench by an epitaxial growth method, and the first conductivity type silicon substrate and the trench are formed. In a method of manufacturing a semiconductor device having a super junction structure in which a pn junction structure is formed at an interface with a second conductivity type region, a trench is formed by etching using an oxide film as a mask on the first conductivity type silicon substrate. And growing the region of the second conductivity type on the first conductivity type silicon substrate in which the trench is formed by the epitaxial growth method, and embedding the trench. The time is longer than the time until the region of the second conductivity type is filled to the opening of the trench, The overdeposit layer of the second conductivity type region grown on the oxide film or the silicon substrate from the opening is formed on the overdeposit layer and the oxide film or the silicon substrate from the opening of another adjacent trench. A method for manufacturing a semiconductor device having a super junction structure, characterized in that the time is shorter than the time required for contact. 2. The super junction according to claim 1, wherein in the step of forming the second conductivity type region by epitaxial growth, the second conductivity type region is formed while supplying dichlorosilane or trichlorosilane and HCl gas. A method for manufacturing a semiconductor device having a structure.

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