JP2009229165A - Coulomb counter, and its internal power supply control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a Coulomb counter having a reduced circuit scale, and capable of sufficiently reducing its current consumption after power-on, and outputting a count value having a little error. <P>SOLUTION: In the Coulomb counter which outputs a count value proportional to an input voltage being a potential difference produced between both ends of a sense resistor, a bias generation circuit 32 for generating a driving bias voltage V<SB>B</SB>to be applied to a fully differential input operational amplifier 1 provided in an integrator circuit of the IC section of the counter, is activated by applying a start-up voltage from a start-up circuit 31 in a bias-on state. A logic circuit in the IC section generates and outputs a stop command to the start-up circuit 31 based on a count value (after five counts e.g.) of a clock signal from an oscillation circuit, as a timing at which generation of the bias voltage V<SB>B</SB>after power-on stabilizes, to stop application (operation) by the start-up circuit 31 of the start-up voltage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a coulomb counter and an internal power supply control method thereof.

For example, as disclosed in Patent Document 1, in a mobile device field using a secondary battery such as a notebook personal computer (PC), a mobile phone, or a game machine, the battery of the secondary battery being used for those mobile devices Battery remaining detection devices are widely used to detect the remaining amount. The battery remaining detection device is also called a coulomb counter, converts charge / discharge current flowing through a detection resistor (sense resistor) into a voltage, and grasps the battery remaining amount of the secondary battery based on the converted voltage value.
JP 2006-184035 A

  By the way, in the battery residual detection apparatus disclosed in Patent Document 1, since the number of pulses inversely proportional to the current charged / discharged from the battery is output, an inversion block for inverting the number of pulses is necessary at the final stage. As a result, a count value proportional to the current is output (see, for example, paragraphs [0023] to [0025]). As described above, the conventional example requires a reverse block in order to calculate the remaining battery level, and there is a problem that the circuit scale increases at least by that amount.

In addition, the operational amplifier included in the coulomb counter and the output of the comparator usually include an offset. For this reason, the offset (error) may occur in the count value output from the coulomb counter due to the offset.
Furthermore, no consideration is given to the reduction in current consumption after power-on.
Therefore, the present invention has been made in view of such circumstances, and can reduce the circuit scale, sufficiently reduce current consumption after power-on, and output a count value with less error. An object of the present invention is to provide a coulomb counter and a method for controlling its internal power supply.

[Invention 1] In order to solve the above-described problem, the coulomb counter of Invention 1 includes:
A coulomb counter (for example, the coulomb counter 100 in FIG. 1) that outputs a count value proportional to the input voltage with a potential difference generated between both ends of a detection resistor (for example, the sense resistor Rs in FIG. 1) as an input voltage,
Switch element (eg, switches A1, A2, B1, B2, C1, C2, D1, D2, S1, S2, R1, R2, I1, I2 in FIG. 3), a first capacitor (eg, sampling capacitance in FIG. 3) Cs1, Cs2), a second capacitor (for example, integration capacitors Ci1, Ci2 in FIG. 3), a fully differential input operational amplifier (for example, fully differential input operational amplifier 1 in FIG. 3), and the switch element is operated. Thus, the input voltage is sampled by the first capacitor, and a voltage value obtained by integrating the voltage proportional to the sampled input voltage by the second capacitor is amplified by the fully differential input operational amplifier. Switched capacitor type integration circuit that outputs as output voltage,
The output voltage output from the integrating circuit is compared with a reference value, and if the output voltage is greater than or equal to the reference value, a first signal is output, and if the output voltage is less than the reference value, the second signal is output. A comparison circuit (for example, the comparator 5 in FIG. 3) that outputs the following signal:
A count circuit (for example, the internal counter 11 in FIG. 8) that counts the first signal and the second signal output from the comparison circuit for a predetermined time and outputs the difference as the count value;
A storage circuit (for example, the register 20 in FIG. 8) that holds an offset value included in the count value,
The fully differential input operational amplifier includes a bias circuit (for example, the bias circuit 32 in FIG. 4 or FIG. 5) that generates a driving bias voltage (for example, the bias voltage V _{B in} FIG. 4 or FIG. 5), A startup circuit for starting up the bias circuit (for example, the startup circuit 31 in FIG. 4 or FIG. 5), and the startup circuit is stopped after being started by applying a startup voltage to the bias circuit. It is a feature.

According to such a configuration, the start-up circuit is stopped after the bias circuit is started to sufficiently reduce the current consumption after the power is turned on, and the detection resistor flows from the count value output from the count circuit. The amount of current can be grasped. Therefore, for example, when one end of the detection resistor is connected to the secondary battery, the amount of charge / discharge current flowing through the detection resistor can be determined from the count value. Further, the number of outputs of the first and second signals (that is, the number of pulses) output from the comparison circuit is a number that is proportional to the potential difference (that is, the input voltage) that occurs at both ends of the detection resistor, It is a number proportional to. Therefore, the inversion block is unnecessary and the circuit scale can be reduced.
Further, since the offset value is held by the memory circuit, the offset value can be corrected for the count value output from the comparison circuit, and the count value not including the offset value can be output.

[Invention 2] The Coulomb counter of Invention 2 is
The start-up circuit (for example, the start-up circuit 31 in FIG. 4 or FIG. 5) is characterized in that the operation is stopped after a predetermined time has elapsed after the power is turned on by a stop command given from the outside.
According to such a configuration, the startup circuit can stably start the bias circuit after the power is turned on, and then can shift to the operation stop, so that the current consumption can be reduced without affecting the amplification operation of the fully differential input operational amplifier. Figured.

[Invention 3] The coulomb counter of Invention 3 is
A logic circuit (for example, the logic circuit 10 in FIG. 3) including the count circuit and the memory circuit, and an oscillation circuit for generating a clock signal (for example, CLOCK in FIG. 3) instructing timing of operation processing by the logic circuit; With
The logic circuit generates and outputs the stop command for the startup circuit (for example, the startup circuit 31 in FIG. 4) based on the count value of the clock signal.
According to such a configuration, the current consumption can be effectively reduced only by the components of the coulomb counter.

[Invention 4] The Coulomb counter of Invention 4 is:
A logic circuit (for example, logic circuit 10 in FIG. 3) including the count circuit and the memory circuit;
The logic circuit responds to a feedback signal of a bias voltage (for example, the bias voltage V _{B in} FIG. 5) after activation of the bias circuit (for example, the bias circuit 32 in FIG. 5). The stop command for the start-up circuit 31) is generated and output.
Even with such a configuration, the current consumption can be effectively reduced only by the components of the coulomb counter, as in the case of the third invention.

[Invention 5] The Coulomb counter of Invention 5 is:
The logic circuit (for example, the logic circuit 10 in FIG. 3) generates and outputs an offset measurement command for measuring the offset value in the coulomb counter and outputs the stop command before measuring the offset value after power-on. The data is sent to the startup circuit (for example, the startup circuit 31 in FIG. 4 or FIG. 5) (for example, the relationship between the startup circuit and offset measurement in FIG. 6).
According to such a configuration, since the startup circuit stably starts the bias circuit before the offset value is measured after the power is turned on, the operation is stopped. Therefore, the offset is accurately and accurately achieved with low current consumption. The value can be measured.

[Invention 6] The coulomb counter of Invention 6 is
The logic circuit (for example, the logic circuit 10 in FIG. 3) generates and outputs an offset measurement command for measuring the offset value in the coulomb counter, and outputs the stop command after measuring the offset value after power-on. It is characterized by being sent to a start-up circuit (for example, the start-up circuit 31 in FIG. 4 or FIG. 5) (for example, the relationship between the start-up circuit and offset measurement in FIG. 7).
According to such a configuration, if the startup circuit is stopped when measuring the offset value after the power is turned on, the bias voltage applied from the bias circuit to the fully differential input operational amplifier fluctuates. Can be prevented from becoming unstable, and the offset value can be accurately and accurately measured after stopping the startup circuit after measuring the offset value and reducing the current consumption without adversely affecting the offset value measurement. Can be measured.

[Invention 7] The internal power control method for the coulomb counter of Invention 7 is as follows:
A coulomb counter that outputs a count value proportional to the input voltage with a potential difference generated between both ends of the detection resistor as an input voltage, and samples the input voltage with a first capacitor and is proportional to the sampled input voltage The bias voltage is generated when a starting voltage is applied to generate a driving bias voltage applied to a fully differential input operational amplifier that amplifies a voltage value obtained by integrating the voltage to be output by a second capacitor and outputs the amplified voltage value as an output voltage. The application of the starting voltage is stopped later.
According to such a method, since the starting voltage is not used after the generation of the driving bias voltage is stabilized, the current consumption can be sufficiently reduced after the power is turned on.

[Invention 8] The internal power control method for the coulomb counter of Invention 8 is as follows:
The application of the starting voltage is stopped before or after the offset measurement in the coulomb counter.
According to such a method, since the timing of applying and stopping the start-up voltage is set before or after the offset measurement so as not to adversely affect the measurement of the offset value, the offset value can be accurately measured. Become.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
(Embodiment)
FIG. 1 is a conceptual diagram showing a relationship between a coulomb counter 100 according to an embodiment of the present invention and a system S to which the coulomb counter 100 is applied. In FIG. 1, a system S to which the coulomb counter 100 is applied is, for example, an electronic device such as a notebook computer, a mobile phone, or a game machine. In such a system S, for example, a rechargeable secondary battery such as a lithium ion battery is detachably mounted.

  As shown in FIG. 1, a coulomb counter 100 includes a detection resistor (hereinafter referred to as a sense resistor) Rs and an IC unit 50 that outputs a count value proportional to the input voltage using a potential difference generated between both ends of the sense resistor Rs as an input voltage. Is provided. Among these, the sense resistor Rs is a resistance element for detecting a current flowing into or out of the secondary battery (that is, a charge / discharge current), and one end thereof is, for example, a secondary battery on the system S side. The other end is connected to a ground potential, for example.

Further, the IC section 50 is provided with two input terminals Vin ⁺ and Vin ⁻ , and these input terminals Vin ⁺ and Vin ⁻ are respectively connected to both ends of the sense resistor Rs. When a charging / discharging current flows through the sense resistor Rs, a potential difference (that is, an input voltage) is generated between the input terminals Vin ⁺ and Vin ⁻ according to the direction and magnitude of the current. In other words, the charge / discharge current is converted into the input voltage by the sense resistor Rs. Then, for example, a 13-bit count value is output from the IC unit 50 in proportion to the input voltage.

FIG. 2 is a diagram illustrating the relationship between the input voltage and the count value. In FIG. 2, the vertical axis represents the input voltage to the IC unit 50, and the horizontal axis represents the 13-bit count value output from the IC unit 50. As shown by the straight line a in FIG. 2, the input voltage and the count value are in a proportional relationship, for example, increasing to the right. Here, the input voltage is set to, for example, a maximum value of 50 mV and a minimum value of −50 mV by the reference voltage VREF of the reference voltage generation circuit, and the count value when the input voltage takes the maximum value is 8192 (= 2 ^13). ) And the count value when taking the minimum value is set to -8192. A positive input voltage indicates that, for example, discharge current is flowing through the sense resistor Rs, and a negative input voltage indicates that, for example, a charging current is flowing through the sense resistor Rs. As described above, when a charging / discharging current flows through the sense resistor Rs illustrated in FIG. 1, a count value of −8192 to +8192 is output from the IC unit 50.

  Here, the value of the input voltage can be set within a certain range by, for example, the reference voltage VREF of the reference voltage generation circuit. For example, by adjusting the resistance value of the sense resistor Rs, the charge / discharge current can be set within a certain range in which the value can be measured. As will be described later, the IC unit 50 included in the coulomb counter 100 includes a fully differential input operational amplifier 1 and a comparator 5, and these outputs usually include an offset. Here, the offset is a voltage that is slightly output although the input signal is 0V. For this reason, as indicated by the broken line characteristic b with respect to the solid line characteristic a in FIG. 2, there is a possibility that a deviation occurs in the internal count value output from the IC unit 50 due to the offset. Hereinafter, the deviation of the internal count value is also referred to as an offset value. The offset value varies depending on semiconductor chip manufacturing variations, temperature, and the like.

Next, the configuration of the IC unit 50 will be described.
FIG. 3 is a block diagram illustrating a circuit configuration of the IC unit 50. As shown in FIG. 3, the IC unit 50 included in the coulomb counter 100 includes, for example, switches A1, A2, B1, B2, C1, C2, D1, D2, S1, S2, R1, R2, I1, I2, Sampling capacitors Cs1 and Cs2 as one capacitor, integration capacitors Ci1 and Ci2 as second capacitors, a fully differential input operational amplifier 1, a reference voltage generating circuit 3 for generating a reference voltage VREF, and a comparison circuit A comparator 5 and a logic circuit 10 are provided.
Among these, switches A1, A2, B1, B2, C1, C2, D1, D2, S1, S2, R1, R2, I1, I2, sampling capacitors Cs1, Cs2, integration capacitors Ci1, Ci2, and fully differential The input operational amplifier 1 forms a switched capacitor type integration circuit. The reference voltage VREF from the reference voltage generation circuit 3 is applied to the integration circuit.

Next, the connection relationship between these units will be described. As shown in FIG. 3, the input side of the sampling capacitor Cs1 (i.e., the left side in the drawing) electrodes is connected to the input terminal Vin ⁺ via the switches A1, an input terminal Vin through the switch B1 ^- is connected to the ing. The input-side electrode is connected to the X terminal of the reference voltage generating circuit 3 through the switch C1 and is connected to the Y terminal of the reference voltage generating circuit 3 through the switch D1. Further, the output side (that is, the right side in the drawing) electrode of the sampling capacitor Cs1 is connected to the positive (+) input terminal of the fully differential input operational amplifier 1, and a common voltage (hereinafter, referred to as a reference value) via the switch S1. , Called VCM). The VCM is 1V, for example.

Input electrode of the sampling capacitor Cs2 is input terminal Vin through the switch A2 ^- is connected to, and is connected to the input through the switch B2 terminals Vin ^+. The input side electrode is connected to the X terminal of the reference voltage generating circuit 3 via the switch D2, and is connected to the Y terminal of the reference voltage generating circuit 3 via the switch C2. The output-side electrode of the sampling capacitor Cs2 is connected to the negative (−) input terminal of the fully-differential input operational amplifier 1, and is connected to the VCM via the switch S2.

These switches A1, A2, B1, B2, C1, C2, D1, D2, S1, S2, R1, R2, I1, and I2 are composed of, for example, MOS field effect transistors, and the on / off of the logic circuit 10 This is performed by a control signal output from.
The integration capacitor Ci1 has an input side electrode connected to the positive input terminal of the fully differential input operational amplifier 1, and an output side electrode connected to the negative output terminal of the fully differential input operational amplifier 1 via the switch I1. Yes. The integration capacitor Ci2 has an input side electrode connected to the negative input terminal of the fully differential input operational amplifier 1, and an output side electrode connected to the positive output terminal of the fully differential input operational amplifier 1 via the switch I2. Yes. Further, discharge switches R1 and R2 are connected to both ends of the integration capacitors Ci1 and Ci2, respectively.

Negative output terminal and positive output terminal of the full differential input operational amplifier 1 is connected to the comparator 5, respectively, the potential Vout of the negative output terminal side ^- is input to the input terminal of the comparator 5 an In +, the positive output terminal side potential Vout ⁺ Is input to the input terminal In− of the comparator 5. Further, the comparator 5 is connected to the logic circuit 10, and the signal Q as the first signal output from the output terminal Q of the comparator 5 and the signal QB as the second signal output from the output terminal QB of the comparator 5. Are respectively input to the logic circuit 10. Although not shown, the oscillation circuit is also connected to the logic circuit 10, and a clock (CLOCK) signal generated by the oscillation circuit is input to the logic circuit 10. Incidentally, the components other than the logic circuit 10 in the IC unit 50 perform A / D (analog / digital) conversion in signal processing, as will be described later, and can be regarded as an A / D conversion circuit. .

  That is, the reference voltage generation circuit 3 is not directly connected to the integration circuit, and a selector is interposed between the reference voltage generation circuit 3 and the switches C1 and D2 and the switches C2 and D1. The reference voltage VREF from the reference voltage generation circuit 3 is switched according to the states of the signals Q and QB and applied to the X terminal and the Y terminal. Therefore, the reference voltage VREF from the reference voltage generating circuit 3 is intermittently applied to the integrating circuit. Further, the voltage output from the fully differential input operational amplifier 1 is output symmetrically about the VCM. The comparator 5 outputs the signal Q when the negative output of the fully-differential input operational amplifier 1 is larger than the positive output, and outputs the signal QB in the opposite case.

By the way, the fully differential input operational amplifier 1 includes a bias circuit that generates a driving bias voltage and a startup circuit (also called a kick circuit) that starts the bias circuit. The bias circuit is indispensable for basic operation in order to apply a bias voltage for driving the fully-differential input operational amplifier 1. However, the startup circuit that applies the starting voltage for starting the bias circuit is necessary in the initial operation time until the bias circuit operates stably after the power is turned on. Since the operation is continued by applying the power supply voltage, the current consumption here is about 5 μA, which is about 10% of the entire IC unit 50, and is wasted.
Therefore, in this embodiment, waste of current consumption in the startup circuit attached to the bias circuit in the fully-differential input operational amplifier 1 is improved, and the startup circuit is stopped after the bias circuit is stably operated. .

FIG. 4 is a block diagram illustrating an example of a bias circuit 32 having a startup circuit 31 provided in the fully differential input operational amplifier 1.
Here, the start-up circuit 31 applies a start-up voltage to the bias circuit 32 in the bias-on state, and the bias circuit 32 raised by the start-up voltage generates a bias voltage V _B for driving the fully-differential input operational amplifier 1. The state of output is shown. In order to stop the start-up circuit 31 after the bias circuit 32 has stably operated, for example, the start-up circuit 31 may be controlled to be stopped after a predetermined time has elapsed after power-on by a stop command given from the outside. If such control is performed, the startup circuit 31 can stably start the bias circuit 32 after the power is turned on, and after that, the operation is stopped and the current consumption is reduced without affecting the amplification operation of the fully differential input operational amplifier 1. Can be achieved.

  More specifically, the coulomb counter 100 is provided with an oscillation circuit that generates a clock signal CLOCK instructing the timing of operation processing by the logic circuit 10. Generates and outputs a stop command to the startup circuit 31 based on the count value (for example, after 5 counts) of the clock signal CLOCK from the logic circuit 10 (for example, if the bias-on signal in the bias-on state is H, this is set to L to start-up The case of sending to the circuit 31 can be exemplified). With this configuration, it is possible to effectively reduce the current consumption only with the components of the coulomb counter 100.

FIG. 5 is a block diagram showing another example of a bias circuit 32 having a startup circuit 31 provided in the fully differential input operational amplifier 1.
Also in this case, the start-up circuit 31 applies a start-up voltage to the bias circuit 32 in the bias-on state, and the bias circuit 32 raised by the start-up voltage generates a bias voltage V _B for driving the fully-differential input operational amplifier 1. The output is shown, and the same control as in the case described with reference to FIG. 4 is performed.

However, here, the logic circuit 10 generates and outputs a stop command for the start-up circuit 31 according to the feedback signal (feedback) of the bias voltage V _B after the start of the bias circuit 32 (the bias-on signal in the bias-on state is also H here) If this is the case, this can be exemplified as a case where L is sent to the startup circuit 31 from the logic circuit 10). Also with this configuration, the current consumption can be effectively reduced only with the components of the coulomb counter as in the case of the third aspect of the invention.

The start-up circuit 31 is stopped after the bias circuit 32 after the power is turned on stably by the logic control by the clock count explained in FIG. 4 or the logic control by the bias feedback explained in FIG. The current consumption for about 5 μA is reduced. Since a well-known technique can be applied to the configuration of the bias circuit 32, it will not be described in detail here. For example, a bias voltage V _B that can generate and output a bias voltage V _B in a range from slightly higher than 2V to slightly lower than 1V is combined, for example. If it is good.

By the way, the logic circuit 10 has a function of measuring the offset value in the coulomb counter 100 (the offset value measurement itself will be described in detail later). For this purpose, the logic circuit 10 generates and outputs an offset measurement command. However, if the startup circuit 31 is stopped during the measurement of the offset value after the power is turned on, the bias voltage V _B applied from the bias circuit 32 to the fully differential input operational amplifier 1 fluctuates, and thus the amplification operation is performed. It becomes unstable.
Therefore, when the operation of the start-up circuit 31 is stopped, it is necessary to consider the timing that avoids such a problem and does not adversely affect the measurement of the offset value.

FIG. 6 is a timing chart showing the processing operation when the operation of the startup circuit 31 is stopped before the offset value is measured by the logic circuit 10.
Here, after the power is turned on, the startup circuit 31 and the bias circuit 32 are sequentially started up, and after the startup circuit 31 is shut down and stopped operating, the offset measurement is performed by the startup and ends by the shutdown. ing.

When such a sequence is executed by the logic control in the logic circuit 10, the logic circuit 10 sends a stop command to the startup circuit 31 before measuring the offset value after power-on, stops the operation of the startup circuit 31, and then the IC unit. What is necessary is just to send the offset measurement command which performs the measurement of an offset value to 50 A / D conversion parts.
According to such a configuration, since the startup circuit 31 stably starts the bias circuit 32 before the offset value is measured after the power is turned on, the operation is stopped. The offset value can be measured well.

FIG. 7 is a timing chart showing a processing operation when the operation of the startup circuit 31 is stopped after the offset value is measured by the logic circuit 10.
Here, the start-up circuit 31 and the bias circuit 32 are sequentially started up after the power is turned on, and after the offset measurement is performed by the start-up and finished by the turn-off, the start-up circuit 31 is turned off and the operation is stopped. ing.
When such a sequence is executed by the logic control in the logic circuit 10,
The logic circuit 10 sends an offset measurement command for measuring an offset value after power-on to the A / D converter of the IC unit 50, and then sends a stop command to the startup circuit 31 after measuring the offset value. It ’s fine.

According to such a configuration, without adversely affecting the measurement of the offset value, after the offset value is measured, the operation of the startup circuit 31 is stopped to reduce the current consumption, and the offset value can be measured accurately and accurately. It can be carried out.
In any case, the logic control function by the start-up circuit 31 of this embodiment and the related logic circuit 10 is characterized by stopping the operation of the start-up circuit 31 after the stable operation of the bias circuit 32 and reducing the current consumption. .

  FIG. 8 is a block diagram illustrating a circuit configuration of the logic circuit 10 provided in the IC unit 50. As shown in FIG. 8, the logic circuit 10 includes an internal counter 11 as a count circuit, a frequency divider 13, an update pulse generator 15, a CMR (Current Measurement Resistor) 17, an arithmetic circuit 18, and an ACR. (Accumulated Current Resistor) 19 and a register 20 as a storage circuit for holding an offset value. The CMR 17 and the ACR 19 are registers each composed of a plurality of flip-flops, for example. The register 20 is also composed of a plurality of flip-flops.

  As shown in FIG. 8, the internal counter 11 has a CLOCK signal generated by an oscillation circuit (not shown) and the CLOCK signal divided by, for example, two by the frequency divider 13 (that is, the pulse width is adjusted to double). A) a divided signal ClkDiv1, a register update pulse (hereinafter referred to as an update pulse) generated by an update pulse generator based on the CLOCK signal, and signals Q and QB output from the comparator 5 (see FIG. 3). It is designed to be entered.

Further, the internal counter 11 has at least three or more output terminals, the first terminal is connected to the CMR 17, the second terminal is connected to the ACR 19 through the arithmetic circuit 18, and the third terminal is a register 20 is connected. Here, the CMR 17 holds the internal count value output from the internal counter 11 when the update pulse is input as “count value per one conversion time”, and outputs the held value. ing. The arithmetic circuit 18 performs predetermined arithmetic processing on the internal count value output from the internal counter 11 when the update pulse is input, and outputs the arithmetic value. The ACR 19 accumulates the calculated values sequentially to hold a “count value per unit time” and output the held value. The “count value per conversion time” and “count value per unit time” are both data indicating the charge / discharge state of the secondary battery.
The register 20 holds, for example, an offset value (per conversion time) and outputs the held offset value. This offset value is used for offset correction of the “count value per conversion time” output from the CMR 17 and the “count value per unit time” output from the ACR 19.

Next, an operation example of the coulomb counter 100 will be described.
FIG. 9 is a timing chart showing an operation example of a switch included in the IC unit 50 of the coulomb counter 100. In FIG. 9, “CLKR” indicates the clock operation of the switches R1 and R2 illustrated in FIG. 3, “CLKA” indicates the clock operation of the switches A1 and A2, and “CLKB” indicates the clock operation of the switches B1 and B2. , “CLKC” indicates the clock operation of the switches C1 and C2, “CLKD” indicates the clock operation of the switches D1 and D2, “CLKS” indicates the clock operation of the switches S1 and S2, and “CLKI” indicates the switch S1, The clock operation of S2 is shown. “EN” indicates an output control signal (Enable) input to the comparator 5.

First, at Timing (timing) 1 in FIG. 9, the switches R1 and R2 are turned on, and the charges of the integration capacitors Ci1 and Ci2 are discharged. As a result, the accumulated charges of the integration capacitors Ci1 and Ci2 become 0 (zero). This discharge operation is performed only before the start of the counting operation by the coulomb counter, that is, at the time of resetting.
Next, in Timing 2, the switches A1, A2, S1, and S2 are turned on, and all other switches are turned off. Thereby, an input voltage sampling operation is performed. Here, the potential of the input terminal Vin ⁺ (hereinafter simply referred to as Vin ⁺ ) is applied to the input side electrode of the sampling capacitor Cs1, and VCM is applied to the output side electrode. Further, the potential of the input terminal Vin ⁻ (hereinafter simply referred to as “Vin ^−” ) is applied to the input side electrode of the sampling capacitor Cs2, and VCM is applied to the output side electrode thereof. As a result, charges corresponding to (VCM−Vin ⁺ ) are accumulated in the sampling capacitor Cs1, and charges corresponding to (VCM−Vin ⁻ ) are accumulated in the sampling capacitor Cs2. Further, VCM is input to each of the positive input terminal and the negative input terminal of the fully differential input operational amplifier 1, and the negative output terminal and the positive output terminal are electrically separated from the integration capacitors Ci1 and Ci2. As a result, the negative output terminal side potential Vout ^- and, the potential of the positive output terminal side Vout ⁺ are both the VCM.

Next, in Timing 3, the switches B1, B2, I1, and I2 are turned on, and all other switches are turned off. Thereby, the integration operation of the input voltage is performed. Here, Vin ⁻ is applied to the input side electrode of the sampling capacitor Cs1. Further, the output side electrode of the sampling capacitor Cs1 is electrically disconnected from the VCM. As a result, the output side electrode of the sampling capacitor Cs1 becomes VCM + (Vin ⁻ −Vin ⁺ ), and the electric charge moves between the sampling capacitor Cs1 and the integration capacitor Ci1 in accordance with the change in potential, and the input side of the integration capacitor Ci1 the electrode ^- caused a voltage V1 proportional to ^(Vin + -Vin). That is, the voltage V1 proportional to the input voltage is transferred to the integration capacitor Ci1.

At the same time, Vin ⁺ is applied to the input side electrode of the sampling capacitor Cs2, and the output side electrode of the sampling capacitor Cs2 is electrically disconnected from the VCM. As a result, the sampling capacitor output side electrode of Cs2 is VCM ⁺ (Vin ⁺ -Vin ^-), and the charge between the sampling capacitor Cs2 and the integration capacitor Ci2 is moved according to the change of the potential, the input side of the integrating capacitor Ci2 A voltage −V1 proportional to (Vin ⁻ −Vin ⁺ ) is generated at the electrode. That is, the voltage −V1 is transferred to the integration capacitor Ci2.
Such integration operation, the voltage V1 appear at the negative output terminal side of the fully differential input operational amplifier 1, the potential Vout ^- is "VCM + V1". At the same time, −V1 appears on the positive output terminal side of the fully-differential input operational amplifier 1, and the potential Vout ⁺ becomes “VCM−V1”.

Next, at Timing 4, the switches C1, C2, S1, and S2 are turned on, and all other switches are turned off. Thereby, the sampling operation of the reference voltage VREF is performed. The reference voltage VREF is output from the above-described reference voltage generation circuit 3 and indicates a potential difference between the terminals X and Y in operation. Here, the potential of the X terminal (hereinafter simply referred to as potential X) of the reference voltage generating circuit 3 is applied to the sampling capacitor Cs1, and the potential of the Y terminal (hereinafter simply referred to as potential Y) of the reference voltage generating circuit 3 is applied. Applied to the sampling capacitor Cs2. Further, VCM is input to the positive input terminal and the negative input terminal of the fully differential input operational amplifier 1, and the output side thereof is electrically separated from the integration capacitors Ci1 and Ci2. Thus, the negative output terminal side potential Vout ^- and, the potential of the positive output terminal side Vout ⁺ are both the VCM.

  Next, in Timing 5, the switches D1, D2, I1, and I2 are turned on, and all other switches are turned off. Thereby, the integration operation of the reference voltage VREF is performed. Here, the potential Y is applied to the input side electrode of the sampling capacitor Cs1. Further, the output side electrode of the sampling capacitor Cs1 is electrically separated from the VCM. As a result, the output side electrode of the sampling capacitor Cs1 becomes VCM + (Y−X), and the electric charge moves between the sampling capacitor Cs1 and the integration capacitor Ci1 in accordance with the change in potential, and the input side electrode of the integration capacitor Ci1 is transferred. Produces a voltage V2 proportional to the reference voltages VREFP and VREFN (XY). This voltage V2 is transferred to the integration capacitor Ci1.

At the same time, the potential X is applied to the input side electrode of the sampling capacitor Cs2. The output side electrode of the sampling capacitor Cs2 is electrically separated from the VCM. As a result, the output side electrode of the sampling capacitor Cs2 becomes VCM + (XY), and the electric charge moves between the sampling capacitor Cs2 and the integration capacitor Ci2 in accordance with the change in potential, and the input side electrode of the integration capacitor Ci2 Produces a voltage -V2 proportional to (Y-X). This voltage -V2 is transferred to the integration capacitor Ci2.
Such integration operation, appears voltage V2 to the negative output terminal side of the fully differential input operational amplifier 1, the potential Vout ^- is "VCM + V1 + V2". At the same time, -V2 appears on the positive output terminal side of the fully differential input operational amplifier 1, and the potential Vout ⁺ becomes "VCM-V1-V2". Thereafter, the operations of Timing 2 to 4 are repeated to convert the input voltage into signals Q and QB.

FIG. 10 is a diagram for explaining a method of converting an input voltage into signals Q and QB. Here, Vin ⁺ shown in FIG. 3 is 10 mV and Vin ⁻ is 0 mV for more specific explanation. The reference voltage generation circuit 3 has a function of switching the potential difference between the terminal X and the terminal Y to, for example, 51.2 mV or −51.2 mV when the reference voltage VREF = 51.2 mV. As an example of the function of the generation circuit 3, the potential of the terminal X indicating the potential difference of the reference voltage VREF can be switched to 50 mV or −50 mV, and the potential of the terminal Y is fixed to 0 mV. In FIG. 10, “CLOCK”, “CLKR”, “CLKI”, and “EN” are not shown, but the clock operations at Timings 2 to 5 are the same as those in FIG.

As shown in FIG. 10, first, a reset (i.e., Timing1) In the first Timing2 after, since the sampling operation of the input voltage is carried out, Vout ^- is a VCM. Next, at Timing3, the output side electrode of the sampling capacitor Cs1 becomes VCM-10 mV, and the charge moves between the sampling capacitor Cs1 and the integration capacitor Ci1 in accordance with the change of -10 mV, and the input side electrode of the integration capacitor Ci1 Produces a voltage “10” proportional to the input voltage of 10 mV. Thus, Vout ^- rose "10" from the VCM, the VCM + 10.

At this time, comparator 5, Vout ^- outputs a signal Q to validate that it is ≧ VCM, feeds back the output signal Q to a reference voltage generating circuit 3. Thereby, in the reference voltage generating circuit 3, the potential of the terminal X is set to −50 mV.
Next, in Timing4, since the sampling operation of the reference voltage VREF is performed, Vout ^- is again VCM. In Timing 5, the output side electrode of the sampling capacitor Cs1 becomes VCM + 50 mV, and the electric charge moves between the sampling capacitor Cs1 and the integration capacitor Ci1 according to the change of 50 mV, and the reference voltage is applied to the input side electrode of the integration capacitor Ci1. A voltage “−50” proportional to −50 mV is generated. Thus, Vout ^- the VCM + 10 "-50" is being added together, the VCM-40.

Next, in the second round of Timing2, Vout ^- it is again VCM. In Timing 3, the output side electrode of the sampling capacitor Cs1 becomes VCM-10 mV, and a voltage “10” proportional to the input voltage 10 mV is generated in the input side electrode of the integration capacitor Ci1. As a result, Vout ⁻ rises by “10” from VCM-40 and becomes VCM-30. At this time, comparator 5, Vout - <with confirmation and outputs a signal QB that has a ^VCM, it feeds back the output signal QB to the reference voltage generating circuit 3. Thereby, in the reference voltage generating circuit 3, the potential of the terminal X is set to 50 mV. Next, in Timing4, since the sampling operation of the reference voltage VREF is performed, Vout ^- is again VCM. At Timing 5, the output side electrode of the sampling capacitor Cs1 becomes VCM-50 mV, and a voltage “50” proportional to the reference voltage 50 mV is generated at the input side electrode of the integration capacitor Ci1. Thus, Vout ^- the VCM-30 "50" has been added together, a VCM + 20.

In the following the same procedure, third, by repeating the fourth and Timing2～5, Vout when each time the Timing3 ^- the monitoring comparator 5. Then, Vout in the case of Timing3 ^- is, Vout ^- when ≧ VCM, has become both a signal Q from the comparator 5, sets the terminal X of the reference voltage generating circuit 3 to -50 mV. Also, Vout in the case of Timing3 ^- is, Vout ^- <VCM, when that is the, along with issues a signal QB from the comparator 5, sets the terminal X of the reference voltage generating circuit 3 to 50 mV. Thus, comparator 5, Vout in the case of each round of Timing3 ^- binarizing based on VCM, and outputs the digital signal Q, the QB. Then, the output signals Q and QB are counted (that is, integrated) for a predetermined time in the logic circuit 10, and the count value is output to the outside after offset correction.

FIG. 11 is a diagram illustrating a counting method of the signals Q and QB. In FIG. 11, one period of the frequency-divided signal ClkDiv1 is set to 102 μsec (≈0.8 sec / 8192, 8192 = 2 ¹³ ), for example. Further, one cycle of the update pulse is set to, for example, 0.8 sec (≈3600 sec / 4096, 4096 = 2 ¹² ), and the update pulse is output approximately 2 ¹² times per hour.

  In FIG. 11, when ClkDiv1 is LOW (low) and the CLOCK signal falls, the internal counter 11 counts +1 if the signal Q is input, and counts -1 if the signal QB is input. To do. At the input timing of the update pulse, the internal counter 11 outputs a value obtained by adding the signals Q and QB (hereinafter referred to as an internal count value) to both the CMR 17 and the ACR 19 and sets the internal count value to zero (0). Reset to. For example, in FIG. 11, 6726 is described as an example of the internal count value when the update pulse is input, but this internal count value (6726) is output to both the CMR 17 and the ACR 19 simultaneously.

Incidentally, when only the signal Q is input to the internal counter 11 between the input of the update pulse and the input of the next update pulse, the internal count value is 8192, for example. Conversely, when only the signal QB is input to the internal counter 11, the internal count value is, for example, -8192.
As described above, when the internal count value (6726) is simultaneously output to both the CMR 17 and the ACR 19, the CMR 17 holds the internal count value as “count value per one conversion time”. Here, the one-time conversion time is the time from when an update pulse is input until the next update pulse is input (that is, one cycle of the update pulse). The “count value per conversion time” held by the CMR 17 indicates the charge / discharge amount per conversion time as shown in FIG. 2, and this value is output to the outside after offset correction. Is done.

Further, the internal count value (6726) output to the ACR 19 is input to the ACR 19 after being processed by the arithmetic circuit 18. For example, the internal count value (6726) is divided by 4096 (= 2 ¹² ) by the arithmetic circuit, and a value (for example, integer 1) rounded down after the decimal point is input to the ACR 19. Each time an update pulse is input, the ACR 19 adds such an integer value and holds it as a “count value per unit time”. Here, the unit time is a time that can be arbitrarily set, for example, one conversion time × 4096 times (≈0.8 sec × 4096≈1 hour). The “count value per unit time” held by the ACR 19 indicates the charge / discharge amount per unit time as shown in FIG. 2, and this value is output to the outside after offset correction.

Fully differential with a configuration in which the startup circuit 31 is stopped before or after the offset measurement after the bias circuit 32 after the power is turned on stably after receiving the logic control by the clock count or the bias feedback. When the input operational amplifier 1 is used, current consumption can be reduced without affecting the offset measurement itself.
That is, the technical point of the coulomb counter 100 according to the present embodiment is that the start-up voltage is generated after the bias voltage V _B is generated when the start-up voltage is applied to generate the drive bias voltage V _B to be applied to the fully differential input operational amplifier 1. In other words, this is an internal power control method for the coulomb counter that stops the application of voltage. In addition, the timing to stop applying the start-up voltage is set before or after the offset measurement so as not to adversely affect the measurement of the offset value. The offset value is often measured.

Next, a method for measuring the offset value of the coulomb counter 100 will be described.
FIG. 12 is a timing chart of operation processing signals shown for explaining an example of a method for measuring the offset value of the coulomb counter 100. In FIG. 12, “CLOCK”, “CLKR”, “CLKI”, and “EN” are not illustrated, but the clock operations at Timings 2 to 5 are the same as those in FIG. 9, for example. Further, in FIG. 12, Vout as an example a case where charges respectively from the previous measurement of the offset value of the integration capacitor Ci1, Ci2 are accumulated ^- shows.

As shown in FIG. 12, when the measurement of the offset value of the coulomb counter 100 is started, Timing 1 (that is, the discharging operation of the integration capacitors Ci1 and Ci2) is not performed and the measurement starts from Timing2. That is, the measurement of the offset value is started while holding the charges accumulated in the integration capacitors Ci1 and Ci2. As shown in FIG. 12, in Timing 2, the switches S1 and S2 are turned on, and the other switches A1, A2, B1, B2, C1, C2, D1, and D2 are turned off. Thereby, the input side electrodes of the sampling capacitors Cs1 and Cs2 are electrically separated from Vin ⁺ and Vin ⁻ , respectively. At this time, the potential Vout of the negative output terminal side of the fully differential input operational amplifier 1 ^- a, the potential of the positive output terminal side Vout ⁺ will be respectively VCM.

Next, at Timing 3, the switches A1, A2, B1, B2, C1, C2, D1, D2, S1, and S2 are turned off. Thereby, the input side electrodes of the sampling capacitors Cs1 and Cs2 are maintained in a state of being electrically separated from Vin ⁺ and Vin ⁻ , respectively, and no potential change occurs in these input side electrodes. That is, the input voltage at the time of offset measurement is set to 0 mV. As a result, the input voltage 0 mV is integrated into the integration capacitors Ci1 and Ci2. Here, since the charge each are accumulated from previous measurements of the offset value of the integration capacitor Ci1, Ci2, Vout ^- is the VCM larger or smaller. For example, Vout ^- is the VCM-20. The comparator 5, Vout ^- <with confirmation and outputs a signal QB that has a VCM, feeds back the output signal QB to the reference voltage generating circuit 3. Thereby, in the reference voltage generating circuit 3, the potential of the terminal X is set to 50 mV.

Next, at Timing 4, the switches C1, C2, S1, and S2 are turned on, and the switches A1, A2, B1, B2, D1, and D2 are turned off. Thus, the sampling operation of the reference voltage VREF is made, Vout ^- is again VCM. In Timing 5, the switches D1 and D2 are turned on, and the switches A1, A2, B1, B2, C1, C2, S1, and S2 are turned off. As a result, the output side electrode of the sampling capacitor Cs1 becomes VCM-50 mV, and a voltage “50” proportional to the reference voltage 50 mV is generated at the input side electrode of the integration capacitor Ci1. As a result, Vout ^- the VCM-20 "50" has been added together, a VCM + 30.

Next, at the second Timing 2, the input electrodes of the sampling capacitors Cs1 and Cs2 are electrically separated from Vin ⁺ and Vin ⁻ , respectively, and Vout ⁻ and Vout ⁺ become VCM again. Next, in Timing 3, since the input electrodes of the sampling capacitors Cs1 and Cs2 are electrically separated from Vin ⁺ and Vin ⁻ , the input voltage 0 mV is integrated into the integration capacitors Ci1 and Ci2, respectively. As a result, Vout ^- is, for example, VCM + 30. The comparator 5, Vout ^- outputs a signal Q to validate that it is ≧ VCM, feeds back the output signal Q to a reference voltage generating circuit 3. Thereby, in the reference voltage generating circuit 3, the potential of the terminal X is set to −50 mV.

Next, in Timing4, since the sampling operation of the reference voltage VREF is performed, Vout ^- is again VCM. At Timing 5, the output side electrode of the sampling capacitor Cs1 becomes VCM + 50 mV, and a voltage “−50” proportional to the reference voltage −50 mV is generated at the input side electrode of the integration capacitor Ci1. Thus, Vout ^- the VCM + 30 "-50" is being added together, the VCM-20.

Thereafter, in the same procedure, for example, Timing 2 to 5 are repeated from the third time, the fourth time to the 8192th time. The count values of the signal Q (+1) and the signal QB (−1) obtained by repeating up to 8192 times are offset values per conversion time. Here, when the offsets of the fully-differential input operational amplifier 1 and the comparator 5 are completely zero or close to zero, the signal Q and the signal QB are counted by 4096 respectively, and the offset value is 0 (= 4096−4096). Become. In addition, the offset value increases as the offset of the fully differential input operational amplifier 1 or the comparator 5 increases. Thus, the offset value measured by the internal counter 11 is output from the internal counter 11 and held in the register 20.
As described above, this offset value is used for offset correction between the “count value per conversion time” output from the CMR 17 and the “count value per unit time” output from the ACR 19.

  The offset correction method for the coulomb counter 100 will be described below. First, an offset correction method for the CMR 17 will be described. For example, when the “count value per one conversion time” output from the CMR 17 is 6726 and the offset value held in the register 20 is 10 at that time, the signal Q is 10 more than the signal QB due to the influence of the offset. Many have been counted. Accordingly, 10 is subtracted from “count value per conversion time” 6726 as offset correction. As a result, the “count value per conversion time” after the offset correction is 6716 (= 6726-10). Conversely, if the “count value per conversion time” output from the CMR 17 is 6726 and the offset value held in the register 20 at that time is −10, the signal Q is 10 less than the signal QB. Since it is counted, 10 is added to the count value. As a result, the “count value per conversion time” after the offset correction is 6736 (= 6726 + 10).

  Next, an offset correction method for the ACR 19 will be described. For example, when setting unit time = one conversion time (about 0.8 sec) × 4096 times, the offset value per unit time is obtained by dividing the offset value (per conversion time) by 4096, and A value obtained by integrating 4096 times. That is, “offset value per unit time” = “offset value per conversion time”. Therefore, for example, when the “count value per unit time” output from the ACR 19 is 6803 and the offset value held in the register 20 is 10 at that time, 10 is subtracted from the count value. As a result, the “count value per unit time” after offset correction is 6793 (= 6803-10). Conversely, if the “count value per unit time” output from the ACR 19 is 6803 and the offset value held in the register 20 at that time is −10, 10 is added to the count value. As a result, the “count value per unit time” after the offset correction is 6813 (= 6803 + 10).

Note that the offset value varies depending on semiconductor chip manufacturing variations, temperature, and the like. Therefore, for example, it is preferable to measure the offset value and store the value in the register 20 every conversion time × 1024 times (≈0.8 sec × 1024≈15 min). As a result, the latest offset value can be reflected in the “offset value per conversion time” and the “count value per unit time”.
As described above, according to the coulomb counter 100 of the embodiment of the present invention, unlike the conventional example disclosed in Patent Document 1, the number of outputs of the signals Q and QB output from the comparator 5 (that is, the number of pulses). Is a number proportional to the input voltage, and is a number proportional to the current flowing through the sense resistor Rs. For this reason, an inverting block is unnecessary, the circuit scale can be reduced, and a sufficiently low current consumption can be achieved after power-on.

  Further, in the conventional example disclosed in Patent Document 1, since both ends of the internal capacitor are shorted and discharged every conversion time, a slight battery charging / discharging current of 1 LSB (Least Significant Bit) or less is detected. I can't. On the other hand, in the embodiment of the present invention, both ends of the integrating capacitors Ci1 and Ci2 are short-circuited once when the operation of the IC unit 50 is started (that is, when Timing1 is set). It is not necessary to short-circuit both ends of the integration capacitors Ci1 and Ci2 for each conversion time. Accordingly, even if a charge / discharge current of 1 LSB or less flows during the counting operation, charges continue to accumulate little by little in the integration capacitors Ci1 and Ci2, and if they accumulate up to 1LSB, the count values of the signals Q and QB are obtained. Is output. For this reason, even a small current of 1 LSB or less can be detected.

Furthermore, according to the method for measuring the offset value of the coulomb counter 100 and the method for correcting the offset value, the start-up circuit is stopped after the bias circuit is activated with the existing function of the components of the coulomb counter. In order to reduce the current consumption, the offset value is accurately measured before or after the offset measurement so that the offset timing is not adversely affected. In addition to measuring the count value (that is, the offset value) when 0 is 0V, the offset value is held by the register 20, so that the offset value can be corrected for the count value output from the comparator 5, A count value not including an offset value can be output. That is, the count values output from the CMR 17 and the ACR 19 include offset values, but thereafter, the offset values are removed from these count values by offset correction. Therefore, a count value with little error can be output to the outside as a final count value.
In FIG. 12, the case where the switches A1, A2, B1, and B2 are turned off during the timings 2 to 5 and the offset value is measured has been described. However, the method for measuring the offset value is not limited to this. For example, the offset value may be measured by a switch operation as shown in FIG.

FIG. 13 is a timing chart of processing signals shown for explaining another example of the method for measuring the offset value of the coulomb counter 100. In FIG. 13, “CLOCK”, “CLKR”, “CLKI”, and “EN” are not shown, but the clock operations at Timings 2 to 5 are the same as those described with reference to FIG. Similarly to FIG. 12, also in FIG. 13, Vout as an example a case in which charges respectively are accumulated from previous measurements of the offset value of the integration capacitor Ci1, Ci2 ^- shows.

As shown in FIG. 13, the measurement of the offset value starts from Timing2. In Timing2, the switches A1, A2, S1, and S2 are turned on, and the other switches B1, B2, C1, C2, D1, and D2 are turned off. As a result, Vin ⁺ and Vin ⁻ are applied to the input side electrodes of the sampling capacitors Cs1 and Cs2, respectively, and VCM is applied to the output side electrodes. The potential Vout of the negative output terminal side of the fully differential input operational amplifier 1 ^- a, the potential of the positive output terminal side Vout ⁺ will be respectively VCM. As shown in FIG. 13, here, the switches A1 and A2 are turned from on to off in a short period (for example, 20 μsec) until the transition from Timing2 to Timing3.

Next, in Timing 3, the switches A1 and A2 are turned on again, and the switches B1, B2, C1, C2, D1, D2, S1, and S2 are turned off. At this time, Vin ⁺ and Vin ⁻ are applied to the input-side electrodes of the sampling capacitors Cs 1 and Cs ² , so that their potentials are the same as those at Timing 1. Therefore, the input voltage to be sampled is substantially 0 mV, and the input voltage 0 mV is integrated into the integration capacitors Ci1 and Ci2. In Figure 13, since it is assumed that charges each from the previous measurement of the offset value of the integration capacitor Ci1, Ci2 are accumulated, Vout ^- is the VCM-20, for example. The comparator 5, Vout ^- <with confirmation and outputs a signal QB that has a VCM, feeds back the output signal QB to the reference voltage generating circuit 3. Thereby, in the reference voltage generating circuit 3, the potential of the terminal X is set to 50 mV.

The switch operation of Timings 4 and 5 is the same as that described with reference to FIG. That is, in Timing4, since the sampling operation of the reference voltage VREF is performed, Vout ^- is again VCM. At Timing 5, the output side electrode of the sampling capacitor Cs1 becomes VCM-50 mV, and a voltage “50” proportional to the reference voltage 50 mV is generated at the input side electrode of the integration capacitor Ci1. Thus, Vout ^- the VCM-20 "50" has been added together, a VCM + 30.

Thereafter, in the same procedure, for example, Timing 2 to 5 are repeated from the second time, the third time to the 8192th time. As with the example described above, Vout in the case of Timing2 ^- is Vout ^- with outputs a signal Q when it is in a ≧ VCM, setting the potential of the terminal X to -50 mV. Also, Vout in the case of Timing2 ^- is Vout ^- <together outputs a signal QB When in the VCM, setting the potential of the terminal X to 50 mV. The count values of the signal Q (+1) and the signal QB (−1) obtained by repeating Timing 2 to 5 up to 8192 times are offset values per conversion time.
As described above, the switches A1 and A2 are continuously turned on twice at Timings 2 and 3 in FIG. 13, thereby generating an input voltage of 0 mV. Therefore, Vout in time of input voltages 0 mV ^- can output a signal of the time Q, the count value of QB can be measured as an offset value.

  The example of the offset value measuring method described with reference to FIG. 12 and the other example of the offset value measuring method described with reference to FIG. 13 are basically sampled by the sampling capacitors Cs1 and Cs2. This is the same in that the input voltage is 0 mV by making the applied voltage constant, without controlling the voltage on the system S side. However, one example has a significant advantage over the other examples. In one example, since the sense resistor Rs and the sampling capacitors Cs1 and Cs2 are electrically separated from each other, even if the potentials at both ends of the sense resistor Rs change during the sampling period, the sampling capacitors Cs1 and Cs2 There is no effect on the input side electrode.

  That is, in the other example, the current flowing through the sense resistor Rs changes in a short time between Timing 2 (turns on the first switches A1 and A2) and Timing 3 (turns on the second switches A1 and A2). Then, the input voltage changes from 0 mV. For this reason, when the change of the current flowing through the sense resistor Rs is large, there is a possibility that the offset value cannot be measured accurately. On the other hand, in the example, since the sense resistor Rs and the sampling capacitors Cs1 and Cs2 are electrically separated, the input voltage can be maintained at 0 mV regardless of the current change of the sense resistor Rs. it can. Therefore, the offset value can be measured more correctly.

  Note that the step of measuring the offset value according to another example of the method of measuring the offset value, the step of holding the measured offset value in the register 20, and the count value output from the comparator 5 according to the input voltage, Even when the offset value is corrected so as to include the step of reflecting the offset value held in the register 20, as in the case described in the above-described example, the bias is applied with the existing function of the constituent part of the coulomb counter. The startup circuit 31 is stopped after the circuit 32 is started to sufficiently reduce the current consumption after the power is turned on, and the timing of the operation stop before the offset measurement or the offset value measurement is not adversely affected. The offset value is measured accurately after the offset measurement, and Can be offset correction count value output from the regulator 5 can output the offset-corrected low count of errors.

The figure which shows the relationship between the coulomb counter 100 and system S which concern on embodiment of this invention. The figure which shows the relationship between an input voltage and a count value. It is the figure which illustrated the circuit structure of IC part 50 of the coulomb counter 100 shown in FIG. FIG. 4 is a block diagram showing an example of a bias circuit 32 having a startup circuit 31 provided in the fully differential input operational amplifier 1 shown in FIG. 3. FIG. 4 is a block diagram showing another example of a bias circuit 32 having a startup circuit 31 provided in the fully differential input operational amplifier 1 shown in FIG. 3. FIG. 4 is a timing chart showing a processing operation when the startup circuit 31 is stopped before the offset value is measured by the logic circuit 10 shown in FIG. 3. FIG. 4 is a timing chart showing a processing operation when the startup circuit 31 is stopped after the offset value is measured by the logic circuit 10 shown in FIG. 3. FIG. 4 is a block diagram illustrating a circuit configuration of a logic circuit 10 provided in the IC unit 50 illustrated in FIG. 3. 4 is a timing chart showing an example of the operation of a switch provided in the IC unit 50 shown in FIG. 3. It is the figure which showed the conversion method of the input voltage to the signals Q and QB. It is a figure which shows the counting method of signals Q and QB. 5 is a timing chart of operation processing signals shown to explain an example of a method for measuring an offset value of the coulomb counter 100. 6 is a timing chart of operation processing signals shown for explaining another example of a method of measuring the offset value of the coulomb counter 100.

Explanation of symbols

  1 fully differential input operational amplifier, 3 reference voltage generation circuit (VREF), 5 comparator, 10 logic circuit, 11 internal counter, 13 frequency divider, 15 update pulse generator, 17 CMR, 18 arithmetic circuit, 19 ACR, 20 register , 31 Start-up circuit, 32 Bias circuit, A1, A2, B1, B2, C1, C2, D1, D2, S1, S2, R1, R2, I1, I2 Switch, Cs1, Cs2 Sampling capacity, Ci1, Ci2 Integration capacity

Claims (8)

A coulomb counter that outputs a count value proportional to the input voltage with a potential difference generated between both ends of the detection resistor as an input voltage,
A switch element, a first capacitor, a second capacitor, and a fully differential input operational amplifier. When the switch element is operated, the input voltage is sampled by the first capacitor, and the sampled A switched-capacitor type integrating circuit that amplifies a voltage value obtained by integrating a voltage proportional to an input voltage by the second capacitor by the fully-differential input operational amplifier and outputs it as an output voltage;
The output voltage output from the integrating circuit is compared with a reference value, and if the output voltage is greater than or equal to the reference value, a first signal is output, and if the output voltage is less than the reference value, the second signal is output. A comparison circuit that outputs the signal of
A count circuit that counts the first signal and the second signal output from the comparison circuit for a predetermined time and outputs the difference as the count value;
A storage circuit that holds an offset value included in the count value,
The fully-differential input operational amplifier includes a bias circuit that generates a driving bias voltage and a startup circuit that activates the bias circuit, and the startup circuit is activated by applying the activation voltage to the bias circuit. A coulomb counter which is later stopped.   2. The coulomb counter according to claim 1, wherein the startup circuit is stopped after a predetermined time elapses after the power is turned on by a stop command given from outside. A logic circuit including the count circuit and the memory circuit; and an oscillation circuit that generates a clock signal that instructs the timing of operation processing by the logic circuit;
3. The coulomb counter according to claim 2, wherein the logic circuit generates and outputs the stop command for the startup circuit based on a count value of the clock signal. A logic circuit including the count circuit and the memory circuit;
3. The coulomb counter according to claim 2, wherein the logic circuit generates and outputs the stop command for the start-up circuit in accordance with a feedback signal of the bias voltage after the bias circuit is activated.   The logic circuit generates and outputs an offset measurement command for measuring an offset value in the coulomb counter, and sends the stop command to the startup circuit before measuring the offset value after power-on. The coulomb counter according to claim 3 or 4.   The logic circuit generates and outputs an offset measurement command for measuring an offset value in the coulomb counter, and sends the stop command to the start-up circuit after measuring the offset value after power-on. The coulomb counter according to claim 3 or 4.   A coulomb counter that outputs a count value proportional to the input voltage with a potential difference generated between both ends of the detection resistor as an input voltage, and samples the input voltage with a first capacitor and is proportional to the sampled input voltage The bias voltage is generated when a starting voltage is applied to generate a driving bias voltage applied to a fully differential input operational amplifier that amplifies a voltage value obtained by integrating the voltage to be output by a second capacitor and outputs the amplified voltage value as an output voltage. A method of controlling the internal power supply of the coulomb counter, wherein the application of the starting voltage is stopped later.   8. The method of controlling an internal power supply for a coulomb counter according to claim 7, wherein the application of the starting voltage is stopped before or after the offset measurement in the coulomb counter.

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