JP2009223714A - Arithmetic circuit and failure analysis method of arithmetic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable analysis including a process leading to a failure state even for a commercially operating device by acquiring a state of a program without affecting the current operation. <P>SOLUTION: History information accumulated in a history memory 30 is read from the history memory 30 as history information 300 via a history control part 20 by use of a read command from a command controller 50. According to this, even in a situation such that failure frequently occurs during operation of the program, two or more pieces of failure information can be retrospectively obtained since the history data is stored, for every occurrence of failure, in a different area on the history memory 30, and the time of failure analysis of the program can be reduced. Since live monitoring information 102 of operation of the program is acquired in a predetermined condition, the state of the program can be acquired without affecting the current state even in the commercially-operated device. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an arithmetic circuit and an abnormality analysis method for the arithmetic circuit, and more particularly to an arithmetic circuit including a central processing unit (CPU) and a memory and an abnormality analysis method for analyzing an abnormality occurring in the arithmetic circuit.

  In an arithmetic circuit including a CPU and a memory, it is generally performed to detect an abnormality in a program being executed by the CPU using a watch dog timer (WDT) (see, for example, Patent Document 1). In this patent document, the CPU transmits data on the execution location of the program together with the I / O signal during normal operation of the program, and the WDT has a predetermined count number when the CPU malfunctions due to program runaway or the like. Is exceeded, the program execution location data is stored in the backup memory, and information on the abnormality is displayed outside the apparatus.

  Also, in the above-mentioned Patent Document 1, when CPU operation is abnormal, information on the CPU recovery method is recorded and then the program is executed again, and recovery is performed so as to avoid the part where the abnormality has occurred by referring to the above information. A method of switching between methods is disclosed.

  There is also known a method for detecting an abnormal part (error) of a program using an error processing program embedded in advance in the program. The error processing program has a mechanism in which information such as an instruction code, a pointer value, and CPU register information of an operation part of a program in which an error has occurred is read from the CPU and held. In this abnormality detection method, a mechanism is generally used in which a program writes the detected error state to an external memory, or an error log (history) is left by the program writing the internal state of the CPU to the memory. .

JP 2006-23970 A

  However, the abnormality detection method described in Patent Document 1 is premised on the provision of WDT, and is used as a trigger for abnormal operation by WDT, and various conditions cannot be set as a trigger for abnormal operation. Further, only data at the time when WDT occurs (that is, data at a location where the CPU has abnormally operated) is recorded, and analysis of abnormal operation cannot be performed.

  Further, in the abnormality detection method described in Patent Document 1, when the CPU operation is abnormal, the information about the CPU recovery method is recorded and then the program is executed again to avoid the part where the abnormality has occurred by referring to the above information. However, this is possible only when the target of the abnormality is WDT. If the general CPU and its operation program become abnormal other than a WDT error, the abnormality is detected. Cannot be avoided.

  On the other hand, in the method of detecting an abnormal part (error) of a program with an error processing program, the error log (history) written in the memory is often erased by a CPU reset or recovery from a power failure. In addition, the error processing program has a drawback that the acquired information cannot be changed during the operation because the information to be acquired is determined in advance.

  In addition, information such as instruction code, pointer value, and CPU register information of the operation part of the program in which the error has been read and held by the error processing program from the CPU is recorded only once at the time of the program error. Although the information at the time of the program stop is known, it is difficult to determine the circumstances of the abnormality. In addition, it is possible to analyze the background by running the program while debugging it, but debugging is not possible in a system in commercial operation.

  Furthermore, a program in which operation timing is an important requirement for an embedded system or the like may change the operation timing due to the application of the debug system, and the program error may not be reproduced. As described above, in the method of detecting a program error by the error processing program, the reproducibility is low, it is difficult to identify the cause of the error, or the analysis until the cause of the error is identified requires a very long time. There are disadvantages such as.

  The present invention has been made in view of the above points, and provides an arithmetic circuit and an abnormality analysis method for an arithmetic circuit that can grasp the state of a program without affecting the current operation even for devices in commercial operation. For the purpose.

  It is another object of the present invention to provide an arithmetic circuit and an arithmetic circuit abnormality analysis method that enable analysis including a process leading to an abnormal state, and can greatly reduce the failure analysis time of a program.

  In order to achieve the above object, an arithmetic circuit according to the present invention includes a central processing unit, a program memory storing program code for operating the central processing unit, and data for storing data used when the program operates. In an arithmetic circuit having a memory, the central processing unit has means for generating monitoring information indicating whether a program operating on the central processing unit is normal or abnormal under a predetermined condition for detecting an abnormal operation state of the program. And having history information storage means for storing, as history information, instruction codes and data of a program up to the time of abnormality detection and information in the central processing unit at the time of abnormality detection based on monitoring information output from the central processing unit It is characterized by.

  In order to achieve the above object, the arithmetic circuit abnormality analysis method according to the present invention generates monitoring information indicating whether the operating program is normal or abnormal under a predetermined condition for detecting an abnormal operation state of the program. A central processing unit having means, and the instruction code and data of the program up to the time of abnormality detection and information in the central processing unit at the time of abnormality detection are stored as history information based on the monitoring information output from the central processing unit A first step of debugging the history information read from the history information storage means based on the debug information and separating it into physical data and an operation code, comprising: The second step of comparing the source code obtained by decompiling the operation code with the physical data, and the comparison result of the second step Based on, characterized in that it comprises a third step of obtaining analysis results of abnormal location by operating the program in the debugger.

  According to the present invention, it is possible to grasp the state of a program without affecting the current operation even for a device in commercial operation, and to enable analysis including the process leading to an abnormal state. The failure analysis time can be significantly shortened.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 shows a block diagram of a first embodiment of an arithmetic circuit according to the present invention. The arithmetic circuit of this embodiment includes a central processing unit (CPU) 10, a program memory 11 and a data memory 12 connected to the CPU 10 via a bidirectional data bus 100, a history control unit 20, and a bidirectional monitor for the CPU 10. The history memory 30 is connected by a line 103 and the command control device 50 is connected to the history control unit 20 by a command line 101.

  The program memory 11 stores program code for operating the CPU 10. The data memory 12 stores data used when the program operates. The command control device 50 is arranged for the purpose of setting the trigger when the program operation is abnormal, reading the history information, and deleting the history information with respect to the history control unit 20, and reading the history information when the trigger condition needs to be changed. Only when the history information needs to be erased, information is given to the history control unit 20. The trigger information given to the history control unit 20 from the command control device 50 includes predetermined program error conditions, interrupt factors, specific instruction execution, address, data, occurrence count designation, history information data amount, ring buffer setting, Various conditions necessary for acquiring history information such as overwriting buffer settings can be set. By specifying the number of trigger occurrences for completing the history recording from the command control device 50 external to the CPU 10, history information for the number of triggers can be stored in the history memory 30.

  The history control unit 20 has a nonvolatile memory, and holds all the information given from the command control device 50 in the nonvolatile memory. Therefore, the information held in the history control unit 20 is not erased even when the power is turned off or the CPU 10 is reset. The history control unit 20 is connected to the CPU 10 using the monitoring information 102. The monitoring information 102 is sent from the CPU 10 to the history control unit 20 as information on whether the program operation is normal or abnormal. Further, the history control unit 20 outputs the control information 200 to the history memory 30, and the history information 300 is supplied from the history memory 30. This control information 200 is a message indicating a control method of the history information held by the history control unit 20, and instructs how to use the history memory 30.

  The history memory 30 is supplied with all commands and data processed by the CPU 10 via the monitor line 103 and stores them by the control method instructed by the history control unit 20. The history memory 30 is configured by a non-volatile memory in which the CPU 10 is reset when the power is turned off, and the accumulated information is not erased even when booting up or rebooting. The history information 300 is used to read the contents of the history memory 30 via the history control unit 20 under the control of the command control device 50.

  Next, the operation of this embodiment will be described. First, when the program in the program memory 11 that operates the CPU 10 is normal, the CPU 10 notifies the history control unit 20 of a normal state by the monitoring information 102. In this case, the history control unit 20 does not issue an error information retention command to the history memory 30, and the history memory 30 continuously accumulates the CPU 10 commands and data supplied via the monitor line 103.

  Next, a case where the program is in an abnormal state will be described. When the CPU 10 detects an abnormal operation of the program under a predetermined detection condition of the abnormal operation state of the program and the program is in a fatal defect state, a process using the program error processing routine is executed, An abnormal interrupt is used to enter an error state such as a watchdog timer timeout. At that time, the CPU 10 notifies the history control unit 20 of the abnormal state by the monitoring information 102. When the history control unit 20 detects an abnormal state of the program based on the monitoring information 102, the history control unit 20 outputs an error message as the control information 200.

  The history memory 30 is an error message given by the control information 200, holds one record of history information, and adds the error log information of the CPU 10 to the history information when the error message is received. In the normal operation of the CPU 10, it is set whether the program starts again from the initial state when an error occurs or stops in the same state. When the operation start is set again, the history memory 30 starts to store all instructions and data processed by the CPU 10 in an address area different from the record once stored, and constructs new history information. .

  As described above, in this embodiment, when the program itself detects an error that occurs due to the operation of the program, or when the CPU 10 itself detects an error or abnormality, an abnormal state such as occurrence of a timeout of the watch dog timer is detected. At this time, by constructing a mechanism for informing the history control unit 20 that an abnormal state has occurred, the history of the program operation information up to immediately before the detection of the program operation abnormality and the various information in the CPU 10 at the time of the abnormality occurrence are recorded. It can be stored in the memory 30. The history control unit 20 stores history information in different areas on the history memory 30 every time an abnormality occurs.

  In the present embodiment, the abnormal operation is only a trigger for recording, and the operation information of the program up to immediately before detecting the abnormality of the operation of the program retroactively and various information in the CPU 10 when the abnormality occurs are stored in the history memory 30. Therefore, the content range of the information to be left is wider than the case of only the data of the abnormal part of the CPU.

  In the present embodiment, the history information stored in the history memory 30 is read from the history memory 30 as the history information 300 via the history control unit 20 by using a read command from the command control device 50, thereby Even when an abnormality occurs many times during operation, the history data is stored in a different area on the history memory 30 every time an abnormality occurs, so that the abnormality information can be traced back multiple times. This makes it possible to know the circumstances leading to an abnormality, and to shorten the time for analyzing the failure of the program.

  Further, in this embodiment, since the raw monitoring information 102 on which the program operates is acquired under predetermined conditions, even if the device is in commercial operation, the program status is not affected without affecting the current operation. Can be grasped.

  In addition, in the configuration of Patent Document 1 in which an abnormality target is WDT so that the recovery method is switched so as to avoid the part where the abnormality has occurred when the abnormality occurs once and then the program part is passed, If the target of the abnormality is the CPU and its operation program other than the WDT error, it cannot be detected and cannot be avoided. However, in this embodiment, the purpose is not recovery but analysis. An abnormality other than the WDT error can also be analyzed.

  Furthermore, in this embodiment, since a history holding circuit can be configured by a mechanism external to the CPU 10, it can be applied to a general CPU board.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 2 shows a block diagram of a second embodiment of the arithmetic circuit according to the present invention. In the figure, the same components as those in FIG. The arithmetic circuit of this embodiment is a CPU 60 with a history holding function in which the main part of the arithmetic circuit of the first embodiment shown in FIG. 1 is incorporated. That is, in FIG. 2, the CPU 60 with a history holding function has a configuration in which the CPU 10, the history control unit 20, and the history memory 30 are built in one CPU.

  The operation of this embodiment is the same as the operation described in FIG. 1, and has the same features as those of the first embodiment. That is, in the present embodiment as well as the first embodiment, a mechanism for recording a history of instruction codes and data on which the program has been operated on the CPU 10, a mechanism for recording a factor at the time of the program error, and a recorded 2 It has a mechanism for holding two pieces of information, and has a means for reading out and erasing the held information by a command given to the CPU 10 from the outside, and a command given from the outside to the CPU 10 as to whether to record the history and the factor. It is configured to have means that can be selected. Also, in the present embodiment, the history information recorded in the history memory 30 has a function that allows the user to select whether the function that is not erased by the reset of the CPU 10 and that is initialized by the recovery from the power failure is not initialized. The recording completion trigger condition and the history holding method can be changed, and an optimum failure history suitable for the system can be acquired.

  Furthermore, in this embodiment, since the CPU 10, the history control unit 20, and the history memory 30 are incorporated in the CPU 60 with history holding function, the overall shape when the CPU 60 with history holding function is a large scale integrated circuit (LSI). Can be made smaller than in the first embodiment.

(Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 3 shows a block diagram of a third embodiment of the arithmetic circuit according to the present invention. In the figure, the same components as those in FIG.

  As shown in FIG. 3, the arithmetic circuit of this embodiment includes a program memory 11, a data memory 12, and a command control device outside a CPU 70 with a history holding function that has a CPU 10, a history control unit 20, and a history memory 30 inside. 50 and an external history memory 31 are provided. The CPU 70 with history retention function of the present embodiment has substantially the same configuration as the CPU 60 with history retention function of the second embodiment, but the CPU 70 with history retention function receives the control information 200 from the history control unit 20 as an external history. It differs from the CPU 60 with history holding function in that the history information 301 is supplied from the external history memory 31 as well as being supplied to the memory 31.

  The external history memory 31 has a function equivalent to that of the history memory 30, and all commands and data processed by the CPU 10 are supplied via the monitor line 103 and stored by a control method instructed by the history control unit 20. The external history memory 31 is composed of a non-volatile memory that is reset when the power is cut off and is not erased even when booted up or rebooted. As a result, according to the present embodiment, the use of the external history memory 31 makes it possible to easily expand the capacity of the history memory.

  Next, a method for analyzing an abnormality from history information according to the present invention will be described.

  FIG. 4 shows an explanatory diagram of an embodiment of an abnormality analysis method for an arithmetic circuit according to the present invention. The history information 300 read from the history memory 30 (or the external history memory 31) based on the read command from any one of the command control devices 50 in FIGS. 1 to 3 is held in the command control device 50. Shall. The retained history information is read as operation log information from the command control device 50 into the log analysis tool 500 of FIG. 4 placed outside. Hereinafter, the operation of the log analysis tool 500 will be described.

  The history information 300 input to the log analysis tool 500 is first taken into the debugger 501. The debugger 501 is set to operate based on the debug information 502. The debug information 502 includes all the information necessary for the actual operating environment, such as the original source code for operating the CPU 10, the configuration information of the CPU 10, I / O information, memory information, memory stack information, and external device information. included.

  The debugger 501 separates the history information 300 into physical data 511 and operation codes 512 based on the debug information 502 described above. The physical data 511 is converted into the extracted data 513 after physical information conversion such as memory area, register data expansion, real address, relative address, and access time is performed in the physical data processing unit 503. This is given to the comparison unit 506.

  On the other hand, the operation code 512 is decompiled from the operation code 512 to the mnemonic information of the CPU 10 or the high-level language level specified by the debugger 501 in the decompilation 504, and the source code is generated from the operation code portion of the history information 300. The generated source code is given the execution time and order that the history information 300 has, and is given to the code comparison unit 505 as the source code 514.

  Next, the code comparison unit 505 compares the original source code on the debugger 501 with the source code 514 obtained from the history information 300 to detect a matching portion, and compares the detected code matching data 515 with the data comparison. Part 506. The data comparison unit 506 compares the extracted data 513 with the code match data 515, and maintains the association between the history time of the source code match detection and the history time of the extracted data 513, while using the execution time of the source code 514 as a key. The comparison of the access order of the data is performed to generate comparison result data 516, and the comparison result data 516 is given to the abnormal part specifying unit 507.

  The abnormal part specifying unit 507 incorporates the comparison result data 516 into the data on the debugger 501, operates the program on the debugger 501, runs to the part where the abnormality occurred in the actual operation, normality of the processing flow, processing data Normality, information immediately before an abnormal state, and the like are analyzed, and the obtained analysis result 517 is given to the display portion 508 of the abnormal part.

  The abnormal part display unit 508 translates the analysis result 517 input from the abnormal part specifying unit 507 into a form such as a source program, processing data, a cause of the abnormality, and the like (GUI ( graphical user interface) etc.

  As described above, since the present embodiment has a function of analyzing and displaying the abnormal state from the history information 300, it is possible to display it in a form that is easy for humans to understand rather than machine language or real memory data.

  The present invention is not limited to the above embodiment. For example, the log analysis tool 500 of FIG. 4 can be realized by a software configuration, and can be incorporated into the command control device 50 according to the present invention or an external personal computer. It can be used in computers and server devices.

  In the embodiment of FIG. 3, the history memory is provided inside and outside the CPU 70 with history holding function, but may be provided only outside. Furthermore, although the history memory 30 has been described as a nonvolatile memory, the history memory 30 may be configured so that a volatile memory or a nonvolatile memory can be selected. The stored history information is deleted.

  The arithmetic circuit of the present invention can be used for CPU boards and circuits in the field of embedded devices, CPU circuits of in-vehicle devices, CPUs and peripheral circuit LSIs thereof.

1 is a block diagram of a first embodiment of an arithmetic circuit according to the present invention. It is a block diagram of 2nd Embodiment of the arithmetic circuit of this invention. It is a block diagram of 3rd Embodiment of the arithmetic circuit of this invention. It is explanatory drawing of one Embodiment of the abnormality analysis method of the arithmetic circuit of this invention.

Explanation of symbols

10 Central processing unit (CPU)
DESCRIPTION OF SYMBOLS 11 Program memory 12 Data memory 20 History control part 30 History memory 31 External history memory 50 Command control apparatus 60, 70 CPU with history holding function
DESCRIPTION OF SYMBOLS 100 Data bus 101 Command line 102 Monitoring information 103 Monitor line 200 Control information 300, 301 History information 500 Log analysis tool 501 Debugger 502 Debug information 503 Physical data processing part 504 Decompilation 505 Code comparison part 506 Data comparison part 507 Identification of abnormal part Part 508 Abnormal part display part

Claims (15)

In an arithmetic circuit having a central processing unit, a program memory storing program code for operating the central processing unit, and a data memory storing data used when the program operates,
The central processing unit includes means for generating monitoring information indicating whether a program operating on the central processing unit is normal or abnormal under a predetermined condition for detecting an abnormal operation state of the program,
Based on the monitoring information output from the central processing unit, history information storage means for storing, as history information, instruction codes and data of the program up to the time of abnormality detection and information in the central processing unit at the time of abnormality detection An arithmetic circuit comprising: In an arithmetic circuit having a central processing unit, a program memory storing program code for operating the central processing unit, and a data memory storing data used when the program operates,
The central processing unit includes means for generating monitoring information indicating whether a program operating on the central processing unit is normal or abnormal under a predetermined condition for detecting an abnormal operation state of the program,
A history memory for storing instruction codes and data of the program and information in the central processing unit as history information;
When the monitoring information is input and a condition necessary for acquiring history information is set, the monitoring information indicates an abnormality, and when the condition is satisfied, the instruction code of the program until the abnormality is detected And a history control means for storing data and information in the central processing unit at the time of abnormality detection together with error log information of the central processing unit as one history information in the history memory. .   The system further comprises command control means for setting conditions necessary for acquiring the history information to the history control means, reading out the history information stored in the history memory, and erasing the stored history information. Item 3. The arithmetic circuit according to Item 2.   The command control means sets at least one of a predetermined program error condition, interrupt factor, specific instruction execution, address, and data as a condition necessary for acquiring the history information in the history control means. The arithmetic circuit according to claim 3, wherein:   5. The arithmetic circuit according to claim 2, wherein the history control unit stores the history information in a different area on the history memory for each abnormality detection based on the monitoring information.   5. The central processing unit, the history memory, and the history control unit are incorporated in a central processing unit with a history holding function different from the central processing unit. The arithmetic circuit according to one item.   Outside the central processing unit with history holding function, when the monitoring information shows an abnormality by the history control means and when the condition is satisfied, the instruction code and data of the program until the abnormality is detected and the abnormality 5. An external history memory for storing information in the central processing unit at the time of detection as one history information together with error log information of the central processing unit is further provided. The arithmetic circuit according to any one of claims.   5. The history control unit stores conditions necessary for acquiring the history information in a nonvolatile storage unit, and the history memory is a nonvolatile memory. Arithmetic circuit. A central processing unit comprising means for generating monitoring information indicating whether the operating program is normal or abnormal under the detection condition of the abnormal operation state of the predetermined program;
Based on the monitoring information output from the central processing unit, history information storage means for storing, as history information, instruction codes and data of the program up to the time of abnormality detection and information in the central processing unit at the time of abnormality detection An abnormality analysis method for an arithmetic circuit comprising:
A first step of debugging the history information read from the history information storage means based on debug information and separating it into physical data and an operation code;
A second step of comparing the physical data with the source code obtained by decompiling the operation code;
And a third step of obtaining an analysis result of the abnormal part by operating the program on a debugger based on the comparison result of the second step. A central processing unit comprising means for generating monitoring information indicating whether the operating program is normal or abnormal under the detection condition of the abnormal operation state of the predetermined program;
A history memory for storing instruction codes and data of the program and information in the central processing unit as history information;
When the monitoring information is input and a condition necessary for acquiring history information is set, the monitoring information indicates an abnormality, and when the condition is satisfied, the instruction code of the program until the abnormality is detected And a history control means for storing data and information in the central processing unit at the time of abnormality detection together with error log information of the central processing unit as one history information in the history memory. Because
A first step of debugging the history information read from the history memory based on debug information and separating the history information into physical data and an operation code;
A second step of detecting a match between the source code obtained by decompiling the operation code and the source code of the original history information to be debugged in the first step;
While maintaining the association between the code matching detection history time obtained in the second step and the physical data history time, the physical data access order is rearranged using the execution time of the source code as a key. A third step of generating comparison result data;
A fourth step of incorporating the comparison result data generated in the third step into data on a debugger and operating the program to obtain an analysis result of the abnormal part, analysis method.   The arithmetic circuit further includes command control means for setting conditions necessary for acquiring the history information to the history control means, and for reading the storage history information from the history memory and erasing the stored history information. The abnormality analysis method for an arithmetic circuit according to claim 10.   11. The arithmetic circuit abnormality analysis method according to claim 10, wherein the history memory stores the history information in a different area for each abnormality detection based on the monitoring information by the history control means.   11. The abnormality of the arithmetic circuit according to claim 10, wherein the central processing unit, the history memory, and the history control unit are incorporated in a central processing unit with a history holding function different from the central processing unit. analysis method.   Outside the central processing unit with history holding function, when the monitoring information shows an abnormality by the history control means and when the condition is satisfied, the instruction code and data of the program until the abnormality is detected and the abnormality 11. The arithmetic circuit according to claim 10, further comprising an external history memory for storing information in the central processing unit at the time of detection as one history information together with error log information of the central processing unit. Anomaly analysis method.   11. The arithmetic circuit abnormality analysis method according to claim 10, wherein the history control means stores a condition necessary for acquiring the history information in a nonvolatile storage unit, and the history memory is a nonvolatile memory.

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