JP2009207031A - Amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier circuit in which an unwanted wave suppression ratio is made high in an integrated circuit without using an external filter element that causes cost increase. <P>SOLUTION: An amplifier circuit includes an input matching circuit 1; a transconductor circuit 2 that outputs, with a positive phase, a current in proportion to conductance with respect to an input voltage; a cascode circuit 3 which fetches an input current with input impedance and outputs, with a positive phase, an output current in proportion to the input current with output impedance; a load circuit 4 which converts the input current into a voltage signal; an output matching circuit 5; and a feedback circuit 6 connected between an input terminal and an output terminal of the transconductor circuit 2. Thus, an amplifier circuit is accomplished that corresponds to frequency dependency of impedance generated by the feedback circuit 6 and improves an unwanted wave suppression property. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a radio communication circuit that constitutes a radio communication system, and more particularly to a technique that is effective when applied to the configuration of an amplifier circuit having an unnecessary wave suppression function.

  According to a study by the present inventor, there are technologies described in Patent Documents 1 and 2 and Non-Patent Documents 1 to 4 for the wireless communication circuits constituting the wireless communication system.

  Patent Document 1 describes a low noise amplifier circuit having a switchable amplification factor. In this amplifier circuit, a parallel connection constituted by the first and second signal amplifier circuits is provided between the input portion and the output portion of the high-frequency signal. The first signal amplifier circuit includes a transistor in the base circuit, and the second signal amplifier circuit includes a transistor in the emitter circuit together with the input impedance adaptor.

  Patent Document 2 describes an active tunable filter circuit for use as an active filter that can be integrated in a mobile radio apparatus. The circuit includes an active amplifier circuit and a passive resonant circuit connected to the active amplifier circuit. The active amplifier circuit includes a reactive feedback network, and the passive resonant circuit includes an inactive semiconductor device portion that resonates with the inductive portion during operation.

  Non-Patent Document 1 proposes a configuration that realizes a steep attenuation filter (band elimination filter, also known as notch filter) on an integrated circuit, and can confirm good filter characteristics at 2 GHz. A spiral inductor is formed by using wiring of an integrated circuit, and its resistance component is compensated by connecting a negative resistance circuit including a transistor in series to realize an inductor having a high Q. It is described that a low noise amplifier circuit (LNA: Low Noise Amplifier) equipped with a band elimination filter having a sharp and large attenuation characteristic can be configured by the inductor and the capacitance obtained in this way.

  Non-Patent Document 2 describes a technique for mounting a balun element that outputs a balanced output after an unbalanced input of a signal on an integrated circuit and converts it to a differential signal. A notch circuit that gives a steep attenuation characteristic to the differential signal is constituted by a cross-coupled transistor, an integrated transformer, and a variable capacitance element for changing the notch frequency. By incorporating this notch circuit into the LNA, only a specific frequency component within the band is attenuated, and a low-noise amplifier circuit for UWB having an unnecessary signal rejection ratio of about 35 dB at 5 GHz is realized.

  In Non-Patent Document 3, for the high frequency in the 60 GHz band, in the receiver configuration, the superheterodyne method is used in the first stage frequency conversion that handles the 60 GHz band, and the direct conversion system is used in the next stage frequency conversion in which the frequency is lowered to the 9 GHz band. The technology to apply is described. The first-stage low-noise amplifier incorporates a notch filter circuit constituted by a transmission line, and is provided with an image signal removal function. Even in the transmitter configuration, after converting the baseband signal to IF frequency using the direct conversion method at the first stage, the superheterodyne system is applied to the next stage that outputs a 60 GHz band signal, and the double sideband is used at the modulator output. An amplifier with an image signal removal function is provided for converting the signal into a single band signal.

Non-Patent Document 4 describes that a super-heterodyne method generally requires a removal ratio of about 60 dB as an image signal removal function in order to integrate RF circuits according to differences in wireless communication transmission / reception methods and modulation techniques. Yes.
Special table 2004-534470 gazette JP 2005-503064 gazette J. et al. A. Macedo and M.M. A. Copeland, “A 1.9-GHz Silicon Receiver with Monolithic Image Filtering”, IEEE Journal of Solid-State Circuits, vol. 33, no. 3 March 1998, pp. 378-386 Andrew Bevilacqua et al. “A 0.13 μm CMOS LNA with Integrated Balun and Notch Filter for 3-to-5 GHz UWB Receivers” IEEE Solid-state Circuits. 420-421 Brian Floyd et al. “A Silicon 60 GHz Receiver and Transmitter Chipset for Broadband Communications” IEEE Solid-state Circuits Conference 2006, Paper # 10.3. 184-185 Tsunehara Tsunehara “Introduction to CMOS RF Circuit Design”, Nikkei Electronics January 28 issue, January 28, 2008, pp. 164-174

  By the way, as a result of the study of the present inventor regarding the radio communication circuit constituting the radio communication system as described above, the following has been clarified.

  Conventionally, amplifiers for wireless communication have been developed as indispensable components for wireless communication devices. Applications that lead the development of amplifiers include GSM (Global System for Mobile Communications), PDC (Personal Digital-Phone System), PHS (Personal Handy-phone System E), and PCS (Personal Communication E mobile phone standard). Wireless communication devices that constitute wireless LANs that comply with 802.11a, 802.11b, and 802.11g, which are wireless communication specifications stipulated in, and wireless MAN (Wireless Metropolitan Area Network) and high-speed data rate wireless communication Millimeter-Wave Wireless PAN (Wireless Personal Area Network) over a wide range, such as, the upper frequency limit is ranging from quasi-millimeter wave band to the millimeter-wave band.

  These wireless communication devices are always required to be low-priced, downsized, and low in power consumption for long-time operation for the purpose of widespread use. One method for meeting these requirements is to mount a wireless communication circuit on a smaller number of semiconductor integrated circuits (ICs). In particular, many attempts have been made to realize wireless communication circuits using silicon (Si) ICs due to the low cost of substrate materials and high yield due to high maturity of semiconductor processes. Have provided. Future development will further reduce the number of external components and realize the entire wireless communication system on a silicon chip at a low cost. By incorporating it with digital function circuits such as a microprocessor unit (MPU), the system will also include a wireless communication function. There is a strong expectation to provide on-chip.

  Various configurations of wireless communication systems have been proposed, but a superheterodyne system in which a mixer corresponding to an RF signal outputs an IF signal of a low frequency to perform subsequent signal processing, and a DC data signal directly from the RF signal by a mixer The direct conversion method to convert to is roughly classified. The superheterodyne method has a complicated configuration and more external components than the direct conversion method. However, the superheterodyne method is adopted in many wireless communication systems because it has good channel selectivity and reception sensitivity in which the frequency band to be used is divided. Architecture. The superheterodyne method has a large influence of the image signal in the reception path, and a large influence of the unnecessary spectrum signal generated in the modulation mixer in the transmission path, and an external filter having a steep attenuation characteristic for the purpose of removing these unnecessary wave signals. Is indispensable.

  Since the operating frequency of a wireless communication device for a cellular phone or a wireless LAN is in the microwave band region, it is possible to use a SAW (Surface Acoustic Wave) filter or an FBAR (Film Bulk Acoustic Resonator) filter. The external filter can be realized. On the other hand, the practical use of external filters with steep attenuation characteristics in the quasi-millimeter wave band and the millimeter wave band has not progressed, and it is not possible to use a filter constituted by a wiring pattern on a mounting board or a transmission line on an integrated circuit. I do not get. In this case, since the loss of the wiring pattern and the transmission line is large, the Q factor does not increase and the attenuation characteristic becomes slow. As described above, the superheterodyne method requires a filter having a steep attenuation characteristic. However, the microwave can be used with an external filter, and the passive filter with a low Q factor can be used in the quasi-millimeter wave band and the millimeter wave band. Each of them has a problem of an increase in cost and a lack of required damping performance.

  In order to solve these problems, the contents relating to the integration of the filters are known as in Non-Patent Documents 1 and 2. However, in the configuration of Non-Patent Document 1, an increase in bias current due to a transistor constituting the negative resistance circuit, or a sufficiently high transistor performance with respect to the operating frequency is required, and an expensive process must be used. There is a problem. In Non-Patent Document 2, a sufficiently high-speed transistor performance is required to increase chip cost due to an increase in circuit scale, increase power consumption due to an increase in bias current, and ensure an operation margin for a notch circuit. There are problems such as increased process costs.

  Further, the technique of Patent Document 1 must have a resistance having a resistance value that generates a sufficient gain, a voltage drop occurs at this resistance, it is difficult to reduce the power supply voltage, and power consumption is large. There is a problem that there is no input matching circuit and the Q factor cannot be increased in a frequency selective manner. Further, the technique of Patent Document 2 requires a feedback circuit having frequency selectivity and a filter network for unnecessary wave suppression, which increases the circuit scale and increases the cost.

  By the way, reflecting the recent needs for wireless transmission of large-capacity information such as video and video data, and the tightness of microwave band frequencies used in mobile phones and wireless LANs, it is possible to ensure high-bandwidth transmission at higher frequencies. There are strong expectations for building a wireless communication system. Among high-frequency systems, wireless communication systems in the quasi-millimeter wave band centered on the 24 GHz ISM band and the millimeter wave band centered on the 60 GHz band Unbanded band have been studied from the viewpoint of application and provision of communication devices that support it. Yes. A super heterodyne system is applied as an RF architecture even in a radio communication system using these high frequency bands. As an example, the technique of Non-Patent Document 3 can be cited. The image signal removal ratio is about 30 dB for both the receiver and the transmitter. The required image removal ratio will vary depending on the application, but the superheterodyne method generally requires a removal ratio of about 60 dB as described in Non-Patent Document 4, and further, It is a problem to realize an unnecessary wave removal function that enables high image removal in an integrated circuit.

  Therefore, the present invention relates to an integrable unnecessary wave removal filter used in a superheterodyne system, and is made to overcome the disadvantages exemplified in Non-Patent Documents 1, 2, and 3 above the microwave band. This technology can also be used in the quasi-millimeter wave band and the millimeter wave band, and realizes steep unnecessary wave suppression characteristics within a range in which there is no excessive increase in area and increase in power consumption. That is, a typical object of the present invention is to provide an amplifier circuit having a high unnecessary wave suppression ratio in an integrated circuit without using an external filter element, which is expensive.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the outline of a typical circuit is as follows. In a single-phase amplifier circuit, an input matching circuit that generates a predetermined matching impedance for the output impedance of the previous stage at the input terminal, and an input voltage applied from the input matching circuit. Conductor circuit that outputs current proportional to conductance in positive phase, cascode circuit that takes input current applied from this conductor circuit as input impedance, and outputs output current proportional to input current as output phase in positive phase, and this cascode A load circuit that converts an input current applied from the circuit into a voltage signal, an output matching circuit that is connected to the input terminal of the load circuit and generates a predetermined matching impedance for the input impedance of the next stage, and an input terminal of the conductor circuit And a feedback circuit connected between the output terminal and the input terminal. An input terminal of the external input terminal of the circuit, characterized in that the output terminal of the output matching circuit and the output terminal to the outside.

  In the differential amplifier circuit, the first and second input matching circuits that generate a predetermined matching impedance with respect to the output impedance of the previous stage at the input terminal, and the first and second input matching circuits are applied. A differential conductor circuit that outputs a differential current that is proportional to the conductance relative to the differential input voltage in positive phase, and an input current that is applied from the differential conductor circuit is captured by the input impedance, and an output current that is proportional to the input current is obtained. First and second cascode circuits that output a positive phase with output impedance, a differential load circuit that converts a differential input current applied from the first and second cascode circuits into a differential voltage signal, and the difference A first and a second output matching circuit connected to the differential input terminal of the dynamic load circuit and generating a predetermined matching impedance for the input impedance of the next stage; A differential feedback circuit connected between the differential input terminal and the differential output terminal of the conductor circuit, wherein the input terminals of the first and second input matching circuits are the differential input terminals to the outside; The output terminal of the second output matching circuit is a differential output terminal with the outside.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In other words, the effect obtained by the typical one can provide an amplifier circuit having a high unnecessary wave suppression ratio in an integrated circuit without using an external filter element that is expensive.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. Moreover, in each embodiment, although the part which becomes a feature is mainly demonstrated, it is not irrelevant about each other part, and each has relations, such as a modification, an application example, and supplementary explanation.

<< First Embodiment >>
A first embodiment of the present invention will be described with reference to FIGS. In the present embodiment, in order to make the features of the present embodiment (the present invention) easier to understand, the present embodiment will be described in comparison with the technologies studied as the premise of the present invention (FIGS. 3 and 4).

  FIG. 1 is a diagram showing a configuration of an amplifier circuit with an unnecessary wave suppression function formed on a semiconductor chip of a semiconductor integrated circuit according to a first embodiment of the present invention. Amplifier circuits 301 (corresponding to FIG. 16 described later) and 403 (corresponding to FIG. 17 described later) shown in FIG. 1 have an input matching circuit (MCIN) 1 that generates a predetermined matching impedance with respect to the output impedance of the previous stage at the input terminal, A transconductor circuit (GMC) 2 that is connected to the output terminal of the input matching circuit 1 and outputs a current in proportion to the conductance with respect to the input voltage applied from the input matching circuit 1, and an output of the transconductor circuit 2 A cascode circuit (CASC) 3 connected to a terminal and taking in an input current applied from the transconductor circuit 2 with a low input impedance and outputting an output current proportional to the input current in a positive phase with a high output impedance. Connected to the output terminal, the input current applied from the cascode circuit 3 is a voltage signal. A load circuit (LOADC) 4 for conversion, an output matching circuit (MCOUT) 5 that is connected to an input terminal of the load circuit 4 and generates a predetermined matching impedance for an input impedance of the next stage, and an input terminal of the transconductor circuit 2 The feedback circuit (FBC) 6 is connected to the input terminal and the output terminal is connected to the output terminal of the transconductor circuit 2.

  The input matching circuit 1 is a circuit network that determines matching with respect to the driving impedance Zs in the previous stage of the amplifier circuit. The degree of matching depends on the application of the amplifier circuit. When used as a low noise amplifier circuit, the output noise is set to be a predetermined value or less, and when used as a power amplifier circuit, the power transfer efficiency is set to be a predetermined value or more. Even a low noise amplifier circuit may be set to a moderate matching state so as to satisfy predetermined values of both low noise characteristics and power amplification characteristics. In the scope of the present invention, the input matching circuit 1 is treated as a matching circuit for satisfying the required performance of the amplifier circuit.

The transconductor circuit 2 is a circuit network that generates an output current signal i _o1 that is proportional to the voltage signal v ₁ applied to the input terminal. The input impedance varies depending on the configuration of the transconductor circuit 2 but is equivalently assumed to be Z _i1 . It has a function of generating an output current i _o1 at a ratio of transconductance g _m1 to the voltage applied to Z _i1 . The output impedance is Z _o1 and is arranged in parallel with the output current source.

The cascode circuit 3 receives a current signal i _o1 ′ applied to the input terminal with a low input impedance Z _i2 , and outputs a current having the same magnitude as i _o1 ′ as an output current i _{o2 with} a high output impedance Z _o2. .

The load circuit 4 and the output matching circuit 5 use the load impedance Z _L as a voltage signal v ₂ for the output current i _o2 obtained from the cascode circuit 3, and perform output impedance matching to change the output voltage vo to the impedance of the next stage. Give to.

The feedback circuit 6 is a feedback circuit disposed between the input terminal and the output terminal of the transconductor circuit 2. At the same time, it has a function of connecting the input terminal of the transconductor circuit 2 to the low input impedance of the cascode circuit 3 through the feedback circuit 6. The configuration of the feedback circuit 6 itself realizes a high impedance (Z _FBH ) at a frequency at which a desired gain is desired in terms of the characteristics of the amplifier circuit, and a low impedance (Z _FBL ) at a frequency at which unnecessary gain suppression is desired without gain. Network. Here, the realization characteristics of the configuration example of FIG. 1 are analytically shown by using FIG. 2 that represents an equivalent circuit of the basic function of FIG.

FIG. 2 is an equivalent circuit diagram for analyzing the unwanted wave suppression ratio in the configuration of FIG. 1, and represents from the input terminal of the transconductor circuit 2 to the output terminal of the cascode circuit 3 in the configuration example of FIG. 1. Yes. The degree of unnecessary wave suppression realized in the present embodiment can be shown by the transfer characteristic analysis of the equivalent circuit network shown in FIG. Here, the input matching circuit 1 of FIG. 1 is omitted from the equivalent circuit of FIG. In FIG. 2, the drive voltage of the amplifier circuit is vs, and the drive impedance is Zs. The ratio of the output current i _o2 of the cascode circuit 3 to Vs will be examined below. After i _o2 is obtained, it is converted into a voltage signal or a power signal by the load circuit 4 and the output matching circuit 5.

_{Here, Zs = 50 [Ω],} Z i1 = 1000 [Ω], Z i2 = 25 [Ω], g m1 = 0.04 and _[S], the _{Z FB Z FBH = 1000 [Ω} ], Z FBH = 2 [30] is entered, and the formula (1) is evaluated.

When high impedance Z _FBH = 1000 [Ω] is used for Z _FB , G1 = 0.033. On the other hand, when a low impedance Z _FBL = 30 [Ω] is used, G1 is as small as 0.0012. The ratio of the values of G1 in these two cases is from 0.033 / 0.0012 to about 26.1 times. When converted to decibels, it is 28.3 dB.

  In order to show the effect of this embodiment, the same analysis is shown for two examples (FIGS. 3 and 4) of the amplifier circuit studied as a premise of the present invention. 3 and 4 are equivalent circuit diagrams for analyzing the unwanted wave suppression ratio in the configuration of the amplifier circuit studied as a premise of the present invention.

First, the feedback circuit 6 is connected from the output terminal of the transconductor circuit 2 to the ground, the impedance of the feedback circuit is set to a high impedance (Z _FBH ) at a frequency where a desired gain is desired, and unnecessary wave suppression is performed without gain. Set to a low impedance (Z _FBL ) at the desired frequency. This analysis is performed for a circuit imitating the circuit configuration used in Non-Patent Document 1. An equivalent circuit is shown in FIG. In this case, the ratio G2 of the output current i _o2 of the cascode circuit 3 with respect to Vs can be expressed by the following formula (2).

When the same constant as that in the above-described embodiment of FIG. 2 is used, when Z _FBH = 1000 [Ω] having high impedance is used for Z _FB , G 2 = 0.037. On the other hand, when low impedance Z _FBL = 30 [Ω] is used, G2 = 0.021, which is a small value. The ratio of G2 values in these two cases is about 1.78 times from 0.037 / 0.021. When converted to decibels, it is 5.0 dB, and it is clear from the analysis that it is 23.3 dB inferior to the unwanted wave suppression ratio 28.3 dB in the present embodiment calculated as G1.

Another consideration is that the feedback circuit 6 is connected from the input terminal of the transconductor circuit 2 to the ground so that the impedance of the feedback circuit is high, a high impedance (Z _FBH ) is required at a frequency where a desired gain is desired, and no gain is required and unnecessary. This is a case where a low impedance (Z _FBL ) is set at a frequency at which wave suppression is desired. An equivalent circuit is shown in FIG. In this case, the ratio G3 of the output current i _o2 of the cascode circuit 3 with respect to Vs can be expressed by the following formula (3).

When the same constant as that in the present embodiment in FIG. 2 is used, when Z _FBH = 1000 [Ω] having a high impedance is used for Z _FB , G 3 = 0.036. On the other hand, when low impedance Z _FBL = 30 [Ω] is used, G3 = 0.015, which is a small value. The ratio of G3 values in these two cases is from about 0.036 / 0.015 to about 2.4 times. When converted to decibels, it is 7.6 dB, and it is clear from the analysis that it is 20.7 dB inferior to the unnecessary wave suppression ratio 28.3 dB in this embodiment calculated as G1.

  From the above examination, the configuration of the present embodiment in FIG. 1 (FIG. 2) is significantly unnecessary in the case of the same feedback circuit characteristics as compared with the configuration studied as the premise of the present invention in FIGS. 3 and 4. It was analytically revealed that the wave suppression ratio can be improved.

Next, FIG. 5 shows a configuration example of the feedback circuit 6 and the frequency dependence of the impedance of the feedback circuit obtained by a circuit simulator. FIG. 5A shows the configuration of a third-order notch filter circuit. The notch filter circuit can be composed of three elements: a capacitor (C1) 63, a capacitor (C2) 62, and an inductor (L1). C1p is a parasitic capacitance of the capacitor 63, C _L1 is a parasitic capacitance of an equivalent circuit of the inductor L1, and R _L1 is a parasitic resistance of an equivalent circuit of the inductor L1. When the impedance viewed from the input terminal P1 with the output terminal P2 grounded is represented by a notch impedance _Znotch , it can be expressed by Equation (4). Here, s is expressed by s = j · ω using each frequency ω.

From the equation (4), the desired frequency f _wanted to pass the signal and the frequency f _image to attenuate the unnecessary wave component can be calculated as the following equations (5) and (6).

Actually, in order to realize the configuration of FIG. 5A on an integrated circuit, there is an influence of a parasitic element. FIG. 5B shows the configuration of FIG. 5A assuming a four-layer aluminum wiring process that can be formed on a Si substrate (configuration viewed from P1 with P2 of the third-order notch filter circuit grounded). The frequency dependence of Z _notch obtained by the above is shown. In this case, f _image is set to 18 GHz, and f _wanted is set to 22 GHz. The inductor L1 is assumed to be a spiral inductor, and in the frequency band exceeding 10 GHz, an equivalent circuit 61 is used in consideration of the influence of the series parasitic resistance R _L1 and the parasitic capacitance C _L1 on the Si substrate. From FIG. 5B, it can be confirmed that the absolute value of Z _{notch in} f _image is about 30Ω and the value in f _wanted exceeds 1000Ω.

Therefore, the minimum value 30Ω and the maximum value 1000Ω of the feedback circuit impedance used for the analysis in FIGS. 2 to 4 are sufficiently feasible values in the integrated circuit. Although FIG. 5 shows that a third-order notch filter circuit is used as a feedback circuit, the present invention is not limited to this in the scope of the present invention, and a high impedance and one at one or more desired frequencies f _wanted . Needless to say, a feedback circuit that can set a low impedance at the frequency f _image for attenuating unnecessary wave components can be applied.

  From the above examination, by using the configuration of the present embodiment shown in FIG. 1, the circuit configuration of the technique studied as the premise of the present invention at the frequency at which the unnecessary wave component determined by the impedance characteristics of the feedback circuit 6 is attenuated. In comparison, it is clear that the gain attenuation is greatly generated and an excellent unnecessary wave suppression function can be achieved. In this way, by adopting the basic configuration of the amplifier circuit shown in FIG. 1, the maximum gain of the amplifier circuit and the gain at the unnecessary wave frequency can be increased even if a passive element having a large loss is used while maintaining current consumption. An effect can be obtained in that the ratio with the attenuation is greatly increased with respect to the technique studied as the premise of the present invention.

<< Second Embodiment >>
A second embodiment of the present invention will be described with reference to FIGS.

  FIG. 6 is a diagram showing a specific configuration of the amplifier circuit with an unnecessary wave suppression function formed in the semiconductor chip of the semiconductor integrated circuit according to the second embodiment of the present invention. The amplifier circuits 301 and 403 shown in FIG. 6 are the input matching circuit (MCIN) 1, the transconductor circuit (GMC) 2, the cascode circuit (CASC) 3, and the load circuit (LOADC) described in the first embodiment. 4. In addition to the basic components of the output matching circuit (MCOUT) 5 and the feedback circuit (FBC) 6, a stabilizing circuit (STBC) that operates stably as an amplifier circuit and suppresses the occurrence of an oscillation phenomenon at a characteristic frequency. 7 is comprised.

  The input matching circuit 1 includes a capacitor 11 and a capacitor 12. One terminal of the capacitor 11 is used as an input terminal of the input matching circuit 1 connected to the input terminal 101 connected to the outside, and the other terminal of the capacitor 11 is used as the capacitor 12. Is connected to one of the terminals as an output terminal of the input matching circuit, and the other of the capacitor 12 is grounded.

  The transconductor circuit 2 includes an n-type bipolar transistor (T1) 21, a resistor 23, and an inductor 22. The base of the transistor 21 is used as an input terminal of the transconductor circuit 2, and the collector of the transistor 21 is output from the transconductor circuit 1. The terminal of the inductor 22 is connected to the emitter of the transistor 21, the other terminal of the inductor 22 is grounded, the one terminal of the resistor 23 is connected to the base of the transistor 21, and the other terminal of the resistor 23 is connected It is configured as a bias terminal of the transconductor circuit 2 connected to the external bias voltage terminal 104.

  The cascode circuit 3 includes an n-type bipolar transistor (T2) 31, supplies a stable first potential to the base of the transistor 31 through the external voltage terminal 105, and the emitter of the transistor 31 is connected to the cascode circuit 3. And the collector of the transistor 31 is configured as the output terminal of the cascode circuit 3.

  The load circuit 4 includes an inductor 41, supplies a stable second potential to one terminal of the inductor 41 through an external power supply voltage terminal 103, and uses the other terminal of the inductor 41 as an input terminal of the load circuit 4. Composed.

  The output matching circuit 5 includes a capacitor 51 and a capacitor 52. One terminal of the capacitor 51 is used as an input terminal of the output matching circuit 5, and the other terminal of the capacitor 51 is connected to one terminal of the capacitor 52. The output matching circuit 5 is connected to the output terminal 102, and the other terminal of the capacitor 52 is grounded.

  The feedback circuit 6 includes a capacitor 63, a capacitor 62, and an inductor 61. One terminal of the capacitor 63 is used as an output terminal of the feedback circuit 6, and the other terminal of the capacitor 63 is connected to one terminal of the capacitor 62. The other terminal of 62 is grounded, one terminal of the inductor 61 is connected to one terminal of the capacitor 62, and the other terminal of the inductor 61 is configured as an input terminal of the feedback circuit 6.

  The stabilization circuit 7 includes a resistor 71 and a capacitor 72, one terminal of the resistor 71 is connected to the input terminal of the load circuit 4, and the other terminal of the resistor 71 is connected to one terminal of the capacitor 72. The other terminal 72 is grounded.

  As described above, the input matching circuit 1 and the output matching circuit 5 are composed of capacitive passive elements. Each of the matching circuits can be arbitrarily designed independently of the configuration of the feedback circuit 6 so as to realize noise matching, power matching, or matching that satisfies a plurality of matching factors at a frequency that requires matching.

  The transconductor circuit 2 and the cascode circuit 3 are configured by n-type bipolar transistors or heterojunction bipolar transistors. In particular, in the transconductor circuit 2, an inductor 22 is inserted into the emitter of the transistor 21 to improve noise characteristics. The bias voltage terminal 104 determines the voltage applied to the base of the transistor 21 and is based on the premise that a stable potential is supplied. The bias voltage terminal 105 is provided to give a stable potential to the base potential of the transistor 31 operating as the cascode circuit 3. Note that the transconductor circuit 2 using bipolar transistors is not limited to a circuit configuration in which an inductor is inserted into the emitter.

  The load circuit 4 is configured by an inductor 41. However, depending on the operating frequency, the load circuit 4 is realized by an arbitrary passive element network configured by one or more inductors and one or more capacitors in order to generate a specific impedance. .

  The stabilization circuit 7 is a circuit that generates a loss so that the entire amplifier circuit does not oscillate at a specific frequency. In order to prevent an increase in power consumption, a capacitor 72 is sandwiched in series and a resistor 71 is used.

  The feedback circuit 6 uses a circuit configuration in which the third-order notch filter shown in FIG. 5 is realized by one inductor 61 and two capacitors 62 and 63. As described above, there is no problem even if an arbitrary number of one or more desired frequencies for passing signals and frequencies for attenuating unnecessary wave components are set in the notch impedance.

  FIG. 7 shows the calculation results of gain and noise characteristics obtained by the circuit simulator for the amplifier circuit configuration shown in FIG. The characteristics of the feedback circuit 6 used here are those disclosed in FIG. As the transistor characteristics, SiGe HBT characteristics capable of achieving high-speed performance with a cutoff frequency of 150 GHz were used.

  S21 shown in FIG. 7A indicates the frequency dependence of the gain of the amplifier circuit. The characteristic indicated by the solid line is the characteristic of the circuit in which the feedback circuit 6 is omitted in FIG. It has a peak with a gain of 9.72 dB at 24 GHz. The gain at 18 GHz is 4.93 dB, and the unwanted wave frequency gain with respect to the desired frequency gain is attenuated by 4.79 dB. The characteristic indicated by the broken line indicates the calculation result when the terminal on the side having the inductor 61 of the feedback circuit 6 shown in FIG. 6 is removed from the input terminal of the transconductor circuit 2 and connected to an ideal ground potential. Although it has a peak of gain of 9.75 dB at 24 GHz, the gain at 18 GHz is further attenuated with respect to the characteristics of the solid line to 2.26 dB, and the ratio of the unwanted wave frequency gain to the desired frequency gain is 7.49 dB. It is. The characteristic indicated by the alternate long and short dash line indicates the characteristic of the feedback circuit 6 shown in FIG. While the gain increases to 13.9 dB at 24 GHz, the gain attenuates to −16.7 dB at 18 GHz, and the ratio of the unwanted wave frequency gain to the desired frequency gain is greatly improved to 30.6 dB. it is obvious.

  In the amplifier circuit, noise characteristics are important as well as gain. In FIG. 7B, the NF value indicating the noise characteristic is displayed in decibels and its frequency dependency is shown. The characteristic of the circuit shown by the solid line and omitting the feedback circuit 6 in FIG. 6 is 3.97 dB at 24 GHz which is the frequency of the desired wave. When the terminal on the side having the inductor 61 of the feedback circuit 6 shown in FIG. 6 shown by a broken line is removed from the input terminal of the transconductor circuit 2 and connected to an ideal ground potential, the gain is temporarily increased at an unnecessary wave frequency. Therefore, the NF value becomes a local maximum value. On the other hand, at 24 GHz, it was estimated that 4.06 dB and substantially the same characteristics as those without the feedback circuit 6 could be realized. The characteristics of the feedback circuit 6 shown in FIG. 6 indicated by the alternate long and short dash line are that noise is greatly deteriorated at the unnecessary wave frequency, while NF is 4.78 dB at the required frequency of 24 GHz, and NF is deteriorated by the application of the feedback circuit 6. However, low noise characteristics can still be maintained.

  From the characteristics shown in FIG. 7, it has become clear that the effect of the basic configuration of the first embodiment shown in FIG. 1 can be confirmed also in the configuration of FIG. 6 using bipolar transistors.

Next, another configuration example of the feedback circuit 6 is shown in FIG. The configuration including the inductor L1, the capacitance C1, and the capacitance C2 is a third-order notch filter, but is a configuration 62a in which the capacitance value of the capacitance C2 is not fixed but variable. The variable capacitor C2 is configured by connecting in parallel a series connection circuit of switches SW1 to SWn that can be opened and closed by the control terminals of the capacitors C2 _{1 to} C2 _n and the control voltages VSW1 to VSWn. The variability of the capacitance value is realized by individually connecting connection switches / switches SW1 to SWn to / from the ground potential for small capacitors from C2 ₁ to C2 _n obtained by dividing C2. The changeover switch is controlled by the control voltages VSW1 to VSWn. The change-over switch is configured by connecting the gate of the FET type transistor to the control voltage input terminal, and connecting the drain and source to the small capacitors C2 _{1 to} C2 _n and the ground potential. The number of small-capacity divisions can be determined in accordance with the variable range and variable resolution of the desired frequency f _wanted of the notch filter and the frequency f _image that attenuates unwanted wave components. By using the feedback circuit 6 of this configuration example and changing the capacitance of C2, the notch characteristic of the feedback circuit 6 and the notch characteristic of the amplifier circuit can be made variable. Specifically, by changing the capacitance C2, the desired frequency and the frequency at which the unwanted wave component is attenuated can be simultaneously shifted in the same direction.

  FIG. 9 shows the frequency dependence of the gain when the configuration example of the feedback circuit 6 shown in FIG. 8 is used in the amplifier circuit shown in FIG. By changing the value of the capacitor C2 to 49 fF, 64 fF, 81 fF, and 100 fF, as shown in FIG. 9, both the frequency of the gain peak in the amplifier circuit and the frequency at which the gain attenuation characteristic occurs can be shifted in the same direction. . From the above results, it is possible to vary the frequency of the gain peak of the amplifier circuit and the frequency at which the gain attenuation characteristic is generated by making the elements constituting the feedback circuit 6 variable. It is apparent that the image removal function can be realized and can be used as a means for compensating for characteristic variations caused by variations in the semiconductor process for creating the amplifier circuit.

<< Third Embodiment >>
A third embodiment of the present invention will be described with reference to FIGS.

  FIG. 10 is a diagram showing a configuration of an amplifier circuit with an unnecessary wave suppression function formed on a semiconductor chip of a semiconductor integrated circuit according to the third embodiment of the present invention. The amplifier circuits 301 and 403 shown in FIG. 10 are configured to enable differential signal input and differential signal output, and have two input matching circuits (MCIN) 1a and 1b, a differential transconductor circuit (GMC) 2a, The circuit includes two cascode circuits (CASC) 3a and 3b, a differential load circuit (LOADC) 4a, two output matching circuits (MCOUT) 5a and 5b, and a differential feedback circuit (FBC) 6a. In addition to performing the functions shown in the first embodiment of the entire amplifier circuit, these components have a differential circuit configuration, so that they are amplified by common-mode signal components, power supply voltages, and bias voltages between differential inputs. There is a feature that fluctuations in circuit characteristics can be suppressed.

  That is, in this differential type amplifier circuit with unnecessary wave suppression function, the input matching circuits 1a and 1b are circuits that generate a predetermined matching impedance with respect to the output impedance of the previous stage at the input terminal. The differential transconductor circuit 2a is connected to the output terminals of the input matching circuits 1a and 1b, and outputs a differential current proportional to the conductance with respect to the differential input voltage applied from the input matching circuits 1a and 1b. It is a circuit to output. The cascode circuits 3a and 3b are connected to the differential output terminal of the differential transconductor circuit 2a, take in the input current applied from the differential transconductor circuit 2a with a low input impedance, and output proportional to the input current. This circuit outputs positive current with high output impedance. The differential load circuit 4a is connected to the output terminals of the cascode circuits 3a and 3b, and converts the differential input current applied from the cascode circuits 3a and 3b into a differential voltage signal. The output matching circuits 5a and 5b are circuits that are connected to the differential input terminal of the differential load circuit 4a and generate a predetermined matching impedance with respect to the input impedance of the next stage. The differential feedback circuit 6a has a differential input terminal connected to the differential input terminal of the differential transconductor circuit 2a, and a differential output terminal connected to the differential output terminal of the differential transconductor circuit 2a. Circuit. The input terminals of the input matching circuits 1a and 1b are configured as differential input terminals 101a and 101b with the outside, and the output terminals of the output matching circuits 5a and 5b are configured as differential output terminals 102a and 102b with the outside.

  FIG. 11 shows a configuration example of the differential load circuit 4a used in the differential type amplifier circuit with unnecessary wave suppression function of FIG. The differential load circuit 4a includes inductors 41a and 41b. One terminal of the inductor 41a is a positive-phase input (contact 204a side) of the differential input terminal of the differential load circuit 4a, and one of the inductors 41b is connected. The terminal is set as a reverse-phase input (contact 204b side) of the differential input terminal of the differential load circuit 4a, and the other terminal of the inductor 41a and the other terminal of the inductor 41b are connected to stabilize the differential load circuit 4a. A power supply voltage terminal 103 for applying a potential is used, and an inductive coupling is provided between the inductors 41a and 41b.

  As described above, the differential load circuit 4a includes the two inductors 41a and 41b that are differentially coupled with each other with the mutual inductance M (M> 0), whereby the effective differential inductance is converted into the self-inductance. It can be set larger than LL. Therefore, in order to realize a required differential inductor, the self-inductance can be set smaller than the case where the mutual inductance cannot be obtained. When the load circuit is configured with spiral inductance, the occupied area on the integrated circuit can be reduced.

  FIG. 12 shows a configuration example of the differential feedback circuit 6a used in the differential amplifier circuit with unnecessary wave suppression function of FIG. The differential feedback circuit 6a includes capacitors 62a, 62b, 63a, 63b and inductors 61a, 61b. One terminal of the capacitor 63a is connected to the positive phase output (contact 202a) of the differential output terminal of the differential feedback circuit 6a. 203a side), the other terminal of the capacitor 63a is connected to one terminal of the capacitor 62a, the other terminal of the capacitor 62a is grounded, and one terminal of the inductor 61a is connected to one terminal of the capacitor 62a, The other terminal of the inductor 61a is the positive phase input (contact 201a side) of the differential input terminal of the differential feedback circuit 6a, and one terminal of the capacitor 63b is the opposite phase of the differential output terminal of the differential feedback circuit 6a. Output (contact 202b, 203b side), the other terminal of the capacitor 63b is connected to one terminal of the capacitor 62b, the other terminal of the capacitor 62b is grounded, and the other terminal of the inductor 61b is connected to the capacitor 62b. Connected to one terminal, the other terminal of the inductor 61b is a reverse phase input (contact 201b side) of the differential input terminal of the differential feedback circuit 6a, and has an inductive coupling between the inductors 61a and 61b. Is done.

  As described above, the differential feedback circuit 6a forms a feedback circuit by the two inductors 61a and 61b and the capacitors 62a, 62b, 63a, and 63b that are differentially coupled by the mutual inductance M (M> 0). Regarding the two inductors 61a and 61b, the differential inductance can be set larger than the self-inductance Lc. Therefore, in order to realize a required differential inductor, the self-inductance can be set smaller than the case where the mutual inductance cannot be obtained. When the feedback circuit is configured with spiral inductance, the occupied area on the integrated circuit can be reduced.

  Note that the differential feedback circuit 6a may have a configuration in which capacitances variability are given to the capacitors 62a and 62b, similarly to the feedback circuit shown in FIG.

  FIG. 13 shows a configuration example of the differential transconductor circuit 2a used in the differential amplifier circuit with unnecessary wave suppression function of FIG. The differential transconductor circuit 2a includes n-type bipolar transistors (T1a) 21a and (T1b) 21b, resistors 23a and 23b, inductors 22a and 22b, and a constant current source circuit 24. The base of the transistor 21a is differentially provided. The differential input terminal of the type transconductor circuit 2a is the positive phase input (contact 201a side), the base of the transistor 21b is the negative phase input of the differential input terminal of the differential type transconductor circuit 2a (contact 201b side), and the transistor The collector of 21a is the positive phase output (contact 202a side) of the differential output terminal of the differential transconductor circuit 2a, and the collector of the transistor 21b is the negative phase output (contact of the differential output terminal of the differential transconductor circuit 2a). 202b), and connect one terminal of the resistor 23a to the base of the transistor 21a. One terminal of the resistor 23b is connected to the base of the transistor 12b, and the other terminal of the resistor 23a is connected to the other terminal of the resistor 23b to form the bias voltage terminal 104 of the differential transconductor circuit 2a. The emitter is connected to one terminal of the inductor 22a, the emitter of the transistor 21b is connected to one terminal of the inductor 22b, and the other terminal of the inductor 22a is connected to the other terminal of the inductor 22b to connect the constant current source circuit 24. And having an inductive coupling between the inductors 22a and 22b.

  As described above, the differential transconductor circuit 2a includes the two inductors 22a and 22b that are differentially coupled with each other by the mutual inductance M (M> 0), thereby obtaining an effective differential inductance. It can be set larger than the self-inductance LE. Therefore, in order to realize a required differential inductor, the self-inductance can be set smaller than the case where the mutual inductance cannot be obtained. When the transconductor circuit is configured with the spiral inductance, the occupied area on the integrated circuit can be reduced.

  The differential transconductor circuit 2a may be an n-type field effect transistor instead of the n-type bipolar transistor.

<< Fourth Embodiment >>
A fourth embodiment of the present invention will be described with reference to FIG.

  FIG. 14 is a diagram showing a specific configuration of an amplifier circuit with an unnecessary wave suppression function formed on a semiconductor chip of a semiconductor integrated circuit according to the fourth embodiment of the present invention. The amplifier circuits 301 and 403 shown in FIG. 14 include the input matching circuit (MCIN) 1, the transconductor circuit (GMC) 2, the cascode circuit (CASC) 3, and the load circuit (LOADC) described in the first embodiment. 4. In addition to the basic components of the output matching circuit (MCOUT) 5 and the feedback circuit (FBC) 6, a stabilizing circuit (STBC) that operates stably as an amplifier circuit and suppresses the occurrence of an oscillation phenomenon at a characteristic frequency. 7 is comprised.

  The input matching circuit 1 and the output matching circuit 5 are composed of passive elements having capacitors 11, 12, 51, and 52. Each of the matching circuits can be arbitrarily designed independently of the configuration of the feedback circuit 6 so as to realize noise matching, power matching, or matching that satisfies a plurality of matching factors at a frequency that requires matching.

  The transconductor circuit 2 and the cascode circuit 3 are configured by n-type field effect transistors 21 and 31. In particular, in the transconductor circuit 2, an inductor 22 is inserted into the source of the transistor 21 to improve noise characteristics. The bias voltage terminal 104 determines the voltage applied to the gate of the transistor 21 and is based on the assumption that a stable potential is supplied. The bias voltage terminal 105 is provided to give a stable potential to the gate potential of the transistor 31 operating as the cascode circuit 3. Note that the transconductor circuit 2 using field effect transistors is not limited to a circuit configuration in which an inductor is inserted in the source.

  The load circuit 4 is configured by an inductor 41. However, depending on the operating frequency, the load circuit 4 is realized by an arbitrary passive element network configured by one or more inductors and one or more capacitors in order to generate a specific impedance. .

  The stabilization circuit 7 is a circuit that generates a loss so that the entire amplifier circuit does not oscillate at a specific frequency. In order to prevent an increase in power consumption, a capacitor 72 is sandwiched in series and a resistor 71 is used.

  The feedback circuit 6 uses a circuit configuration in which the third-order notch filter shown in FIG. 5 is realized by one inductor 61 and two capacitors 62 and 63. As described above, a desired frequency that allows a signal to pass through the notch impedance is used. There is no problem even if an arbitrary number of one or more frequencies for attenuating unnecessary wave components is set.

  In the present embodiment, the n-type bipolar transistors of the transconductor circuit 2 and the cascode circuit 3 are replaced with n-type field effect transistors in the configuration of the amplifier circuit shown in FIG. Therefore, a detailed description of the connection of the terminals of the transistors 21 and 31 is omitted, but the base, collector and emitter of the n-type bipolar transistor are simply replaced with the gate, drain and source of the n-type field effect transistor. The connection form is the same.

  By using the configuration example of FIG. 14, the power supply voltage applied to the power supply voltage terminal 103 can be set lower than that of the second embodiment (FIG. 6) using bipolar transistors. For example, when VTH of the field effect transistors of T1 and T2 is 0.4V and VGS of both is 0.6V, the minimum VDS value of T1 and T2 is 0.2V (= VGS−VTH), respectively. Therefore, it is possible to set the power supply voltage applied to the power supply voltage terminal 103 as low as about 0.4V. When the bipolar transistor is used for T1 and T2, the voltage between the collector and the emitter of the bipolar transistor is equal to the voltage between the base and the emitter. The power supply voltage to be applied requires about 1.8V. Therefore, the power supply voltage can be greatly reduced by using the field effect transistor.

  Note that the configuration in which an n-type field effect transistor is used as a transistor as in this embodiment is not limited to a single-phase amplifier circuit, and is similarly applied to a differential amplifier circuit as shown in FIG. It is possible.

<< Fifth Embodiment >>
A fifth embodiment of the present invention will be described with reference to FIG.

  FIG. 15 is a diagram showing a specific configuration of an amplifier circuit with an unnecessary wave suppression function formed in a semiconductor chip of a semiconductor integrated circuit according to the fifth embodiment of the present invention. FIG. 15 shows a two-stage cascade configuration of the amplifier circuit with an unnecessary wave suppression function of the present invention. That is, the amplifier circuit of this embodiment includes a first stage amplifier circuit (input terminal 101a, output terminal 102a, power supply voltage terminal 103a, bias voltage terminal 104a, bias voltage terminal 105a) and second stage amplifier circuit (input). Terminal 101b, output terminal 102b, power supply voltage terminal 103b, bias voltage terminal 104b, and bias voltage terminal 105b), using the feedback circuit shown in FIG. 8 in the configuration of the amplifier circuit shown in FIG. The output terminal 102a of the first stage amplifier circuit is connected to the input terminal 101b of the second stage amplifier circuit. Therefore, detailed description of the configuration and connection form of the first stage amplifier circuit and the second stage amplifier circuit is omitted.

  The configuration shown in FIG. 15 can increase the gain of the amplifier circuit. In addition, by setting the impedance characteristics of the two feedback circuits to different values, the realization range of the unwanted wave suppression characteristics is expanded. For example, by setting the notch characteristic of the feedback circuit 6 of the first stage amplifier circuit to a frequency of 18 GHz and setting the notch characteristic of the feedback circuit 6 of the second stage amplifier circuit to a frequency of 20 GHz, the notch bandwidth of the entire amplifier circuit is It can be expanded by about 18 GHz to 20 GHz, and a steep and broadband notch characteristic can be realized.

  Note that the configuration in which the amplifier circuits are cascade-connected as in the present embodiment is not limited to two stages, and may be three or more stages. The transistor may be a field effect transistor instead of the bipolar transistor. Further, the feedback circuit may be a fixed capacitor instead of the variable capacitor.

<< Sixth Embodiment >>
A sixth embodiment of the present invention will be described with reference to FIG.

  FIG. 16 shows a superheterodyne system to which the amplifier circuit with unnecessary wave suppression function shown in the first to fourth embodiments (corresponding to FIGS. 1, 6, 10 and 14) of the entire amplifier circuit is applied. It is a figure which shows the structure of a receiver. In the receiver of this embodiment, the amplifier circuit with an unnecessary wave suppression function of the above embodiment is applied to the first-stage amplifier circuit (LNAIR) 301 to which the input signal Sig-RF is input.

  The superheterodyne receiver shown in FIG. 16 has an amplification circuit (LNAIR) 301 with an unnecessary wave suppression function for amplifying an RF signal Sig-RF inputted from an RF input terminal, and an output signal of this amplification circuit 301 is generated locally. A reception mixer (MIX) 302 that converts the output signal of the oscillation circuit (LOVCO) 306 into an IF frequency signal, a bandpass filter (IFBPF) 303 for removing unnecessary waves from the output signal of the reception mixer 302, an IF frequency An IF amplifier circuit (IFAMP) 304 that performs band amplification and a demodulation circuit (DEMOD) 305 that demodulates a baseband signal component from the IF signal are included.

  According to the receiver of this embodiment, by using the amplifier circuit with the unnecessary wave suppression function of the above embodiment for the amplifier circuit 301, it is possible to sufficiently attenuate the image signal, and the super signal can be obtained without using external components. A heterodyne receiver can be configured, and the cost and area of the receiver can be reduced.

<< Seventh Embodiment >>
A seventh embodiment of the present invention will be described with reference to FIG.

  FIG. 17 shows a superheterodyne system to which the amplifier circuit with an unnecessary wave suppression function shown in the first to fourth embodiments (corresponding to FIGS. 1, 6, 10, and 14) of the entire amplifier circuit is applied. It is a figure which shows the structure of a transmitter. The transmitter according to the present embodiment includes a PA that attenuates the sideband RF signal component on one side in order to convert the double sideband RF signal after the baseband modulation signal is upconverted to the RF signal into a single sideband RF signal. The amplifier circuit with unnecessary wave suppression function of the above embodiment is applied to the driver amplifier circuit (AMPIR) 403.

  The superheterodyne transmitter shown in FIG. 17 includes a modulation circuit (MOD) 401 that digitally modulates the baseband signal Sig-BB input from the BB signal input terminal, and an output signal of the modulation circuit 401 as a local oscillation circuit. A transmission mixer (MIX) 402 that converts an output signal of (LOVCO) 405 into an RF frequency signal, an amplification circuit (AMPIR) 403 with an unnecessary wave suppression function that amplifies the output signal of the transmission mixer 402 and suppresses an unnecessary wave; A power amplifier circuit (PA) 404 that further amplifies the power of the output signal of the amplifier circuit 403 is included.

  According to the transmitter of this embodiment, the PA output signal can be output as a single sideband RF signal by using the amplifier circuit with unnecessary wave suppression function of the above embodiment for the amplifier circuit 403. Further, it is possible to sufficiently attenuate an unnecessary single sideband signal without using an external filter, and it is possible to configure a superheterodyne transmitter without using external components. The receiver shown in FIG. In the same manner, the cost and area of the transmitter can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the amplifying element used in the present invention is shown as a bipolar transistor, a heterojunction bipolar transistor or a field effect transistor. However, a MOS field effect transistor, a high electron mobility transistor, a metal semiconductor junction field effect transistor is used. It goes without saying that the same effect can be obtained even if the above is used.

  Further, the amplifier circuit shown in FIGS. 1, 6, 10 and 14 has a basic one-stage amplifier circuit configuration, but is configured by cascading a plurality of amplifier circuits, one or more of which are connected. The amplifier circuit with an unnecessary wave suppression function of the present invention can be used in this amplifier circuit.

1 is a diagram showing a configuration of an amplifier circuit with an unnecessary wave suppression function formed on a semiconductor chip of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is an equivalent circuit diagram for analyzing an unnecessary wave suppression ratio in the configuration of FIG. 1. It is an equivalent circuit diagram for analyzing the unwanted wave suppression ratio in the amplifier circuit studied as a premise of the present invention. It is an equivalent circuit diagram for analyzing the unnecessary wave suppression ratio in another amplifier circuit examined as a premise of the present invention. FIG. 4 is a circuit diagram (a) showing a configuration of a feedback circuit used in the first embodiment of the present invention and a diagram (b) showing frequency dependence of the impedance of the feedback circuit obtained by a circuit simulator. It is a figure which shows the structure of the amplifier circuit with an unnecessary wave suppression function formed in the semiconductor chip of the semiconductor integrated circuit by the 2nd Embodiment of this invention. FIG. 7 is a diagram illustrating a calculation result obtained by obtaining a gain characteristic (a) and a noise characteristic (b) by a circuit simulator in the configuration of FIG. 6. It is a circuit diagram which shows the structure of another feedback circuit used in the 2nd Embodiment of this invention. It is a figure which shows the frequency dependence of the gain of the amplifier circuit with an unnecessary wave suppression function at the time of using the feedback circuit shown in FIG. It is a figure which shows the structure of the amplifier circuit with an unnecessary wave suppression function formed in the semiconductor chip of the semiconductor integrated circuit by the 3rd Embodiment of this invention. It is a figure which shows the structure of the differential type | mold load circuit used in the 3rd Embodiment of this invention. It is a figure which shows the structure of the differential type feedback circuit used in the 3rd Embodiment of this invention. It is a figure which shows the structure of the differential type | mold transconductor circuit used in the 3rd Embodiment of this invention. It is a figure which shows the structure of the amplifier circuit with an unnecessary wave suppression function formed in the semiconductor chip of the semiconductor integrated circuit by the 4th Embodiment of this invention. It is a figure which shows the structure of the amplifier circuit with an unnecessary wave suppression function formed in the semiconductor chip of the semiconductor integrated circuit by the 5th Embodiment of this invention. FIG. 10 is a diagram illustrating a configuration of a superheterodyne receiver to which a single-phase or differential amplifier circuit with an unnecessary wave suppression function is applied in a sixth embodiment of the present invention. In the 6th Embodiment of this invention, it is a figure which shows the structure of the transmitter of a superheterodyne system to which the amplification circuit with a single phase type or a differential type unnecessary wave suppression function is applied.

Explanation of symbols

1, 1a, 1b: Input matching circuit 2, 2a: Transconductor circuit 3, 3a, 3b: Cascode circuit 4, 4a: Load circuit 5, 5a, 5b: Output matching circuit 6, 6a: Feedback circuit 7: Stabilization circuit 101, 101a, 101b: input terminals 102, 102a, 102b: output terminals 103, 103a, 103b: power supply voltage terminals 104, 104a, 104b: bias voltage terminals 105, 105a, 105b: bias voltage terminals 301: amplifying circuit 302 : Reception mixer 303: band pass filter 304: IF amplifier circuit 305: demodulation circuit 306: local oscillation circuit 401: modulation circuit 402: transmission mixer 403: amplification circuit 404: power amplification circuit 405: local oscillation circuit

Claims (20)

An input matching circuit that generates a predetermined matching impedance for the output impedance of the previous stage at the input terminal;
A conductor circuit that is connected to an output terminal of the input matching circuit and outputs a current proportional to conductance in positive phase with respect to an input voltage applied from the input matching circuit;
A cascode circuit connected to the output terminal of the conductor circuit, taking in an input current applied from the conductor circuit as an input impedance, and outputting an output current proportional to the input current in a positive phase with an output impedance;
A load circuit connected to an output terminal of the cascode circuit and converting an input current applied from the cascode circuit into a voltage signal;
An output matching circuit that is connected to the input terminal of the load circuit and generates a predetermined matching impedance for the input impedance of the next stage;
A feedback circuit having an input terminal connected to the input terminal of the conductor circuit and an output terminal connected to the output terminal of the conductor circuit;
Comprising
An amplifying circuit comprising: an input terminal of the input matching circuit as an external input terminal; and an output terminal of the output matching circuit as an external output terminal. In claim 1,
An amplifying circuit, further comprising a stabilizing circuit connected to an input terminal of the load circuit and generating a resistive power loss in a specific frequency range. In claim 1,
The feedback circuit has a frequency band that generates one or more high impedances and a frequency band that generates one or more low impedances in the impedance appearing between the input terminal and the output terminal. Amplifying circuit. In claim 1,
The feedback circuit includes an input terminal, an output terminal, and one or more control terminals, a frequency band that generates one or more high impedances in an impedance appearing between the input terminal and the output terminal, and one or more A frequency band that generates a low impedance, and a frequency band that generates the high impedance and a frequency band that generates the low impedance by a control signal that is applied to the one or more control terminals. An amplification circuit characterized by being variable. In claim 1,
In the amplifier circuit, the frequency band in which the gain of the amplifier circuit is maximized and the gain of the amplifier circuit are locally minimized in accordance with the frequency dependence of the impedance appearing between the input terminal and the output terminal of the feedback circuit. An amplifying circuit comprising: setting a frequency band capable of suppressing unnecessary wave signals. In claim 1,
The feedback circuit includes a first capacitor, a second capacitor, and a first inductor. One terminal of the first capacitor is used as an output terminal of the feedback circuit, and the other terminal of the first capacitor is used. Is connected to one terminal of the second capacitor, the other terminal of the second capacitor is grounded, one terminal of the first inductor is connected to one terminal of the second capacitor, An amplifier circuit comprising the other terminal of the first inductor as an input terminal of the feedback circuit. In claim 1,
The feedback circuit includes a first capacitor, a first variable capacitor, and a first inductor. One terminal of the first capacitor is used as an output terminal of the feedback circuit, and the other terminal of the first capacitor is used. A terminal is connected to one terminal of the first variable capacitor, the other terminal of the first variable capacitor is grounded, and one terminal of the first inductor is connected to one terminal of the first variable capacitor. The other terminal of the first inductor is the input terminal of the feedback circuit, the control terminal of the first variable capacitor is the control terminal of the feedback circuit,
The first variable capacitor is characterized in that the capacitance value of the entire variable capacitor is made variable by connecting in series a series connection circuit of one or more switches that can be opened and closed by a capacitor and a control terminal. Amplifying circuit. In claim 1,
The input matching circuit includes a first capacitor and a second capacitor. One terminal of the first capacitor is used as an input terminal of the input matching circuit, and the other terminal of the first capacitor is used as the first capacitor. Connected to one terminal of the capacitor of 2 to serve as the output terminal of the input matching circuit, the other of the second capacitor is grounded,
The conductor circuit includes a first n-type bipolar transistor, a first resistor, and a first inductor, and a base of the first n-type bipolar transistor is used as an input terminal of the conductor circuit. The collector of the n-type bipolar transistor is used as the output terminal of the conductor circuit, one terminal of the first inductor is connected to the emitter of the first n-type bipolar transistor, and the other terminal of the first inductor is connected. A terminal is grounded, one terminal of the first resistor is connected to a base of the first n-type bipolar transistor, and the other terminal of the first resistor is used as a bias terminal of the conductor circuit;
The cascode circuit includes a second n-type bipolar transistor, supplies a stable first potential to a base of the second n-type bipolar transistor, and an emitter of the second n-type bipolar transistor. As the input terminal of the cascode circuit, and the collector of the second n-type bipolar transistor as the output terminal of the cascode circuit,
The load circuit includes a second inductor, supplies a stable second potential to one terminal of the second inductor, and uses the other terminal of the second inductor as an input terminal of the load circuit. Consisting of
The output matching circuit includes a third capacitor and a fourth capacitor. One terminal of the third capacitor is used as an input terminal of the output matching circuit, and the other terminal of the third capacitor is used as the first capacitor. 4 is connected to one terminal of the capacitor 4 as the output terminal of the output matching circuit, the other terminal of the fourth capacitor is grounded,
The stabilizing circuit includes a second resistor and a fifth capacitor, one terminal of the second resistor is connected to an input terminal of the load circuit, and the other terminal of the second resistor is connected to the second resistor. An amplifier circuit connected to one terminal of a fifth capacitor and having the other terminal of the fifth capacitor grounded. In claim 1,
The input matching circuit includes a first capacitor and a second capacitor. One terminal of the first capacitor is used as an input terminal of the input matching circuit, and the other terminal of the first capacitor is used as the first capacitor. Connected to one terminal of the capacitor of 2 to serve as the output terminal of the input matching circuit, the other of the second capacitor is grounded,
The conductor circuit includes a first n-type field effect transistor, a first resistor, and a first inductor, the gate of the first n-type field effect transistor is used as an input terminal of the conductor circuit, and the first The drain of the n-type field effect transistor is used as the output terminal of the conductor circuit, one terminal of the first inductor is connected to the source of the first n-type field effect transistor, and the other terminal of the first inductor is connected. A terminal is grounded, one terminal of the first resistor is connected to a gate of the first n-type field effect transistor, and the other terminal of the first resistor is configured as a bias terminal of the conductor circuit;
The cascode circuit includes a second n-type field effect transistor, supplies a stable first potential to a gate of the second n-type field effect transistor, and a source of the second n-type field effect transistor. As the input terminal of the cascode circuit, and the drain of the second n-type field effect transistor as the output terminal of the cascode circuit,
The load circuit includes a second inductor, supplies a stable second potential to one terminal of the second inductor, and uses the other terminal of the second inductor as an input terminal of the load circuit. Consisting of
The output matching circuit includes a third capacitor and a fourth capacitor. One terminal of the third capacitor is used as an input terminal of the output matching circuit, and the other terminal of the third capacitor is used as the first capacitor. 4 is connected to one terminal of the capacitor 4 as the output terminal of the output matching circuit, the other terminal of the fourth capacitor is grounded,
The stabilizing circuit includes a second resistor and a fifth capacitor, one terminal of the second resistor is connected to an input terminal of the load circuit, and the other terminal of the second resistor is connected to the second resistor. An amplifier circuit connected to one terminal of a fifth capacitor and having the other terminal of the fifth capacitor grounded. In claim 1,
The amplifier circuit is formed by cascading two or more of the amplifier circuits and setting independent unnecessary wave suppression characteristics. First and second input matching circuits for generating a predetermined matching impedance for the output impedance of the previous stage at the input terminal;
Connected to the output terminals of the first and second input matching circuits, and outputs a differential current proportional to conductance in positive phase with respect to the differential input voltage applied from the first and second input matching circuits. A differential conductor circuit;
First and second terminals connected to a differential output terminal of the differential conductor circuit, taking an input current applied from the differential conductor circuit as an input impedance, and outputting an output current proportional to the input current as a positive phase with an output impedance. Two cascode circuits;
A differential load circuit that is connected to output terminals of the first and second cascode circuits and converts a differential input current applied from the first and second cascode circuits into a differential voltage signal;
First and second output matching circuits connected to the differential input terminal of the differential load circuit and generating a predetermined matching impedance for the input impedance of the next stage;
A differential feedback circuit in which a differential input terminal is connected to a differential input terminal of the differential conductor circuit, and a differential output terminal is connected to a differential output terminal of the differential conductor circuit;
Comprising
The input terminals of the first and second input matching circuits are differential input terminals to the outside, and the output terminals of the first and second output matching circuits are differential output terminals to the outside. Amplifying circuit. In claim 11,
An amplifier circuit further comprising first and second stabilizing circuits connected to the differential input terminals of the differential load circuit and generating resistive power loss in a specific frequency range. In claim 11,
The feedback circuit has a frequency band that generates one or more high impedances and a frequency band that generates one or more low impedances in the impedance appearing between the input terminal and the output terminal. Amplifying circuit. In claim 11,
The feedback circuit includes an input terminal, an output terminal, and one or more control terminals, a frequency band that generates one or more high impedances in an impedance appearing between the input terminal and the output terminal, and one or more A frequency band that generates a low impedance, and a frequency band that generates the high impedance and a frequency band that generates the low impedance by a control signal that is applied to the one or more control terminals. An amplification circuit characterized by being variable. In claim 11,
In the amplifier circuit, the frequency band in which the gain of the amplifier circuit is maximized and the gain of the amplifier circuit are locally minimized in accordance with the frequency dependence of the impedance appearing between the input terminal and the output terminal of the feedback circuit. An amplifying circuit comprising: setting a frequency band capable of suppressing unnecessary wave signals. In claim 11,
The feedback circuit includes first, second, third, fourth capacitors, and first and second inductors, and one terminal of the first capacitor is connected to a positive output terminal of the feedback circuit. Phase output, the other terminal of the first capacitor is connected to one terminal of the second capacitor, the other terminal of the second capacitor is grounded, and the one terminal of the first inductor is connected Connected to one terminal of the second capacitor, the other terminal of the first inductor as a positive phase input of the differential input terminal of the feedback circuit, and one terminal of the third capacitor as the feedback circuit The second output terminal of the third capacitor is connected to one terminal of the fourth capacitor, the other terminal of the fourth capacitor is grounded, and the second capacitor output terminal is connected to the second terminal. One terminal of the second inductor is connected to one terminal of the fourth capacitor, and the other terminal of the second inductor Amplifier circuit, characterized in that the negative input of the differential input terminals of the feedback circuit, comprising a inductive coupling between the first and second inductors. In claim 11,
The feedback circuit includes first and second capacitors, first and second variable capacitors having one or more capacitance control terminals, and first and second inductors, and one of the first capacitors. The terminal is a positive phase output of the differential output terminal of the feedback circuit, the other terminal of the first capacitor is connected to one terminal of the first variable capacitor, and the other terminal of the first variable capacitor is connected Is grounded, one terminal of the first inductor is connected to one terminal of the first variable capacitor, and the other terminal of the first inductor is connected to the positive phase input of the differential input terminal of the feedback circuit. And one terminal of the second capacitor is a reverse phase output of the differential output terminal of the feedback circuit, the other terminal of the second capacitor is connected to one terminal of the second variable capacitor, The other terminal of the second variable capacitor is grounded, and one terminal of the second inductor is connected to the second variable capacitor. One terminal of a variable capacitor is connected, and the other terminal of the second inductor is used as a negative-phase input of a differential input terminal of the feedback circuit, and the first and second variable capacitors each have one or more The frequency dependence of the differential impedance appearing between the differential input terminal and the differential output terminal of the feedback circuit is made variable by the voltage applied to the capacitance control terminal, and inductive coupling is established between the first and second inductors. An amplifier circuit comprising: an amplifier circuit; In claim 11,
The differential load circuit includes first and second inductors, and one terminal of the first inductor is a positive phase input of a differential input terminal of the differential load circuit, and the second inductor One terminal is used as a negative phase input of the differential input terminal of the differential load circuit, and the other terminal of the first inductor and the other terminal of the second inductor are connected to stabilize the differential load circuit. A power supply terminal for providing a high potential, and having an inductive coupling between the first and second inductors,
The differential conductor circuit includes first and second n-type bipolar transistors, first and second resistors, third and fourth inductors, and a constant current source circuit. The base of the type transistor is a positive phase input of the differential input terminal of the differential conductor circuit, the base of the second n-type bipolar transistor is a negative phase input of the differential input terminal of the differential conductor circuit, and The collector of the first n-type bipolar transistor is the positive phase output of the differential output terminal of the differential conductor circuit, and the collector of the second n-type bipolar transistor is the differential output terminal of the differential conductor circuit. A negative phase output is provided, one terminal of the first resistor is connected to a base of the first n-type bipolar transistor, and one terminal of the second resistor is connected to the second n-type bipolar transistor. A first transistor connected to the base of the first transistor, the other terminal of the first resistor connected to the other terminal of the second resistor to serve as a bias application terminal of the differential conductor circuit; The emitter of the bipolar transistor is connected to one terminal of the third inductor, the emitter of the second n-type bipolar transistor is connected to one terminal of the fourth inductor, and the third inductor And the other terminal of the fourth inductor is connected to the constant current source circuit, and inductive coupling is provided between the third and fourth inductors. Amplifying circuit. In claim 11,
The differential load circuit includes first and second inductors, and one terminal of the first inductor is a positive phase input of a differential input terminal of the differential load circuit, and the second inductor One terminal is used as a negative phase input of the differential input terminal of the differential load circuit, and the other terminal of the first inductor and the other terminal of the second inductor are connected to stabilize the differential load circuit. A power supply terminal for providing a high potential, and having an inductive coupling between the first and second inductors,
The differential conductor circuit includes first and second n-type field effect transistors, first and second resistors, third and fourth inductors, and a constant current source circuit, and includes the first n-type electric field circuit. The gate of the effect transistor is a positive phase input of the differential input terminal of the differential conductor circuit, the gate of the second n-type field effect transistor is a negative phase input of the differential input terminal of the differential conductor circuit, and The drain of the first n-type field effect transistor is a positive-phase output of the differential output terminal of the differential conductor circuit, and the drain of the second n-type field effect transistor is the differential output terminal of the differential conductor circuit. A negative phase output is provided, one terminal of the first resistor is connected to the gate of the first n-type field effect transistor, and one terminal of the second resistor is connected to the second n-type field effect transistor. Gate And connecting the other terminal of the first resistor to the other terminal of the second resistor to serve as a bias application terminal of the differential conductor circuit, and the source of the first n-type field effect transistor is Connected to one terminal of the third inductor, connected to the source of the second n-type field effect transistor to one terminal of the fourth inductor, and connected to the other terminal of the third inductor and the first 4. An amplifier circuit comprising: an inductor connected to the other terminal of the four inductors and connected to the constant current source circuit; and an inductive coupling between the third and fourth inductors. In claim 11,
The amplifier circuit is formed by cascading two or more of the amplifier circuits and setting independent unnecessary wave suppression characteristics.

Images