JP2009283603A - Detection apparatus, light-receiving element array, and fabrication process therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an InGaAs light-receiving element array which has photosensitivity in a wavelength region exceeding 1.7 μm, and a low dark current, and to provide its fabrication process and a detection apparatus using the InGaAs light-receiving element array. <P>SOLUTION: A light-receiving element array comprises: an InGaAs light-receiving layer 3 having In composition exceeding 0.53; an InAsP window layer 4, located in contact with the InGaAs light-receiving layer and having a p-type total thickness portion or a thickness portion on the reverse side of a substrate; and an n-type isolation region 19 extending from the p-type InAsP window layer to reach the inside of the InGaAs light-receiving layer and formed by introducing n-type impurities to surround the light-receiving region of the light-receiving element. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a detection device, a light receiving element array, and a manufacturing method thereof, and more specifically, a light receiving element array having light receiving sensitivity in the near infrared region, a manufacturing method thereof, an imaging device and a sensor including the light receiving element, and the like The present invention relates to a detection device.

Since the near-infrared wavelength region corresponds to the absorption spectrum related to living organisms such as animals and plants and the environment, development of light-receiving elements in the near-infrared to infrared region using III-V compound semiconductors in the light-receiving layer is actively conducted. Has been done. Among them, an In _0.53 Ga _0.47 As semiconductor (cut-off wavelength 1.7 μm) lattice-matched to an InP substrate can obtain a good crystal, so that one-dimensional or A light-receiving element array arranged two-dimensionally has been developed (Non-Patent Document 1). Further, in order to expand the light receiving sensitivity to a longer wavelength region, a general explanation has been made on a light receiving element having an In composition higher than 0.53 (Non-patent Document 2). This explanation includes a light receiving element having an In composition of 0.53 or less.

Since an InGaAs light receiving layer having an In composition exceeding 0.53 cannot be lattice-matched with the InP substrate, a method of forming the InGaAs light receiving layer by gradually changing the lattice constant through the graded buffer layer on the InP substrate. Has been proposed (Patent Document 1). However, with the method in which the graded buffer layer is interposed, a sufficiently good crystal cannot be obtained, and as a result, it is difficult to reduce the dark current to a practical level. For this reason, in the configuration in which the In composition is high and the lattice matching with the InP substrate is not performed, a pn junction is formed in the InP window layer instead of the structure in which the pn junction is provided in the InGaAs light receiving layer, and the depletion layer is formed in the InP window layer A limiting structure has been proposed (Patent Document 2). According to this structure, the photocharge generated by the light reception generated in the light receiving layer moves to the depletion layer by diffusion, and then moves by the electric field in the depletion layer to generate a photocurrent, thereby reducing the dark current. it can.
ARSugg, MJLange, MHEttenberg, MJCohen, GHOlsen, "InGaAs / InP lineardetector arrays for spectroscopic and imaging applications on 75 mm substrates", 1998 IEEE ThH5,9 9:15 am-9:30am,pp.73-74 Akimasa Tanaka, "Recent Progress of Eye-Safe Wavelength and Mid-Infrared Detectors", Laser Research, Vol. 25, No. 1, pp 25-28 JP 2002-373999 A JP 2002-151727 A

  When a light receiving element in the near-infrared region is put into practical use in the field of view of an imaging device or the like, an array of light receiving elements is essential, and the dark current must be lowered in the state of the light receiving element array. However, when the light receiving elements are arrayed, a large dark current that cannot be predicted from the dark current in a single light receiving element occurs. In the method of Patent Document 2, only a part of the window layer on the surface side is made p-type and a depletion layer is provided in the window layer to reduce dark current. However, sufficient sensitivity cannot be obtained. If the reverse bias voltage is increased in order to extend the depletion layer to the light receiving layer, the dark current resulting from the reverse bias voltage increases. In particular, in the light receiving element array, the dark current due to the increase of the reverse bias voltage becomes large.

  An object of the present invention is to provide an InGaAs light receiving element array having a light receiving sensitivity in a wavelength region exceeding 1.7 μm and a low dark current, a manufacturing method thereof, and a detection apparatus using the InGaAs light receiving element array.

In the light receiving element array of the present invention, a plurality of light receiving elements are arranged in one epitaxial laminated body of III-V group compound semiconductor formed on an InP substrate. The light receiving element array includes an InGaAs light receiving layer having an In composition exceeding 0.53, a p-type InAsP window layer in contact with the InGaAs light receiving layer and positioned on the opposite side of the InP substrate across the InGaAs light receiving layer, and a p type And an n-type isolation region formed by introducing an n-type impurity so as to surround the light-receiving region of the light-receiving element from the InAsP window layer into the InGaAs light-receiving layer.

  According to the above configuration, the p-type InAsP window layer portion of the light receiving region is surrounded by the n-type isolation region between the adjacent light receiving elements, so that the p-type InAsP window layer portion of the adjacent light receiving region is made of p-type impurities. There is no fear of being connected in distribution, and separation can be ensured. Thereby, since there is no electrical short circuit between adjacent light receiving elements, a light receiving element array for the near infrared region with a small dark current can be obtained. The n-type isolation region is formed by introducing an n-type impurity. Unlike the introduction of an impurity for forming a pn junction, the n-type isolation region is introduced so as to surround a light-receiving region portion of the pn junction that is an already formed interface. Therefore, even when the image is blurred in the lateral direction, the short circuit between the light receiving elements is not promoted at all, and the n-type isolation region simply spreads and spreads. Therefore, as described above, the InGaAs light receiving layer is not lattice-matched to the InP substrate, the lattice defect density of the InGaAs light receiving layer and the p-type window layer is high, and the dark current is suppressed in the light receiving element array that is likely to cause abnormal diffusion. Is particularly effective.

The p-type carrier concentration of the p-type InAsP window layer can be a 1 × 10 ¹⁶ / cm ³ or more 3 × 10 ¹⁸ / cm ³ or less. By setting the p-type carrier concentration of the window layer to 1 × 10 ¹⁶ / cm ³ or more, the contact resistance between the p-side electrode provided in the p-type InAsP window layer and the p-side InAsP window layer is not excessive, and is constant. The voltage component of the voltage power supply can be efficiently applied to the pn junction in the light receiving region. The higher the p-type carrier concentration in the window layer, the lower the contact resistance. However, if the p-type carrier concentration is too high, a very large amount of n-type impurities must be introduced when forming the n-type isolation region. Cause problems. If the p-type carrier concentration of the window layer is 3 × 10 ¹⁸ / cm ³ or less, an n-type impurity can be introduced into the window layer having the p-type carrier concentration to make it n-type relatively easily.

  The n-type carrier concentration value in the InGaAs light receiving layer can be made smaller than the p-type carrier concentration value in the InAsP window layer. As a result, the InGaAs light-receiving layer is depleted without applying a reverse voltage so high, the dark current is reduced, and near-infrared light in a wavelength region exceeding 1.7 μm can be received with high sensitivity.

  The n-type isolation region can be formed by selective diffusion of n-type impurities. As a result, a high-quality n-type isolation region can be formed by a relatively simple method in which a mask pattern for selective diffusion is formed using conventional lithography, and the diffusion material and the InP substrate are then vacuum sealed and heat-treated. Can be formed.

  The n-type isolation region can also be formed by ion implantation of n-type impurities. As a result, the n-type isolation region can be formed easily and quickly.

  The In composition of the InGaAs light receiving layer can be 0.6 or more and 0.85 or less. This makes it possible to obtain light receiving sensitivity for near infrared light in a wavelength region exceeding 1.8 μm while using an InP substrate.

  A graded buffer layer composed of a plurality of layers can be interposed between the InP substrate and the InGaAs light receiving layer. As a result, an epitaxial layer of an InGaAs light receiving layer having an In composition greater than 0.53 that does not lattice match with the InP substrate can be formed on the InP substrate without increasing the dark current.

  The space between the light receiving elements can be 2 μm or more and 40 μm or less. This configuration enables high integration. For example, by setting the arrangement pitch of the light receiving elements to 20 μm or more and 50 μm or less, it becomes possible to obtain several two-dimensional arrays of the 100,000 pixel class on a 2-inch wafer, considering the yield. However, the prospect of practical use can be obtained.

  The method for manufacturing a light receiving element array according to the present invention is a method for manufacturing a light receiving element array in which a plurality of light receiving elements are arranged in one epitaxial laminated body of III-V group compound semiconductors located on an InP substrate. This method includes a step of forming an InGaAs light receiving layer having an In composition exceeding 0.53 on an InP substrate, a step of forming a p-type InAsP window layer in contact with the InGaAs light receiving layer, Forming an n-type isolation region so that an n-type impurity reaches the InGaAs light-receiving layer and surrounds the light-receiving region from the InAsP window layer around the light-receiving region.

  According to the above manufacturing method, since the light receiving region is surrounded by the n-type isolation region between the adjacent light receiving elements, the p-type InAsP window layer portion of the adjacent light receiving region is connected by the distribution of the p-type impurity. There is no fear and separation can be ensured. Thereby, since there is no electrical short circuit between adjacent light receiving elements, a light receiving element array for the near infrared region with a small dark current can be obtained. The n-type isolation region is formed by introducing an n-type impurity. Unlike the introduction of an impurity for forming a pn junction, the n-type isolation region is introduced so as to surround a light-receiving region portion of the pn junction that is an already formed interface. Therefore, even when the image is blurred in the lateral direction, the short circuit between the light receiving elements is not promoted at all, and the n-type isolation region simply spreads and spreads. For this reason, in the above manufacturing method, the InGaAs light receiving layer is not lattice-matched to the InP substrate, the lattice defect density of the InGaAs light receiving layer and the p-type window layer is high, and the dark current of the light receiving element array that is likely to cause abnormal diffusion is suppressed. It is beneficial to.

  The detection device of the present invention is a detection device such as an imaging device or a sensor, and includes any one of the light receiving element arrays described above or the light receiving element array manufactured by the manufacturing method described above, and receives a signal from each light receiving element. A CMOS that outputs a read electrical signal is provided. As a result, a detection device having the characteristics of each of the light receiving element arrays can be obtained.

  According to the present invention, it is possible to obtain an InGaAs light receiving element array having a light receiving sensitivity in a wavelength region exceeding 1.7 μm and a low dark current, and a manufacturing method thereof.

(Embodiment 1)
FIG. 1 is a plan view of an imaging device using the light receiving element array 50 according to the first embodiment of the present invention as viewed from the light incident side. Although the number of elements, element size, etc. are shown, they are merely examples. In this example, 640 × 512 light receiving elements 10 are arranged in an array size of 20 mm wide × 16 mm long. 2 is a cross-sectional view taken along line II-II in FIG. This imaging device 50 has an epi-down mounting in which the window layer 4 or the p-side electrode 12 side is electrically connected to a CMOS multiplexer by bonding bumps 22, that is, a back-side incident arrangement. In the case of a two-dimensional array of light receiving elements, it is not preferable to cross the wiring from the p-side electrode of each light receiving element on the light incident side, so that a back-incident structure is adopted.

The laminated structure of the light receiving element array 50 in FIG. 2 is formed in the following order from the back surface side to the epitaxial layer side.
(AR (Anti-Reflection) film 29 / InP substrate 1 / n-type graded buffer layer 2 / undoped or low-concentration n-type InGaAs light receiving layer 3 / p-type InAsP window layer 4 / n-type impurity selective diffusion mask pattern 5 / Insulating protective film 9)
The p-type InAsP window layer 4 has an n-type isolation region 19 formed by n-type impurities diffused and introduced so as to reach the InGaAs light receiving layer 3 from the opening of the n-type impurity selective diffusion mask pattern 5. Therefore, the InAsP window layer 4 is formed of an n-type isolation region 19 and a p-type region 15 surrounded by the n-type isolation region 19. This p-type region 15 corresponds to the light receiving region 10 a of the light receiving element 10.

  In the selective diffusion of n-type impurities, it is necessary to introduce n-type impurities exceeding the p-type carrier concentration of the p-type InAsP window layer epitaxially grown on the InGaAs light receiving layer 3 to form an n-type region. The n-type isolation region 19 surrounds the light receiving region 10a of the light receiving element 10 and separates adjacent light receiving elements. The light receiving region 10 a of the light receiving element 10 substantially corresponds to the p-type region 15 surrounded by the n-type isolation region 19.

  At the time of selective diffusion for forming the n-type isolation region 19, an n-type impurity, for example, Sn may be diffused in the lateral direction, and an n-type impurity concentration distribution may exist in a portion close to the p-type region 15. However, even if there is a considerable amount of n-type impurity diffusion in the lateral direction, the p-type location is advantageous as the location where the photocharge moves in the light receiving region 10a. The dark current does not increase. A pn junction is formed between the p-type region 15 and the n-type isolation region 19, and a potential barrier is formed against the photocharge. Therefore, the adjacent light receiving elements 10 are separated by the n-type isolation region 19.

  The n-side electrode 11 is electrically connected to the n-type graded buffer layer 2 so as to be grounded in common to all the light receiving elements 10. Further, the p-side electrode 12 is electrically connected to the p-type region 15 for each light receiving element 10 and serves as an electrode for individually reading an optical signal from the light receiving element. The light receiving element array 50 is connected to the bonding bump 22 located on the electrode pad of the CMOS 21 for each light receiving element 10 through the p-side electrode 12. The CMOS 21 reads out the photoelectrically converted charge from the light receiving element 10 as a pixel signal, then converts the charge signal into a voltage signal, amplifies it, and outputs it to the signal processing unit.

(1) InGaAs light receiving layer 3 and graded buffer layer 2
The InGaAs light receiving layer 3 shown in FIG. 2 is In _0.8 Ga _0.2 As having an In composition larger than 0.53 in order to make the cutoff wavelength larger than 1.7 μm. That is, 0.8 the In composition in order to reduce the band gap energy, as a result, the lattice constant is larger than the In _0.53 Ga _0.47 As the In composition 0.53 to lattice matching with the InP substrate 1. For this reason, In _0.8 Ga _0.2 As does not lattice match with the InP substrate 1, and if grown on the InP substrate 1 as it is, the lattice defect density becomes very high, or the light receiving layer which can be called an epitaxial layer is formed. Difficult to get. Therefore, the graded buffer layer or the step buffer layer 2 is interposed so as to gradually increase from the lattice constant of the InP substrate 1 to the lattice constant of the In _0.8 Ga _0.2 As light receiving layer 3. However, the graded buffer layer 2 that is laminated while gradually increasing the lattice constant for each layer, however, always has a difference in lattice constant from the underlayer even if it is laminated with dozens of layers. It is sequentially increased and accumulated. For this reason, the In _0.8 Ga _0.2 As light-receiving layer 3 with very good crystallinity cannot be obtained. For this reason, the dark current cannot be reduced so as not to cause a problem at a practical level. The In _0.8 Ga _0.2 As light receiving layer 3 can have light receiving sensitivity up to a wavelength of 2.6 μm.

(2) Problems in the conventional light receiving element array (see FIG. 8)
The above (1) is a problem even with a single light receiving element, but the conventional light receiving element array 150 has the following problem. 8, by the interposition of graded buffer layer 102, and is In _0.8 Ga _0.2 As light receiving layer 103 can be obtained epitaxial film while poor crystallinity, in contact with the In _0.8 Ga _0.2 As light-receiving layer 103 formed Since the window layer thus taken over inherits the lattice defects of the underlying In _0.8 Ga _0.2 As light-receiving layer 103, as described above, it does not become a very good crystalline epitaxial layer. In order to form the pn junction 117, when selectively diffusing Zn of the p-type impurity, the temperature and time are set so as to reach the In _0.8 Ga _0.2 As light receiving layer 103 through the InAs _0.63 P _0.37 window layer 104. At this time, since the lattice defect density of the InAs _0.63 P _0.37 window layer 104 is high, Zn is considered to diffuse through the lattice defects at a rate higher than the diffusion rate in the normal crystal. For example, it is known that the diffusion rate of atoms is higher when diffusing at a crystal grain boundary having a higher lattice defect density than when diffusing inside a crystal grain.

  Since the amount of impurities diffused through such lattice defects is small compared to the amount of impurities diffused in the crystal, this is a serious problem in terms of diffusion in the depth direction for forming a pn junction. Don't be. However, even if the amount of Zn that diffuses laterally through lattice defects is small, it is a serious problem in the light receiving element array 150 in which adjacent light receiving elements are arranged at a short pitch. In the case of the light receiving element array 150, if Zn diffuses into the adjacent light receiving element 110 and continues with the adjacent p-type region 115, an electrically shorted state occurs, and the dark current becomes large. That is, when the p-type wiring is formed by the Zn distribution extending in the lateral direction, the p-type region 115 of the light receiving element 110 is connected, and the dark current becomes large. In order to solve this problem, the present invention aims to reduce dark current in a light receiving element array having light receiving sensitivity to near infrared light in a long wavelength region exceeding a cutoff wavelength of 1.7 μm. The points of the embodiment of the present invention are as follows.

(3) Points of the Embodiment of the Present Invention FIG. 3 is a diagram for explaining the points of the embodiment of the present invention. The configuration shown in FIG. 3 is characterized by the following point (P1).
(P1) The p-type region 15 of the p-type InAsP window layer 4 is surrounded by an n-type isolation region 19 that reaches from the surface of the InAsP window layer 4 to the InGaAs light-receiving layer 3, thereby separating the light receiving elements 10. The n-type isolation region 19 may be formed by any method, and may be formed by selective diffusion like the conventional p-type region 115, for example. Even if lateral diffusion is promoted by using selective diffusion to form the n-type isolation region 19 due to the high lattice defect density in the crystal, the photocharge can be read out to the p-side electrode 12. Has no effect. For dark current, even if there is lateral diffusion, separation between the light receiving elements becomes more reliable, so it may be preferable to a predetermined limit.

Next, a method for manufacturing the light receiving element array 50 shown in FIG. 1 will be described with reference to FIGS.
(1) The n-type graded buffer layer 2 is formed on the InP substrate 1 by OMVPE (Organic Metal Vapor Phase Epitaxy). At this time, the difference between the lattice constant of InP and the lattice constant of the In _0.8 Ga _0.2 As light receiving layer 3 is preferably divided into several tens of steps to form several tens of graded buffer layers 2. The InP substrate 1 is preferably made n-type by S doping when the n-side electrode 11 is connected. In addition, as shown in FIG. 2, when the n-side electrode 11 is connected to the layer of the n-type graded buffer layer 2 in contact with the light-receiving layer 3, only that layer may be n-type, The graded buffer layer 2 may be n-type.
(2) Next, the In _0.8 Ga _0.2 As light-receiving layer 3 is epitaxially grown on the graded buffer layer 2 to a thickness of about 2 μm to 6 μm. The growth method may be anything as long as it can be epitaxially grown, and the OMVPE method is also MBE (Molecular
Beam Epitaxy) method is also acceptable. As described above, the In _0.8 Ga _0.2 As light receiving layer 3 has light receiving sensitivity to light having a wavelength of 2.0 μm to 2.6 μm. The In _0.8 Ga _0.2 As light-receiving layer 3 is preferably undoped or has an n-type carrier concentration of low concentration of 1 × 10 ¹⁶ / cm ³ or less.
(3) Thereafter, a p-type InAs _0.63 P _0.37 window layer 4 is epitaxially formed on the In _0.8 Ga _0.2 As light-receiving layer 3. The thickness is, for example, 0.8 μm or less. This growth method may be anything as long as it can be epitaxially grown. The p-type carrier concentration is preferably 1 × 10 ¹⁶ / cm ³ or more and 3 × 10 ¹⁸ / cm ³ or less as described above. It is an important point in the embodiment of the present invention that the InAsP window layer 4 has the p-type carrier concentration. Note that the window layer 4 may be replaced with InAlAs. Further, the buffer layer 2 can also be a plurality of graded buffer layers in which the In composition of InAlAs is changed stepwise or a single layer having a predetermined In composition.

(4) SiN is deposited by an evaporation method, and an n-type impurity, for example, a Sn selective diffusion mask pattern 5 is formed by a photolithography method and etching. As shown in FIG. 5A, the selective diffusion mask pattern 5 at this time covers a region corresponding to the light receiving region 10a of the light receiving element, and the periphery thereof is an open (no SiN layer) pattern. N-type impurities should not be diffused and introduced into the light receiving region 10a. For example, Sn is diffused and introduced so as to form the n-type isolation region 19 only in the surrounding region. The introduction of n-type impurities by selective diffusion may be replaced with an ion implantation method.
(5) Next, Sn is selectively diffused so as to reach the InGaAs light receiving layer 3 from the opening of the Sn selective diffusion mask pattern 5 to form the n-type isolation region 19. At this time, a vacuum sealed tube (quartz) is used as a diffusion processing chamber, and the InP substrate on which the above epitaxial laminated structure and the selective diffusion mask pattern are formed is sealed in a quartz tube together with an n-type impurity material, and selective diffusion is performed. When the n-type impurity Sn is selectively diffused, it is preferable to use an n-type impurity material obtained by adding In to twice the amount of Sn saturated at 600 ° C. InP-containing Sn is loaded into a quartz tube together with the InP substrate, and is evacuated and sealed. The quartz tube is put in an electric furnace and heated to 600 ° C., and Sn is introduced so as to reach the InGaAs light receiving layer 3 through the InAsP window layer 4 from the opening (around the light receiving region). By this selective diffusion, an n-type isolation region 19 is formed. For example, the light receiving region 10a may be a regular square having a side of 15 μm as shown in FIG. For example, a pixel region in which 640 pixels × 512 pixels are arranged at a pitch of 25 μm is formed (see FIG. 1). For example, on a 2 inch diameter InP substrate 1, several pixel regions in which 640 pixels in the horizontal direction and 512 pixels in the vertical direction are arranged are provided. As a result, several 300,000 pixel class two-dimensional arrays can be arranged on a 2-inch wafer, and the 300,000 pixel class two-dimensional array can be put into practical use even in consideration of yield.
(6) After selective diffusion of Sn (state shown in FIG. 5A), as shown in FIG. 5B, an insulating protective film 9 is formed, and the n-type isolation region 19 and Sn of the InAsP window layer 4 are formed. The selective diffusion mask pattern 5 is covered. Next, a resist film 37 is formed on the insulating protective film 9. Next, as shown in FIG. 5C, a selective diffusion mask is included so as to be included in the p-type region 15 in order to make the p-side electrode 12 contact the p-type region 15 by photolithography and etching. 5. An opening 37 h is provided in the insulating protective film 9 and the resist film 37. FIG. 5D is a diagram showing a state where the p-side electrode 12 is provided in ohmic contact with AuZn in the opening 37h and the resist pattern 37 is lifted off. Further, the n-side electrode 11 is formed of AuGeNi so as to be in ohmic contact with the surface in contact with the light receiving layer 3 of the graded buffer layer 2 so that the ground potential is common to all the light receiving elements. Further, an SiON film having a refractive index of 1.8 and a film thickness of 330 nm is formed on the entire surface as the AR film 29 on the back surface of the InP substrate 1.

  The light receiving element array 50 manufactured by the above procedure has a light receiving sensitivity in the near infrared region exceeding 1.7 μm, and low dark current even if several pixel regions of 400,000 pixel class are provided on a 2-inch wafer. An imaging device can be obtained. The point where such a light receiving element array 50 is possible is that the InGaAs light receiving layer 3 and the p-type InAsP window layer 4 form a hetero pn junction 17, and the n type that reaches around the light receiving region into the InGaAs light receiving layer 3. This is because it is surrounded by the separation region 19.

(Embodiment 2)
FIG. 6 is a plan view showing a one-dimensional light receiving element array 50 according to Embodiment 2 of the present invention. FIG. 7 is a sectional view taken along line VII-VII in FIG. As shown in FIG. 6, in this light receiving element array 50, elongated light receiving elements 10 each having a size of 12 μm × 1 mm are arranged in a one-dimensional manner at a pitch of 20 μm along a direction orthogonal to the longitudinal direction. The planar shape of the light receiving element array 50 is, for example, a rectangle of 8 mm wide × 2 mm long. A connection structure of the p-side electrode 12, the wiring electrode 27, and the pad portion 25 is disposed at one end of the light receiving element 10. The pad portion 25 is connected to the CMOS read electrode by wire bonding. And the connection structure of said p side electrode 12, the wiring electrode 27, and the pad part 25 is arrange | positioned so that it may become alternately upper and lower in FIG. 5 between adjacent light receiving elements. The p-side electrode 12 corresponds to one light receiving unit or unit light receiving unit. In the one-dimensional array, for example, a total of 384 light receiving units are arranged in a row at a pitch of 20 μm.

  As shown in FIG. 7, the stacked structure is the same as that of the two-dimensional array shown in FIG. 2, but the two-dimensional array is back-side incident, that is, epi-down mounting, whereas the one-dimensional array of FIG. The difference is that the top surface incidence, that is, epi-up mounting. However, in the two-dimensional arrangement, it is unavoidable that the incident light is on the back surface, but in the one-dimensional arrangement, the light can be incident on the back surface or the top surface. Among the electrodes, the p-side electrode 12 is arranged at the end of the light receiving element as described above in order to employ the top incidence. The n-side electrode 11 is provided on the back surface of the S-doped n-type InP substrate 1. The material for forming the p-side electrode 12 and the n-side electrode 11 can be the same as in the first embodiment.

  The InAsP window layer 4 includes p-type carriers having a medium concentration or more, and each light receiving region 10a is surrounded by the n-type isolation region 19 as in the first embodiment. Therefore, the InAsP window layer 4 is also composed of a portion constituting the p-type region 15 and an n-type isolation region 19 positioned so as to surround the periphery thereof, as in the case of the two-dimensional array shown in FIG. .

  From the above, the characteristics of the configurations of the one-dimensional array and the two-dimensional array are the same. As a result, the one-dimensional light receiving element array in the present embodiment also has light receiving sensitivity in a wavelength region exceeding 1.7 μm, and darkness. A light receiving element array with a low current can be obtained.

Next, the function and effect of the light receiving element array of the present invention will be verified by examples. Test specimens were prepared for two examples of the present invention and a comparative example.
(Example of the present invention): For the four types in which the shape of the light receiving element shown in FIGS. 1 and 2 is 15 μm square and the space between the light receiving elements (see FIG. 3) is changed to 1 μm, 5 μm, 10 μm, and 15 μm, An imaging device was produced.
(1) The p-type InAs0.63P0.37 window layer 4 was made p-type by Zn doping. The p-type carrier concentration was 1 × 10 ¹⁸ / cm ³ .
(2) The n-type isolation region 19 was formed by selectively diffusing Sn. As described above, selective diffusion of Sn was performed by vacuum-sealing Sn containing excessive InP together with a wafer on which a selective diffusion mask pattern was formed, and heating to 600 ° C. The doping amount of Sn was 3 × 10 ¹⁸ / cm ³ . As the n-type impurity, Si or S may be used instead of Sn, and ion implantation may be used regardless of selective diffusion.
(3) The n-type carrier concentration of the low-concentration n-type In _0.8 Ga _0.2 As light-receiving layer 3 was 1 × 10 ¹⁶ / cm ³ .
(4) The AR film 29 was made of SiON so as to overlap the light receiving region.

(Comparative example): The light receiving element array 150 shown in FIG. 8 was produced. Differences from the example of the present invention are as follows.
(1) The In _0.8 Ga _0.2 As light-receiving layer 103 was undoped, and its n-type carrier concentration was 5 × 10 ¹⁵ / cm ³ .
(2) The window layer 104 was formed of InAs _0.63 P _0.37 having a thickness of 1.2 μm, and the n-type carrier concentration was 1 × 10 ¹⁵ / cm ³ . That is, the thickness is 1.7 times that of the example of the present invention, and the n-type carrier concentration is 1/50.
(3) The selective diffusion of Zn for forming the p-type region 115 was performed by vacuum-sealing the Zn raw material together with the wafer on which the selective diffusion mask pattern 105 was formed, and performing heat treatment.

(Evaluation methods):
(1) Measurement of dark current when a voltage of -1 V is applied (2) ± 10 mV RoA (product of shunt resistance and light receiving area)

(Measurement result):
1. Dark current (Fig. 9)
When the space between adjacent light receiving elements 10 (space between light receiving elements) is 1 μm, the dark current becomes extremely large in both the present invention example and the comparative example. However, although the example of the present invention is bad, the dark current is surely lower than that of the comparative example.
When the space between the light receiving elements is 5 μm, the dark current in the example of the present invention is about 5 × 10 ⁻⁸ A, and it can be seen that the dark current is significantly reduced as compared with the comparative example of 1 × 10 ⁻⁶ A. When the distance between the light receiving elements is 1 μm, it is considered that an electrical short circuit with an adjacent light receiving element cannot be prevented depending on the structure according to the example of the present invention.
2. RoA (Figure 10)
Regarding RoA, which is an index of sensitivity, as in the case of dark current, in the case of a space of 1 μm between the light receiving elements, the example of the present invention was about 15 Ωcm ² , which was inferior. Moreover, about the comparative example, it was 0.1 ohm-cm < ² > when the said space is 1 micrometer. As in the case of dark current, the example of the present invention is better than the comparative example even though the example of the present invention is low when the space is 1 μm.
In the space 5μm or more, RoA becomes 90Omucm ² or more in the present invention example, the better. In contrast, in the comparative example, a 0Ωcm around ² even space 5 [mu] m, the first several [Omega] cm ² approximately becomes a space 10 [mu] m.
From the relationship between the above dark current and RoA and the space between the light receiving elements, it was confirmed that the characteristics of the inventive example were qualitatively improved as compared with the comparative example.

(Other embodiments)
1. In the above embodiment, a structure in which the graded buffer layer is interposed between the InP substrate and the InGaAs light receiving layer is illustrated. A single buffer layer may be used. Further, if the In composition is low or if there is no such condition, the buffer layer may be omitted if the InGaAs light receiving layer can be epitaxially grown.
2. In the above embodiment, the structure of back-surface incidence is shown in the case of a two-dimensional light-receiving element array, and the top-surface incidence is shown in the case of a one-dimensional light-receiving element array. , It is not an essential problem. However, in the two-dimensional light receiving element array, it is better to make the light incident on the back surface so that the incident light to each light receiving region is not affected by the readout wiring of the pixel signal.
3. The window layer is exemplified only when the total thickness layer is p-type, but the window layer may be p-type on the side opposite to the InP substrate, that is, on the surface side opposite to the InGaAs light receiving layer. Considering the sensitivity of light in the long-wavelength region in the near infrared region, it is preferable that the entire thickness layer is p-type, but the applications of the light receiving element array of the present invention are very diverse. There is also an application in which light sensitivity is not so required and priority is given to more complete separation between light receiving elements.

  Although the embodiments and examples of the present invention have been described above, the embodiments and examples of the present invention disclosed above are merely examples, and the scope of the present invention is the implementation of these inventions. It is not limited to the form. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

  According to the present invention, it is possible to obtain an InGaAs light receiving element array having a light receiving sensitivity in a wavelength region exceeding 1.7 μm, in which dark current is reduced by a simple mechanism, and development of a high-resolution near-infrared light imaging device. Is expected to contribute.

It is a top view which shows the imaging device using the light receiving element array in Embodiment 1 of this invention. It is sectional drawing which follows the II-II line of the light receiving element array of FIG. It is a figure for demonstrating the point of the invention in this Embodiment. It is a figure which shows the manufacturing method of the light receiving element array of FIG. It is a top view which shows the surface from the mask pattern pattern for selective diffusion to p side electrode formation, (a) is a mask pattern for selective diffusion, and the stage which carried out the diffusion introduction of Sn of n type impurity, (b) (C) shows the step of forming a resist pattern having an opening for the p-side electrode, and (d) lifts off the resist pattern by forming the p-side electrode. It is a figure which shows each step. It is a top view which shows the light receiving element array in Embodiment 2 of this invention. It is sectional drawing which follows the VII-VII line of the light receiving element array of FIG. It is sectional drawing of the imaging device using the conventional light receiving element array which is a comparative example in an Example. It is a figure which shows the relationship between the dark current (measured value) of the imaging device of the example of this invention and a comparative example, and the space between light receiving elements. It is a figure which shows the relationship between RoA (measured value) of the imaging device of the example of this invention and a comparative example, and the space between light receiving elements.

Explanation of symbols

1 InP substrate, 2 buffer layer, 3 InGaAs light receiving layer, 4 window layer, 5 Zn selective diffusion mask pattern, 9 insulating protective film, 10 light receiving element, 10a light receiving region, 11 n side electrode, 12 p side electrode, 15 p Type region, 17 hetero pn junction, 19 n type isolation region, 21 CMOS (Multiplexer), 22 junction bump, 25 pad portion, 27 wiring electrode, 29 AR (Anti-Reflection) film, 37 p side electrode forming resist pattern, 37h opening, 50 imaging device.

Claims (10)

A light receiving element array in which a plurality of light receiving elements are arranged in one epitaxial layered body of III-V compound semiconductor formed on an InP substrate,
An InGaAs light-receiving layer having an In composition exceeding 0.53;
A p-type InAsP window layer that is in contact with the InGaAs light receiving layer and is located on the opposite side of the InP substrate across the InGaAs light receiving layer;
An n-type isolation region formed by introducing an n-type impurity so as to reach the InGaAs light-receiving layer from the InAsP window layer and surround the light-receiving region of the light-receiving element. 2. The light receiving element array according to claim 1, wherein a p-type carrier concentration of the p-type region of the InAsP window layer is 1 × 10 ¹⁶ / cm ³ or more and 3 × 10 ¹⁸ / cm ³ or less.   3. The light receiving element array according to claim 1, wherein an n type carrier concentration value in the InGaAs light receiving layer is smaller than a p type carrier concentration value in a p type region of the InAsP window layer.   The light receiving element array according to claim 1, wherein the n-type isolation region is formed by selective diffusion of n-type impurities.   The light receiving element array according to claim 1, wherein the n-type isolation region is formed by ion implantation of an n-type impurity.   6. The light receiving element array according to claim 1, wherein an In composition of the InGaAs light receiving layer is 0.6 or more and 0.85 or less.   The light receiving element array according to any one of claims 1 to 6, wherein a graded buffer layer including a plurality of layers is interposed between the InP substrate and the InGaAs light receiving layer.   The light receiving element array according to claim 1, wherein a space between the light receiving elements is 2 μm or more and 40 μm or less. A method of manufacturing a light-receiving element array in which a plurality of light-receiving elements are arranged on one epitaxial stacked body of a group III-V compound semiconductor located on an InP substrate,
Forming an InGaAs light-receiving layer having an In composition exceeding 0.53 on the InP substrate;
Forming a p-type InAsP window layer in contact with the InGaAs light-receiving layer;
And a step of forming an n-type isolation region so that an n-type impurity reaches the InGaAs light-receiving layer and surrounds the light-receiving region from the InAsP window layer. . A detection device such as an imaging device or a sensor, comprising: the light receiving element array according to any one of claims 1 to 8; or the light receiving element array manufactured by the manufacturing method according to claim 9. A detection apparatus comprising a CMOS (Complementary Metal Oxide Semiconductor) that reads a signal from an element and outputs an electrical signal.

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