JP2009128678A - Image display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display panel capable of restraining a metal thin film in a gate line driving circuit from being corroded. <P>SOLUTION: In this liquid crystal panel 300 of the present invention, an array substrate 100 formed with the gate line driving circuit 160 is bonded with a color filter substrate 200 to be opposed each other via a seal 350, and contact holes 217a, 217b of the gate line driving circuit are coated with an oriented film 270 extended from a display area DA. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image display panel, and is particularly suitable for application to a liquid crystal display panel employing an amorphous silicon thin film transistor in a gate line driving circuit having a contact hole.

  In an image display panel such as a liquid crystal display device, as a gate line driving circuit (scanning line driving circuit) for scanning the display panel, a shift register that performs a shift operation that makes a round in one frame period of a display signal is used. it can. The shift register is preferably composed only of field effect transistors of the same conductivity type in order to reduce the number of steps in the manufacturing process of the display device.

  A liquid crystal display device in which a shift register of a gate line driving circuit is composed of an amorphous silicon thin film transistor (hereinafter referred to as “a-Si TFT”) is easy to increase in area and has high productivity. For example, a notebook PC, a portable information terminal (PDA), multimedia player (PMP), and simple car navigation system (PND: Personal Navigation Device) screens (see Non-Patent Document 1).

Further, in order to narrow the frame of the image display panel used in the liquid crystal display device, the vicinity of the sealing material formed so that the gate line driving circuit surrounds the periphery of the liquid crystal display panel or a part of the driving circuit is made of the sealing material. It is necessary to place it below.
The gate line driving circuit has a large number of contact holes for connecting different kinds of metal wirings. The contact hole is for electrically connecting the first metal thin film and the second metal thin film formed in different layers, the contact hole formed on the first metal thin film, and the second metal thin film. Some of them have contact holes formed on them, and the contact holes are bridged by a conductive film.
A transparent conductive film such as ITO is generally used as a material for the conductive film that connects the metal wirings opened by the contact holes. Since this ITO film has poor coverage characteristics (see Patent Document 1), there is a portion of the contact hole where the metal thin film is not covered with the transparent conductive film and the metal thin film is exposed.
Near the inside of the sealing material and under the sealing material, it is easily affected by moisture, impurities, etc. Impurities come into contact. And wiring, a terminal, an electrode, etc. which consist of a metal thin film will be corroded by oxidation. (Hereafter, the corrosion phenomenon of the metal wiring near the contact hole is referred to as contact hole corrosion.)

  In particular, in the case of a gate line driving circuit composed of a-si TFTs, the signal amplitude in the circuit is very large, for example, if the High voltage is 24V and the Low voltage is -6V, the potential difference is 30V. Contact hole corrosion is a major problem.

  In addition, this poor coverage characteristic of the ITO film occurs very frequently, particularly when a process is used in which the ITO film is formed amorphous and then crystallized. In general, wet etching with a chemical is often used for patterning an ITO film. In the case of a crystalline ITO film, it is necessary to use a strong acid comprising a hydrochloric acid + nitric acid aqueous solution as a chemical solution used for wet etching. In such a case, if a metal thin film such as Al, Ag, or Mo coexists as a gate signal line, a source signal line, or a reflective electrode, the metal thin film is corroded during wet etching of the ITO film. There was a fear.

  On the other hand, in the case of an amorphous ITO film, wet etching can be performed with a weak acid such as an oxalic acid aqueous solution. For this reason, even if metal thin films such as Al, Ag, or Mo coexist, these metal thin films are not corroded. Therefore, first, an ITO film is formed in an amorphous state, patterned using an oxalic acid etchant, and then crystallized using, for example, a heating means, and finally chemically stabilized. It is preferable to use the process.

However, when the ITO film undergoes a phase change from the amorphous state to the crystallized state, volume shrinkage (the distance between crystal atoms becomes small) accompanying the change from the disordered arrangement structure of atoms to the ordered arrangement occurs. For this reason, since a tensile stress from the substrate is applied to the ITO film, a break in the ITO film is likely to occur particularly at a stepped portion such as a contact hole. As described above, covering the contact hole with the amorphous ITO film is good in terms of etching, but the coverage is not good. For this reason, the contact hole corrosion may be caused by the intrusion of moisture or impurities.
JP 11-281992 A Jin Young Choi, Jin Jeon, Jong Heon Han, Seob Shin, Se Chun Oh, Jun Ho Song, Kee Han Uh, and Hyung Guel Kim, `` A Compact and Cost-efficient TFT-LCD through the Triple-Gate Pixel Structure '', Pages 274-276, SID '06 DIGEST

  SUMMARY An advantage of some aspects of the invention is that it provides an image display panel that can suppress contact hole corrosion of a gate line driving circuit.

  The image display panel according to the present invention is bonded via a sealing material so that the first substrate on which the scanning line driving circuit is formed and the first substrate and the second substrate face each other. At least the contact hole of the scanning line driving circuit is covered with a resin film in the same layer as the display region.

  An image display panel capable of suppressing contact hole corrosion of a gate line driving circuit can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in order to avoid duplication and redundant description, elements having the same or corresponding functions are denoted by the same reference symbols in the respective drawings.

Embodiment 1 FIG.
FIG. 1 is a plan view of a liquid crystal display device according to Embodiment 1 of the present invention, and FIG. 2 is a cross-sectional view taken along line III-III in FIG. As shown in FIG. 1, a display device 400 according to the present embodiment includes a display panel 300 that displays an image, and source lines (data lines) that are included in the display panel 300 and output drive signals to the display panel 300. ) A driver IC 150 and a gate line driving circuit (scanning line driving circuit) 160.
Further, the display panel 300 includes a first transparent substrate 110, a plurality of gate lines (scan lines) (GL1 to GLn) disposed on the substrate, and a plurality of sources intersecting with the gate lines via an insulating film. Array substrate 100 (first array) composed of lines (data lines) (SL1 to SLm), a plurality of pixel electrodes PE arranged at intersections thereof, thin film transistors (hereinafter referred to as TFTs) for driving the pixel electrodes PE, and the like. One substrate), a color filter substrate 200 (second substrate) facing the array substrate 100, a liquid crystal layer 330 sandwiched between the array substrate 100 and the color filter substrate 200, and the liquid crystal layer 330 is configured by a sealing material 350 that holds the array substrate 100 and the color filter substrate 200 together.

Each output of the source line driver IC 150 is connected to each of the source lines (SL1 to SLm), and applies a source driving signal to each source line. Similarly, the outputs of the gate line driving circuit 160 are connected to the gate lines (GL1 to GLn), respectively, and apply a gate driving signal to each gate line. A counter electrode CE is formed on the surface of the color filter substrate 200 facing the array substrate, and the light transmittance of the liquid crystal layer 330 is controlled by an electric field generated between the pixel electrode PE. Further, an auxiliary capacitor C is disposed for each pixel between the drain electrode and the common electrode (not shown) of the TFT.
In FIG. 1, the pixel electrode PE1 disposed at the intersection of the first gate line GL1 and the first source line SL1 among the plurality of pixels arranged in a matrix corresponding to the display area DA for displaying an image. The connection diagram of the TFT (TR1), the counter electrode CE, and the auxiliary capacitor Cs1 is particularly shown, but the same applies to other pixels (not shown).

The display panel 300 includes the display area DA, a first peripheral area PA1 disposed so as to surround the display area DA, and a second peripheral area PA2 adjacent to the outside of the first peripheral area PAI.
As described above, the first to nth gate lines GL1 to GLn and the first to mth source lines SL1 to SLm are formed on the first transparent substrate 110 of the array substrate 100 corresponding to the display area DA. Is formed.
Of the plurality of TFTs, the gate electrode of the first TFT (TR1) is electrically connected to the first gate line GL1, and the source electrode of the first TFT (TR1) is electrically connected to the first source line SL1. The drain electrode of the TFT (TR1) is connected to the first pixel electrode PE1 and the first auxiliary capacitor Cs1 among the plurality of pixel electrodes.

As shown in FIG. 2, on the second transparent substrate 210 of the color filter substrate 200 corresponding to the display area DA, a color filter layer 220 including red, green and blue pixels R, G, B and A first light shielding layer 230 formed between two adjacent color pixels of red, green, and blue is disposed. In addition, a second light shielding layer 240 is disposed adjacent to the first light shielding layer 230 on the second transparent substrate 210 corresponding to the surrounding area PA1.
A transparent electrode (ITO film) 250 is provided on the color filter layer 220, the first light shielding layer 230, and a part of the first light shielding layer. The transparent electrode 250 applies voltage to the liquid crystal layer as a counter electrode with respect to the pixel electrode.
In FIG. 1 described above, the first light shielding layer 230, the first light shielding layer, the transparent electrode (ITO film) 250, and the alignment film 270 on the color filter substrate 200 are not illustrated because they are complicated.

  On the other hand, in the second peripheral area PA2, the first transparent substrate 110 extends longer than the second transparent substrate 210 (upward in the example of FIG. 1), and the source line driver IC 150 is mounted. Yes. The first drive signal output from the source line driver IC 150 includes first to mth source signals, and the first to mth sources are provided via a plurality of source line lead lines formed in the second peripheral area PA2. The voltage is applied to each of the source lines SL1 to SLm.

On the other hand, on one side (left side in FIG. 1) of the first peripheral area PA1 having a frame shape, the gate line driving circuit 160 generated simultaneously through the same process as the process of forming the plurality of TFTs and the display area DA is provided. Is arranged. The gate line driving circuit 160 is electrically connected to the first to nth gate lines GL1 to GLn formed in the display area DA. The gate driving signal output from the gate line driving circuit 160 includes first to nth gate signals (OUT1 to OUTn), and the first to nth gate signals include the first to nth gate lines GL1 to GL1. Applied to GLn.
In the color filter substrate 200 and the array substrate 100, the surface on which the color filter layer 220 and the counter electrode CE are formed and the surface on which the display area DA is formed are arranged to face each other, and the two substrates are fixed. The liquid crystal layer 330 is sandwiched together with the sealing material 350.
An alignment layer 270 is formed on the color filter substrate 200 and the array substrate 100. The alignment film 270 is a resin film such as polyimide. Here, as shown in FIG. 2, the alignment layer 270 on the array substrate 100 extends from the display area DA to cover the gate line driving circuit 160 (particularly, the contact hole portion), and is further covered with the sealing material 350. Although it is arranged like this, it does not penetrate the sealing material.

As a result of experiments conducted by the present inventors, it was confirmed that the contact hole corrosion is reduced by covering the contact hole of the gate drive circuit 160 with the alignment film 270. This is because the penetration of moisture and impurities into the contact hole is reduced by covering with the alignment film 270.
Further, the alignment film 270 is disposed so as not to come out of the sealing material 350. This is because if the alignment film 270 is taken out of the sealing material 350, moisture may be absorbed through the alignment film 270.

Further, as shown in FIG. 2, the display panel 300 of the present embodiment has a transparent electrode (ITO film) 250 formed on the color filter layer 220 sealed at least in an area where the gate drive circuit 160 exists. A region corresponding to the material 350 is removed by patterning, and is arranged so as not to go out of the seal material through the seal material 350.
As a result of experiments conducted by the present inventors, when the transparent electrode (ITO film) 250 is taken out of the sealing material, moisture permeates into the sealing material through the transparent electrode (ITO film) 250 and contact hole corrosion occurs. Was confirmed to accelerate. This is because moisture, impurities, and the like enter through the gap between the sealing material 350 and the ITO and through the ITO itself.

  Next, the circuit configuration and operation of the gate line driving circuit 160 will be described in detail with reference to FIGS. FIG. 3 is a diagram showing a configuration of a plurality of stages of the shift register portion constituting the gate line driving circuit. FIG. 4 is a circuit diagram showing the configuration of one stage (unit shift register) SRn of the shift register section constituting the gate line driving circuit. 3 includes n unit shift registers SR1, SR2, SR3,..., SRn connected in cascade, and a dummy unit shift register SRD provided further downstream of the last unit shift register SRn. (Hereinafter, the unit shift registers SR1, SR2,... SRn, SRD are collectively referred to as “unit shift register SR”). Each of the unit shift registers SR has the circuit configuration of FIG.

  Further, the clock generator 31 shown in FIG. 3 supplies two-phase clock signals CLKA and CLKB having opposite phases (the active periods do not overlap) to the plurality of unit shift registers SR. In the gate line driving circuit 160, these clock signals CLKA and CLKB are controlled to be activated in order at a timing synchronized with the scanning cycle of the display device 400.

  As shown in FIGS. 3 and 4, each unit shift register SR has an input terminal IN1, an output terminal OUT, a clock terminal CK1, and a reset terminal RST. Each unit shift register SR is supplied with the low-potential-side power supply potential VSS (= 0 V) via the first power-supply terminal S1, and is supplied with the high-potential-side power supply potential VDD via the second power-supply terminal S2. (Not shown in FIG. 3).

  As shown in FIG. 4, the output stage of the unit shift register SR includes a transistor Q1 connected between the output terminal OUT and the clock terminal CK1, and a transistor Q2 connected between the output terminal OUT and the first power supply terminal S1. It is configured. That is, the transistor Q1 is a transistor (first transistor) that supplies the clock signal CLKA input to the clock terminal CK1 to the output terminal OUT, and the transistor Q2 is a transistor that discharges the output terminal OUT (second transistor). . Hereinafter, a node to which the gate (control electrode) of the transistor Q1 is connected is defined as “node N1”, and a node to which the gate of the transistor Q2 is connected is defined as “node N2”.

  A capacitive element C1 is provided between the gate and source of the transistor Q1 (that is, between the node N1 and the output terminal OUT). The capacitive element C1 is an element (bootstrap capacitance) that capacitively couples the output terminal OUT and the node N1 and boosts the node N1 in response to a rise in the level of the output terminal OUT. However, the capacitor C1 can be replaced if the gate-channel capacitance of the transistor Q1 is sufficiently large, and may be omitted in such a case.

  A transistor Q3 whose gate is connected to the input terminal IN1 is connected between the node N1 and the second power supply terminal S2. A transistor Q4 whose gate is connected to the reset terminal RST is connected between the node N1 and the first power supply terminal S1. That is, the transistor Q3 constitutes a charging circuit that charges the node N1 according to the signal input to the input terminal IN1, and the transistor Q4 discharges the node N1 according to the signal input to the reset terminal RST. Is configured. The gate (node N2) of the transistor Q2 is also connected to the reset terminal RST.

  As shown in FIG. 3, the output terminal OUT of the preceding unit shift register SR is connected to the input terminal IN1 of each unit shift register SR. However, a predetermined start pulse ST is input to the input terminal IN1 of the unit shift register SR1, which is the first stage. One of the clock signals CLKA and CLKB is input to the clock terminal CK1 of each unit shift register SR so that clock signals having different phases are input to the unit shift registers SR adjacent to the front and rear.

  The output terminal OUT of the next unit shift register SR is connected to the reset terminal RST of each unit shift register SR. However, a predetermined end pulse EN is input to the reset terminal RST of the dummy unit shift register SRD provided in the next stage of the last unit shift register SRn. In the gate line driving circuit, the start pulse ST and the end pulse EN are input at timings corresponding to the beginning and end of each frame period of the image signal, respectively.

  Next, the operation of each unit shift register SR shown in FIG. 4 will be described. Basically, all the unit shift registers SR of each stage operate in the same manner, so here, the operation of the k-th unit shift register SRk among the multi-stage shift registers will be described as a representative. Assume that the clock signal CLKA is input to the clock terminal CK1 of the unit shift register SRk (for example, the unit shift registers SR1 and SR3 in FIG. 3 correspond to this).

  Here, it is assumed that the H level potential of the clock signals CLKA and CLKB is VDD (high potential side power source potential) and the L level potential is VSS (low potential side power source potential). The threshold voltage of each transistor Qx constituting the unit shift register SR is represented as Vth (Qx).

  FIG. 5 is a timing chart showing the operation of the unit shift register SRk (FIG. 4). First, as an initial state of the unit shift register SRk, it is assumed that the node N1 is at the L level (hereinafter, the state where the node N1 is at the L level is referred to as a “reset state”). The input terminal IN1 (previous output signal Gk-1), the reset terminal RST (next output signal Gk + 1), and the clock terminal CK1 (clock signal CLKA) are all at L level. At this time, since the transistors Q1 and Q2 are both off, the output terminal OUT is in a high impedance state (floating state). In the initial state, the output terminal OUT (output signal Gk) is also at L level.

  From that state, at time t1, when the clock signal CLKA changes to L level and the clock signal CLKB changes to H level, and the output signal Gk-1 of the previous stage (start pulse ST in the first stage) becomes H level, The transistor Q3 of the unit shift register SRk is turned on, and the node N1 is charged and becomes H level (hereinafter, the state where the node N1 is at H level is referred to as “set state”). At this time, the potential level of the node N1 (hereinafter simply referred to as “level”) rises to VDD−Vth (Q3). In response, transistor Q1 is turned on.

  At time t2, the clock signal CLKB changes to L level and the clock signal CLKA changes to H level, and the output signal Gk-1 in the previous stage becomes L level. Then, the transistor Q3 is turned off, and the node N1 is in the floating state with the H level. Since the transistor Q1 is on, the level of the output terminal OUT rises following the clock signal CLKA.

  When the levels of the clock terminal CK1 and the output terminal OUT rise, the level of the node N1 is boosted as shown in FIG. 5 by the coupling through the capacitance element C1 and the gate-channel capacitance of the transistor Q1. Since the boost amount at this time substantially corresponds to the amplitude (VDD) of the clock signal CLKA, the node N1 is boosted to approximately 2 × VDD−Vth (Q3).

  As a result, the voltage between the gate (node N1) and source (output terminal OUT) of the transistor Q1 is kept large even while the output signal Gk is at the H level. That is, since the on-resistance of the transistor Q1 is kept low, the output signal Gk follows the clock signal CLKA and rises at a high speed to become the H level. At this time, since the transistor Q1 operates in the linear region (non-saturated region), the level of the output signal Gk rises to the same VDD as the amplitude of the clock signal CLKA.

  Furthermore, when the clock signal CLKB changes to H level and the clock signal CLKA changes to L level at time t3, the on-resistance of the transistor Q1 is kept low, and the output signal Gk follows the clock signal CLKA and falls at high speed. Return to L level.

  At time t3, the output signal Gk + 1 at the next stage becomes H level, so that the transistors Q2 and Q4 of the unit shift register SRk are turned on. As a result, the output terminal OUT is sufficiently discharged through the transistor Q2, and is surely set to the L level (VSS). Node N1 is discharged to low level by transistor Q4. That is, the unit shift register SRk returns to the reset state.

  Then, after the output signal Gk + 1 of the next stage returns to the L level at time t4, the unit shift register SRk is maintained in the reset state until the next output signal Gk-1 is input, and the output signal Gk Is kept at L level.

  In summary, the unit shift register SRk is in a reset state during which no signal (start pulse SP or the previous stage output signal Gk-1) is input to the input terminal IN1, and the transistor Q1 is kept off. The output signal Gk is maintained at the L level (VSS). When a signal is input to the input terminal IN1, the unit shift register SRk is switched to the set state. Since the transistor Q1 is turned on in the set state, the output signal Gk is at the H level while the signal (clock signal CLKA) at the clock terminal CK1 is at the H level. After that, when a signal (next-stage output signal Gk + 1 or end pulse EN) is input to the reset terminal RST, the original reset state is restored.

  Next, the operation of a multi-stage shift register unit in which a plurality of unit shift registers SR are cascade-connected will be described with reference to FIG. 6 which is a timing chart showing the operation of the gate line driving circuit. First, when the start pulse ST is input to the first-stage unit shift register SR1, the output signal G is shifted at the timing synchronized with the clock signals CLKA and CLKB by using it as a trigger (trigger). As shown in FIG. 6, unit shift registers SR1, SR2, SR3. In the gate line driving circuit 160, the output signal G output in this order is used as a horizontal (or vertical) scanning signal of the display panel.

  Hereinafter, a period during which a specific unit shift register SR outputs the output signal G is referred to as a “selection period” of the unit shift register SR.

  The dummy unit shift register SRD is provided to reset the unit shift register SRn by the output signal GD immediately after the last unit shift register SRn outputs the output signal Gn. For example, in the case of a gate line driving circuit, if the unit shift register SRn at the last stage is not reset immediately after the output signal Gn is output, the corresponding gate line (scanning line) is activated unnecessarily, resulting in display defects. It will occur.

  Note that the dummy unit shift register SRD is reset by the end pulse EN input at a timing after the output signal GD is output. When the signal shift operation is repeatedly performed as in the gate line driving circuit, the start pulse ST of the next frame period may be used instead of the end pulse EN.

  In the case of driving using a two-phase clock as shown in FIG. 3, each of the unit shift registers SR is reset by the output signal G of the next stage of itself, so that the unit shift register SR of the next stage is at least The normal operation as shown in FIGS. 5 and 6 cannot be performed unless it has been operated once. Therefore, prior to the normal operation, it is necessary to perform a dummy operation for transmitting a dummy signal from the first stage to the last stage. Alternatively, a reset transistor is separately provided between the reset terminal RST (node N2) and the second power supply terminal S2 (high potential side power supply) of each unit shift register SR, and the node N2 is forcibly set before the normal operation. You may perform the reset operation which makes it H level. In this case, however, a reset signal line is required separately.

  7 is an enlarged cross-sectional view showing a region corresponding to a part of the circuit including the TFT (Q1) in the gate line driving circuit 160 on the array substrate 100 (a circuit surrounded by a broken line in FIG. 4). . In the array substrate 100, a gate electrode 212 made of a conductive material such as a metal is formed on a first transparent substrate 110, and a silicon nitride film (SiNx) or a silicon oxide film (SiO2) is formed thereon. The configured gate insulating film 213 covers the gate electrode 212.

  An active layer 214 made of amorphous silicon is formed on the gate insulating film 213 above the gate electrode 212, and an ohmic contact layer made of amorphous silicon doped with impurities is formed thereon. 215 is formed.

  A source / drain electrode 216 made of a conductive material such as metal is formed on the ohmic contact layer 215. The source / drain electrodes 216 together with the gate electrode 212 form a TFT (Q1). The gate electrode 212 is in the same layer as the gate wiring 219 that connects each node in the gate line driver circuit, and is formed simultaneously with the gate wirings GL1 to GLn. The source / drain electrodes 216 are connected to source / drain wirings 221 that connect the respective nodes in the gate line driving circuit. (“Gate wiring” refers to wiring in the same layer as the gate electrode of the TFT. Similarly, “source / drain wiring” refers to wiring in the same layer as the source / drain electrode of the TFT.)

  Subsequently, a protective layer 217 made of a silicon nitride film, a silicon oxide film, or an organic insulating film is formed on the source / drain electrode 216, and the protective layer 217 exposes the source / drain wiring and the gate wiring. Contact holes 217a and 217b are provided.

  A transparent conductive film 218 is formed on the protective layer 217, and the transparent conductive film 218 connects the source / drain wiring 221 and the gate wiring 219 via contact holes 217a and 217b. A coverage defect 21 occurs in the step portion of the contact hole.

  As described above, in the first embodiment, the alignment film 270 on the array substrate 100 is disposed so as to cover the gate line driving circuit 160, and the transparent electrode (ITO) formed on the color filter layer 220 is disposed. Film) 250 is disposed at least in a region where the gate driving circuit 160 exists so as not to penetrate the sealing material 350 and to come out of the sealing material, so that intrusion of moisture, impurities and the like can be prevented. Even if the coverage defect 21 occurs, it is possible to prevent connection failure due to contact hole corrosion.

Embodiment 2. FIG.
In the liquid crystal display device 400 according to the second embodiment of the present invention, the source line driver IC 150, the gate line driving circuit 160, the first to nth gate lines GL1 to GLn, and the first to first gates, which are the main components of the display panel 300. The m-th source lines SL1 to SLm, the TFT, the pixel electrode PE, the auxiliary capacitor C, the liquid crystal layer 330, the color filter substrate 200, the sealing material 350, and the like are the same as those in the first embodiment, and detailed description thereof is omitted. The differences from the first embodiment will be described in detail below with reference to the sectional view and FIG.
8 is a cross-sectional view taken along line III-III of the liquid crystal display device shown in FIG. 1 according to the second embodiment of the present invention. Here, as in the first embodiment, the display panel 300 includes a display area DA for displaying an image, a first peripheral area PA1 arranged so as to surround the display area DA, and an outside of the first peripheral area PA1. Includes a second peripheral area PA2.

  Further, an overcoat layer 260 exists on the upper surface of the surface of the second transparent substrate 210 facing the array substrate 100. The overcoat layer 260 is composed of an organic film. The overcoat layer is used particularly when flatness is required for the color filter substrate 200, and is particularly frequently used in an IPS liquid crystal display device. In this embodiment, an example of an IPS liquid crystal display device is also shown.

  FIG. 9 is a cross-sectional view showing details of the display area DA of the liquid crystal display device adopting the IPS liquid crystal mode. In the IPS liquid crystal mode, a liquid crystal is generated by a component of an electric field parallel to the array substrate 100 generated between the pixel electrode PE formed on the array substrate 100 and the reference electrode CE formed on the array substrate 100 and facing the pixel electrode PE. Controls the light transmittance of the layer 330.

The pixel electrode PE and the reference electrode CE shown in FIG. 9 are both formed on the array substrate 100, and therefore the electric field generated between them is a component substantially parallel to the array substrate 100 (IPS liquid crystal mode). .
In the case of the IPS method shown in FIG. 8 described above, since the IPS method is a method in which liquid crystal molecules are rotationally driven by a lateral electric field, there is no transparent electrode (ITO film) on the color filter substrate 200.

  Here, as shown in FIG. 8, in the display panel 300 of this embodiment, the overcoat 260 formed on the color filter layer 220 is applied to the sealing material 350 at least in an area where the gate drive circuit 160 exists. Corresponding regions are removed by patterning, and are arranged so as not to penetrate the sealing material 350 and come out of the sealing material (in FIG. 8, the sealing material 350 is in contact so as to cover the end of the overcoat 260. However, in the present invention, it is sufficient that the overcoat layer 260 does not protrude from the sealing material 350. For example, the overcoat layer 260 and the sealing material 350 may be configured not to contact each other. According to experiments, it was confirmed that contact hole corrosion was accelerated when the overcoat layer 260 was taken out of the sealing material. 0 has a high water absorption, when issuing an overcoat layer 260 outside of the sealing material, moisture penetrates into the inside of the sealing material through the overcoat layer 260, because the contact hole corrosion occurs.

  In this embodiment, the liquid crystal display device adopting the IPS liquid crystal mode is described as an example of the display panel 300 in which the overcoat layer 260 is provided on the color filter layer 220. However, the above-described overcoat 260 is described. The patterning is not directly related to the IPS liquid crystal mode, and can be employed without any problem in a liquid crystal display other than the IPS liquid crystal mode, for example, a TN liquid crystal mode or a VA liquid crystal mode. It also has an effect of preventing 160 contact hole corrosion.

Embodiment 3 FIG.
In this embodiment, the shape of the contact hole in which the poor coverage portion 21 described in the first embodiment is unlikely to occur will be described. That is, in this embodiment, a contact hole shape in which the taper shape of the contact hole cross section is improved is used for the layer conversion portion of the drive circuit.

In the present embodiment, the minimum size contact used on the panel (usually, the minimum size contact hole allowed in the process is used for the pixel portion in order to prioritize the transmittance) is used in the drive circuit. The contact hole diameter is a relatively large size.
FIG. 10 is a plan view thereof (a partial plan view including TFTs of the shift register circuit shown in FIG. 4, that is, a plan view of FIG. 7). As a result of experiments (high temperature and high humidity test) by the present inventors, it was confirmed that contact hole corrosion is reduced by increasing the contact hole diameter of the gate drive circuit 160. The results are shown in Table 1.

そこで、ゲート駆線動回路１６０のコンタクトホール径を大きくすることで腐食が低減する理由を以下に示す。

Therefore, the reason why corrosion is reduced by increasing the contact hole diameter of the gate drive circuit 160 will be described below.

  Here, FIGS. 11 and 12 show partial cross-sectional views of the contact hole forming process employed in the third embodiment (in FIG. 11, reference numeral 30 denotes a contact hole for exposing the contact hole portion of the resist 8 in the exposure process). It is a photomask and is not necessary and does not exist in the dry etching process). When the insulating film 7 is removed in the dry etching process, the resist 8 on the insulating film 7 is also removed simultaneously with the exposed insulating film 7. In the etching step, etching is performed until the portion of the insulating film 7 exposed from the beginning is completely removed.

When the contact size shown in FIG. 12 is large, the etching reaction time becomes long because the exposed region of the insulating film 7 is large. When the insulating film 7 is removed by dry etching, the resist on the insulating film 7 is also removed simultaneously with the exposed insulating film 7. In particular, since the corner portions of the resist are removed, the resist gradually becomes tapered. Since the resist 8 in the tapered portion is thinner than the normal portion, the insulating film is exposed during the dry etching. Then, the area of the insulating film 7 to be dry etched becomes wider.
Usually, in the etching process, etching is performed until the portion of the insulating film 7 exposed from the beginning is completely removed. Therefore, the portion of the insulating film 7 in which the resist 8 has a tapered shape is not completely removed. Part remains. Therefore, the insulating film 7 after dry etching has a tapered shape with a gentle angle reflecting the taper shape of the resist 8 before dry etching, and it is possible to form ITO with good coverage on the top.

As shown in FIGS. 11 and 12, a cross-sectional view (FIG. 11) of a contact hole of a minimum size contact (usually used for a pixel) used in the display panel 300 and a contact when the contact hole is enlarged. Comparing with the sectional view of the hole (FIG. 12), it can be seen that the taper angle 40 of the insulating film 7 becomes gentle when the contact hole diameter is increased. Reference numeral 12 denotes an opening of the photomask 30.
In this embodiment, as a result of experimenting with a plurality of contact hole diameters, it was possible to form ITO with good coverage when the contact hole diameter was 14 μm or more, and an effect of suppressing coverage failure was obtained.

  Further, since contact hole corrosion usually occurs in the vicinity of a contact hole to which an H voltage (VDD or a voltage close to VDD) is applied, application in the present embodiment applies an H voltage (VDD or a voltage close to VDD). The contact hole to which the L voltage (VSS or a voltage close to VSS) is applied is not applied in this embodiment, and the contact hole is made to have the same size as the contact hole of the pixel. May be.

  In addition, the number of contact holes shown in FIG. 10 is one for each of the locations where the gate wiring 219 and the transparent conductive film 218 are connected and the locations where the source / drain wiring 221 and the transparent conductive film 218 are connected. If it is necessary to reduce the contact resistance, a large number of contact holes meeting this condition may be arranged.

Embodiment 4 FIG.
The transmissive liquid crystal display panel emits light from a backlight and controls the amount of light transmitted to display an image. Such a transmissive liquid crystal display panel has high visibility in a dark place, but low visibility in a bright place. For this reason, a reflection type liquid crystal display panel that uses ambient light is used as a light source in portable information terminal devices and the like that are frequently carried outdoors and used outdoors. The reflective liquid crystal display panel uses a reflective film instead of a transparent film for the pixel electrode portion of the substrate. Then, the display is performed by reflecting the ambient light on the surface of the reflective film. As described above, the reflective liquid crystal display panel does not require a backlight, and thus has an advantage that power consumption can be reduced. However, when the ambient light is dark, it has the disadvantage that the visibility is extremely lowered.

  In order to solve these problems, a reflection-transmission type liquid crystal display panel that transmits part of backlight light and reflects part of ambient light is well known. The reflection / transmission type liquid crystal display panel includes a transmission part in which a transmission film is used for the pixel electrode part and a reflection part in which a reflection film is used for the pixel electrode part. Thereby, both the transmissive display and the reflective display can be realized by one liquid crystal display panel.

  Next, the configuration of the reflective / transmissive liquid crystal display panel will be described with reference to FIGS. FIG. 13 is a plan view showing a pixel portion composed of a TFT and a pixel electrode portion of a reflection / transmission type liquid crystal display panel. FIG. 14 is a cross-sectional view showing the configuration of the TFT and the pixel electrode portion of the reflection / transmission type liquid crystal display panel. FIG. 14 also shows the cross-sectional configuration of the contact holes 106a and 106b in the driver circuit portion.

Similar to the transmissive liquid crystal display panel, the reflective transmissive liquid crystal display panel includes the TFT 10, the transmissive electrode 101, the gate wiring 102, the source / drain wiring 103, the contact hole 106a on the gate wiring, and the contact hole 106b on the source / drain wiring. In the drive circuit portion, the gate wiring 102 and the source / drain wiring 103 are connected via a transparent conductive film in the same manner as in the transmissive liquid crystal display panel.
Further, in the reflection / transmission type liquid crystal display panel, the reflection electrode 107 is formed in a substantially half region of the pixel on the TFT 10 side. Thus, the transmissive electrode 101 and the reflective electrode 107 are used as pixel electrodes. As the reflective electrode 107, Ag or Al is often used. The organic planarizing film 6 is made of a photosensitive acrylic resin or the like.

The organic planarizing film 6 made of this photosensitive acrylic resin tends to absorb moisture. In particular, in an environment where high temperature, high humidity, or dew condensation occurs, the organic flattening film 6 absorbs excessive moisture, and moisture taken into the flattening film 6 penetrates into the liquid crystal layer 9 to contact holes. There was a problem of causing corrosion.
In the fourth embodiment, as shown in FIG. 14, the organic flattening film 6 is prevented from penetrating the sealing material 350 and coming out of the sealing material. By doing so, the intrusion of moisture from the planarizing film 6 is suppressed, and the contact hole corrosion of the drive circuit 160 can be prevented.
The organic planarization film 6 and the sealing material 350 shown in FIG. 14 are arranged without a gap, but a gap may be provided between the two if the outer dimensions of the display panel 300 are permitted. Needless to say, the organic planarizing film 6 should not come out of the sealing material 350.

In this embodiment, the reflective / transmissive liquid crystal display panel has been described. However, a reflective liquid crystal display panel using an organic flattening film, and a transmissive liquid crystal display using an organic flattening film to improve the aperture ratio. It can also be applied to panels.
In addition, the configuration examples described in the individual embodiments can be combined, and by doing so, a liquid crystal display panel that is more resistant to contact hole corrosion can be obtained.

  Furthermore, in the first to fourth embodiments of the present invention, the liquid crystal display device has been described as an example. For example, an organic EL display device that employs a white EL light emitting element and a color filter layer, or an RGB, three-color EL device. In a scanning line driving circuit such as an organic EL display device using an overcoat layer on a light emitting layer, and an organic EL display device using an organic resin between a substrate and a cathode, the present invention prevents contact hole corrosion of the circuit. It can be adopted.

This is a configuration of the liquid crystal display device according to the first to fourth embodiments of the present invention. It is sectional drawing of the liquid crystal display device which concerns on Embodiment 1 of this invention. It is a block diagram of the gate line drive circuit in FIG. FIG. 4 is a circuit diagram for one stage of a shift register in FIG. 3. FIG. 4 is a timing chart showing the operation of the unit shift register in FIG. 3. FIG. 2 is a timing chart showing an operation of the gate line driving circuit in FIG. 1. FIG. 5 is a partial cross-sectional view including a TFT of the shift register circuit shown in FIG. 4. It is sectional drawing of the liquid crystal display device which concerns on Embodiment 2 of this invention. It is sectional drawing showing the detail of the display area DA of the liquid crystal display device in FIG. FIG. 5 is a partial plan view including TFTs of the shift register circuit shown in FIG. 4. It is a partial cross section figure of the normal contact hole formation process in Embodiment 3 of this invention. It is a partial cross section figure of the contact hole formation process with a large contact size in Embodiment 3 of this invention. It is a top view showing the structure of the pixel part of the reflective transmissive liquid crystal display panel which concerns on Embodiment 4 of this invention. FIG. 14 is a cross-sectional view of a pixel portion and contact holes of the liquid crystal display panel shown in FIG. 13.

Explanation of symbols

6 Organic flattening film 10, Q1, Q2, Q3, Q4, Qx, TR1 Thin film transistor 100 Array substrate 102, 219 Gate wiring 103, 221 Source / drain wiring 105, 218 Transparent conductive film 106, 217a, 217b Contact hole 110 First Transparent substrate 160 gate line driving circuit 200 color filter substrate 210 second transparent substrate 212 gate electrode 213 gate insulating film 214 active layer 215 ohmic contact layer 216 source / drain electrode 217 protective layer 220 color filter layer 250 transparent electrode 260 overcoat Layer 270 Alignment film 300 Display panel 330 Liquid crystal layer 350 Sealing material 400 Display device GL1, GLn Gate line SL1, SLn Source line CE, CE1 Counter electrode DA Display area PA1 First peripheral area PA2 Second Surrounding area

Claims (7)

A first substrate on which a scanning line driving circuit is formed;
An image display panel bonded through a seal so that the first substrate and the second substrate face each other,
At least a contact hole of the scanning line driving circuit is covered with a resin film in the same layer as the display region. A first substrate on which a scanning line driving circuit is formed;
An image display panel bonded through a seal so that the first substrate and the second substrate face each other,
A transparent conductive film is disposed on the surface of the second substrate facing the first substrate,
The transparent conductive film is disposed over substantially the entire display area,
In the peripheral region of the display region, the transparent conductive film does not penetrate the seal at least in a region corresponding to the scanning line driving circuit. A first substrate on which a scanning line driving circuit is formed;
An image display panel bonded through a seal so that the first substrate and the second substrate face each other,
The contact hole formed in the scanning line driving circuit is larger in size than the contact hole formed in the pixel. A first substrate on which a scanning line driving circuit is formed;
An image display panel bonded through a seal so that the first substrate and the second substrate face each other,
In the first substrate, an organic planarization film is provided on a surface facing the second substrate,
The organic flattening film does not penetrate through the seal at least in a region corresponding to the scanning line driving circuit. The scanning line driving circuit includes a first metal wiring, a second metal wiring, and a contact hole.
5. The image display according to claim 1, wherein the contact hole is electrically connected to the first metal wiring and the second metal wiring formed in different layers through a transparent conductive film. 6. panel. A color filter layer is disposed on the second substrate;
6. The image display panel according to claim 1, wherein the overcoat layer of the color filter layer does not penetrate the seal at least in a region corresponding to the scanning line driving circuit. The image display panel according to any one of claims 1 to 6,
An image display panel, wherein a transistor constituting the scanning line driving circuit is an amorphous silicon thin film transistor.

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