JP2009124636A - Data processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress latency increase of other access to a minimum without reducing priorities of DMA transfer of a Y signal and a C signal. <P>SOLUTION: A data processing apparatus includes: an image data input module (32) capable of separating the Y signal and the C signal from a video signal; a DMA controller capable of performing DMA transfer of the Y signal and C signal to a predetermined semiconductor memory; and a bus capable of exchanging signals between the image data input module and the DMA controller. Then, the image data input module is provided with a DMA transfer control circuit (323) for issuing, after waiting for the lapse of just predetermined bus cycles on the bus from the DMA transfer of either one of the Y signal or the C signal, the DMA transfer request of the other signal to the DMA controller, thereby suppressing the latency increase of other access to the minimum without reducing priorities of DMA transfer of the Y signal and the C signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a DMA (direct memory access) transfer technique for a signal separated from a video signal.

  The video signal is composed of a luminance signal (Y signal) representing brightness and a color difference signal (chroma signal, C signal) representing color. The composite video signal is transmitted by combining the Y signal and the C signal in order to improve transmission efficiency. Composite video signals are widely used in television broadcasting and general video equipment because they can transmit video signals with a single cable. When the transmitted composite video signal is reproduced, it is necessary to separate the original Y signal and the C signal, and what performs this is called a Y / C separation circuit. As a Y / C separation technique, for example, as described in Patent Document 1, a technique using two types of frequency filters, a technique using a two-line comb filter, a technique using a three-line comb filter, and the like are known. .

JP 2006-25098 A

  For example, in a SoC (system on chip) including a codec function that enables compression / decompression processing of image data, a Y signal and a C signal separated from the composite video signal by Y / C separation are DMA (direct memory. An access controller writes data in a predetermined semiconductor memory without intervention of a CPU (central processing unit). When the input image data is separated into the Y / C space and stored in the semiconductor memory, the C signal has the same timing as the Y signal (when the transfer data size is the same, 4: 2: 2 every time, 4: 2: : In the case of 0, a DMA transfer request is made every other time). Generally, the data access priority of data transfer with high real-time characteristics such as image input is high, and the Y signal and the C signal are DMA-transferred continuously.

  However, when the transfer of the Y signal and the C signal is performed continuously, the bus is occupied by the DMA during that time, so other accesses are waited for two data transfers for the Y signal and the C signal, This will increase the latency. The Y signal and the C signal only need to complete data transfer within a certain period, but access that causes system performance degradation (or failure) when latency increases (for example, CPU access and average data transfer amount are small) However, this may cause trouble if it conflicts with DMA transfer or the like where access must be completed in a short cycle after the data transfer request is issued. Therefore, it is conceivable to lower the priority of DMA transfer for the Y signal and the C signal.

  However, if the priority of the DMA transfer is lowered for the Y signal and the C signal, other non-real-time access is prioritized, and the DMA transfer for the Y signal and the C signal in which the real-time property is important is performed within a certain time. There is a risk that it will not be completed.

  An object of the present invention is to provide a data transfer control technique for minimizing an increase in latency of other accesses without lowering the priority of DMA transfer for Y and C signals.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A representative one of the inventions disclosed in the present application will be briefly described as follows.

  That is, an image data input module capable of separating a Y signal and a C signal from a video signal, a DMA controller capable of performing DMA transfer of the Y signal and the C signal to a predetermined semiconductor memory, the image data input module, and the above A bus is provided that enables the exchange of signals with the DMA controller. Then, after waiting for a predetermined number of bus cycles in the bus from the DMA transfer for one of the Y signal and the C signal, a DMA transfer request for the other is issued to the DMA controller A DMA transfer control circuit is provided in the image data input module to minimize the increase in latency of other accesses without lowering the priority of DMA transfer for the Y and C signals.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to provide a technique for suppressing an increase in latency of other accesses without lowering the priority of DMA transfer for the Y signal and the C signal.

1. Representative Embodiment First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A data processing apparatus (10) according to a typical embodiment of the present invention includes an image data input module (32) capable of separating the Y signal and the C signal from a video signal including the Y signal and the C signal. ) And a Y controller and a C signal separated by the image data input module can be DMA-transferred to a predetermined semiconductor memory, and a signal can be transmitted between the image data input module and the DMA controller. And a bus (41) that enables exchange of data. The image data input module waits for a predetermined number of bus cycles in the bus from the DMA transfer for one of the Y signal and the C signal, and then issues a DMA transfer request for the other. A DMA transfer control circuit (323) issued to the DMA controller is included.

  In the above configuration, after the DMA transfer control circuit, for example, the DMA transfer for the Y signal is completed, the DMA transfer request for the C signal is sent to the DMAC after waiting for a predetermined number of bus cycles. Issue. The DMA transfer for the C signal is delayed from the DMA transfer for the Y signal by a period corresponding to the predetermined number of bus cycles, and the right to use the bus is released during this period. Data transfer with low priority can be performed. In addition, since the transfer for the Y signal and the C signal are both high-priority transfers, the transfer for the Y signal and the C signal is performed even when the low-priority data transfer requests are issued continuously. It is possible to minimize waiting.

  [2] The image data input module is a control register that can set the number of bus cycles from the DMA transfer for one of the Y signal and the C signal until the DMA transfer request for the other is issued. 321), and the DMA transfer control circuit can be configured to control the DMA transfer with reference to setting information of the control register.

  [3] When the DMA transfer request for one of the Y signal and the C signal is received by the DMA controller, the DMA transfer control circuit has passed a predetermined number of bus cycles based on the completion of the reception. After that, the DMA transfer request for the other can be issued to the DMA controller.

  [4] The DMA transfer control circuit sends a DMA transfer request for the other to the DMA controller after a predetermined cycle has elapsed with reference to the start of DMA transfer for one of the Y signal and the C signal. Can be configured to issue.

  [5] The DMA transfer control circuit sends a DMA transfer request for the other to the DMA controller after a predetermined cycle has elapsed with reference to the end of the DMA transfer for one of the Y signal and the C signal. Can be configured to issue.

2. Next, the embodiment will be described in more detail.

  FIG. 2 shows a configuration example of a codec SoC (system on chip) which is an example of a data processing apparatus according to the present invention. The codec SoC 10 shown in FIG. 2 is not particularly limited, but includes a processor unit 30, an image data processing module (VBLX) 31, an image data input module (CRU) 32, a DMAC (direct memory access controller) 33, and bus access. The control and SDRAM access control unit 34 is seen and formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique. The codec SoC 10 is coupled to an SDRAM (Synchronous Dynamic Random Access Memory) 20 via an external bus (user system bus) 29.

  The processor unit 30 includes, but is not limited to, a CPU (Central Processing Unit) core 35, a built-in memory 36, a DMAC 37, and other peripheral modules 38, which are coupled to each other via a CPU bus 39 so as to exchange signals. Has been. The CPU core 35 executes predetermined arithmetic processing according to a preset program. The built-in memory 36 is an SRAM (Static Random Access Memory), and is used as a work area for arithmetic processing in the CPU core 35 and a storage area for various data. The DMAC 37 controls DMA transfer between the built-in memory 36 and other modules.

  The image data processing module 31 is coupled to the bus access control and SDRAM access control unit 34 via a super highway bus 43, and is coupled to the image data input module 32 via a customer bus 40. The image data processing module 31 enables compression / decompression processing of image data input via the super highway bus 43. The operation of the image data processing module 31 is controlled by the CPU core 35 via the customer bus 40.

  The image data input module 32 is coupled to the F1 bus 41, the customer bus 40, and the parallel bus 42, and separates the Y signal and the C signal included in the video signal captured from the outside via the parallel bus 42. It has the function to do. A technique known per se as described in Patent Document 1 can be applied to the separation of the Y signal and the C signal. The operation of the image data input module 32 can be controlled by the CPU core 35 via the customer bus 40.

  The DMAC 33 DMA-transfers the Y signal and C signal separated by the image data input module 32 to the SDRAM 20 via the F1 bus 41 and the external bus 29 without the intervention of the CPU core 35. At this time, the right to use the F1 bus 41 and the external bus 29 is occupied by the DMAC 33.

  The bus access control and SDRAM access control unit 34 has a function as an interface with an external module, and controls access to the external bus 29 and the SDRAM 20.

  FIG. 1 shows a configuration example of the image data input module 32.

  As shown in FIG. 1, the image data input module 32 includes a control register 321, a VD sampling circuit 322, a DMA transfer control circuit 323, a luminance data DMA buffer 324, a color difference data DMA buffer 325, and an I / F (interface). A circuit 326 and a code analysis unit 327 are included.

  Various signals are taken into the VD sampling circuit 322 via the parallel bus 42. The various signals include a video clock signal VCLK, 16-bit video data VD [15: 0], a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, a vertical valid signal VVLD, a horizontal valid signal HVLD, and an optional field signal FIELD. Is included. The VD sampling circuit 322 includes a sampling buffer 328 and a switch 329, and samples the video data VD in synchronization with the video clock signal VCLK, the vertical synchronization signal VSYNC, and the horizontal synchronization signal HSYNC.

  The code analysis unit 327 includes four flip-flop circuits FF, and analyzes the code held in the four flip-flop circuits FF. By this code analysis, the Y signal and the C signal are separated. The separated Y signal and C signal are written in the luminance data DMA buffer 324 and the color difference data DMA buffer 325, respectively.

  The Y signal held in the luminance data DMA buffer 324 and the C signal held in the color difference data DMA buffer 325 can be output to the F1 bus 41 via the I / F circuit 326 in the subsequent stage. The The operation of the I / F circuit 326 is controlled by the DMA transfer control circuit 323. The DMA transfer control circuit 323 issues DMA transfer request signals F1DREQ_Y and F1DREQ_C to the DMAC 33, and according to the acknowledge signals F1DACK_Y and F1DACK_C output from the DMAC 33, the luminance data DMA buffer 324 and the color difference data A function of outputting the output data of the DMA buffer 325 to the F1 bus 41. For example, when the DMA transfer request signal F1DREQ_Y for the Y signal held in the luminance data DMA buffer 324 is issued by the DMA transfer control circuit 323 and accepted by the DMAC 33, the acknowledge signal F1DACK_Y is asserted by the DMAC 33. Thereby, DMA transfer for the Y signal is performed. Similarly, when the DMA transfer request signal F1DREQ_C for the C signal is issued by the DMA transfer control circuit 323 and is accepted by the DMAC 33, the acknowledge signal F1DACK_C is asserted by the DMAC 33, whereby the DMA transfer for the C signal is performed. Done.

  In particular, in this example, the DMA transfer control circuit 323 waits for a predetermined number of bus cycles after the DMA transfer for one of the Y signal and the C signal is completed, A DMA transfer request for the other is issued to the DMAC 33. For example, as shown in FIG. 3A, when the DMA transfer is performed in the order of the Y signal and the C signal, the DMA transfer control circuit 323 performs the DMAC 33 after the DMA transfer for the Y signal is completed. The right to use the F1 bus 41 and the external bus 29 is released. The DMA transfer control circuit 323 issues a DMA transfer request for the C signal to the DMAC 33 after waiting for a predetermined number of bus cycles. When the acknowledge signal F1DACK_C for the DMA transfer request for the C signal is transmitted to the DMA transfer control circuit 323, the right to use the F1 bus 41 and the external bus 29 is again occupied by the DMAC 33, so that the C DMA transfer for the signal is started. Thereby, the DMA transfer for the C signal is delayed from the DMA transfer for the Y signal by a period (denoted by 300 in FIG. 3) corresponding to the predetermined number of bus cycles. The predetermined number of bus cycles is determined according to information set in the control register 321. The setting information of the control register 321 can be appropriately changed by the CPU core 35 via the customer bus 40.

  As described above, the DMA transfer for the C signal is delayed from the DMA transfer for the Y signal by a period (denoted by 300 in FIG. 3) corresponding to the predetermined number of bus cycles. During this period, since the right to use the F1 bus 41 and the external bus 29 is released, data transfer with a lower priority than, for example, transfer of the C signal can be performed using the F1 bus 41 or the external bus 29. . In addition, since the transfer for the Y signal and the C signal are both high-priority transfers, the transfer for the Y signal and the C signal is performed even when the low-priority data transfer requests are issued continuously. Waiting can be minimized and system failure is avoided.

  According to the above example, the following effects can be obtained.

  (1) The DMA transfer control circuit 323 waits for a predetermined number of bus cycles after the DMA transfer for the Y signal is completed, and then issues a DMA transfer request for the C signal to the DMAC 33. Thus, the DMA transfer for the C signal is delayed from the DMA transfer for the Y signal by a period (denoted by 300 in FIG. 3) corresponding to the predetermined number of bus cycles. Since the right to use the F1 bus 41 and the external bus 29 is released during this period, for example, data transfer with a lower priority than transfer of the C signal can be performed. In addition, since the transfer for the Y signal and the C signal are both high-priority transfers, the transfer for the Y signal and the C signal is performed even when the low-priority data transfer requests are issued continuously. Waiting can be kept to a minimum, thereby avoiding system failure.

  (2) Due to the effect of (1) above, access that causes system performance degradation (or failure) when the latency is long (eg, CPU access or average data transfer amount is small, but in a short cycle after issuing a data transfer request) Contention with the DMA transfer that the access must be completed) can be avoided, so that the increase in latency of other accesses is minimized without lowering the priority of the DMA transfer for the Y signal and the C signal. Can do.

  (3) The image data input module 32 includes a control register 321 capable of setting the number of bus cycles from the DMA transfer for the Y signal until the DMA transfer request for the C signal is issued. Since the transfer control circuit 323 can control the DMA transfer with reference to the setting information in the control register 321, the optimal number of bus cycles is determined for each user system to which the codec SoC 10 is applied. Can be set to

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above example, when the DMA transfer for the Y signal is completed, the DMA transfer request for the C signal is issued to the DMAC 33 after a predetermined number of bus cycles have elapsed with reference to the completion. However, when the DMA transfer for the Y signal is started, a DMA transfer request for the C signal is issued to the DMAC 33 after a predetermined number of bus cycles have elapsed with reference to the start. You may make it do. When a DMA transfer request for the Y signal is accepted by the DMAC 33, the DMA transfer request for the other is issued to the DMAC 33 after a predetermined number of bus cycles have elapsed with reference to the completion of the acceptance. You may make it do. Whether or not the DMA transfer request is accepted by the DMAC 33 can be determined by an acknowledge signal.

  Furthermore, in the above example, the case where the DMA transfer is performed in the order of the Y signal and the C signal has been described. However, the DMA transfer may be performed in the order of the C signal and the Y signal. In this case, the DMA transfer control circuit 323 issues a DMA transfer request F1DREQ_Y for the Y signal after waiting for a predetermined number of bus cycles from the DMA transfer for the C signal.

  In the above description, the case where the invention made mainly by the present inventor is applied to the codec SoC 10 which is the field of use behind the present invention has been described. However, the present invention is not limited to this and is widely applied to various data processing apparatuses. Can be applied.

1 is a block diagram illustrating an example of the configuration of an image data input module included in a codec SoC as an example of a data processing apparatus according to the present invention. It is a block diagram of an example of the overall configuration of the codec SoC. It is explanatory drawing of DMA transfer control in the said image data input module.

Explanation of symbols

10 Codec SoC
20 SDRAM
29 External Bus 30 Processor Unit 31 Image Data Processing Module 32 Image Data Input Module 33 DMAC
34 Bus access control and SDRAM access control unit 35 CPU core 36 Built-in memory 37 DMAC
38 Peripheral module 321 Control register 322 VD sampling circuit 323 DMA transfer control circuit 324 Brightness data DMA buffer 325 Color difference data DMA buffer 326 I / F circuit 327 Code analysis unit

Claims (5)

An image data input module capable of separating the Y signal and the C signal from a video signal including the Y signal and the C signal;
A DMA controller capable of DMA-transferring the Y signal and the C signal separated by the image data input module to a predetermined semiconductor memory;
A data processing device comprising: a bus that enables exchange of signals between the image data input module and the DMA controller;
The image data input module waits for a predetermined number of bus cycles in the bus from the DMA transfer for one of the Y signal and the C signal, and then issues a DMA transfer request for the other to the DMA signal. A data processing apparatus comprising a DMA transfer control circuit for issuing to a controller. The image data input module includes a control register capable of setting the number of bus cycles from the DMA transfer for one of the Y signal and the C signal until a DMA transfer request for the other is issued,
The data processing apparatus according to claim 1, wherein the DMA transfer control circuit controls the DMA transfer with reference to setting information of the control register.   When a DMA transfer request for one of the Y signal and the C signal is received by the DMA controller, the DMA transfer control circuit waits for a predetermined number of bus cycles with reference to the completion of the reception. 2. The data processing apparatus according to claim 1, wherein a DMA transfer request for the other is issued to the DMA controller.   The DMA transfer control circuit issues a DMA transfer request for the other to the DMA controller after a predetermined cycle has elapsed with reference to the start of DMA transfer for one of the Y signal and the C signal. Item 2. A data processing apparatus according to Item 1.   The DMA transfer control circuit issues a DMA transfer request for the other to the DMA controller after a predetermined cycle has elapsed with reference to the end of the DMA transfer for one of the Y signal and the C signal. Item 2. A data processing apparatus according to Item 1.

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