JP2009105083A - Method of manufacturing thin film transistor, and thin film transistor manufactured by the manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a thin film transistor having excellent conduction characteristics between a source electrode, a drain electrode and a semiconductor layer, and to provide the thin film transistor manufactured by the manufacturing method. <P>SOLUTION: A gate electrode 6 is formed on the upper surface of a substrate 2 of a thin film transistor 1. A gate insulating layer 5 is formed in such a manner that the gate electrode 6 is covered. A source electrode 3, a drain electrode 4, and a semiconductor layer 7 are provided on the upper surface of the gate insulating layer 5. A silver nano ink 9 is applied to the gate insulating layer 5 between the source electrode 3 and the semiconductor layer 7 in such a manner that the end of the source electrode 3 and the end of the semiconductor layer 7 are covered, and the source electrode and the semiconductor layer are electrically connected (in contact) with each other. A silver nano ink 10 is applied to the gate insulating layer 5 between the drain electrode 4 and the semiconductor layer 7 in such a manner that the end of the drain electrode 4 and the end of the semiconductor layer 7 are covered and the drain electrode and the semiconductor layer are electrically connected (in contact) with each other. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a thin film transistor and a thin film transistor manufactured by the method, and more particularly, to a method for manufacturing a thin film transistor using a dispersion composed of an aqueous solution containing carbon nanotubes and a method for manufacturing the thin film transistor. The present invention relates to a manufactured thin film transistor.

  Conventionally, in order to control or amplify high frequency digital signals and analog electric signals, field effect transistors having excellent high frequency characteristics have been used. In order to realize a bright and easy-to-view flexible display such as organic EL, film liquid crystal, and electronic paper, each pixel of the flexible display has an active drive circuit including a field effect transistor as a TFT (Thin Film Transistor). Embedded.

  In such field effect transistors, digital signals and analog electrical signals with frequencies higher than those that can be processed by field effect transistors made of gallium arsenide are controlled with the recent increase in information processing and communication speed. Alternatively, an electronic device for amplification has become necessary. For this purpose, in a field effect transistor comprising a channel in which charged particles travel, a source electrode and a drain electrode connected to a part of each channel, and a gate electrode that is electromagnetically coupled to the channel, the channel is composed of carbon nanotubes. A field effect transistor has been proposed (see, for example, Patent Document 1).

  Further, as a method for forming a carbon nanotube pattern, a method of printing a desired pattern on a substrate surface using a carbon nanotube dispersion using a photosensitive organic solvent and fixing the pattern layer has been proposed (for example, (See Patent Document 2).

When a field effect transistor is formed using a carbon nanotube dispersion by a conventional method, a gate electrode 6 is formed on a substrate 2 and covered with a gate insulating layer 5 as shown in FIG. Next, the source electrode 3 and the drain electrode 4 were formed on the gate insulating layer 5, and then the carbon nanotube dispersion was dropped between the source electrode 3 and the drain electrode 4 to form the semiconductor layer 7.
JP 2003-17508 A JP 2006-69848 A

  However, the diameter of the carbon nanotube is 0.5 to 5 nm, and the source electrode 3 and the drain electrode 4 that are spaced apart so as to ride on the source electrode 3 and the drain electrode 4 having a thickness of several tens to several hundreds of nanometers. When applied on the substrate 2 in the meantime, due to the thickness of the source electrode 3 and the drain electrode 4, the electrical properties of the semiconductor layer 7 made of the carbon nanotube, the end face of the source electrode 3, and the end face of the drain electrode 4 as shown in FIG. There was a problem that it was difficult to get enough connections.

  The present invention has been made in order to solve the above-described problem. When a semiconductor layer is formed by applying a dispersion of carbon nanotubes between a source electrode and a drain electrode, the source electrode, the drain electrode, and the carbon nanotube are used. It is an object of the present invention to provide a method for manufacturing a thin film transistor that can be sufficiently electrically connected to a semiconductor layer, and a thin film transistor manufactured by the method.

  In order to achieve the above object, a method of manufacturing a thin film transistor according to a first aspect of the present invention includes a gate electrode forming step of forming a gate electrode on a substrate, and a gate insulating layer on the substrate so as to cover the gate electrode. Forming a gate insulating layer; forming a source / drain electrode on the gate insulating layer separately from each other; and forming the source / drain electrode on the gate insulating layer between the source electrode and the drain electrode. A semiconductor layer forming step of forming a semiconductor layer made of carbon nanotubes by applying a dispersion made of an aqueous solution containing at least carbon nanotubes apart from the source electrode and the drain electrode; and the semiconductor layer and the source electrode And a conductive portion is formed by applying a conductive liquid between the semiconductor layer and between the semiconductor layer and the drain electrode. Characterized in that a conductive liquid coating process.

  According to a second aspect of the present invention, there is provided a method of manufacturing a thin film transistor, wherein a source / drain electrode forming step of forming a source electrode and a drain electrode on a substrate apart from each other, and the substrate between the source electrode and the drain electrode on the substrate A semiconductor layer forming step of forming a semiconductor layer made of carbon nanotubes by applying a dispersion made of an aqueous solution containing at least carbon nanotubes apart from the source electrode and the drain electrode; and the semiconductor layer and the source electrode A conductive liquid applying step of forming a conductive portion by applying a conductive liquid between the semiconductor layer and between the semiconductor layer and the drain electrode, so as to cover the source electrode, the drain electrode, and the conductive portion A gate insulating layer forming step for forming a gate insulating layer; and the gate insulating layer formed in the gate insulating layer forming step. On the layer, characterized by comprising a gate electrode forming step of forming a gate electrode.

  According to a third aspect of the present invention, there is provided a method for producing a thin film transistor, wherein, in the semiconductor layer forming step, the carbon nanotubes are dried by applying and then drying the dispersion. The semiconductor layer is formed by fixing.

  According to a fourth aspect of the present invention, there is provided a method of manufacturing a thin film transistor, wherein the semiconductor layer is washed after fixing in addition to the structure of the third aspect of the invention, and includes at least one of a surfactant and a drying inhibitor. It is characterized by performing a cleaning process to remove the.

  According to a fifth aspect of the present invention, there is provided a method for manufacturing a thin film transistor, wherein, in addition to the configuration of the first or second aspect, the conductive liquid application step is performed after the dispersion is applied in the semiconductor layer forming step. Then, the carbon nanotube and the conductive liquid are fixed by drying.

  According to a sixth aspect of the present invention, there is provided a method of manufacturing a thin film transistor, wherein, in addition to the configuration of the first aspect of the present invention, a resist layer that prevents adhesion of a conductive liquid is partially formed on the semiconductor layer. Forming a resist coating step for controlling a channel length, performing the conductive liquid coating step after forming the resist layer, and then performing a stripping step for stripping the resist layer.

  According to a seventh aspect of the present invention, there is provided a thin film transistor manufacturing method comprising a protective layer forming step of forming a protective layer on the uppermost layer in addition to the structure of the first aspect of the present invention. And

  In addition to the configuration of the invention according to any one of claims 1 to 7, the method for manufacturing a thin film transistor according to the invention according to claim 8 includes silver nanoink, gold nanoink, or a conductive polymer as the conductive liquid. Any one of the liquids to be contained is used.

  According to a ninth aspect of the present invention, there is provided a method of manufacturing a thin film transistor, in addition to the configuration of the first aspect of the present invention, in the conductive liquid application step, the conductive liquid is an inkjet method or screen printing. It is characterized in that it is applied by either a method or a dispenser method.

  In addition to the constitution of the invention according to any one of claims 1 to 9, the manufacturing method of the thin film transistor of the invention according to claim 10 is characterized in that, in the conductive liquid coating step, the dispersion is applied by an ink jet method or a screen printing method. And applying by any of the dispenser methods.

  A thin film transistor according to an eleventh aspect of the present invention is manufactured by the method for manufacturing a thin film transistor according to any one of the first to tenth aspects.

  In the method for manufacturing a thin film transistor according to the first aspect of the present invention, in the method for manufacturing a bottom gate type thin film transistor, at least a carbon nanotube and a surface activity are formed on the gate insulating layer between the source electrode and the drain electrode in the semiconductor layer forming step. A dispersion liquid composed of an aqueous solution containing an agent and an anti-drying agent is applied and then dried to fix the carbon nanotubes to form a semiconductor layer. Furthermore, in the conductive liquid application step, the conductive portion is formed by applying the conductive liquid between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode. And the conduction between the semiconductor layer and the drain electrode can be ensured satisfactorily. Accordingly, the occurrence rate of conduction failure can be reduced.

  According to a method of manufacturing a thin film transistor according to a second aspect of the present invention, in the method of manufacturing a top gate type thin film transistor, at least a carbon nanotube, a surfactant, and a dry are formed on the gate insulating layer between the source electrode and the drain electrode in the semiconductor layer forming step. A dispersion liquid composed of an aqueous solution containing an inhibitor is applied and then dried to fix the carbon nanotubes, thereby forming a semiconductor layer. Furthermore, in the conductive liquid application step, the conductive portion is formed by applying the conductive liquid between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode. And the conduction between the semiconductor layer and the drain electrode can be ensured satisfactorily. Accordingly, the occurrence rate of conduction failure can be reduced.

  In the thin film transistor manufacturing method according to a third aspect of the invention, in addition to the effect of the first or second aspect of the invention, in the semiconductor layer forming step, the dispersion is applied and then dried to fix the carbon nanotubes. Then, the process can move to the next step.

  In the thin film transistor manufacturing method according to a fourth aspect of the invention, in addition to the effect of the third aspect of the invention, the semiconductor layer is washed in a washing step after fixing, and at least one of the surfactant and the drying inhibitor is removed. Since the impurities contained are removed, the characteristics of the thin film transistor can be improved.

  In the method for producing a thin film transistor of the invention according to claim 5, in addition to the effect of the invention according to claim 1 or 2, the conductive liquid application step is performed after the dispersion is applied in the semiconductor layer formation step. Thereafter, the carbon nanotube and the conductive liquid are fixed by drying, so that the drying can be completed once, and the manufacturing efficiency of the thin film transistor can be improved.

  In the thin film transistor manufacturing method according to the sixth aspect of the invention, in addition to the effect of the invention according to any one of the first to fifth aspects, a resist layer that prevents adhesion of conductive liquid is formed on a part of the semiconductor layer. Then, the resist coating process for controlling the channel length is performed, the conductive liquid coating process is performed after the resist layer is formed, and the stripping process for stripping the resist layer is performed. Therefore, the length and width of the resist are finely controlled. Thus, the channel length can be finely controlled.

  In the method for manufacturing a thin film transistor according to the seventh aspect, in addition to the effect of the invention according to any one of the first to sixth aspects, a protective layer can be formed on the uppermost layer of the thin film transistor by the protective layer forming step. Therefore, a durable thin film transistor can be realized by protecting the source electrode, the drain electrode, and the semiconductor layer.

  In the thin-film transistor manufacturing method according to an eighth aspect of the invention, in addition to the effect of the invention according to any one of the first to seventh aspects, a liquid containing silver nanoink, gold nanoink, or a conductive polymer as the conductive liquid. Since either of these is used, the conductive portion can be formed easily.

  In the thin film transistor manufacturing method according to the ninth aspect of the invention, in addition to the effect of the invention according to any one of the first to eighth aspects, in the conductive liquid application step, the conductive liquid is applied by an ink jet method, a screen printing method, a dispenser. Since the coating is performed by any of the methods, the conductive portion can be formed efficiently and accurately.

  In the method for manufacturing a thin film transistor according to a tenth aspect of the invention, in addition to the effects of the invention according to any one of the first to ninth aspects, in the semiconductor layer forming step, the dispersion liquid may be an inkjet method, a screen printing method, or a dispenser method. Since it is applied by either, the semiconductor layer can be accurately formed by a simple method.

  Since the thin film transistor of the invention according to claim 11 is manufactured by the method of manufacturing a thin film transistor according to any of claims 1 to 10, the effect of the invention of any of claims 1 to 10 is achieved. Can do.

  Hereinafter, the structure of the thin film transistor 1 according to the first embodiment of the thin film transistor and the manufacturing method thereof embodying the present invention will be described with reference to FIGS. FIG. 1 is a plan view of the thin film transistor 1, and FIG. 2 is an enlarged partial cross-sectional view of a portion where the semiconductor layer 7 is formed in the cross-sectional view taken along the line I-I in FIG.

  The thin film transistor 1 shown in FIGS. 1 and 2 is a so-called “bottom gate type” thin film transistor in which the gate electrode 6 is positioned below the source electrode 3 and the drain electrode 4 (on the substrate 2 side). The thin film transistor 1 includes a plate-like substrate 2 having a predetermined thickness. The substrate 2 is a member that supports each member constituting the thin film transistor 1, and as the substrate 2, for example, a glass substrate, polyethersulfone (PES), polyethylene terephthalate (PET), polyimide (PI), and polyethylene naphthalate are used. An insulating plate-like substrate such as a plastic substrate made of phthalate (PEN) or the like is used. When the flexibility is given to the substrate 2, a plastic substrate is used. Various base layers (films) such as an adhesive layer for improving the adhesiveness between the substrate 2 and the gate electrode 6 may be provided on the substrate 2.

  A gate electrode 6 patterned using a material containing a conductive material is formed in a strip shape with a predetermined width (for example, 100 μm) at the center of the upper surface of the substrate 2. Examples of conductive materials include metals such as aluminum (Al), molybdenum (Mo), gold (Au), and chromium (Cr), and conductive polymers such as poly-3,4-ethylenedioxythiophene (PEDOT). These conductive materials can be used, and one kind or a combination of two or more kinds can be used. PEDOT is a conductive polymer obtained by polymerizing 3,4-ethylenedioxythiophene (3,4-ethylenedioxythiophene) in high molecular weight polystyrene sulfonic acid.

The upper surface of the substrate 2 and the upper surface of the gate electrode 6 are covered with the gate insulating layer 5. The gate insulating layer 5 is for insulating the gate electrode 6 from a source electrode 3 and a drain electrode 4 described later, and is formed using an inorganic material or an organic material so as to cover the gate electrode 6. When an inorganic material is employed as the material of the gate insulating layer 5, for example, aluminum oxide (Al ₂ O ₃ ), silicon oxide (SiO ₂ ), silicon nitride (SiN), or the like is applied. On the other hand, when an organic material is used as the material of the gate insulating layer 5, polyimide (PI), polymethyl methacrylate (PMMA), polyparavinylphenol (PVP), or the like is applied.

  In addition, a source electrode 3 and a drain electrode 4 are provided on the upper surface of the gate insulating layer 5 with a predetermined interval therebetween. As a material for the source electrode 3 and the drain electrode 4, a transparent conductive material such as ITO (Indium tin oxide), a conductive polymer such as PEDOT, etc. can be applied in addition to metals such as Al, Mo, Au, and Cr. A semiconductor layer 7 is provided on the upper surface of the gate insulating layer 5 between the source electrode 3 and the drain electrode 4 so as to be separated from the source electrode 3 and the drain electrode 4. The semiconductor layer 7 is arranged so as to face the gate electrode 6 with the gate insulating layer 5 interposed therebetween. The semiconductor layer 7 is formed using a carbon nanotube dispersion for forming a semiconductor layer, which is an aqueous solution containing single-walled carbon nanotubes, a surfactant and a drying inhibitor.

  Further, on the gate insulating layer 5 between the source electrode 3 and the semiconductor layer 7, silver nano ink 9 is applied so as to cover the end portion of the source electrode 3 and the end portion of the semiconductor layer 7 to be electrically connected ( Contact). Also, silver nano-ink 10 is applied on the gate insulating layer 5 between the drain electrode 4 and the semiconductor layer 7 so as to cover the end portion of the drain electrode 4 and the end portion of the semiconductor layer 7 to be electrically connected ( Contact). On the semiconductor layer 7, the silver nano ink 9 and the silver nano ink 10 are dropped at a constant interval (for example, several tens of μm). Therefore, the length portion indicated by the arrow 300 shown in FIG. 2 is a “channel” in which carriers move in the semiconductor layer 7. Here, the “channel length” is the length of the portion indicated by the arrow 300 in FIG. Here, the silver nano inks 9 and 10 correspond to “conductive portions”.

  Next, the surfactant contained in the carbon nanotube dispersion for forming the semiconductor layer will be described. As the surfactant, any of anionic, cationic, amphoteric and nonionic surfactants may be used. Examples of the anionic surfactant include sodium pyrene butyrate (SPB), sodium dodecyl sulfate (SDS) that is solid (powder) at room temperature, sodium cholate (CAS), deoxycholate. Sodium (sodium deoxycholate, DOC), sodium taurodeoxycholate (TDOC), or the like can be used. In addition, as an anionic surfactant, for example, sodium dodecylbenzenesulfonate (DDBS) or dioctylsulfoccatenate, sodium salt (DIOCT) which is liquid at room temperature can be used. As the cationic surfactant, for example, cetyltrimethylammonium bromide (CTABr), cetylpyridinium chloride (CPCI), or the like can be used. Further, as the amphoteric surfactant, 3-[(3-Cholamidopropyl) dimethylamino] propansulfonate (CHAPS), 3-[(3-Chromadopropyl) dimethylamino] -2-hydroxypropansulfate (AP), etc. can be used. Furthermore, as the nonionic surfactant, Polyoxyethylene (20) Sorbitan Monolaurate (Tween (registered trademark of ICI Americas) 20), Polyoxyethylene (20) Soritan Monopalitate (Tween (registered trademark) 20) (Tween (registered trademark) 60), Polyoxyethylene (20) Sorbitan Monooleate (Tween (registered trademark) 80), polyvinylpyrrolidone (PVP), and the like can be used. These surfactants may be used alone or in combination of two or more.

  Among such surfactants, a surfactant that is solid at room temperature is preferably used. Surfactants that are solid at room temperature are usually in powder form. Therefore, in the method of manufacturing the thin film transistor 1 described later, the handling of preparing a carbon nanotube dispersion for forming a semiconductor layer used to form the semiconductor layer 7 is difficult. This is because it is easy. The room temperature in the present invention means 25 degrees Celsius. More preferably, the surfactant uses at least one of sodium deoxycholate and sodium dodecyl sulfate. This is because in the method for manufacturing the thin film transistor 1 described later, single-walled carbon nanotubes can be satisfactorily dispersed in a carbon nanotube dispersion for forming a semiconductor layer even if the amount of surfactant added is small.

  The addition amount of the surfactant is not particularly limited as long as the single wall carbon nanotubes are uniformly dispersed, but the addition amount may be a minute amount and about 1 wt% of the total weight of the dispersion is functionally sufficient. . Further, the surfactant can be removed by an operation such as washing in the manufacturing process. In that case, the semiconductor layer 7 does not contain the surfactant. In terms of functionality, the effect can be achieved even with a smaller amount. For example, if 0.001 to 1 wt% of a surfactant is added, the effect of dispersing the carbon nanotubes can be exhibited.

  On the other hand, the single wall carbon nanotubes to be included in the carbon nanotube dispersion for forming the semiconductor layer may be those containing semiconducting single wall carbon nanotubes. However, a higher proportion of non-aggregated single-walled carbon nanotubes is preferable in terms of excellent switching characteristics than a case where the proportion of non-aggregated single-walled carbon nanotubes is smaller. In addition, it is preferable that the ratio of semiconducting single-walled carbon nanotubes is large in terms of excellent switching characteristics as compared with the case where the ratio of metallic single-walled carbon nanotubes is large. Furthermore, the single-walled carbon nanotubes are randomly distributed in the shortest distance direction so that the longitudinal direction of the single-walled carbon nanotubes included in the semiconductor layer 7 is parallel to the straight line connecting the source electrode and the drain electrode. Compared with the case where it is arrange | positioned, it is preferable at the point which is excellent in switching characteristics.

  Moreover, the drying inhibitor contained in the carbon nanotube dispersion for forming the semiconductor layer is added for the purpose of preventing the carbon nanotube dispersion from drying on the surface of the inkjet nozzle in a short time. Glycerin, ethylene glycol, diethylene glycol, polyethylene glycol, or the like is used as an anti-drying agent for inkjet ink. If the amount added is increased, the effect of preventing drying is increased, but the viscosity is also increased. Therefore, an appropriate amount corresponding to the optimum viscosity of the ink jet system is usually added. In the case of glycerin, the volume ratio of the carbon nanotube dispersion and glycerin was 4: 6, and in the case of diethylene glycol, the volume ratio was 3: 7. However, the optimum viscosity of the ink jet system has a certain tolerance, and is not limited to this ratio.

The thin film transistor 1 according to the first embodiment described in detail above includes the semiconductor layer 7 including single-walled carbon nanotubes. The semiconductor layer 7 and the source electrode 3 are connected (contacted) with the silver nano-ink 9, and the semiconductor layer 7 And the drain electrode 4 are connected (contacted) by the silver nano-ink 10. In the thin film transistor 1 including the semiconductor layer 7 containing carbon nanotubes and the thin film transistor including the organic semiconductor layer, the former is superior in terms of carrier mobility. For example, the carrier mobility of a thin film transistor in which an organic semiconductor layer is formed of polythiophene (solution method) is 9.4 × 10 ⁻³ cm ² / V · sec, and the organic semiconductor layer is formed of pentacene (vacuum evaporation method). The carrier mobility of the formed thin film transistor is 1 cm ² / V · sec. On the other hand, in the thin film transistor provided with the semiconductor layer containing the carbon nanotube, it is 3 to 10 cm ² / V · sec.

  In addition, the single-walled carbon nanotube contained in the semiconductor layer 7 is a thread-like material having high flexibility and high tensile strength, and thus has an advantage that it can be applied to a flexible device. In addition, since the single-walled carbon nanotubes are arranged almost uniformly in the semiconductor layer 7, a thin film transistor having stable transistor characteristics can be obtained. For this reason, the thin film transistor 1 can be suitably used for a miniaturized device such as a flexible display.

  Next, an example of a method for manufacturing the thin film transistor 1 will be described with reference to FIGS. 3 is a flowchart of a manufacturing process of the thin film transistor 1, FIG. 4 is a cross-sectional view of the substrate 2, and FIG. 5 is a cross-sectional view in a state where the gate electrode 6 is formed on the upper surface of the substrate 2 shown in FIG. It is. 6 is a cross-sectional view of the state in which the gate insulating layer 5 is formed on the upper surface of the substrate 2 shown in FIG. 5, and FIG. 7 shows the source electrode 3 and the drain on the surface of the gate insulating layer 5 shown in FIG. It is sectional drawing of the state in which the electrode 4 was formed. 8 is a cross-sectional view showing a state where the semiconductor layer 7 is formed on the surface of the gate insulating layer 5 shown in FIG. 7, and FIG. 9 is a cross-sectional view showing a state where the protective layer 21 is formed. FIG. 10 is a perspective view of the ink jet apparatus 400 used in the semiconductor layer forming step.

  In the method for manufacturing the thin film transistor 1, first, a gate electrode forming step (S11) for forming the gate electrode 6 on the upper surface of the substrate 2 is performed as shown in the flowchart of the manufacturing step in FIG. Next, a gate insulating layer forming step (S12) for forming the gate insulating layer 5 so as to cover the gate electrode 6 on the upper surface of the substrate 2 is performed. Next, a source / drain electrode formation step (S13) for forming the source electrode 3 and the drain electrode 4 on the gate insulating layer 5 is performed, and then the gate insulating layer 5 between the source electrode 3 and the drain electrode 4 is A semiconductor layer forming step (S14) for forming the semiconductor layer 7 is performed at a predetermined distance from the source electrode 3 and the drain electrode 4.

  Here, the carbon nanotube dispersion for semiconductor layer formation used in the semiconductor layer formation step (S14) is a centrifugal separation step (centrifugation of a dispersion containing single wall carbon nanotubes, a surfactant, and a drying inhibitor ( Prepared separately in S1).

  After the semiconductor layer forming step (S14), a cleaning step (S15) for removing the surfactant and the drying inhibitor from the semiconductor layer 7 is performed. Thereafter, silver nanoink is applied on the gate insulating layer 5 between the source electrode 3 and the semiconductor layer 7 so as to cover the end portion of the source electrode 3 and the end portion of the semiconductor layer 7, and the drain electrode 4 and the semiconductor layer On the gate insulating layer 5 between 7, a conductive liquid application step (S <b> 17) for applying the silver nano-ink 10 so as to cover the end of the drain electrode 4 and the end of the semiconductor layer 7 is performed. Finally, a breakdown process (S20) for burning out the conductive single wall carbon nanotubes is performed. The breakdown step (S20) is not necessarily performed, and is performed as necessary. Further, after the breakdown step (S20), a protective layer forming step of forming a protective layer on the uppermost layer may be performed to provide the protective layer 21 on the uppermost layer of the thin film transistor 1 as shown in FIG.

Next, the detail of said manufacturing process is demonstrated. First, the gate electrode formation step (S11) will be described. In this gate electrode formation step (S11), first, the substrate 2 shown in FIG. 4 is sufficiently cleaned by applying ultrasonic waves for 5 minutes with acetone. Next, the substrate 2 is degassed, and a gate electrode 6 made of Al is formed on the substrate 2 by mask vapor deposition as shown in FIG. Note that the conditions of the mask vapor deposition at this time are a vacuum degree of 3 × 10 ⁻⁴ Pa, and heating of the substrate 2 is unnecessary. In the first embodiment, in this gate electrode formation step, a strip-shaped gate electrode 6 having a film thickness of 60 nm and a width of 100 μm is formed on the upper surface of the substrate 2.

  Next, a gate insulating layer forming step (S12) is performed. In the gate insulating layer forming step (S12), as shown in FIG. 6, the gate insulating layer 5 containing polyimide (PI) is formed on the upper surface of the substrate 2 on which the gate electrode 6 is formed by spin coating. In this spin coating method, a 5 wt% solution of a highly heat-resistant polyimide resin (manufactured by Kyocera Chemical Co., Ltd .: trade name “CT4112”) is applied to the upper surface of the substrate 2 and then the substrate 2 is rotated horizontally. Thereafter, the gate insulating layer 5 having a thickness of 350 nm can be formed by drying at 180 ° C. for 1 hour. As an advantage of the spin coating method, it is easy to precisely control the film thickness of the gate insulating layer 5.

Next, a source / drain electrode formation step (S13) is performed. In this source / drain electrode formation step (S13), as shown in FIG. 7, for example, a source electrode 3 made of Au and a drain electrode 4 are formed on the surface of the gate insulating layer 5 by mask vapor deposition. Note that the conditions of the mask vapor deposition at this time are a vacuum degree of 3 × 10 ⁻⁴ Pa, and heating of the substrate 2 is unnecessary. Thus, as an example, the strip-like source electrode 3 and drain electrode 4 each having a thickness of 100 nm, a width of 150 μm, and a length of 500 μm can be formed on the surface of the gate insulating layer 5.

  Subsequently, a semiconductor layer forming step (S14) is performed. In the semiconductor layer forming step (S14), the carbon nanotube dispersion liquid for forming the semiconductor layer prepared in the centrifugal step (S1) that is separately executed is used to form a gate insulating layer between the source electrode 3 and the drain electrode 4 using an ink jet device. A semiconductor layer 7 is formed by discharging to a position spaced apart from the source electrode 3 and the drain electrode 4 by a fixed distance (25 μm as an example) (see FIG. 8). Then, it dries in natural drying or a thermostat. Here, as an example, dry fixing was performed at 120 ° C. for about 10 minutes in a thermostatic bath, and the semiconductor layer 7 was dried by removing moisture, thereby fixing the carbon nanotubes.

  Here, the centrifugation step (S1) for preparing the carbon nanotube dispersion for forming the semiconductor layer will be described. In this centrifugation step (S1), an ultracentrifugation process for preparing a carbon nanotube dispersion for forming a semiconductor layer used for forming the semiconductor layer 7 is performed. In the first embodiment, a carbon nanotube dispersion for forming a semiconductor layer is prepared as follows. First, a dispersion containing a single wall carbon nanotube, a surfactant, and a drying inhibitor is prepared. As the surfactant used at this time, as described above, any of anionic, cationic, amphoteric and nonionic surfactants may be used, and when one kind of surfactant is used. In addition, two or more surfactants may be used in combination. In the first embodiment, 0.1 wt% of single wall carbon nanotubes (trade name “HiPco (registered trademark)”, manufactured by Carbon Nanotechnologies) and 1 wt% of SDS (made by Wako Pure Chemical Industries) in 100 ml of pure water. The mixture was stirred at 200 rpm for about 1 hour using a stirring device, and then shaken for about 3 hours with an ultrasonic cleaning device. At this stage, the single wall carbon nanotubes contained in the dispersion are stably dispersed in the dispersion due to the action of the surfactant, but there are many aggregates of single wall carbon nanotubes.

  Furthermore, the prepared dispersion may be further subjected to ultracentrifugation for 90 minutes at a rotational speed of about 40,000 rpm using an ultracentrifugation device (Ultracentrifugation device CP80WX manufactured by Hitachi High-Tech). By centrifuging at a rotational speed of about 40,000 rpm, a centrifugal force of about 150,000 × g is applied to the dispersion. The supernatant of the dispersion after ultracentrifugation was collected to obtain a carbon nanotube dispersion for forming a semiconductor layer. As a result of such ultracentrifugation, the aggregated single-walled carbon nanotubes settle in the dispersion. Therefore, the carbon nanotube dispersion for forming the semiconductor layer, which is the supernatant of the dispersion, is dispersed before the ultracentrifugation. Compared with, the proportion of single-walled carbon nanotubes that are not aggregated is higher. In addition, this centrifugation process should just be performed before a semiconductor layer formation process (S14).

  Finally, 150 ml of glycerin is mixed with 100 ml of the dispersion thus prepared, and stirred for about 1 hour at 200 rpm using a stirrer to complete a dispersion with a desired viscosity.

  Next, an example of an ink jet apparatus used in the semiconductor layer forming step (S14) will be briefly described with reference to FIG. As shown in FIG. 10, the ink jet apparatus 400 is a so-called ink jet printer, in which holding frames 441 and 442 are erected from a rear end portion of a base frame 402 formed in a substantially square shape, and the holding frames 441 and 442 are interposed between the holding frames 441 and 442. An X-axis frame 404 is installed, and a linear scale 405 that configures the X-axis is provided on the X-axis frame 404. On the linear scale 405, a carriage 406 holding a print head 414 in which a carbon nanotube dispersion for forming a semiconductor layer is sealed is placed so as to be slidable in the longitudinal direction of the linear scale 405. An X-axis motor 407 is provided at the right end portion of the X-axis frame 404 so as to reciprocate the carriage 406 along the linear scale 405. The carriage 406 is provided with four drive circuit boards 408 that respectively drive the four print heads 414.

  Further, the base frame 402 is provided with a Y-axis frame 409 at a position orthogonal to the X-axis frame 404, and a substantially rectangular planar platen 410 is disposed on the Y-axis frame 409 in the longitudinal direction of the Y-axis frame 409. The Y-axis motor 411 is provided at the end of the Y-axis frame 409, and the platen 410 is reciprocated along the Y-axis by the Y-axis motor 411. A flushing position 412 is provided at the left end of the base frame 402. The flushing position 412 is a place where a flushing operation for discharging the carbon nanotube dispersion liquid for forming the semiconductor layer is performed to eliminate clogging of the print head 414. A maintenance unit 413 that performs a wiping operation of the nozzle surface of the print head 414 and a suction operation (purge operation) of the carbon nanotube dispersion liquid for forming a semiconductor layer in the nozzle of the print head is provided at the right end portion of the print head 414.

  Next, the carbon nanotube dispersion for forming a semiconductor layer, which is prepared in the centrifugal separation step (S1) separately performed using the inkjet device 400 described above, is applied to the gate insulating layer 5 between the source electrode 3 and the drain electrode 4. Next, a method of forming the semiconductor layer 7 by discharging to a position spaced apart from the source electrode 3 and the drain electrode 4 by a certain distance will be described. The X-axis motor 407 and the Y-axis motor 411 are driven by the control unit provided in the ink jet apparatus 400, and the carbon nanotube dispersion liquid for forming the semiconductor layer is discharged to a predetermined position.

  In the first embodiment, the gap between the source electrode 3 and the drain electrode 4 is 150 μm, and the carbon nanotube-dispersed droplets for forming the semiconductor layer are ejected at a pitch of 10 μm so that the width is 100 μm. The discharge amount of the carbon nanotube dispersion liquid for forming the semiconductor layer discharged at a time is several pl. In addition, after the carbon nanotube dispersed droplets for forming the semiconductor layer are dropped and applied using the ink jet device 400, it is subjected to drying and fixing at 120 ° C. for about 10 minutes in a natural drying or thermostatic bath to include single wall carbon nanotubes. A semiconductor layer 7 is formed.

  Next, a cleaning step (S15) is performed. In this cleaning step (S15), impurities such as a surfactant and a drying inhibitor are removed from the semiconductor layer 7 after drying and fixing using pure water or ethanol. When glycerin, ethylene glycol, diethylene glycol, or polyethylene glycol is used as an anti-drying agent, these substances are well dissolved in pure water or ethanol, and thus can be sufficiently washed. As this cleaning method, ultrasonic cleaning may be performed using pure water or ethanol as an example for 30 minutes, or it may be immersed in pure water or ethanol for several hours.

  Next, a conductive liquid application step (S17) is performed. In the conductive liquid application step (S17), a conductive liquid (one example) is formed on the gate insulating layer 5 between the source electrode 3 and the semiconductor layer 7 so as to cover the end portion of the source electrode 3 and the end portion of the semiconductor layer 7. In addition, the silver nano ink 9) is applied by dropping, and the conductive material is also formed on the gate insulating layer 5 between the drain electrode 4 and the semiconductor layer 7 so as to cover the end portion of the drain electrode 4 and the end portion of the semiconductor layer 7. A liquid (as an example, silver nanoink 10) is applied dropwise. At this time, the silver nano ink is dropped so that the interval between the silver nano ink 9 and the silver nano ink 10 is separated by a predetermined channel length (as an example, several tens of μm).

  As an example of the conductive liquid used in this conductive liquid coating step (S17), silver nano-ink was used. As the silver nano-ink, low-temperature firing type silver ink L-Ag series manufactured by ULVAC Materials, manufactured by Nippon Paint Co., Ltd. Fine spheres, CAbot AG-IJ-G-100-S1, etc. are available. Further, a conductive polymer material may be used as the conductive liquid. Examples of the conductive polymer material include PEDOT / PSS (3,4-ethylenedioxythiophene (3,4-ethylenedioxythiophene) polymerized in a high molecular weight polystyrene sulfonic acid). As an example, Examples include Baytron (trade name) of Starck Vitec, and Orgacon (trade name) of AGFA-GEVAERT. Furthermore, gold nano ink or the like may be used as the conductive liquid. In this conductive liquid application step (S17), the conductive liquid is applied by any one of an inkjet method, a screen printing method, a dispenser method, and the like.

  In the conductive liquid application step (S17), the silver nano inks 9 and 10 were fixed by baking at 150 ° C. for 10 minutes after dropping.

  Finally, preferably, a breakdown step (S20) is performed. The single-wall carbon nanotubes included in the semiconductor layer 7 include both semiconducting and conductive ones. In this breakdown step (S20), the conductive nanotubes are burned off by energization, and the semiconductor The process is performed to leave only the characteristic nanotubes. Specifically, by applying a voltage between the source electrode 3 and the drain electrode 4, the conductive single wall carbon nanotubes are burned out by heat generated by energization. In this way, a desired semiconductor layer 7 in which only the semiconductor single wall carbon nanotubes are left is formed. Note that this breakdown step may be omitted if necessary.

  In the thin film transistor 1 manufactured by the manufacturing method of the first embodiment, conduction was confirmed between the source electrode 3 and the drain electrode 4 in 9 out of 10 prototyped elements. On the other hand, about 50% of the thin film transistors manufactured by the conventional method have been confirmed to be electrically conductive in the prototype device. Therefore, in the thin film transistor 1 manufactured by the thin film transistor manufacturing method of the first embodiment, electrical connection (contact) between the source electrode 3 and the semiconductor layer 7 and between the drain electrode 4 and the semiconductor layer 7 are performed. A sufficient electrical connection (contact) could be secured, and the conduction failure could be reduced.

 Next, a manufacturing method of the thin film transistor of the second embodiment will be described with reference to FIG. FIG. 11 is a flowchart of the method for manufacturing the thin film transistor of the second embodiment. In the thin film transistor manufacturing method of the second embodiment, the order of the cleaning step (S18) is only different from that of the thin film transistor manufacturing method of the first embodiment. In the thin film transistor manufacturing method of the second embodiment, the gate electrode forming step (S11) to the semiconductor layer forming step (S14) of the thin film transistor manufacturing method of the first embodiment are the same. Then, in the semiconductor layer forming step (S14), as in the first embodiment, the carbon nanotube dispersion liquid for forming the semiconductor layer created in the centrifugation step (S1) separately executed is sourced using an inkjet device. On the gate insulating layer 5 between the electrode 3 and the drain electrode 4, the semiconductor layer 7 is formed by discharging the source electrode 3 and the drain electrode 4 to positions separated from each other by a certain distance (for example, 25 μm). Thereafter, as an example, in a thermostatic bath, drying and fixing are performed at 120 ° C. for about 10 minutes, and moisture of the semiconductor layer 7 is blown and dried to fix the carbon nanotubes.

  Then, a conductive liquid application process (S17) is performed without performing a cleaning process. In the conductive liquid application step (S17), a conductive liquid (one example) is formed on the gate insulating layer 5 between the source electrode 3 and the semiconductor layer 7 so as to cover the end portion of the source electrode 3 and the end portion of the semiconductor layer 7. In addition, the silver nano ink 9) is applied by dropping, and the conductive material is also formed on the gate insulating layer 5 between the drain electrode 4 and the semiconductor layer 7 so as to cover the end portion of the drain electrode 4 and the end portion of the semiconductor layer 7. A liquid (as an example, silver nanoink 10) is applied dropwise. At this time, the silver nano ink is dropped so that the interval between the silver nano ink 9 and the silver nano ink 10 is separated by a predetermined channel length (as an example, several tens of μm).

  In the conductive liquid coating step (S17), the silver nano inks 9 and 10 were dropped and baked at 150 ° C. for 10 minutes to be fixed.

 Next, a cleaning step (S18) was performed. In this cleaning step (S18), impurities such as a surfactant and a drying inhibitor are removed from the semiconductor layer 7 after drying and fixing using pure water or ethanol.

  Finally, a breakdown process (S20) for burning out the conductive single wall carbon nanotubes is performed. The breakdown step (S20) is not necessarily performed, and is performed as necessary. Further, after the breakdown step (S20), a protective layer forming step of forming a protective layer on the uppermost layer may be performed to provide the protective layer 21 on the uppermost layer of the thin film transistor 1 as shown in FIG.

  In the method of manufacturing the thin film transistor according to the second embodiment, since the carbon nanotube film can be confirmed before cleaning, there is an effect that the positioning of dropping the silver nano ink is facilitated.

  Next, a method for manufacturing the thin film transistor according to the third embodiment will be described with reference to the flowchart of FIG. The thin-film transistor manufacturing method of the third embodiment is different from the thin-film transistor manufacturing method of the second embodiment in that in the semiconductor layer forming step (S14), the carbon nanotube dispersion for forming the semiconductor layer is used as an ink jet device. The semiconductor layer 7 is formed by discharging the source electrode 3 and the drain electrode 4 on the gate insulating layer 5 between the source electrode 3 and the drain electrode 4 at positions separated from the source electrode 3 and the drain electrode 4 by a predetermined distance (for example, 25 μm). The point is that the conductive liquid application step (S17) is performed without performing dry fixing. After the carbon nanotube dispersion droplets for forming the semiconductor layer are not dried and fixed, the silver nano ink is dropped, and then, for example, drying and fixing is performed at 150 ° C. for about 10 minutes in a thermostatic bath. The carbon nanotubes are fixed and the silver nano ink is baked at the same time (S17). Thereafter, a cleaning step (S18) is performed to remove impurities such as a surfactant and a drying inhibitor from the semiconductor layer 7 after drying and fixing using pure water or ethanol. Other steps are the same as those in the method of manufacturing the thin film transistor of the second embodiment.

  In the method of manufacturing the thin film transistor of the third embodiment, the carbon nanotube dispersion liquid and the silver nanoink can be dropped in the same step, and the subsequent drying and fixing can be performed simultaneously. Therefore, the semiconductor layer forming step (S14) and The conductive liquid application step (S17) can be performed almost simultaneously, and the manufacturing efficiency is improved.

  Next, a method for manufacturing the thin film transistor according to the fourth embodiment will be described with reference to the flowchart of FIG. 12 and FIGS. FIG. 12 is a flowchart of the method of manufacturing the thin film transistor according to the fourth embodiment, FIG. 13 is an enlarged plan view of the central portion of the thin film transistor 1 showing a state where the resist layer 8 is applied, and FIG. 8 is a cross-sectional view of the thin film transistor 1 showing a state in which the thin film transistor 1 is applied, and FIG. 15 is a cross-sectional view of the thin film transistor 1 in a state where the silver nano inks 9 and 10 are applied in a state where the resist layer 8 is applied.

  In the method of manufacturing the thin film transistor according to the fourth embodiment, a resist layer 8 is formed on the semiconductor layer 7 (S16), and then a conductive liquid application step (S17) is performed to remove the resist layer 8. The difference from the first to third embodiments is that (S19) is provided. In the thin film transistor manufacturing method of the fourth embodiment, the gate electrode forming step (S11) to the semiconductor layer forming step (S14) of the thin film transistor manufacturing method of the first to third embodiments are the same. In the semiconductor layer forming step (S14), as in the first embodiment, the carbon nanotube dispersion liquid for forming the semiconductor layer prepared in the separately performed centrifugation step (S1) is used as the source electrode 3 by using an inkjet apparatus. Then, the semiconductor layer 7 is formed by discharging at a certain distance (for example, 25 μm) from the source electrode 3 and the drain electrode 4 on the gate insulating layer 5 between the drain electrode 4 and the drain electrode 4. Thereafter, as an example, in a thermostatic bath, drying and fixing are performed at 120 ° C. for about 10 minutes, and moisture of the semiconductor layer 7 is blown and dried to fix the carbon nanotubes.

  Next, a photosensitive resist (for example, OFPR800 (trade name) manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied to the semiconductor layer 7 made of the carbon nanotube film without cleaning by 0.5 μm. Then, the resist layer 8 which consists of a photosensitive resist pattern is formed by exposing so that it may become desired channel length, and removing an excess part (S16). This state is the cross-sectional structure shown in FIG. Thereafter, as shown in FIG. 13, a sufficient amount of the silver nano ink 30 is dropped and baked at 150 ° C. for 10 minutes (S17). This state is the structure of the cross-sectional view shown in FIG. In this state, the source electrode 3 and the drain electrode 4 are electrically connected by the silver nano ink 30.

  After that, when the resist layer 8 is peeled off with a solvent (S19), the silver nano ink 30 placed on the resist layer 8 is also peeled off at the same time, and the structure of the thin film transistor 1 shown in FIG. 2 can be formed. Therefore, the electrical connection (contact) between the source electrode 3 and the drain electrode 4 by the silver nano ink 30 is cut off, and the electrical connection between the source electrode 3 and the semiconductor layer 7 and between the drain electrode 4 and the semiconductor layer 7 is performed. (Contact) is held.

  Thereafter, a breakdown process (S20) for burning out the conductive single wall carbon nanotubes is performed. The breakdown step (S20) is not necessarily performed, and is performed as necessary. Further, after the breakdown step (S20), a protective layer forming step of forming a protective layer on the uppermost layer may be performed to provide the protective layer 21 on the uppermost layer of the thin film transistor 1 as shown in FIG.

  In the method of manufacturing the thin film transistor according to the fourth embodiment, a fine channel of several μm can be formed by pattern formation of the photosensitive resist. As the resist, a water-repellent resist or a water-repellent coating agent (Asahi Glass Co., Ltd., Cytop (trade name), etc.) can also be used. In the case where a water-repellent resist is used, in FIG. 13, if the silver nano-ink 30 is water-soluble, it will be repelled by the resist layer 8 and will not remain on the upper portion, so that the subsequent resist layer 8 peeling process is easy. become.

  The present invention is not limited to the first to fourth embodiments described in detail above, and various modifications may be made without departing from the scope of the present invention. For example, the material, size, shape, and arrangement of the substrate 2, the gate electrode 6, the source electrode 3, the drain electrode 4, the gate insulating layer 5, and the semiconductor layer 7 constituting the thin film transistor 1 are limited to those in the first embodiment. However, it can be changed as appropriate.

  The addition amount of single wall carbon nanotubes and a surfactant for preparing a carbon nanotube dispersion for forming a semiconductor layer used for forming the semiconductor layer 7, and the amount of dispersion containing the single wall carbon nanotubes and the surfactant Conditions such as stirring conditions and ultracentrifugation can be changed as appropriate, and are not limited to the case of the first embodiment. For example, if the conditions for ultracentrifugation of a dispersion containing single wall carbon nanotubes and a surfactant are 150,000 × g or more, the aggregated single wall carbon nanotubes contained in the dispersion are allowed to settle. Can do. Moreover, the ultracentrifugation process may be omitted and a carbon nanotube dispersion for forming a semiconductor layer may be prepared.

  In the first to fourth embodiments, the semiconductor layer 7 is formed using the inkjet method in the semiconductor layer forming step (S14). However, other coating methods such as a screen printing method and a dispenser method are used. The semiconductor layer 7 may be formed.

  Next, as a fifth embodiment, a manufacturing method of a so-called “top gate type” thin film transistor 11 in which the gate electrode 16 is located above the source electrode 13 and the drain electrode 14 will be described with reference to FIGS. FIG. 16 is a cross-sectional view of the thin film transistor 11 of the fifth embodiment.

  The thin film transistor 11 is different in structure from the “bottom gate type” thin film transistor 1, but the material of each layer is the same. Therefore, in the fifth embodiment, the structure of the thin film transistor 11 and the manufacturing method thereof will be mainly described, and description of the material will be omitted.

  First, the cross-sectional structure of the thin film transistor 11 will be described. A thin film transistor 11 illustrated in FIG. 16 includes a plate-like substrate 12 and a source electrode 13 and a drain electrode 14 provided on the substrate 12.

  Further, a semiconductor layer 17 is provided on the surface of the substrate 12 sandwiched between the source electrode 13 and the drain electrode 14 so as to be separated from the source electrode 13 and the drain electrode 14 by a predetermined distance (for example, 25 μm). Then, on the substrate 12 between the source electrode 13 and the semiconductor layer 17, the upper surface and side surface of the end portion of the source electrode 13 on the semiconductor layer 17 side, and the upper surface and side surface of the end portion of the semiconductor layer 17 on the source electrode 13 side, Is covered with silver nano-ink 19. Further, on the substrate 12 between the drain electrode 14 and the semiconductor layer 17, the upper surface and side surface of the end portion of the drain electrode 14 on the semiconductor layer 17 side, the upper surface and side surface of the end portion of the semiconductor layer 17 on the drain electrode 14 side, and Are covered with silver nano-ink 20. A gate insulating layer 15 is provided so as to cover the surface of the semiconductor layer 17, the surfaces of the source electrode 13 and the drain electrode 14, and the surfaces of the silver nanoink 19 and the silver nanoink 20. Further, a gate electrode 16 is provided on the surface of the gate insulating layer 15 at a position facing the semiconductor layer 17.

  Next, a method for manufacturing the thin film transistor 11 will be described with reference to FIGS. FIG. 17 is a flowchart of the manufacturing process of the top-gate thin film transistor 11 according to the fifth embodiment. 18 is a cross-sectional view of the substrate 12, FIG. 19 is a cross-sectional view in a state where the source electrode 13 and the drain electrode 14 are formed on the surface of the substrate 12 shown in FIG. 18, and FIG. 19 is a cross-sectional view of a state in which a semiconductor layer 17 is formed on the substrate 12 between the source electrode 13 and the drain electrode 14 shown in FIG. 21 is a cross-sectional view showing a state in which the silver nano ink 19 and the silver nano ink 20 are applied between the semiconductor layer 17 shown in FIG. 20 and the source electrode 13 and the drain electrode 14, and FIG. 6 is a cross-sectional view showing a state in which a gate insulating layer 15 is provided so as to cover the surface of the semiconductor layer 17, the surfaces of the source electrode 13 and the drain electrode 14, and the surfaces of the silver nanoink 19 and the silver nanoink 20. .

  In the method of manufacturing the thin film transistor 11, as shown in FIG. 17, a source / drain electrode formation step (S31) for forming the source electrode 13 and the drain electrode 14 on the upper surface of the substrate 12, respectively, is performed. A semiconductor layer forming step (S32) is performed in which the semiconductor layer 17 is formed on the surface of the substrate 12 sandwiched between the drain electrodes 14 at a predetermined distance from the source electrode 13 and the drain electrode 14. Thereafter, a cleaning step (S33) for removing the surfactant and the drying inhibitor from the semiconductor layer 17 is performed. Next, a conductive liquid application step (S35) is performed, and then the gate insulating layer is formed so as to cover the surface of the semiconductor layer 17, the surfaces of the source electrode 13 and the drain electrode 14, and the surfaces of the silver nano inks 19 and 20. A gate insulating layer forming step (S36) for forming 15 is performed, and a gate electrode forming step (S37) for forming the gate electrode 16 on the surface of the gate insulating layer 15 is performed. Finally, a breakdown process (S38) is performed. Further, the carbon nanotube dispersion for forming the semiconductor layer used in the semiconductor layer forming step (S32) is adjusted in the centrifugation step (S1) as in the first to fourth embodiments. Hereinafter, each step will be specifically described.

In the manufacturing process of the top-gate thin film transistor 11 of the fifth embodiment, first, a source / drain electrode forming step (S31) is performed. In this source / drain electrode formation step, first, the substrate 12 shown in FIG. 18 is sufficiently cleaned. Next, the substrate 12 is degassed, and, as shown in FIG. 19, a source electrode 13 and a drain electrode 14 made of Au, for example, are formed on the surface of the substrate 12 by mask vapor deposition. The conditions for the mask vapor deposition at this time are a degree of vacuum of 3 × 10 ⁻⁴ Pa and heating of the substrate 12 is unnecessary. Thus, the source electrode 13 and the drain electrode 14 having a thickness of 100 nm can be formed on the surface of the substrate 12, respectively.

  Next, a semiconductor layer forming step (S32) is performed. In the semiconductor layer forming step, as shown in FIG. 20, the carbon nanotube dispersion for forming the semiconductor layer prepared in the centrifugal separation step (S1) separately executed is used to form the gap between the source electrode 13 and the drain electrode 14 using an ink jet device. A semiconductor layer 17 is formed on the substrate 12 by discharging to a position separated from the source electrode 13 and the drain electrode 14 by a predetermined distance (for example, 25 μm). Then, it dries in natural drying or a thermostat. Here, as an example, dry fixing was performed at 120 ° C. for about 10 minutes in a thermostatic bath, and the semiconductor layer 17 was dried by removing moisture to fix the carbon nanotubes. The details of the ink jet method and the centrifugation step (S1) are the same as those in the first embodiment, and a description thereof will be omitted.

  Next, a cleaning step (S33) is performed. In this cleaning step (S33), the surfactant and the drying inhibitor are removed from the semiconductor layer 17 after drying and fixing using pure water or ethanol. When glycerin, ethylene glycol, diethylene glycol, or polyethylene glycol is used as an anti-drying agent, these substances are well dissolved in pure water or ethanol, and thus can be sufficiently washed. As this cleaning method, ultrasonic cleaning may be performed using pure water or ethanol as an example for 30 minutes, or it may be immersed in pure water or ethanol for several hours.

  Next, a conductive liquid application step (S35) is performed. In the conductive liquid application step (S35), as shown in FIG. 21, the end of the source electrode 13 and the end of the semiconductor layer 17 are covered on the substrate 12 between the source electrode 13 and the semiconductor layer 17. A conductive liquid (silver nano ink 19 as an example) is applied dropwise, and the end of drain electrode 14 and the end of semiconductor layer 17 are also covered on substrate 12 between drain electrode 14 and semiconductor layer 17. A conductive liquid (silver nano ink 20 as an example) is applied dropwise. At this time, the silver nano ink is dropped so that the interval between the silver nano ink 19 and the silver nano ink 20 is separated by a predetermined channel length (for example, several tens of μm).

  As the conductive liquid used in this conductive liquid coating step (S35), silver nano ink can be used as in the first embodiment. Examples of the silver nano ink include a low-temperature firing type silver ink L-Ag series manufactured by ULVAC Materials, a fine sphere manufactured by Nippon Paint, and AG-IJ-G-100-S1 manufactured by Cabot. Further, a conductive polymer material may be used as the conductive liquid. Examples of the conductive polymer material include PEDOT / PSS (a conductive polymer obtained by polymerizing 3,4-ethylenedioxythiophene (3,4-ethylenedioxythiophene) in high molecular weight polystyrene sulfonic acid). Examples include Baytron (trade name) of Vitec, and Orgacon (trade name) of AGFA-GEVAERT. Furthermore, gold nano ink or the like may be used as the conductive liquid. In the conductive liquid application step (S35), the conductive liquid is applied by any one of an ink jet method, a screen printing method, a dispenser method, and the like.

  In the conductive liquid coating step (S35), the silver nano inks 19 and 20 were fixed by baking at 150 ° C. for 10 minutes after dropping. Here, the silver nano inks 19 and 20 correspond to “conductive portions”.

  Next, a gate insulating layer forming step (S36) is performed. In the gate insulating layer forming step, as shown in FIG. 22, polyimide (by a spin coat method is used so as to cover the surface of the semiconductor layer 17, the surfaces of the source electrode 13 and the drain electrode 14, and the surfaces of the silver nanoinks 19 and 20. A gate insulating layer 15 made of PI) is formed. In this spin coating method, after applying a 5 wt% solution of high heat resistant polyimide resin, the substrate 12 is rotated horizontally. Thereafter, the gate insulating layer 15 having a thickness of 350 nm can be formed by drying at 180 ° C. for about 1 hour.

Next, a gate electrode forming step is performed (S37). In the gate electrode forming step, the gate electrode 16 made of Al is formed at a position facing the semiconductor layer 17 on the surface of the gate insulating layer 15 by mask vapor deposition. The conditions for the mask vapor deposition at this time are a degree of vacuum of 3 × 10 ⁻⁴ Pa and heating of the substrate 12 is unnecessary. Thus, the gate electrode 16 having a thickness of 60 nm can be formed on the surface of the gate insulating layer 15, and the thin film transistor 11 shown in FIG. 16 can be manufactured.

  Finally, preferably, a breakdown step (S38) is performed. This step is a step for burning out the conductive nanotubes by energization and leaving only the semiconducting nanotubes, and the details are the same as in the first embodiment, and the description thereof is omitted. Note that this breakdown step may be omitted if necessary.

  According to the manufacturing method of the thin film transistor 11 of the fifth embodiment described in detail above, the same effect as in the case of the first embodiment can be obtained. Furthermore, since the source electrode 13 and the drain electrode 14 that require the most positional accuracy are formed on the flat substrate 12, the positional accuracy is better than that of the bottom gate type in which the source electrode and the drain electrode are formed on the gate insulating film. Can be formed. In the thin film transistor 11 manufactured by the thin film transistor manufacturing method of the fifth embodiment, the electrical connection (contact) between the source electrode 13 and the semiconductor layer 17 and the connection between the drain electrode 14 and the semiconductor layer 17 are also provided. A sufficient electrical connection (contact) can be secured, and poor conduction can be reduced.

  The present invention is not limited to the fifth embodiment described in detail above, and various modifications may be made without departing from the scope of the present invention. For example, the material, size, shape, and arrangement of the substrate 12, the gate electrode 16, the source electrode 13, the drain electrode 14, the gate insulating layer 15, and the semiconductor layer 17 constituting the thin film transistor 11 are limited to those in the first embodiment. However, it can be changed as appropriate.

  In the fifth embodiment, in the semiconductor layer forming step (S32), the semiconductor layer 17 is formed using the inkjet method. However, the semiconductor layer 17 is formed using another coating method such as a screen printing method or a dispenser method. May be formed.

  Moreover, in the washing | cleaning process (S15, S18, S33) of the said embodiment, although surfactant and the drying inhibitor were removed using pure water or ethanol, it is below the heat-resistant temperature of the base film which comprises the board | substrates 2 and 12. The surfactant and the drying inhibitor may be removed by incineration. Further, the surfactant and the drying inhibitor may be evaporated at a relatively low temperature by heating under reduced pressure. That is, a method suitable for removing the surfactant and drying inhibitor to be used may be used.

  Moreover, you may change a part of process of the said 5th embodiment like the said 2nd thru | or 4th embodiment.

  The thin film transistor manufacturing method and the thin film transistor of the present invention can be applied to a so-called bottom gate type or top gate type thin film transistor and a method for manufacturing the same.

1 is a plan view of a thin film transistor 1. FIG. It is the fragmentary sectional view which expanded the part in which the semiconductor layer 7 is formed among the arrow direction sectional views in the II line | wire of FIG. 3 is a flowchart of a manufacturing process of the thin film transistor 1. 2 is a cross-sectional view of a substrate 2. FIG. FIG. 5 is a cross-sectional view showing a state in which a gate electrode 6 is formed on the upper surface of the substrate 2 shown in FIG. 4. FIG. 6 is a cross-sectional view showing a state in which a gate insulating layer 5 is formed on the upper surface of the substrate 2 shown in FIG. 5. It is sectional drawing of the state in which the source electrode 3 and the drain electrode 4 were formed in the surface of the gate insulating layer 5 shown in FIG. FIG. 8 is a cross-sectional view showing a state in which a semiconductor layer 7 is formed on the surface of the gate insulating layer 5 shown in FIG. 7. It is sectional drawing which shows the state in which the protective layer 21 was formed. It is a perspective view of the inkjet apparatus 400 used in a semiconductor layer formation process. It is a flowchart of the manufacturing method of the thin-film transistor of 2nd embodiment. It is a flowchart of the manufacturing method of the thin-film transistor of 4th embodiment. 2 is an enlarged plan view of a central portion of a thin film transistor 1 showing a state where a resist layer 8 is applied. FIG. It is sectional drawing in the middle of manufacture of the thin-film transistor 1 which shows the state which apply | coated the resist layer 8. FIG. It is sectional drawing in the middle of manufacture of the thin-film transistor 1 of the state which apply | coated the silver nanoinks 9 and 10 in the state which apply | coated the resist layer 8. FIG. It is sectional drawing of the thin-film transistor 11 of 5th embodiment. It is a flowchart of the manufacturing process of the top gate type thin-film transistor 11 of 5th embodiment. 2 is a cross-sectional view of a substrate 12. FIG. FIG. 19 is a cross-sectional view illustrating a state in which a source electrode 13 and a drain electrode 14 are formed on the surface of the substrate 12 illustrated in FIG. 18. FIG. 20 is a cross-sectional view showing a state in which a semiconductor layer 17 is formed on the substrate 12 between the source electrode 13 and the drain electrode 14 shown in FIG. 19. FIG. 20 is a cross-sectional view illustrating a state in which silver nanoink 19 and silver nanoink 20 are applied between the semiconductor layer 17 illustrated in FIG. 19 and the source electrode 13 and the drain electrode 14. 20 is a cross-sectional view illustrating a state in which the gate insulating layer 15 is provided so as to cover the surface of the semiconductor layer 17 illustrated in FIG. 20, the surfaces of the source electrode 13 and the drain electrode 14, and the surfaces of the silver nanoink 19 and the silver nanoink 20. It is. It is a longitudinal cross-sectional view of the thin-film transistor 1 manufactured with the conventional manufacturing method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Thin film transistor 2 Substrate 3 Source electrode 4 Drain electrode 5 Gate insulating layer 6 Gate electrode 7 Semiconductor layer 9 Silver nano ink 10 Silver nano ink 11 Thin film transistor 12 Substrate 13 Source electrode 14 Drain electrode 15 Gate insulating layer 16 Gate electrode 17 Semiconductor layer 19 Silver nano ink 20 Silver nano ink

Claims (11)

A gate electrode forming step of forming a gate electrode on the substrate;
Forming a gate insulating layer on the substrate so as to cover the gate electrode; and
A source / drain electrode forming step of forming a source electrode and a drain electrode spaced apart from each other on the gate insulating layer;
On the gate insulating layer between the source electrode and the drain electrode, a dispersion layer made of an aqueous solution containing at least carbon nanotubes is applied apart from the source electrode and the drain electrode to form a semiconductor layer made of carbon nanotubes. A semiconductor layer forming step,
A thin film transistor comprising: a conductive liquid application step of forming a conductive portion by applying a conductive liquid between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode. Manufacturing method. A source / drain electrode forming step of forming a source electrode and a drain electrode on a substrate apart from each other;
A semiconductor in which a semiconductor layer made of carbon nanotubes is formed on the substrate between the source electrode and the drain electrode by applying a dispersion made of an aqueous solution containing at least carbon nanotubes apart from the source electrode and the drain electrode. A layer forming step;
A conductive liquid applying step of forming a conductive portion by applying a conductive liquid between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode;
A gate insulating layer forming step of forming a gate insulating layer so as to cover the source electrode, the drain electrode, and the conductive portion;
Forming a gate electrode on the gate insulating layer formed in the gate insulating layer forming step; and
A method for producing a thin film transistor, comprising:   3. The method of manufacturing a thin film transistor according to claim 1, wherein, in the semiconductor layer forming step, the semiconductor layer is formed by fixing the carbon nanotubes by drying after applying the dispersion liquid.   4. The method of manufacturing a thin film transistor according to claim 3, wherein the semiconductor layer is washed after fixing to perform a washing step of removing impurities including at least one of a surfactant and a drying inhibitor.   3. The method according to claim 1, wherein after applying the dispersion liquid in the semiconductor layer forming step, the conductive liquid application step is performed, and then the carbon nanotubes and the conductive liquid are fixed by drying. A method for manufacturing a thin film transistor. Forming a resist layer for preventing the adhesion of conductive liquid on a part of the semiconductor layer, and comprising a resist coating process for controlling a channel length;
The conductive liquid application step is performed after the resist layer is formed,
6. The method of manufacturing a thin film transistor according to claim 1, wherein a peeling step for peeling the resist layer is performed thereafter.   7. The method of manufacturing a thin film transistor according to claim 1, further comprising a protective layer forming step of forming a protective layer as an uppermost layer.   8. The method of manufacturing a thin film transistor according to claim 1, wherein any one of silver nanoink, gold nanoink, and a liquid containing a conductive polymer is used as the conductive liquid.   9. The method of manufacturing a thin film transistor according to claim 1, wherein in the conductive liquid application step, the conductive liquid is applied by any one of an ink jet method, a screen printing method, and a dispenser method.   10. The method of manufacturing a thin film transistor according to claim 1, wherein in the semiconductor layer forming step, the dispersion is applied by any one of an ink jet method, a screen printing method, and a dispenser method.   A thin film transistor manufactured by the method for manufacturing a thin film transistor according to claim 1.

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