Nothing Special   »   [go: up one dir, main page]

JP2009176926A - Through wiring substrate and manufacturing method thereof - Google Patents

Through wiring substrate and manufacturing method thereof Download PDF

Info

Publication number
JP2009176926A
JP2009176926A JP2008013676A JP2008013676A JP2009176926A JP 2009176926 A JP2009176926 A JP 2009176926A JP 2008013676 A JP2008013676 A JP 2008013676A JP 2008013676 A JP2008013676 A JP 2008013676A JP 2009176926 A JP2009176926 A JP 2009176926A
Authority
JP
Japan
Prior art keywords
substrate
wiring
conductive layer
manufacturing
modified portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2008013676A
Other languages
Japanese (ja)
Inventor
Satoshi Yamamoto
敏 山本
Hirokazu Hashimoto
廣和 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP2008013676A priority Critical patent/JP2009176926A/en
Publication of JP2009176926A publication Critical patent/JP2009176926A/en
Withdrawn legal-status Critical Current

Links

Images

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a through wiring substrate, capable of forming a reform part on a device in which an electrode pad, a wiring layer, and the like have been completed, being applicable to an actual device. <P>SOLUTION: The manufacturing method is for a through wiring substrate 1 that is equipped with a through wiring 7 where fine holes 5 arranged inside a substrate 2 are packed with conductors 6. The manufacturing method comprises at least following steps in order: a step A in which a conductive layer 3 is formed on one surface of the substrate 2; a step B in which laser beam 10 is radiated to the other surface side of the substrate 2 to form a reform part 4 in which one is connected to the conductive layer 3 while the other is communicated with a position different from the conductive layer 3; a step C in which the reform part 4 is removed to form the fine hole 5; and a step D in which the fine hole 5 is packed with the conductors 6. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、電子デバイスや光学デバイス、MEMSデバイス等の高密度実装、またはそれらのデバイスを一つのパッケージ内でシステム化するSiP(システムインパッケージ)を可能にする貫通配線を備えた貫通配線基板及びその製造方法に関する。   The present invention relates to a through wiring substrate having through wiring that enables high-density mounting of electronic devices, optical devices, MEMS devices, etc., or SiP (system in package) for systematizing these devices in one package, and It relates to the manufacturing method.

近年、携帯電話等の電子機器の高機能化に伴い、それらに使われる電子デバイス等にも更なる高速化、高機能化が要求されている。これを実現するためには、微細化等によるデバイス自身の高速化だけではなく、デバイスのパッケージにも高速化、高密度化に向けた技術開発が必須となっている。   In recent years, with the enhancement of functions of electronic devices such as mobile phones, electronic devices and the like used for them have been required to have higher speed and higher functions. In order to realize this, not only the speed of the device itself by miniaturization and the like, but also the development of technology for the speed and density of the device package is indispensable.

高密度実装を実現する技術としては、チップに微細な貫通電極を設けてチップを積層実装する三次元実装や、貫通電極が形成された貫通電極基板を用いたシステムインパッケージ(SiP)が提案されており、これらの実装技術を実現するための貫通電極形成技術や貫通電極基板の形成技術の研究開発が活発に行われている。また、微細孔形成技術としてレーザー等により基板内部を改質し、改質した部分をエッチングにより除去することで微細孔を形成する技術が研究されている(例えば、特許文献1参照)。   As technologies for realizing high-density mounting, three-dimensional mounting in which chips are stacked by mounting fine through electrodes on a chip and system in package (SiP) using a through electrode substrate on which through electrodes are formed have been proposed. Research and development of through-electrode formation technology and through-electrode substrate formation technology for realizing these mounting technologies are being actively conducted. As a technique for forming micropores, a technique for forming micropores by modifying the inside of a substrate with a laser or the like and removing the modified portion by etching has been studied (for example, see Patent Document 1).

しかしながら、上述した貫通配線およびその製造方法を実用化するに当たっては、例えば(1)既に電極パッドや配線層等が形成され完成しているデバイスに対して改質部及び貫通配線を形成する方法、(2)デバイスで通常用いられているAlパッドなど、酸性の薬液に対して耐性を持たない電極への貫通配線の形成、(3)既に電極パッドや配線層等が形成され完成しているデバイスの耐熱温度を超えないプロセス温度での貫通配線の作製、等、解決すべきいくつかの技術的課題があり、これらを解決しなければその実現は困難であった。
特開2006-303360号公報
However, in putting the above-described through wiring and its manufacturing method into practical use, for example, (1) a method of forming a modified portion and a through wiring for a device that has already been formed with electrode pads, wiring layers, and the like, (2) Formation of through wiring to electrodes that are not resistant to acidic chemicals such as Al pads normally used in devices, (3) Devices that have already been formed with electrode pads, wiring layers, etc. There are some technical problems to be solved, such as fabrication of through wiring at a process temperature not exceeding the heat-resistant temperature, and it has been difficult to realize them unless these are solved.
JP 2006-303360 A

本発明は、このような従来の実情に鑑みて考案されたものであり、既に電極パッドや配線層等が形成され完成しているデバイスに対して改質部を形成する方ことが可能で、実デバイスヘ適用できる貫通配線基板の製造方法を提供することを第一の目的とする。
また、本発明は、デバイス自身の小型化、高機能化、及び高密度実装を実現可能な、より自由度の高い貫通配線を有する貫通配線基板を提供することを第二の目的とする。
The present invention has been devised in view of such a conventional situation, and it is possible to form a modified portion with respect to a device in which an electrode pad, a wiring layer or the like has already been formed, It is a first object to provide a method of manufacturing a through wiring substrate that can be applied to an actual device.
A second object of the present invention is to provide a through wiring substrate having a through wiring with a higher degree of freedom that can realize miniaturization, high functionality, and high-density mounting of the device itself.

本発明の請求項1に記載の貫通配線基板の製造方法は、基板内部に配された微細孔に導体が充填されてなる貫通配線を備えた貫通配線基板の製造方法であって、前記基板の一方の面に導電層を形成する工程Aと、前記基板の他方の面側よりレーザー光を照射し、一方が前記導電層と接続し、他方が前記導電層とは異なる位置に連通された改質部を形成する工程Bと、前記改質部を除去し、前記微細孔を形成する工程Cと、前記微細孔に導体を充填する工程Dと、を少なくとも順に備えることを特徴とする。
本発明の請求項2に記載の貫通配線基板の製造方法は、請求項1において、前記工程Bにおいて、前記基板を透過する波長域にある光源を有する顕微鏡を用いて、位置情報を認識しながら改質部を形成することを特徴とする。
本発明の請求項3に記載の貫通配線基板の製造方法は、請求項1において、前記導電層は複数の層を有し、少なくとも一層は耐酸性の材料からなることを特徴とする。
本発明の請求項4に記載の貫通配線基板の製造方法は、請求項1において、前記工程Cにおいて、前記改質部の除去を、酸溶液によるエッチング法を用いて行うことを特徴とする。
本発明の請求項5に記載の貫通配線基板の製造方法は、請求項1において、前記工程Dにおいて、前記導体の充填を、少なくとも前記基板及び前記導電層の耐熱温度よりも低い温度で行うことを特徴とする。
本発明の請求項6に記載の貫通配線基板は、請求項1乃至請求項5のいずれかに記載の製造方法を用いて製造されたことを特徴とする。
A method for manufacturing a through wiring board according to claim 1 of the present invention is a method for manufacturing a through wiring board having a through wiring in which a fine hole disposed inside the board is filled with a conductor, Step A for forming a conductive layer on one side, laser beam irradiation from the other side of the substrate, one connected to the conductive layer, and the other connected to a position different from the conductive layer. It is characterized in that it comprises at least a process B for forming a mass part, a process C for removing the modified part to form the fine holes, and a process D for filling the fine holes with a conductor.
According to a second aspect of the present invention, there is provided a method for manufacturing a through wiring substrate according to the first aspect of the present invention, in the step B, while recognizing position information using a microscope having a light source in a wavelength region that transmits the substrate. A reforming part is formed.
According to a third aspect of the present invention, there is provided a through wiring substrate manufacturing method according to the first aspect, wherein the conductive layer has a plurality of layers, and at least one layer is made of an acid resistant material.
According to a fourth aspect of the present invention, there is provided a through wiring substrate manufacturing method according to the first aspect, wherein the modified portion is removed by an etching method using an acid solution in the step C.
According to a fifth aspect of the present invention, in the method for manufacturing a through wiring substrate according to the first aspect, in the step D, the conductor is filled at a temperature lower than at least the heat resistant temperature of the substrate and the conductive layer. It is characterized by.
A through wiring board according to a sixth aspect of the present invention is manufactured using the manufacturing method according to any one of the first to fifth aspects.

本発明では、基板の一方の面に導電層を形成し、基板の他方の面側よりレーザー光を照射することで、既に電極パッドや配線層等の導電層が形成されている実デバイスに対しても改質部を形成することができる。その後改質部を除去し、形成された微細孔に導体を充填することで、基板内部で屈曲や分岐をした複雑な構造を持つ貫通配線を形成することが可能な貫通配線基板の製造方法を提供することができる。   In the present invention, a conductive layer is formed on one surface of a substrate, and laser light is irradiated from the other surface side of the substrate, so that an actual device in which a conductive layer such as an electrode pad or a wiring layer is already formed is used. However, the modified portion can be formed. A method of manufacturing a through wiring substrate capable of forming a through wiring having a complicated structure bent or branched inside the substrate by removing the modified portion and then filling the formed fine holes with a conductor. Can be provided.

また、本発明では、請求項1乃至請求項5のいずれかに記載の製造方法を用いて製造されることで、基板内部で屈曲や分岐をした複雑な構造を持つ貫通配線を有するものとなり、デバイス自身の小型化、高機能化、及び高密度実装を実現可能な、より自由度の高い貫通配線を有する貫通配線基板を提供することができる。   Further, in the present invention, by using the manufacturing method according to any one of claims 1 to 5, it has a through wiring having a complicated structure bent or branched inside the substrate, It is possible to provide a through wiring substrate having a through wiring with a higher degree of freedom, which can realize miniaturization, high functionality, and high-density mounting of the device itself.

以下、本発明に係る貫通配線基板及びその製造方法の一実施形態を図面に基づいて説明する。   Hereinafter, an embodiment of a through wiring board and a manufacturing method thereof according to the present invention will be described with reference to the drawings.

図1は、本発明の貫通配線基板の一構成例を模式的に示す断面図である。
この貫通配線基板1は、基板2と、該基板2の一方の面2aに配された導電層3と、基板2内部に配された微細孔5に導体6が充填されてなる貫通配線7と、を備えている。
本発明の貫通配線基板1は、以下に説明するような本発明の製造方法を用いて製造されたことを特徴とする。これにより、貫通配線基板1は、基板2内部で屈曲や分岐をした複雑な構造を持つ貫通配線7を有するものとなる。その結果、本発明の貫通配線基板1は、デバイス自身の小型化、高機能化、及び高密度実装を実現可能な、より自由度の高い貫通配線を有するものとなる。
FIG. 1 is a cross-sectional view schematically showing a configuration example of the through wiring board of the present invention.
The through wiring substrate 1 includes a substrate 2, a conductive layer 3 disposed on one surface 2 a of the substrate 2, and a through wiring 7 in which a conductor 6 is filled in a fine hole 5 disposed inside the substrate 2. It is equipped with.
The through wiring board 1 of the present invention is manufactured by using the manufacturing method of the present invention as described below. Accordingly, the through wiring substrate 1 has the through wiring 7 having a complicated structure bent or branched inside the substrate 2. As a result, the through wiring substrate 1 of the present invention has a through wiring with a higher degree of freedom that can realize miniaturization, high functionality, and high-density mounting of the device itself.

次に、本発明の貫通配線基板の製造方法について説明する。
図2は、本発明の貫通配線基板の製造方法を工程順に示した模式的な断面図である。
本発明の貫通配線基板の製造方法は、基板2の一方の面2aに導電層3を形成する工程Aと、前記基板2の他方の面2b側よりレーザー光を照射し、一方が前記導電層3と接続し、他方が前記導電層3とは異なる位置に連通された改質部4を形成する工程Bと、前記改質部4を除去し、前記微細孔5を形成する工程Cと、前記微細孔5に導体6を充填する工程Dと、を少なくとも順に備えることを特徴とする。
Next, the manufacturing method of the penetration wiring board of the present invention is explained.
FIG. 2 is a schematic cross-sectional view showing the method of manufacturing the through wiring board of the present invention in the order of steps.
In the manufacturing method of the through wiring board according to the present invention, the step A of forming the conductive layer 3 on the one surface 2a of the substrate 2 is irradiated with laser light from the other surface 2b side of the substrate 2, and one is the conductive layer. 3, a process B for forming a modified portion 4 that is connected to a position different from that of the conductive layer 3, and a process C for removing the modified portion 4 to form the micropore 5. And a step D of filling the fine holes 5 with a conductor 6 in order.

本発明では、基板2の一方の面2aに導電層3を形成し、基板2の他方の面2b側よりレーザー光を照射することで、既に電極パッドや配線層等の導電層3が形成されている実デバイスに対しても改質部4を形成することができる。その後改質部4を除去し、微細孔5に導体6を充填することで、基板2内部で屈曲や分岐をした複雑な構造を持つ貫通配線7を形成することが可能となる。
以下、工程順に説明する。なお、以下の説明では、具体的な数値等を挙げて説明しているが、本発明はこの例に限定されるものではない。
In the present invention, the conductive layer 3 is formed on one surface 2a of the substrate 2 and the laser light is irradiated from the other surface 2b side of the substrate 2, so that the conductive layer 3 such as an electrode pad or a wiring layer is already formed. The reforming part 4 can be formed also for the actual device. Thereafter, the modified portion 4 is removed, and the fine hole 5 is filled with the conductor 6, whereby the through wiring 7 having a complicated structure bent or branched inside the substrate 2 can be formed.
Hereinafter, it demonstrates in order of a process. In the following description, specific numerical values and the like are described, but the present invention is not limited to this example.

(1)まず、図2(a)に示すように、基板2を用意し、該基板2の一方の面2aに導電層3を形成する[工程A]。
本実施例では、貫通配線7を形成する基板2として、厚さが500μmのガラス(石英)基板2を用いた。
なお、基板2は石英基板に限定されるものではなく、例えばサファイアやシリコン(Si)等の絶縁基板や、アルカリ成分等を含んだ他の他成分ガラス基板を用いることができ、その厚さも50μm〜数mm程度まで適宜設定できる。
(1) First, as shown in FIG. 2A, a substrate 2 is prepared, and a conductive layer 3 is formed on one surface 2a of the substrate 2 [step A].
In this embodiment, a glass (quartz) substrate 2 having a thickness of 500 μm is used as the substrate 2 on which the through wiring 7 is formed.
The substrate 2 is not limited to a quartz substrate, and for example, an insulating substrate such as sapphire or silicon (Si) or other component glass substrate containing an alkali component can be used, and its thickness is also 50 μm. It can set suitably to about several mm.

はじめに、基板2上に導電層3を成膜する。この導電層3は、電極パッドを構成していてもよく、また、電気回路等の配線層を構成していてもよい。導電層3の形成方法としては特に限定されるものではないが、真空蒸着法やスパッタ法、めっき法等により形成することができる。なお、このは、当該貫通配線7を適用するデバイスの製造プロセスにおいて形成することもできる。   First, the conductive layer 3 is formed on the substrate 2. The conductive layer 3 may constitute an electrode pad or a wiring layer such as an electric circuit. The method for forming the conductive layer 3 is not particularly limited, but the conductive layer 3 can be formed by vacuum deposition, sputtering, plating, or the like. This can also be formed in a device manufacturing process to which the through wiring 7 is applied.

前記導電層3は複数の層を有し、少なくとも一層は耐酸性の材料からなることが好ましい。これにより、後工程[工程C]において、酸溶液を用いて改質部4をエッチンクする際、導電層3がダメージを受けるのを防止することができる。
本実施例においては、導電層3として、いずれも耐酸性の強いチタン(Ti)及び金(Au)を積層したAu(300nm)/Ti(50nm)薄膜を用い、これをパターニングすることによって、一道が100μmの電極パッドを作製した。
The conductive layer 3 preferably includes a plurality of layers, and at least one layer is made of an acid resistant material. Thereby, it is possible to prevent the conductive layer 3 from being damaged when the modified portion 4 is etched using an acid solution in the post-process [Step C].
In this embodiment, as the conductive layer 3, an Au (300 nm) / Ti (50 nm) thin film in which titanium (Ti) and gold (Au) having strong acid resistance are both laminated is used, and this is patterned, so that one way Produced an electrode pad of 100 μm.

なお、導電層3としては、Ptなど、他の耐酸性の強い金属を用いることができ、また、ポリシリコンなど、金属以外の導電体を用いることもできる。また、少なくとも1層が耐酸性の強い材料から構成されていれば良いため、上述した耐酸性の強い薄膜と、他の耐酸性の弱い薄膜、例えばアルミ(Al)等からなる薄膜と積層した構造であっても良い。更に、各層の厚さも数10nm〜1μm程度まで適宜設定することができる。   The conductive layer 3 can be made of another acid-resistant metal such as Pt, or a conductor other than metal such as polysilicon. In addition, since at least one layer only needs to be made of a material with strong acid resistance, a structure in which the above-mentioned thin film with strong acid resistance and another thin film with low acid resistance, for example, a thin film made of aluminum (Al) or the like are laminated. It may be. Furthermore, the thickness of each layer can also be set appropriately from several tens of nm to about 1 μm.

(2)次に、図2(b)に示すように、前記基板2の他方の面(導電層3を形成した面2aとは反対側の面)2b側よりレーザー光10を照射し、一方が前記導電層3と接続し、他方が前記導電層3とは異なる位置に連通された改質部4を形成する[工程B]。
基板2の少なくとも微細孔5を形成したい箇所にレーザー光10を照射して基板2内に改質部4を形成する。導電層3を形成した面2aとは反対側の面2bからレーザー光を照射して基板2の改質を行う。これにより、既に形成された電極パッドや配線層等の導電層3が存在する基板2に対しても内部の改質が可能となる。また、導電層3と接続するように改質部4ひいては微細孔5を形成することが可能となる。
(2) Next, as shown in FIG. 2B, the laser beam 10 is irradiated from the other surface (the surface opposite to the surface 2a on which the conductive layer 3 is formed) 2b of the substrate 2, Is connected to the conductive layer 3, and the modified portion 4 is connected to the other side at a position different from the conductive layer 3 [Step B].
The modified portion 4 is formed in the substrate 2 by irradiating at least a portion of the substrate 2 where the microhole 5 is to be formed with the laser beam 10. The substrate 2 is modified by irradiating laser light from a surface 2b opposite to the surface 2a on which the conductive layer 3 is formed. As a result, it is possible to modify the interior of the substrate 2 on which the conductive layer 3 such as an electrode pad or a wiring layer already formed exists. Further, it is possible to form the modified portion 4 and thus the fine hole 5 so as to be connected to the conductive layer 3.

本実施例においては、レーザー光10の光源として、波長が石英基板に対して透明である800nm、パルス幅が250fs、平均出力800mWのフェムト秒レーザーを用い、基板2内部に焦点を結ぶようにレーザービームを照射し、上記基板2の面2b側から内部に向かって焦点を走査し、例えば径を数μm〜数十μmとした改質部4を形成した。   In this embodiment, a femtosecond laser having a wavelength of 800 nm transparent to a quartz substrate, a pulse width of 250 fs, and an average output of 800 mW is used as a light source of the laser beam 10, and the laser is focused on the inside of the substrate 2. The modified portion 4 having a diameter of, for example, several μm to several tens of μm was formed by irradiating the beam and scanning the focal point from the surface 2b side of the substrate 2 toward the inside.

この際、焦点と基板位置とを制御することにより、様々な形状の改質部4を形成することができる。本発明では、一方が導電層3と接続し、他方が基板2のいずれかの面に開口するように改質部4を形成する。ここでは一例として、クランク状の改質部4A(4)、及びY字状の改質部4B(4)を形成した。これにより、電極パッドや配線層等の導電層3に対して貫通配線7を形成することが可能となる。その結果、本発明を実デバイスヘ応用することが可能となる。   At this time, the modified portion 4 having various shapes can be formed by controlling the focal point and the substrate position. In the present invention, the modified portion 4 is formed so that one is connected to the conductive layer 3 and the other is open to any surface of the substrate 2. Here, as an example, a crank-shaped reforming section 4A (4) and a Y-shaped reforming section 4B (4) are formed. Thereby, the through wiring 7 can be formed in the conductive layer 3 such as an electrode pad or a wiring layer. As a result, the present invention can be applied to actual devices.

また、前記基板2を透過する波長域にある光源(ここではハロゲン光)を有する顕微鏡を用い、基板2内部及び上記導電層3を観察して位置情報を認識し、焦点の走査の制御を行いながら改質部4を形成することが好ましい。これにより、導電層3と接続するように改質部4を形成することができる。   In addition, using a microscope having a light source (here, halogen light) in a wavelength region that transmits the substrate 2, the position information is recognized by observing the inside of the substrate 2 and the conductive layer 3, and the focus scanning is controlled. However, it is preferable to form the modified portion 4. Thereby, the modification part 4 can be formed so as to be connected to the conductive layer 3.

なお、レーザー光10としては、改質する材料に応じて、異なる波長、パルス幅、平均出力であっても良く、また、改質する方向も、先に焦点を導電層3付近に当てておき、基板2内部から表面に向かって改質しても良い。   The laser beam 10 may have a different wavelength, pulse width, and average output depending on the material to be modified. The modification direction is also focused on the vicinity of the conductive layer 3 in advance. The substrate 2 may be modified from the inside toward the surface.

(3)次に、図2(c)に示すように、前記改質部4を除去し、微細孔5を形成する[工程C]。
次に、容器内に入れた所定の薬液中に、改質部4を形成した基板2を浸漬する。これにより、改質部4は薬液によりウェットエッチングされ、基板2内から除去される。その結果、改質部4が存在した部分に、微細孔5が形成される。本実施例では、薬液として濃度が10Wt%のフッ酸(HF)溶液を主成分とする酸溶液を用いた。これにより、改質部4のみを選択的にエッチンクでき、微細孔5の形成が可能となる。
(3) Next, as shown in FIG. 2 (c), the modified portion 4 is removed to form micropores 5 [step C].
Next, the board | substrate 2 in which the modification part 4 was formed is immersed in the predetermined chemical | medical solution put in the container. Thereby, the modified portion 4 is wet-etched with the chemical solution and removed from the substrate 2. As a result, the micropore 5 is formed in the portion where the modified portion 4 is present. In this example, an acid solution mainly composed of a hydrofluoric acid (HF) solution having a concentration of 10 Wt% was used as the chemical solution. As a result, only the modified portion 4 can be selectively etched, and the micropores 5 can be formed.

本エッチングは、改質部4が非改質部4に比べて非常に早く(数十倍)エッチングされる現象を利用するものであり、結果として改質部4に起因した形状の微細孔5を形成することができる。本実施例においては、クランク状の微細孔5A(5)、及びY字状の微細孔5B(5)を形成した。また、微細孔5の孔径は50μmとした。   This etching utilizes the phenomenon that the modified portion 4 is etched very quickly (tens of times) compared to the non-modified portion 4, and as a result, the fine holes 5 having a shape caused by the modified portion 4. Can be formed. In the present embodiment, crank-shaped fine holes 5A (5) and Y-shaped fine holes 5B (5) were formed. The hole diameter of the fine holes 5 was 50 μm.

なお、薬液はフッ酸に限定されず、例えばフッ酸に硝酸等を適量添加したフッ硝酸系の混酸等を用いることができる。また、微細孔5の孔径も、貫通配線7の用途に応じて10μm程度から300μm程度まで適宜設定することができる。さらに、形成する微細孔5も、基板2を貫通するもの、非貫通のものでもどちらでも良い。上述した方法により、基板2の内部に三次元的に自由な構造を持つ微細孔5を形成することができる。   The chemical solution is not limited to hydrofluoric acid, and for example, a hydrofluoric acid-based mixed acid obtained by adding an appropriate amount of nitric acid or the like to hydrofluoric acid can be used. Further, the hole diameter of the fine hole 5 can be appropriately set from about 10 μm to about 300 μm according to the use of the through wiring 7. Further, the fine holes 5 to be formed may be either those that penetrate the substrate 2 or those that do not penetrate. By the method described above, the fine holes 5 having a three-dimensional free structure can be formed inside the substrate 2.

このとき、前記導電層3は複数の層を有し、少なくとも一層は耐酸性の材料からなることで、酸溶液を用いて改質部4をエッチンクする際、導電層3がダメージを受けるのを防止することができる。しかし、基板2上の耐酸性がない部分については、レジスト等を適宜被服してから上記エッチングをおこなうことで、当該部分を保護することができる.さらに微細孔5の径も、数μm〜数百μmで適宜設定することができる。   At this time, the conductive layer 3 includes a plurality of layers, and at least one layer is made of an acid-resistant material, so that the conductive layer 3 is damaged when the modified portion 4 is etched using an acid solution. Can be prevented. However, the portion having no acid resistance on the substrate 2 can be protected by applying the resist or the like and then performing the etching. Furthermore, the diameter of the micropore 5 can also be set as appropriate from several μm to several hundred μm.

なお、レーザー光により石英基板の一部を改質した後、改質した部分をエッチングにより除去する微細孔の形成方法については、例えば「機能材料」2003年2月号、P.44〜51などで開示されている。   In addition, about the formation method of the micropore which removes the modified part by etching after modifying a part of the quartz substrate with laser light, for example, “Functional Materials” February 2003, pages 44 to 51, etc. Is disclosed.

(4)次に、図2(a)に示すように、前記微細孔5に導体6を充填する[工程D]。
微細孔5の内部に導体6を充填することで、貫通配線7を形成する。
本実施例においては、導体6として金錫(Au80wt%−Sn20wt%)を用い、溶融金属充填法により微細孔5内部に充填した。溶融金属充填法は、圧力差を用いて微細孔5内部に溶融した金属を流しこむものであり、複雑な形状をした微細孔5内部にも気密性良く短時間で充填できる方法である。本実施例では、クランク状の貫通配線7A(7)、及びY字状の貫通配線7B(7)を形成した。
(4) Next, as shown in FIG. 2A, the fine holes 5 are filled with a conductor 6 [step D].
By filling the inside of the minute hole 5 with the conductor 6, the through wiring 7 is formed.
In this example, gold tin (Au 80 wt% -Sn 20 wt%) was used as the conductor 6 and filled inside the fine holes 5 by a molten metal filling method. The molten metal filling method is a method in which molten metal is poured into the micro holes 5 using a pressure difference, and the inside of the micro holes 5 having a complicated shape can be filled in a short time with good airtightness. In this embodiment, the crank-shaped through wiring 7A (7) and the Y-shaped through wiring 7B (7) are formed.

ここで、前記導体6の充填を、少なくとも前記基板2及び前記導電層3の耐熱温度よりも低い温度で行うことが好ましい。本実施例では、充填金属として、融点が約280℃である金錫(Au80wt%−Sn20wt%)を用いているため、プロセス温度をAlなど、他の構成材料の耐熱温度より低い温度にすることができる。これにより、構成部材に熱的ダメージを与えることなく貫通配線7の形成が可能となる。   Here, the filling of the conductor 6 is preferably performed at a temperature lower than at least the heat resistance temperature of the substrate 2 and the conductive layer 3. In this embodiment, gold tin (Au 80 wt% -Sn 20 wt%) having a melting point of about 280 ° C. is used as the filling metal, so that the process temperature is lower than the heat resistance temperature of other constituent materials such as Al. Can do. As a result, the through wiring 7 can be formed without causing thermal damage to the constituent members.

なお、本実施例においては、導体6として金錫(Au−Sn)を用いたが、本発明はこれに限定されず、異なる組成を有する金錫合金や、錫(Sn)、インジウム(In)などの金属、また、錫鉛(Sn−Pb)系、錫(Sn)基、鉛(Pb)基、金(Au)基、インジウム(In)基、アルミニウム(Al)基などのはんだを使用することができる。   In this example, gold tin (Au—Sn) was used as the conductor 6, but the present invention is not limited to this, and gold-tin alloys having different compositions, tin (Sn), indium (In) In addition, a solder such as a tin lead (Sn—Pb) group, a tin (Sn) group, a lead (Pb) group, a gold (Au) group, an indium (In) group, or an aluminum (Al) group is used. be able to.

また、充填方法も溶融金属吸引法を用いたが、本発明はこれに限定されず、微細孔5の形状によっては、めっき法による金属充填や印刑法による導電性ペーストの充填、またCVD等によるカーボンナノチューブの充填を利用することができる。   Also, although the molten metal suction method is used as the filling method, the present invention is not limited to this, and depending on the shape of the fine hole 5, the metal filling by the plating method, the filling of the conductive paste by the stamping method, the CVD, etc. Carbon nanotube filling can be utilized.

なお、導体6は、微細孔5内部に完全に充填されていなくとも良いが、MEMSデバイスなどのパッケージには気密性を要求するものが少なくないため、貫通配線基板1などの応用においては、好ましくは微細孔5の内部に完全に充填されているのが良い。
以上の工程により、図1に示したような貫通配線基板1を得ることができる。
The conductor 6 does not need to be completely filled in the microhole 5, but a package such as a MEMS device often requires airtightness. Therefore, it is preferable for applications such as the through wiring board 1 and the like. It is preferable that the inside of the fine hole 5 is completely filled.
Through the above steps, the through wiring substrate 1 as shown in FIG. 1 can be obtained.

上述したような本発明の貫通配線基板の製造方法によれば、既に電極パッドや配線層等の導電層3が形成されているデバイスに対しても、基板2内部で屈曲や分岐をした複雑な構造を持つ貫通配線7を形成することができる。   According to the method for manufacturing a through wiring board of the present invention as described above, even a device in which a conductive layer 3 such as an electrode pad or a wiring layer has already been formed is complicatedly bent or branched inside the board 2. The through wiring 7 having a structure can be formed.

これにより、本発明の製造方法により製造された、本発明の貫通配線基板1は、デバイス自身の小型化、高機能化、及び高密度実装を実現可能な、より自由度の高い貫通配線7を有するものとなる。   Thereby, the through wiring board 1 of the present invention manufactured by the manufacturing method of the present invention has a through wiring 7 with a higher degree of freedom that can realize miniaturization, high functionality, and high density mounting of the device itself. It will have.

なお、実デバイスヘの適用においては、当該貫通配線7と電気的に接続するように、はんだなどのバンプを形成することで、プリント回路基板等にフリップチップ実装できる小型の半導体パッケージを提供することが可能となる。図3に、一例として当該貫通配線7と電気的に接続するはんだバンプ8を形成した際の模式的な断面図を示す。   In application to an actual device, it is possible to provide a small semiconductor package that can be flip-chip mounted on a printed circuit board or the like by forming bumps such as solder so as to be electrically connected to the through wiring 7. It becomes possible. FIG. 3 shows a schematic cross-sectional view when a solder bump 8 electrically connected to the through wiring 7 is formed as an example.

以上、本発明の貫通配線基板及びその製造方法について説明してきたが、本発明はこれに限定されるものではなく、発明の趣旨を逸脱しない範囲で、適宜変更が可能である。   As mentioned above, although the penetration wiring board and its manufacturing method of this invention were demonstrated, this invention is not limited to this, In the range which does not deviate from the meaning of invention, it can change suitably.

本発明は、貫通配線7を有する貫通配線基板及びその製造方法に広く適用可能である。   The present invention can be widely applied to a through wiring substrate having the through wiring 7 and a manufacturing method thereof.

本発明に係る貫通配線基板の一例を示す断面図。Sectional drawing which shows an example of the penetration wiring board which concerns on this invention. 図1に示す貫通配線基板の製造方法の一例を工程順に示す断面図。Sectional drawing which shows an example of the manufacturing method of the penetration wiring board shown in FIG. 1 in order of a process. 図1に示す貫通配線基板にはんだバンプを形成した状態を示す断面図。Sectional drawing which shows the state in which the solder bump was formed in the penetration wiring board shown in FIG.

符号の説明Explanation of symbols

1 貫通配線基板、2 基板、3 導電層、4 改質部、5 微細孔、6 導体、7 貫通配線、8 はんだバンプ、10 レーザー光。   DESCRIPTION OF SYMBOLS 1 Through wiring board, 2 Substrate, 3 Conductive layer, 4 Modified part, 5 Fine hole, 6 Conductor, 7 Through wiring, 8 Solder bump, 10 Laser light.

Claims (6)

基板内部に配された微細孔に導体が充填されてなる貫通配線を備えた貫通配線基板の製造方法であって、
前記基板の一方の面に導電層を形成する工程Aと、
前記基板の他方の面側よりレーザー光を照射し、一方が前記導電層と接続し、他方が前記導電層とは異なる位置に連通された改質部を形成する工程Bと、
前記改質部を除去し、前記微細孔を形成する工程Cと、
前記微細孔に導体を充填する工程Dと、を少なくとも順に備えることを特徴とする貫通配線基板の製造方法。
A method of manufacturing a through wiring board having a through wiring in which conductors are filled in fine holes arranged inside the board,
Forming a conductive layer on one surface of the substrate;
Irradiating a laser beam from the other surface side of the substrate, one of which is connected to the conductive layer, and the other is a step B of forming a modified portion connected to a position different from the conductive layer;
Removing the modified portion and forming the micropores; and
And a step D of filling the fine holes with a conductor at least in order.
前記工程Bにおいて、前記基板を透過する波長域にある光源を有する顕微鏡を用いて、位置情報を認識しながら改質部を形成することを特徴とする請求項1に記載の貫通配線基板の製造方法。   2. The through wiring substrate according to claim 1, wherein in the step B, the modified portion is formed while recognizing position information using a microscope having a light source in a wavelength region that transmits the substrate. Method. 前記導電層は複数の層を有し、少なくとも一層は耐酸性の材料からなることを特徴とする請求項1に記載の貫通配線基板の製造方法。   The method for manufacturing a through wiring substrate according to claim 1, wherein the conductive layer includes a plurality of layers, and at least one layer is made of an acid resistant material. 前記工程Cにおいて、前記改質部の除去を、酸溶液によるエッチング法を用いて行うことを特徴とする請求項1に記載の貫通配線基板の製造方法。   The method for manufacturing a through wiring substrate according to claim 1, wherein in the step C, the modified portion is removed using an etching method using an acid solution. 前記工程Dにおいて、前記導体の充填を、少なくとも前記基板及び前記導電層の耐熱温度よりも低い温度で行うことを特徴とする請求項1に記載の貫通配線基板の製造方法。   2. The method of manufacturing a through wiring substrate according to claim 1, wherein in the step D, the conductor is filled at a temperature lower than at least a heat resistant temperature of the substrate and the conductive layer. 請求項1乃至請求項5のいずれかに記載の製造方法を用いて製造されたことを特徴とする貫通配線基板。   A through wiring substrate manufactured using the manufacturing method according to claim 1.
JP2008013676A 2008-01-24 2008-01-24 Through wiring substrate and manufacturing method thereof Withdrawn JP2009176926A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008013676A JP2009176926A (en) 2008-01-24 2008-01-24 Through wiring substrate and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008013676A JP2009176926A (en) 2008-01-24 2008-01-24 Through wiring substrate and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JP2009176926A true JP2009176926A (en) 2009-08-06

Family

ID=41031719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008013676A Withdrawn JP2009176926A (en) 2008-01-24 2008-01-24 Through wiring substrate and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2009176926A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011048862A1 (en) * 2009-10-23 2011-04-28 株式会社フジクラ Device-mounting structure and device-mounting method
WO2011048858A1 (en) * 2009-10-23 2011-04-28 株式会社フジクラ Device mounting structure and device mounting method
WO2011078345A1 (en) * 2009-12-25 2011-06-30 株式会社フジクラ Through-wired substrate and manufacturing method therefor
WO2011126108A1 (en) * 2010-04-08 2011-10-13 株式会社フジクラ Method of forming microstructures, laser irradiation device, and substrate
JP2012064188A (en) * 2010-09-14 2012-03-29 Samsung Electro-Mechanics Co Ltd Capacitive touch panel and its manufacturing method
CN102422414A (en) * 2009-04-28 2012-04-18 株式会社藤仓 Device mounting structure and device mounting method
CN103308813A (en) * 2012-03-13 2013-09-18 Oht株式会社 Electrode substrate, and circuit pattern inspection device with the same
US8703517B2 (en) 2010-10-29 2014-04-22 Denso Corporation Method of Manufacturing a Semiconductor Device Including Removing a Reformed Layer
JP2016517626A (en) * 2013-04-04 2016-06-16 エル・ピー・ケー・エフ・レーザー・ウント・エレクトロニクス・アクチエンゲゼルシヤフト Method and apparatus for drilling through holes in a substrate and substrate thus manufactured
CN116887522A (en) * 2023-06-19 2023-10-13 武汉铱科赛科技有限公司 Circuit board manufacturing method, system, device and equipment

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002118363A (en) * 2000-10-12 2002-04-19 Nippon Avionics Co Ltd Multilayer printed wiring board and manufacturing method thereof
JP2004200584A (en) * 2002-12-20 2004-07-15 Fujikura Ltd Method of forming penetration electrode and substrate having penetration electrode
JP2004311720A (en) * 2003-04-07 2004-11-04 Fujikura Ltd Multilayer wiring board, base material therefor and its manufacturing method
JP2005032901A (en) * 2003-07-10 2005-02-03 Fcm Kk Conductive sheet
JP2006303360A (en) * 2005-04-25 2006-11-02 Fujikura Ltd Through-wire board, composite board, and electronic apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002118363A (en) * 2000-10-12 2002-04-19 Nippon Avionics Co Ltd Multilayer printed wiring board and manufacturing method thereof
JP2004200584A (en) * 2002-12-20 2004-07-15 Fujikura Ltd Method of forming penetration electrode and substrate having penetration electrode
JP2004311720A (en) * 2003-04-07 2004-11-04 Fujikura Ltd Multilayer wiring board, base material therefor and its manufacturing method
JP2005032901A (en) * 2003-07-10 2005-02-03 Fcm Kk Conductive sheet
JP2006303360A (en) * 2005-04-25 2006-11-02 Fujikura Ltd Through-wire board, composite board, and electronic apparatus

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102422414A (en) * 2009-04-28 2012-04-18 株式会社藤仓 Device mounting structure and device mounting method
US20120205148A1 (en) * 2009-10-23 2012-08-16 Fujikura Ltd. Device packaging structure and device packaging method
WO2011048862A1 (en) * 2009-10-23 2011-04-28 株式会社フジクラ Device-mounting structure and device-mounting method
WO2011048858A1 (en) * 2009-10-23 2011-04-28 株式会社フジクラ Device mounting structure and device mounting method
CN102577637A (en) * 2009-10-23 2012-07-11 株式会社藤仓 Device-mounting structure and device-mounting method
CN102598879A (en) * 2009-10-23 2012-07-18 株式会社藤仓 Device mounting structure and device mounting method
JP2012178611A (en) * 2009-10-23 2012-09-13 Fujikura Ltd Method for manufacturing device mounting structure
JP5085787B2 (en) * 2009-10-23 2012-11-28 株式会社フジクラ Device mounting structure manufacturing method
JP5085788B2 (en) * 2009-10-23 2012-11-28 株式会社フジクラ Device mounting structure
WO2011078345A1 (en) * 2009-12-25 2011-06-30 株式会社フジクラ Through-wired substrate and manufacturing method therefor
JP2011134982A (en) * 2009-12-25 2011-07-07 Fujikura Ltd Through wiring board and method of manufacturing the same
WO2011126108A1 (en) * 2010-04-08 2011-10-13 株式会社フジクラ Method of forming microstructures, laser irradiation device, and substrate
CN102823334A (en) * 2010-04-08 2012-12-12 株式会社藤仓 Method of forming microstructures, laser irradiation device, and substrate
JP2012064188A (en) * 2010-09-14 2012-03-29 Samsung Electro-Mechanics Co Ltd Capacitive touch panel and its manufacturing method
US8703517B2 (en) 2010-10-29 2014-04-22 Denso Corporation Method of Manufacturing a Semiconductor Device Including Removing a Reformed Layer
CN103308813A (en) * 2012-03-13 2013-09-18 Oht株式会社 Electrode substrate, and circuit pattern inspection device with the same
JP2013191682A (en) * 2012-03-13 2013-09-26 Oht Inc Electrode substrate, circuit pattern inspection apparatus including the same
JP2016517626A (en) * 2013-04-04 2016-06-16 エル・ピー・ケー・エフ・レーザー・ウント・エレクトロニクス・アクチエンゲゼルシヤフト Method and apparatus for drilling through holes in a substrate and substrate thus manufactured
US10610971B2 (en) 2013-04-04 2020-04-07 Lpkf Laser & Electronics Ag Method for producing recesses in a substrate
US11618104B2 (en) 2013-04-04 2023-04-04 Lpkf Laser & Electronics Se Method and device for providing through-openings in a substrate and a substrate produced in said manner
CN116887522A (en) * 2023-06-19 2023-10-13 武汉铱科赛科技有限公司 Circuit board manufacturing method, system, device and equipment

Similar Documents

Publication Publication Date Title
JP2009176926A (en) Through wiring substrate and manufacturing method thereof
US11881414B2 (en) Method for manufacturing glass device, and glass device
JP2008288577A (en) Substrate treatment method, through-wire substrate and its manufacturing method, and electronic component
JP4323303B2 (en) Substrate manufacturing method
WO2012153839A1 (en) Through wiring board, electronic device package, and electronic component
CN106664795B (en) Structure and method for manufacturing same
JP5478009B2 (en) Manufacturing method of semiconductor package
KR101215644B1 (en) Semiconductor chip, package and method for manufacturing semiconductor chip
JP2008277733A (en) Semiconductor device
JP2018085412A (en) Through electrode substrate and manufacturing method thereof
JP5828406B2 (en) Substrate bonding method
JP4538058B2 (en) Integrated semiconductor device and integrated three-dimensional semiconductor device
WO2010016351A1 (en) Method for manufacturing semiconductor device
KR100874588B1 (en) Manufacturing method of flip chip for electrical function test
JP5248179B2 (en) Manufacturing method of electronic device
JP5522377B2 (en) Method for forming through electrode and semiconductor substrate
JP2002299553A (en) Module and its manufacturing method
JP4964505B2 (en) Semiconductor device, manufacturing method thereof, and electronic component
JP2008203336A (en) Opto-electric composite substrate, manufacturing method thereof and electronic equipment
CN110120350B (en) Forming method, packaging structure and packaging method of conductive column
JP2007250999A (en) Method for manufacturing semiconductor device
JP2007266381A (en) Method of manufacturing semiconductor device
JP2007305715A (en) Manufacturing method for wiring board
JP2019140343A (en) Semiconductor device and manufacturing method of the same
JP2014086963A (en) Package and method of manufacturing package

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101125

A977 Report on retrieval

Effective date: 20120223

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Effective date: 20120228

Free format text: JAPANESE INTERMEDIATE CODE: A131

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120427

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121211

A521 Written amendment

Effective date: 20130212

Free format text: JAPANESE INTERMEDIATE CODE: A523

A761 Written withdrawal of application

Effective date: 20130621

Free format text: JAPANESE INTERMEDIATE CODE: A761