JP2009164200A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for fully siliciding a gate electrode without causing degradation in characteristics of MISFET, and to provide a semiconductor device having MISFET of excellent characteristics which is formed by such manufacturing method. <P>SOLUTION: The semiconductor device includes a transistor comprising a gate insulating film 18 formed on a semiconductor substrate 10, a gate electrode 26n which includes a metal silicide film 56b formed on the gate insulating film 18 and a metal silicide film 56a formed on the metal silicide film 56b and in which the composition of silicon against metal element in the metal silicide film 56b is higher than that of the silicon against the metal element in the metal silicide film 56a, and an impurity diffusion region pair 54 formed in the semiconductor substrates 10 on both sides of the gate electrode 26n. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a MISFET whose gate electrode is fully silicided and a manufacturing method thereof.

  As a structure for improving the characteristics of the MISFET, a technique for forming a gate electrode using only metal silicide (fully silicided gate (FUSI) technology) has been proposed. By forming the gate electrode from metal silicide, the gate resistance can be reduced as compared with the gate electrode having a polycide structure, and depletion of the gate electrode can be prevented.

  As a method of forming a gate electrode only with metal silicide, a dummy electrode made of amorphous silicon or amorphous silicon is formed on the gate electrode formation portion, and then metal is deposited and heat treatment for silicidation reaction is performed. A method of replacing with silicide has been proposed. According to this method, it is possible to maintain consistency with a conventional process in which the source / drain regions are formed in a self-aligned manner with respect to the gate electrode, and to suppress contamination of the silicon substrate with a metal material.

As a technique for fully siliciding the gate electrode, a method called a CMP method is known. In this method, a dummy electrode made of amorphous silicon or amorphous silicon is formed, an interlayer insulating film covering the dummy electrode is formed, and the interlayer insulating film is flattened by chemical mechanical polishing (CMP) or the like to form a dummy. After the upper surface of the electrode is exposed, a metal film is deposited and silicidation heat treatment is performed to silicidize only the gate electrode.
JP 2004-071653 A JP 2005-228868 A Y. Tsuchiya et al., "Physical mechanism of work function modulation due to impurity pileup at Ni-FUSI / SiO (N) interface", IEDM (IEEE International Electron Devices Meeting) 2005 (December), pp. 637-640 T. Hoffmann et al., "Ni-based FUSI gates: CMOS integration for 45nm node and beyond", IEDM (IEEE International Electron Devices Meeting) 2006 (December), pp. 269-272

  However, it is known that the full silicidation of the gate electrode using the above-described CMP method causes the characteristic deterioration of the N-type MISFET. The characteristic deterioration of the N-type MISFET is due to the volume change accompanying silicidation of the dummy electrode, and stress that is disadvantageous to the N-type MISFET (for example, stress that applies compressive stress in the channel direction) is introduced to the formed gate electrode. It is believed that this is because For this reason, a full silicidation technique for the gate electrode without the characteristic deterioration of the N-type MISFET is desired.

  An object of the present invention is to provide a method for manufacturing a semiconductor device in which a gate electrode can be fully silicided without causing deterioration of the characteristics of the MISFET, and a semiconductor device having an excellent characteristic MISFET formed by using such a manufacturing method. Is to provide.

  According to an aspect of the present invention, a first gate insulating film formed on a first region of a semiconductor substrate, a first metal silicide film formed on the first gate insulating film, A second metal silicide film formed on the first metal silicide film, and the composition of silicon relative to the metal element in the first metal silicide film is silicon relative to the metal element in the second metal silicide film. There is provided a semiconductor device having a first transistor having a first gate electrode larger than the composition of the first gate electrode and a first impurity diffusion region pair formed in the semiconductor substrate on both sides of the first gate electrode. The

  According to another aspect of the present invention, a step of forming a gate insulating film on a semiconductor substrate and a first semiconductor film made of a semiconductor material mainly composed of silicon are formed on the gate insulating film. A step of forming a second semiconductor film made of a semiconductor material mainly composed of silicon on the first semiconductor film via a natural oxide film, the first semiconductor film, and the second semiconductor film. Patterning a semiconductor film to form a gate electrode including the first semiconductor film and the second semiconductor film; depositing a metal film on the gate electrode; and heat treatment to form the gate electrode. A step of reacting a second semiconductor film with the metal film to form a first metal silicide film on the upper surface of the second semiconductor film; a step of removing the unreacted metal film; Gate electrode and said By reacting a first metal silicide film, a method of manufacturing a semiconductor device having a step of metal silicide the entire of the gate electrode.

  According to still another aspect of the present invention, a first gate insulating film is formed on a first region of a semiconductor substrate, and a second gate insulating film is formed on a second region of the semiconductor substrate. Forming a first semiconductor film made of a semiconductor material mainly composed of silicon on the first gate insulating film and the second gate insulating film, and forming the first semiconductor film on the first region. Introducing an impurity at a first concentration into the first semiconductor film and introducing an impurity at a second concentration lower than the first concentration into the first semiconductor film on the second region; And forming a second semiconductor film made of a semiconductor material mainly composed of silicon on the first semiconductor film into which the impurity has been introduced via a natural oxide film, and the first semiconductor film And patterning the second semiconductor film, on the first gate insulating film Forming a first gate electrode including the first semiconductor film and the second semiconductor film, and including the first semiconductor film and the second semiconductor film on the second gate insulating film; A step of forming a second gate electrode; a step of depositing a metal film on the first gate electrode and the second gate electrode; and a step of heat-treating the second semiconductor film and the metal film. A first metal silicide film is formed on the upper surface of the second semiconductor film of the first gate electrode, and a second metal silicide film is formed on the upper surface of the second semiconductor film of the second gate electrode. A step of forming, a step of removing the unreacted metal film, and a heat treatment to cause the first gate electrode and the first metal silicide film to react with each other. While forming a metal silicide, A method of selectively forming a metal silicide of the second semiconductor film of the second gate electrode by reacting the second gate electrode with the second metal silicide film. Provided.

  According to the present invention, since the semiconductor film mainly composed of the silicon film for forming the gate electrode has a two-layer structure and silicidation is performed using flash lamp annealing, the metal silicide film containing excessive silicon in the lower layer portion And a full silicide gate electrode having a low-resistance metal silicide film in the upper layer portion can be formed. Thereby, the resistance value of the gate electrode can be reduced by the upper metal silicide film, and the stress applied to the channel region of the N-type MISFET by the lower metal silicide film can be reduced. Thereby, the gate electrode can be fully silicided without deteriorating the characteristics of the N-type MISFET. Further, by appropriately controlling the concentration of the impurity introduced into the lower semiconductor film, the gate electrode to be fully silicided and the gate electrode having a polycide structure can be separately formed.

[Reference example]
A method of manufacturing a semiconductor device according to a reference example of the present invention will be described with reference to FIGS.

  1 to 4 are process sectional views showing a method of manufacturing a semiconductor device according to this reference example.

  As described above, in the full silicidation technique of the gate electrode by the CMP method, an unfavorable stress is applied to the N-type MISFET, and the characteristics of the N-type MISFET may be deteriorated.

  A full silicidation technique of the gate electrode using a method different from the CMP method will be described below as a reference example.

  First, the element isolation film 12 embedded in the element isolation trench is formed on the main surface of the silicon substrate 10 by, for example, STI (Shallow Trench Isolation). In the figure, the active region on the left side of the central element isolation film 12 is an N-type MISFET formation region, and the active region on the right side of the central element isolation film 12 is a P-type MISFET formation region.

  Next, by photolithography and ion implantation, a P-type well 14 is formed in the silicon substrate 10 in the N-type MISFET formation region, and an N-type well 16 is formed in the silicon substrate 10 in the P-type MISFET formation region (FIG. 1 ( a)).

  Next, for example, heat treatment is performed in a nitrogen atmosphere to activate the impurities constituting the P-type well 14 and the N-type well 16.

  Next, a gate insulating film 18 made of, for example, a silicon oxide film is formed on the active region of the silicon substrate 10 defined by the element isolation film 12 by, eg, thermal oxidation.

  Next, an amorphous silicon film 20 of, eg, a 100 nm-thickness is deposited on the entire surface by, eg, LPCVD (FIG. 1B).

  Next, the amorphous silicon film 20 is patterned by photolithography and dry etching, the gate electrode 26n made of the amorphous silicon film 20 is formed in the N-type MISFET formation region, and the gate electrode made of the amorphous silicon film 20 in the P-type MISFET formation region. 26p is formed.

  Next, after forming a photoresist film (not shown) covering the P-type MISFET formation region by photolithography, ion implantation is performed using the photoresist film and the gate electrode 26n as a mask, and the inside of the silicon substrate 10 on both sides of the gate electrode 26n. Then, an impurity diffusion region 28 to be an extension region and a pocket region is formed.

  Similarly, after a photoresist film (not shown) covering the N-type MISFET formation region is formed by photolithography, ion implantation is performed using the photoresist film and the gate electrode 26p as a mask, and silicon substrates on both sides of the gate electrode 26p. An impurity diffusion region 30 to be an extension region and a pocket region is formed in 10 (FIG. 2A).

  Next, after depositing, for example, a silicon oxide film and a silicon nitride film on the entire surface by, for example, plasma CVD, these films are etched back, and sidewalls made of a silicon oxide film are formed on the side walls of the gate electrodes 26n and 26p. Spacers 32 and sidewall spacers 34 made of a silicon nitride film are formed.

  Next, after forming a photoresist film (not shown) covering the P-type MISFET formation region by photolithography, ion implantation is performed using the photoresist film, the gate electrode 26n, and the side wall spacers 32 and 34 as a mask, and the gate electrode 26n. Impurity diffusion regions 36 to be source / drain regions are formed in the silicon substrates 10 on both sides of the substrate.

  Similarly, after forming a photoresist film (not shown) covering the N-type MISFET formation region by photolithography, ion implantation is performed using the photoresist film, the gate electrode 26p and the side wall spacers 32 and 34 as a mask, and the gate Impurity diffusion regions 38 serving as source / drain regions are formed in the silicon substrate 10 on both sides of the electrode 26p (FIG. 2B).

  Next, after a silicon oxide film, for example, is deposited on the entire surface by, eg, plasma CVD, this film is etched back, and a silicon oxide film is formed on the side walls of the gate electrodes 26n, 26p where the side wall spacers 32, 34 are formed. A side wall spacer 48 is formed.

  Next, after forming a photoresist film (not shown) covering the P-type MISFET formation region by photolithography, ion implantation is performed using the photoresist film, the gate electrode 26n, and the side wall spacers 32, 34, and 48 as a mask. Impurity diffusion regions 50 serving as source / drain regions are formed in the silicon substrate 10 on both sides of the electrode 26n.

  Similarly, after forming a photoresist film (not shown) covering the N-type MISFET formation region by photolithography, ion implantation is performed using this photoresist film, gate electrode 26p and sidewall spacers 32, 34, and 48 as a mask. Then, impurity diffusion regions 40 serving as source / drain regions are formed in the silicon substrate 10 on both sides of the gate electrode 26p.

  Next, heat treatment is performed, for example, in a nitrogen atmosphere, and the impurities constituting the impurity diffusion regions 28, 30, 36, 38, 40, and 50 are activated. As a result, the source / drain regions 52 of the N-type MISFET composed of the impurity diffusion regions 28, 36, 50 are formed in the silicon substrate 10 on both sides of the gate electrode 26n, and in the silicon substrate 10 on both sides of the gate electrode 26p, A source / drain region 54 of the P-type MISFET composed of the impurity diffusion regions 30, 38, 40 is formed (FIG. 3A).

  Next, a nickel (Ni) film is deposited on the entire surface by, eg, sputtering.

Next, annealing is performed for a short time at a temperature of about 200 to 300 ° C., for example, in a nitrogen atmosphere (first annealing). By this heat treatment, nickel in a phase containing a large amount of nickel (for example, Ni ₂ Si) is formed in regions where the nickel film and the exposed portion of silicon are in contact (on the source / drain regions 52 and 54 and on the gate electrodes 26n and 26p). A silicide film 56 is selectively formed.

  Next, the unreacted nickel film is removed by wet etching using, for example, SPM (sulfuric acid / hydrogen peroxide) (FIG. 3B).

  Next, flash lamp annealing (FLA) is performed in an inert atmosphere, for example, a nitrogen atmosphere (second annealing). By this heat treatment, the silicidation reaction further proceeds and the nickel silicide film 56 reaches deeper.

  At this time, since the gate electrodes 26n and 26p formed on the gate insulating film 18 are more easily heated than the source / drain regions 52 and 54 formed in the silicon substrate 10, the gate electrodes 26n and 26p The nickel silicide film 56 formed on 26p reaches deeper than the nickel silicide film 56 formed on the source / drain regions 52 and 54.

  Therefore, by appropriately controlling the flash lamp annealing conditions, the gate electrodes 26n and 26p can be replaced with the nickel silicide film 56 without destroying the junctions of the source / drain regions 52 and 54 (FIG. 4 (a)).

  Next, a silicon nitride film of, eg, a 100 nm-thickness is deposited on the entire surface by, eg, plasma CVD, and a stressor film 58 for applying a tensile stress to the channel region of the N-type MISFET is formed.

  Next, the stressor film 58 in the P-type MISFET formation region is selectively removed by photolithography and dry etching.

  Next, a silicon nitride film of, eg, a 100 nm-thickness is deposited on the entire surface by, eg, plasma CVD, and a stressor film 60 for applying compressive stress to the channel region of the P-type MISFET is formed.

  Next, the stressor film 60 in the N-type MISFET formation region is selectively removed by photolithography and dry etching (FIG. 4B).

  Thereafter, the semiconductor device is completed through a normal multilayer wiring process.

  The manufacturing method of the semiconductor device proposed by the present inventor uses the flash lamp annealing as the second annealing for forming the nickel silicide film 56, so that the gate electrode is fully formed by a normal self-aligned silicide (salicide) technique. It enables silicidation.

  According to this method, the volume change of the gate electrode accompanying silicidation can be suppressed smaller than in the case of the CMP method, so that it is possible to suppress the application of adverse stress to the N-type MISFET. Can do.

  However, on the other hand, the nickel element in the nickel silicide film constituting the gate electrodes 26n and 26p is limited to the nickel element in the nickel silicide film formed in the first annealing, so this nickel in the second annealing. The nickel silicide film in which the elements are formed throughout the region becomes nickel-excess nickel silicide. For this reason, the resistance value of the gate electrode increases about 10 times, which may deteriorate the performance of the MIS transistor.

[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 5 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, FIGS. 6 to 11 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment, and FIG. 12 is a two-layer structure constituting the gate electrode. FIG. 13 and FIG. 14 are graphs showing the threshold voltage roll-off characteristics of the N-type MISFET, and FIG. 15 is a graph showing the relationship between the off-current and the on-current of the N-type MISFET. 16 and 17 are graphs showing the threshold voltage roll-off characteristics of the P-type MISFET, and FIG. 18 is a graph showing the relationship between the off-current and the on-current of the P-type MISFET.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

  An element isolation film 12 that defines an active region is formed on the main surface of the silicon substrate 10. In the figure, the active region on the left side of the central element isolation film 12 is an N-type MISFET formation region, and the active region on the right side of the central element isolation film 12 is a P-type MISFET formation region.

  A P-type well 14 is formed in the silicon substrate 10 in the N-type MISFET formation region. An N-type well 16 is formed in the silicon substrate 10 in the P-type MISFET formation region.

  A gate electrode 26n is formed on the silicon substrate 10 in the N-type MISFET formation region with a gate insulating film 18 interposed therebetween. The gate electrode 26n has a nickel silicide film 56b formed on the gate insulating film 18 and a nickel silicide film 56a formed on the nickel silicide film 56b. The nickel silicide film 56b contains more silicon than the nickel silicide film 56a.

  Side wall spacers 32, 34, and 48 are formed on the side walls of the gate electrode 26n. Source / drain regions 52 are formed in the silicon substrate 10 on both sides of the gate electrode 26n. A nickel silicide film 56 is formed on the source / drain region 52.

  Thus, an N-type MISFET having the gate electrode 26n and the source / drain regions 52 is formed in the N-type MISFET formation region.

  A stressor film 58 for introducing a tensile stress into the channel region of the N-type MISFET is formed on the N-type MISFET.

  On the silicon substrate 10 in the P-type MISFET formation region, a gate electrode 26p is formed via a gate insulating film 18. The gate electrode 26p has a nickel silicide film 56b formed on the gate insulating film 18 and a nickel silicide film 56a formed on the nickel silicide film 56b. The nickel silicide film 56b contains more silicon than the nickel silicide film 56a.

  Sidewall spacers 32, 34, and 48 are formed on the side walls of the gate electrode 26p. Source / drain regions 54 are formed in the silicon substrate 10 on both sides of the gate electrode 26p. A SiGe film 46 is embedded in the source / drain region 54. A nickel silicide film 56 is formed on the SiGe film 46.

  Thus, a P-type MISFET having the gate electrode 26p and the source / drain region 54 and the SiGe film 46 embedded in the source / drain region 54 is formed in the P-type MISFET formation region.

  On the P-type MISFET, a stressor film 60 for introducing tensile stress into the channel region of the P-type MISFET is formed.

  An interlayer insulating film 62 is formed on the semiconductor substrate on which the stressor films 58 and 60 are formed. A contact plug 64 connected to the nickel silicide film on the source / drain regions 52 and 54 is embedded in the interlayer insulating film 62 and the stressor films 58 and 60. On the interlayer insulating film 62 in which the contact plug 64 is embedded, a wiring layer 66 connected to the source / drain regions 52 and 54 of the MISFET via the contact plug 64 is formed.

  As described above, the semiconductor device according to the present embodiment has a full silicide structure in which the gate electrode 26n of the N-type MISFET and the gate electrode 26p of the P-type MISFET are constituted by the nickel silicide films 56a and 56b. Further, the nickel silicide film 56b contains more silicon than the nickel silicide film 56a.

  By configuring the semiconductor device in this manner, the resistance value of the gate electrodes 26n and 26p can be reduced by the upper nickel silicide film 56a, and the lower nickel silicide film containing silicon in excess of the nickel silicide film 56a. The stress applied to the channel region of the N-type MISFET can be reduced by 56b. As a result, the gate electrodes 26n and 26p can be fully silicided without deteriorating the characteristics of the N-type MISFET.

  Further, tensile stress can be introduced from the stressor film 58 in the channel direction to the N-type MISFET, and compressive stress can be introduced from the stressor film 60 and the SiGe film 46 in the channel direction to the P-type MISFET. Thereby, the mobility of carriers flowing in the channel region can be improved, and the characteristics of the MISFET can be improved.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, an element isolation film 12 embedded in an element isolation trench having a depth of, for example, 300 nm is formed on the main surface of the silicon substrate 10 by, eg, STI (Shallow Trench Isolation) method (FIG. 6A). In the figure, the active region on the left side of the central element isolation film 12 is an N-type MISFET formation region, and the active region on the right side of the central element isolation film 12 is a P-type MISFET formation region.

  Next, by photolithography and ion implantation, a P-type well 14 is formed in the silicon substrate 10 in the N-type MISFET formation region, and an N-type well 16 is formed in the silicon substrate 10 in the P-type MISFET formation region (FIG. 6 ( b)).

  Next, for example, in a nitrogen atmosphere, heat treatment is performed at 1000 ° C. for 10 seconds, for example, to activate the impurities constituting the P-type well 14 and the N-type well 16.

  Next, thermal oxidation is performed, for example, in a dry oxygen atmosphere at 800 ° C., and a gate insulating film 18 made of, for example, a 1 nm-thickness silicon oxide film is formed on the active region of the silicon substrate 10 defined by the element isolation film 12. . Note that the gate insulating film may be formed of an insulating material other than a silicon oxide film, such as a silicon oxynitride film.

  Next, an amorphous silicon film 20 of, eg, a 20 nm-thickness is deposited on the entire surface by, eg, LPCVD.

  The film thickness of the amorphous silicon film 20 is desirably as thin as possible within a range in which impurities added in a subsequent process can be sufficiently prevented from penetrating in the direction of the silicon substrate 10. When ion implantation is used to add impurities, the current ion implantation technique has a lower limit of about 20 nm.

  Further, a polysilicon film may be deposited instead of the amorphous silicon film. The amorphous silicon film is used to prevent penetration of impurities added in a later process. If the penetration of impurities can be sufficiently suppressed, a polysilicon film can be used. Further, after depositing the polysilicon film, the surface may be made amorphous by ion implantation or the like.

Next, after forming a photoresist film (not shown) covering the P-type MISFET formation region by photolithography, using this photoresist film as a mask, N-type impurities, for example, phosphorus ions (P ⁺ ), for example, acceleration energy 2 keV, Ion implantation is performed under the condition of a dose of 5 × 10 ¹⁵ cm ⁻² .

Similarly, after forming a photoresist film (not shown) covering the N-type MISFET formation region by photolithography, P-type impurities such as boron ions (B ⁺ ) are accelerated, for example, using this photoresist film as a mask. Ions are implanted under the conditions of an energy of 0.4 keV and a dose of 1 × 10 ¹⁵ cm ⁻² .

  Thereby, P-type impurities are added to the amorphous silicon film 20 in the P-type MISFET formation region, and N-type is added to the amorphous silicon film 20 in the N-type MISFET formation region.

  In the following description, when the amorphous silicon film 20 in the N-type MISFET formation region is distinguished from the amorphous silicon film 20 in the P-type MISFET formation region, the amorphous silicon film 20 in the N-type MISFET formation region is referred to as the amorphous silicon film 20n. The amorphous silicon film 20 in the P-type MISFET formation region is referred to as an amorphous silicon film 20p (FIG. 7A).

  Next, an amorphous silicon film 24 of, eg, a 80 nm-thickness is deposited on the amorphous silicon film 20 to which impurities are added by, eg, LPCVD.

  It should be noted that the surface of the amorphous silicon film 20 is exposed to pretreatment for ion implantation and the atmosphere between the formation process of the amorphous silicon film 20 and the formation process of the amorphous silicon film 24, and the surface of the amorphous silicon film 20 is naturally oxidized. A film is formed. For this reason, a natural oxide film is interposed between the amorphous silicon film 20 and the amorphous silicon film 24. Since the natural oxide film is not uniformly formed on the amorphous silicon film 20, but is formed in an island shape as shown in FIG. 12, for example, the amorphous silicon film 20 and the amorphous silicon film 24 are composed of the natural oxide film 22. In the region where is not formed, it is in direct contact with a part.

  A polysilicon film may be deposited instead of the amorphous silicon film. The amorphous silicon film is used to prevent penetration of impurities added in a later process. If the penetration of impurities can be sufficiently suppressed, a polysilicon film can be used. Further, after depositing the polysilicon film, the surface may be made amorphous by ion implantation or the like.

  Next, a silicon nitride film 25 of, eg, a 80 nm-thickness is formed on the amorphous silicon film 24 by, eg, LPCVD (FIG. 7B).

  Next, the silicon nitride film 25 and the amorphous silicon films 24 and 20 are sequentially patterned by photolithography and dry etching, and the upper surface of the N-type MISFET formation region is covered with the silicon nitride film 25 made of the amorphous silicon films 20n and 24. The gate electrode 26n is formed in the P-type MISFET formation region, and the gate electrode 26p made of the amorphous silicon films 20p and 24 and having the upper surface covered with the silicon nitride film 25 is formed.

Next, after forming a photoresist film (not shown) covering the P-type MISFET formation region by photolithography, ion implantation is performed using the photoresist film and the gate electrode 26n as a mask, and the inside of the silicon substrate 10 on both sides of the gate electrode 26n. Then, an impurity diffusion region 28 to be an extension region and a pocket region is formed. Extension ion implantation is performed using N-type impurities such as arsenic ions (As ⁺ ) under conditions of an acceleration energy of 1.5 keV and an implantation amount of 1 × 10 ¹⁵ cm ⁻² . In the pocket ion implantation, a P-type impurity, for example, boron ion (B ⁺ ) is applied from four directions inclined with respect to the normal direction of the silicon substrate 10 under conditions of an acceleration energy of 10 keV and an implantation amount of 1 × 10 ¹³ cm ^−2. , Do each. For the pocket ion implantation, indium ions (In ⁺ ) may be used.

Similarly, after a photoresist film (not shown) covering the N-type MISFET formation region is formed by photolithography, ion implantation is performed using the photoresist film and the gate electrode 26p as a mask, and silicon substrates on both sides of the gate electrode 26p. An impurity diffusion region 30 to be an extension region and a pocket region is formed in 10 (FIG. 8A). Extension ion implantation is performed using P-type impurities such as boron ions (B ⁺ ) under the conditions of an acceleration energy of 0.5 keV and an implantation amount of 1 × 10 ¹⁵ cm ⁻² . In the pocket ion implantation, N-type impurities such as antimony ions (Sb ⁺ ) are introduced from four directions inclined with respect to the normal direction of the silicon substrate 10 under the conditions of an acceleration energy of 50 keV and an implantation amount of 5 × 10 ¹² cm ^−2. , Do each. Arsenic ions (As ⁺ ) may be used for pocket ion implantation.

  Before forming the impurity diffusion regions 28 and 30, sidewall spacers made of, for example, a silicon oxide film or a silicon nitride film having a thickness of about 10 nm may be formed on the side walls of the gate electrodes 26n and 26p. .

  Next, a silicon oxide film having a thickness of 10 nm and a silicon nitride film having a thickness of 40 nm, for example, are deposited on the entire surface by, eg, plasma CVD, and then the silicon oxide film and the silicon nitride film are etched back to form a gate electrode. Side wall spacers 32 made of a silicon oxide film and side wall spacers 34 made of a silicon nitride film are formed on the side walls 26n and 26p.

Next, after forming a photoresist film (not shown) covering the P-type MISFET formation region by photolithography, ion implantation is performed using the photoresist film, the gate electrode 26n, and the side wall spacers 32 and 34 as a mask, and the gate electrode 26n. Impurity diffusion regions 36 to be source / drain regions are formed in the silicon substrates 10 on both sides of the substrate. The impurity diffusion region 36 is formed by ion-implanting N-type impurities such as arsenic ions (As ⁺ ) or phosphorus ions (P ⁺ ) under the conditions of an acceleration energy of 10 keV and an injection amount of 2 × 10 ¹⁵ cm ⁻² .

Similarly, after forming a photoresist film (not shown) covering the N-type MISFET formation region by photolithography, ion implantation is performed using the photoresist film, the gate electrode 26p and the side wall spacers 32 and 34 as a mask, and the gate Impurity diffusion regions 38 and 40 to be source / drain regions are formed in the silicon substrate 10 on both sides of the electrode 26p (FIG. 8B). The impurity diffusion region 38 is formed by implanting a P-type impurity such as boron ions (B ⁺ ) obliquely under the conditions of an acceleration energy of 8 keV and an injection amount of 2 × 10 ¹³ cm ⁻² . The impurity diffusion region 40 is formed by ion-implanting a P-type impurity, for example, boron ions (B ⁺ ) under conditions of an acceleration energy of 10 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² .

  Next, a silicon oxide film 42 of, eg, a 40 nm-thickness is formed on the entire surface by, eg, plasma CVD.

  Next, the silicon oxide film 42 in the P-type MISFET formation region is selectively removed by photolithography and dry etching.

Next, chemical dry etching (CDE) using, for example, CF ₄ / O ₂ as an etchant on the surface of the silicon substrate 10 using the silicon oxide film 42, the silicon nitride film 25, the side wall spacers 32 and 34, and the element isolation film 12 as a mask. (Chemical Dry Etching) is performed to form recess regions 44 having a depth of about 60 nm on the silicon substrate 10 on both sides of the gate electrode 26p (FIG. 9A). The chemical dry etching conditions are, for example, a pressure of 50 Pa and an applicator power of 100 W.

Next, using the silicon oxide film 42, the silicon nitride film 25, the sidewall spacers 32 and 34, and the element isolation film 12 as a mask, a P-type SiGe film having a thickness of, for example, 80 nm is formed in the recess region 44 by, for example, molecular beam epitaxy. 46 is selectively grown (FIG. 9B). For the growth of the SiGe film 46, for example, SiH ₄ , GeH ₄ , H ₂ , HCl, B ₂ H ₆ is used as a source gas, and the growth temperature is set to 600 ° C., for example. The composition ratio of the SiGe film 46 is such that the germanium concentration is about 15 to 25%, for example, Si _0.80 Ge _0.20 (containing about 20% germanium).

  Next, after depositing a silicon oxide film of, eg, a 50 nm-thickness on the entire surface by, eg, LPCVD, the silicon oxide film and the silicon oxide film 42 are etched back, and the gate electrodes 26n, A sidewall spacer 48 made of a silicon oxide film is formed on the side wall portion 26p.

Next, after forming a photoresist film (not shown) covering the P-type MISFET formation region by photolithography, ion implantation is performed using the photoresist film, the gate electrode 26n, and the side wall spacers 32, 34, and 48 as a mask. Impurity diffusion regions 50 serving as source / drain regions are formed in the silicon substrate 10 on both sides of the electrode 26n. The impurity diffusion region 50 is formed by ion-implanting N-type impurities, for example, arsenic ions (As ⁺ ) under conditions of an acceleration energy of 25 keV and an implantation amount of 8 × 10 ¹⁵ cm ⁻² . As the N-type impurity, phosphorus ion (P ⁺ ) may be used instead of arsenic ion.

  The ion implantation process for forming the impurity diffusion regions 28, 30, 36, 38, 40, 50 also serves as doping to the gate electrodes 26n, 26p.

  Next, for example, annealing is performed at a short time of about 1000 ° C. to activate the impurities constituting the impurity diffusion regions 28, 30, 36, 38, 40 and 50. As a result, the source / drain regions 52 of the N-type MISFET composed of the impurity diffusion regions 28, 36, 50 are formed in the silicon substrate 10 on both sides of the gate electrode 26n, and in the silicon substrate 10 on both sides of the gate electrode 26p, A source / drain region 54 of the P-type MISFET composed of the impurity diffusion regions 30, 38, 40 is formed (FIG. 10A).

  Note that the amorphous silicon films 20 and 24 are crystallized into a polysilicon film in the conventional thermal process, but for convenience, they will be referred to as amorphous silicon films 20 and 24 in the following description.

  Next, a nickel (Ni) film of, eg, a 20 nm-thickness is deposited on the entire surface by, eg, sputtering. A film for preventing oxidation of the nickel film, for example, a titanium nitride (TiN) film may be further formed on the nickel film.

Next, annealing is performed for a short time at a temperature of about 200 to 300 ° C. in an inert atmosphere, for example, a nitrogen atmosphere (first annealing). By this heat treatment, nickel in a phase containing a large amount of nickel (for example, Ni ₂ Si) is formed in regions where the nickel film and the exposed portion of silicon are in contact (on the source / drain regions 52 and 54 and on the gate electrodes 26n and 26p). A silicide film 56 is selectively formed.

  Next, the unreacted nickel film is removed by wet etching using, for example, SPM (sulfuric acid / hydrogen peroxide) (FIG. 10B).

Next, flash lamp annealing (FLA) is performed (second annealing) in an inert atmosphere, for example, a nitrogen atmosphere. Conventional annealing was a heat treatment in seconds, but it became possible to reduce the thermal budget in milliseconds by making the temperature rise and fall steeper. This is flash lamp annealing. The conditions for the second annealing using flash lamp annealing are, for example, a substrate temperature of 300 to 400 ° C. and a dose of 25 mJ / cm ² .

  By this heat treatment, the silicidation reaction further proceeds, and the nickel silicide film 56 is formed deeper and is converted into a phase having a low resistance value (for example, NiSi). At this time, in the gate electrodes 26n and 26p, all of the amorphous silicon films 20 and 24 constituting the gate electrodes 26n and 26p are silicided. However, as shown in FIG. 12, the amorphous silicon constituting the gate electrodes 26n and 26p. Since the natural oxide film 22 is formed between the films 20 and 24, the diffusion of nickel to the amorphous silicon film 20 side is suppressed. Thus, a nickel silicide film 56a having a low resistance value (for example, NiSi) is formed in the amorphous silicon film 24 portion, while a silicon-rich nickel silicide film 56b is formed in the amorphous silicon film 20 portion (FIG. 11 (a)). As a result, the volume change accompanying the silicidation reaction in the amorphous silicon film 20 portion of the gate electrodes 26n and 26p is suppressed, and the characteristic deterioration of the N-type MISFET can be prevented.

  Further, as another merit of making the amorphous silicon film into a two-layer structure, it is possible to apply a stress accompanying volume expansion when the amorphous silicon 20 in the lower layer made amorphous by ion implantation is recrystallized to the channel region of the MISFET. It is done. Unlike the silicidation reaction, the stress generated by recrystallization of the amorphous silicon film 20 is applied in a direction that improves the characteristics of the N-type MISFET.

  Therefore, by combining these effects, it is possible to realize both the silicidation of the gate electrodes 26n and 26p and the improvement of the characteristics of the N-type MISFET at the same time.

Next, a silicon nitride film of, eg, a 100 nm-thickness is deposited on the entire surface by, eg, plasma CVD to form a stressor film 58 made of the silicon nitride film. The stressor film 58 is a film that can apply a tensile stress to the silicon substrate 10 so that a tensile stress is applied to the channel region of the MISFET. For example, a mixed gas of SiH ₄ / NH ₃ / N ₂ is used, the gas ratio is, for example, 10: 1000: 5000 sccm (not necessarily this gas ratio), the film forming temperature is 250 to 450 ° C., and the pressure is 1 The stressor film 58 made of a plasma nitride film can be formed by forming the film at 10 to 10 Torr and a power of 1000 to 1500 W.

  In the case of an N-type MISFET, the formation of the stressor film 58 having a tensile stress of about 1 to 2 GPa on the silicon substrate 10 has an effect of improving the electron mobility flowing through the channel. The film forming conditions for the stressor film 58 are desirably set as appropriate according to the size and type of the MISFET to be formed, the required characteristics, and the like.

  Next, the stressor film 58 in the P-type MISFET formation region is selectively removed by photolithography and dry etching.

Next, a silicon nitride film of, eg, a 100 nm-thickness is deposited on the entire surface by, eg, plasma CVD to form a stressor film 60 made of the silicon nitride film. The stressor film 60 is a film that can apply compressive stress to the silicon substrate 10 so that compressive stress is applied to the channel region of the MISFET. For example, a mixed gas of SiH ₄ / NH ₃ / N ₂ / H ₂ is used, the gas ratio is, for example, 10: 1000: 5000: 5000 sccm (not necessarily this gas ratio), and the film formation temperature is 250 to 350. By forming the film at a temperature of 1 ° C., a pressure of 1 to 10 Torr, and a power of 200 to 1000 W, the stressor film 60 made of a plasma nitride film can be formed.

  In the case of a P-type MISFET, the formation of the stressor film 60 having a compressive stress of about 1 to 3 GPa on the silicon substrate 10 has an effect of improving the mobility of holes flowing through the channel. The film forming conditions for the stressor film 60 are preferably set as appropriate according to the size and type of the MISFET to be formed, the required characteristics, and the like.

  Next, the stressor film 60 in the N-type MISFET formation region is selectively removed by photolithography and dry etching (FIG. 11B).

  Thereafter, the interlayer insulating film 62 covering the stressor films 58 and 60, the contact plug 64 connected to the nickel silicide film 56 formed on the source / drain regions 52 and 54, and the source / drain region via the contact plug 64. After forming the wiring layer 66 and the like connected to 52 and 54 (see FIG. 5), the semiconductor device is completed through a normal multilayer wiring process.

  Next, the results of measuring the characteristics of the MISFET formed by the above manufacturing method will be described with reference to FIGS.

13 and 14 are graphs showing the relationship (threshold voltage roll-off characteristic) between the threshold voltage (V _th ) and the gate length (L _g ) of the N-type MISFET. FIG. 15 is a graph showing the relationship between the off current (I _off ) and the on current (I _on ) of the N-type MISFET. 16 and 17 are graphs showing the relationship (threshold voltage roll-off characteristic) between the threshold voltage (V _th ) and the gate length (L _g ) of the P-type MISFET. FIG. 18 is a graph showing the relationship between the off-current (I _off ) and the on-current (I _on ) of the P-type MISFET. In each figure, the mark ● indicates the characteristics of the MISFET formed by the method of manufacturing a semiconductor device according to the present embodiment, and the mark ○ indicates a normal annealing instead of the flash lamp annealing in the second annealing in the formation process of the nickel silicide film 56. The figure shows the characteristics of a MISFET formed by short-time annealing (temperature annealing at 1010 ° C. in a nitrogen atmosphere, time is 1 second or less).

  Looking at the N-type MISFET, as shown in FIGS. 13 and 14, the MISFET of this embodiment using flash lamp annealing has overall characteristics compared to the MISFET not using flash lamp annealing. It can be seen that the threshold voltage roll-off characteristic is improved because of the shift to the short channel side. When compared with data when the threshold voltage is 0 V, an improvement of about 15 nm in terms of gate length was observed.

  Further, regarding the value of the threshold voltage, as shown in FIG. 14, almost no change is seen on the long channel side, whereas the MISFET of this embodiment is about 90 mV higher on the short channel side. The change in the threshold voltage is accompanied by a change in work function accompanying the full silicidation of the gate electrode.

Further, as shown in FIG. 15, the MISFET of this embodiment using flash lamp annealing has a higher on-current when viewed at the same off-current than the MISFET not using flash lamp annealing. It can be seen that the characteristics are improved. When compared with data when the off-current is 1 × 10 ⁻⁷ A, an improvement of about 9.7% in the on-current was observed.

  When the same measurement was performed on the MISFET prepared by the semiconductor device manufacturing method according to the above-described reference example of the present invention, the improvement effect of the threshold voltage roll-off characteristic was observed, but the phenomenon that the on-current increased could not be confirmed. It was. The effect of improving the on-current is a specific effect obtained by the MISFET of this embodiment.

  As for the P-type MISFET, as shown in FIGS. 16 and 17, the MISFET of this embodiment using flash lamp annealing has a short channel side characteristic as compared with the case of the MISFET not using flash lamp annealing. It can be seen that the threshold voltage roll-off characteristics are improved.

  As for the value of the threshold voltage, as shown in FIG. 17, almost no change is observed on the long channel side, whereas the MISFET of this embodiment is about 90 mV higher on the short channel side. The change in the threshold voltage is accompanied by a change in work function accompanying the full silicidation of the gate electrode.

Also, as shown in FIG. 18, the MISFET of this embodiment using flash lamp annealing has a higher on-current when viewed at the same off-current than the MISFET not using flash lamp annealing. It can be seen that the characteristics are improved. When compared with data when the off-current is 1 × 10 ⁻⁷ A, an improvement of about 8% in the on-current was observed.

  As described above, in the semiconductor device according to the present embodiment, both the N-type MISFET and the P-type MISFET can improve the roll-off characteristics and the on-current.

  As described above, according to the present embodiment, the amorphous silicon film for forming the gate electrode has a two-layer structure, and silicidation is performed using flash lamp annealing, so that the nickel silicide film containing excessive silicon in the lower layer portion. And a full silicide gate electrode having a low resistance nickel silicide film in the upper layer portion can be formed. Thus, the resistance value of the gate electrode can be reduced by the upper nickel silicide film, and the stress applied to the channel region of the N-type MISFET by the lower nickel silicide film can be reduced. Thereby, the gate electrode can be fully silicided without deteriorating the characteristics of the N-type MISFET.

[Second Embodiment]
A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIGS. Components similar to those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 5 to 12 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  19 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, FIGS. 20 to 23 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment, and FIG. 24 is the effective gate insulating film of the N-type MISFET. It is a figure which shows distribution in the wafer surface of a film thickness.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

  An element isolation film 12 that defines an active region is formed on the main surface of the silicon substrate 10. In the figure, the active region on the left side of the central element isolation film 12 is the first N-type MISFET formation region, and the active region on the right side of the central element isolation film 12 is the second N-type MISFET formation region. Shall.

  A P-type well 14 is formed in the silicon substrate 10 in the first N-type MISFET formation region and the second N-type MISFET formation region.

On the silicon substrate 10 in the first N-type MISFET formation region, a gate electrode 26 _H is formed via a gate insulating film 18. The gate electrode _26H has a nickel silicide film 56b formed on the gate insulating film 18 and a nickel silicide film 56a formed on the nickel silicide film 56b. The nickel silicide film 56b contains more silicon than the nickel silicide film 56a.

On the side wall of the gate electrode 26 _H, sidewall spacers 32,34,48 are formed. The silicon substrate 10 on both sides of the gate electrode 26 _H, the source / drain regions 52 are formed. A nickel silicide film 56 is formed on the source / drain region 52.

Thus, a first N-type MISFET having the gate electrode 26 _H and the source / drain regions 52 is formed in the first N-type MISFET formation region.

A gate electrode _26L is formed on the silicon substrate 10 in the second N-type MISFET formation region via the gate insulating film 18. The gate electrode 26 _L has an amorphous silicon film 20 _L formed on the gate insulating film 18, and a nickel silicide film 56a formed on the amorphous silicon film 20 _L. The amorphous silicon film _20L is a name based on the crystal state immediately after film formation, and is actually a polysilicon film.

On the side wall of the gate electrode 26 _L, sidewall spacers 32,34,48 are formed. The silicon substrate 10 on both sides of the gate electrode 26 _L, the source / drain regions 52 are formed. A nickel silicide film 56 is formed on the source / drain region 52.

Thus, a second N-type MISFET having the gate electrode _26L and the source / drain region 52 is formed in the second N-type MISFET formation region.

  On the first N-type MISFET and the second N-type MISFET, a stressor film 58 for introducing a tensile stress into the channel region of the N-type MISFET is formed.

Thus, the semiconductor device according to this embodiment includes a first N-type MISFET having a gate electrode 26 _H consisting of full silicide structure composed of nickel silicide film 56a, a 56b, a nickel silicide film 56a and the amorphous silicon film 20 _And a second N-type MISFET having a gate electrode 26 _L having a polycide structure constituted by _L. The nickel silicide film 56b of the first N-type MISFET contains more silicon than the nickel silicide film 56a.

  By configuring the semiconductor device in this manner, a transistor for high-speed operation in which the gate electrode is required to be fully silicided, such as a logic transistor (first N-type MISFET), is gated by the upper nickel silicide film 56a. The resistance values of the electrodes 26n and 26p can be reduced, and the stress applied to the channel region of the N-type MISFET can be reduced by the lower nickel silicide film 56b containing silicon in excess of the nickel silicide film 56a. As a result, the gate electrodes 26n and 26p can be fully silicided without deteriorating the characteristics of the N-type MISFET. Further, by introducing tensile stress from the stressor film 58 in the channel direction to the N-type MISFET, the mobility of carriers flowing in the channel region can be improved, and the characteristics of the MISFET can be further improved.

  In addition, a transistor for which full silicidation of the gate electrode is not particularly required, for example, an SRAM cell transistor or the like (second N-type MISFET) that is required to suppress variation in characteristics should be a polycide structure gate electrode. Can do.

  The first N-type MISFET and the second N-type MISFET can be simultaneously formed by using a manufacturing method described later.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, an element isolation film 12 embedded in an element isolation trench having a depth of, for example, 300 nm is formed on the main surface of the silicon substrate 10 by, for example, the STI method. In the figure, the active region on the left side of the central element isolation film 12 is a first N-type MISFET formation region having a fully silicided gate electrode, and the active region on the right side of the central element isolation film 12 is a polycide structure. It is assumed that this is a second N-type MISFET formation region having the gate electrode.

  Next, a P-type well 14 is formed in the silicon substrate 10 by photolithography and ion implantation (FIG. 20A). The P-type well 14 may be separately formed using different conditions in the first N-type MISFET formation region and the second N-type MISFET formation region.

  Next, for example, in a nitrogen atmosphere, heat treatment is performed at 1000 ° C. for 10 seconds, for example, to activate the impurities constituting the P-type well 14.

  Next, thermal oxidation is performed in a dry oxygen atmosphere at 800 ° C., for example, and a gate insulating film 18 made of a silicon oxide film having a thickness of 1 nm, for example, is formed on the active region of the silicon substrate 10 defined by the element isolation film 12. .

  Next, an amorphous silicon film 20 of, eg, a 20 nm-thickness is deposited on the entire surface by, eg, LPCVD.

Next, a photolithography is performed to form a photoresist film (not shown) that covers the second N-type MISFET formation region and exposes the first N-type MISFET formation region, and then uses this photoresist film as a mask to form an N-type impurity. For example, phosphorus ions (P ⁺ ) are ion-implanted under the conditions of, for example, acceleration energy of 3 keV and a dose of 3 × 10 ¹⁵ cm ⁻² .

Next, a photoresist film (not shown) that exposes the first N-type MISFET formation region and the second N-type MISFET formation region is formed by photolithography, and N-type impurities, For example, phosphorus ions (P ⁺ ) are ion-implanted under conditions of an acceleration energy of 3 keV and a dose amount of 2 × 10 ¹⁵ cm ⁻² , for example.

As a result, phosphorus ions having a total dose of 5 × 10 ¹⁵ cm ⁻² are implanted into the amorphous silicon film 20 in the first N-type MISFET formation region. Assuming that all phosphorus ions introduced by ion implantation are uniformly added into the amorphous silicon film 20, the phosphorus concentration in the amorphous silicon film 20 is
5.0 × 10 ¹⁵ [cm ⁻² ] / 20 [nm] = 2.5 × 10 ²¹ [cm ⁻³ ]
It becomes.

Further, phosphorus ions having a total dose of 2 × 10 ¹⁵ cm ⁻² are implanted into the amorphous silicon film 20 in the second N-type MISFET formation region. Assuming that all phosphorus ions introduced by ion implantation are uniformly added into the amorphous silicon film 20, the phosphorus concentration in the amorphous silicon film 20 is
2.0 × 10 ¹⁵ [cm ⁻² ] / 20 [nm] = 1.0 × 10 ²¹ [cm ⁻³ ]
It becomes.

In the following description, when the amorphous silicon film 20 having a high phosphorus concentration in the first N-type MISFET formation region is distinguished from the amorphous silicon film 20 having a low phosphorus concentration in the second N-type MISFET formation region, the first The N-type MISFET formation region amorphous silicon film 20 is referred to as an amorphous silicon film 20 _H, and the amorphous silicon film 20 in the second N-type MISFET formation region is referred to as an amorphous silicon film 20 _L (FIG. 20B). .

  Next, an amorphous silicon film 24 of, eg, a 80 nm-thickness is deposited on the amorphous silicon film 20 by, eg, LPCVD (FIG. 21A).

Next, the amorphous silicon films 24 and 20 are sequentially patterned by photolithography and dry etching, and a gate electrode 26 _{H made of} a laminated film of the amorphous silicon film 20 _H and the amorphous silicon film 24 is formed in the first N-type MISFET formation region. forming a, the second N-type MISFET formation region, a gate electrode 26 _L of the layer film of the amorphous silicon film 20 _L and the amorphous silicon film 24 (FIG. 21 (b)).

When the P-type MISFET having the SiGe film 46 buried in the source / drain regions is formed simultaneously as in the first embodiment, the recess regions are formed on the gate electrodes 26 _H and 26 _L and the SiGe film is grown. A film serving as a mask (corresponding to the silicon nitride film 25 of the first embodiment) is formed in advance.

  Next, sidewall spacers 32, 34, 48, source / drain regions 52, and the like are formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 8A to 10A, for example (FIG. FIG. 22 (a)). The structures of the sidewall spacers and the source / drain regions may be different between the second N-type MISFET and the second N-type MISFET.

  Next, a nickel (Ni) film of, eg, a 20 nm-thickness is deposited on the entire surface by, eg, sputtering. A film for preventing oxidation of the nickel film, for example, a titanium nitride (TiN) film may be further formed on the nickel film.

Next, annealing is performed for a short time at a temperature of about 200 to 300 ° C. in an inert atmosphere, for example, a nitrogen atmosphere. By this heat treatment, nickel in a phase containing a large amount of nickel (for example, Ni ₂ Si) is formed in a region where the nickel film and the exposed portion of silicon are in contact (on the source / drain region 52 and on the gate electrodes 26 _H and 26 _L ). A silicide film 56 is selectively formed.

  Next, the unreacted nickel film is removed by wet etching using, for example, SPM (sulfuric acid / hydrogen peroxide) (FIG. 22B).

  Next, flash lamp annealing (FLA) is performed in an inert atmosphere, for example, a nitrogen atmosphere. By this heat treatment, the silicidation reaction proceeds, and the nickel silicide film 56 is formed deeper and is converted into a phase having a low resistance value (for example, NiSi).

At this time, in the gate electrode 26 _H , as in the case of the first embodiment, all of the amorphous silicon films 20 _H and 24 constituting the gate electrode 26 _H are silicided. Further, since the natural oxide film 22 is formed between the amorphous silicon films 20 _H and 24, the diffusion of nickel to the amorphous silicon film 20 side is suppressed. Thereby, a nickel silicide film 56a having a low resistance value (for example, NiSi) is formed in the amorphous silicon film 24 portion, while a silicon-rich nickel silicide film 56b is formed in the amorphous silicon film _20H portion. Thereby, the gate electrode _26H is fully silicided. Further, the volume change accompanying the silicidation reaction in the amorphous silicon film 20 _H portion of the gate electrode 26 _H is suppressed, and the characteristic deterioration of the N-type MISFET can be prevented.

On the other hand, in the gate electrode _26L , the amorphous silicon film 24 is silicided, but the amorphous silicon film _20L is not silicided. Thus, while the amorphous silicon film 24 parts nickel silicide film 56a of low resistance phase (e.g. NiSi) is formed, the amorphous silicon film 20 _L portions amorphous silicon film 20 _L remains unchanged. Thus, the gate electrode 26 _L is a polycide structure.

Although the amorphous silicon film 20 _H of the gate electrode 26 _H is is silicided not clear the mechanism of amorphous silicon film 20 _L of the gate electrode 26 _L is not silicided, the studies of the inventors of the present invention, the amorphous silicon film 20 _L It has been clarified that the concentration of the impurities inside has an influence.

In other words, when the impurity concentration in the amorphous silicon film 20 is about 2 × 10 ²¹ cm ⁻³ or more, the amorphous silicon film 20 is silicided, but the impurity concentration in the amorphous silicon film 20 is less than about 2 × 10 ²¹ cm ^−3. Then, the amorphous silicon film 20 remains as amorphous silicon without being silicided. Therefore, by appropriately changing the impurity concentration in the amorphous silicon film 20 according to the region, it is possible to make a fully silicided gate electrode and a polycide structure gate electrode.

  Similar effects can be expected when other donor impurities such as arsenic (As) or antimony (Sb) are used instead of phosphorus as impurities.

  The inventor of the present application has not confirmed the same phenomenon for the P-type MISFET, but the P-type MISFET also exhibits the same phenomenon as the N-type MISFET by changing the P-type impurity concentration in the amorphous silicon film. There is a possibility that it can be realized.

  Next, a silicon nitride film of, eg, a 100 nm-thickness is deposited on the entire surface by, eg, plasma CVD, and a stressor film 58 for tensile stress is formed in the channel region of the N-type MISFET.

  Thereafter, the interlayer insulating film 62 covering the stressor film 58, the contact plug 64 connected to the nickel silicide film 56 formed on the source / drain region 52, and the source / drain region 52 are connected via the contact plug 64. After forming the wiring layer 66 and the like (see FIG. 5), the semiconductor device is completed through a normal multilayer wiring process.

  Next, the results of measuring the characteristics of the MISFET formed by the above manufacturing method will be described with reference to FIG.

  FIG. 24 is a view showing an in-wafer distribution of the effective film thickness of the gate insulating film of the N-type MISFET. FIG. 24A shows a first N-type MISFET, and FIG. 24B shows a second N-type MISFET. The effective film thickness of the gate insulating film is a film thickness in terms of a silicon oxide film calculated from CV measurement of the MIS capacitor. When the silicidation of the gate electrode proceeds, depletion in the direction of the gate electrode is suppressed, so that the effective film thickness becomes thin.

  In the second N-type MISFET, the effective film thickness is about 2 nm as shown in FIG. On the other hand, in the first N-type MISFET, as shown in FIG. 24A, although there is some variation, it is about 1.5 nm, which is thinner than that of the second N-type MISFET. .

Further, when the first N-type MISFET and the second N-type MISFET were observed with an electron microscope, the electron beam intensity obtained from the lower layer film (amorphous silicon film 20 _L ) of the gate electrode of the second N-type MISFET was observed. However, the electron beam intensity obtained from the lower layer film (nickel silicide film 56b) of the gate electrode of the first N-type MISFET is stronger, and the lower layer film of the gate electrode of the first N-type MISFET has more metal ( Nickel).

  From the above, it was confirmed that the first N-type MISFET having a fully silicided gate electrode and the second N-type MISFET having a polycide-structured gate electrode can be made separately by the same manufacturing process.

  As described above, according to the present embodiment, the amorphous silicon film for forming the gate electrode has a two-layer structure, and silicidation is performed using flash lamp annealing, so that the nickel silicide film containing excessive silicon in the lower layer portion. And a full silicide gate electrode having a low resistance nickel silicide film in the upper layer portion can be formed. Thus, the resistance value of the gate electrode can be reduced by the upper nickel silicide film, and the stress applied to the channel region of the N-type MISFET by the lower nickel silicide film can be reduced. Thereby, the gate electrode can be fully silicided without deteriorating the characteristics of the N-type MISFET. Further, by appropriately controlling the concentration of the impurity introduced into the underlying amorphous silicon film, the gate electrode to be fully silicided and the gate electrode having a polycide structure can be separately formed.

[Third Embodiment]
A semiconductor device and a manufacturing method thereof according to the third embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first and second embodiments shown in FIGS. 1 to 24 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 25 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 26 to 28 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

  An element isolation film 12 that defines an active region is formed on the main surface of the silicon substrate 10. In the figure, the active region on the left side of the central element isolation film 12 is an N-type MISFET formation region, and the active region on the right side of the central element isolation film 12 is a P-type MISFET formation region.

  A P-type well 14 is formed in the silicon substrate 10 in the N-type MISFET formation region. An N-type well 16 is formed in the silicon substrate 10 in the P-type MISFET formation region.

  A gate electrode 26n is formed on the silicon substrate 10 in the N-type MISFET formation region with a gate insulating film 18 interposed therebetween. The gate electrode 26n has a nickel silicide film 56b formed on the gate insulating film 18 and a nickel silicide film 56a formed on the nickel silicide film 56b. The nickel silicide film 56b contains more silicon than the nickel silicide film 56a.

  Side wall spacers 32, 34, and 48 are formed on the side walls of the gate electrode 26n. Source / drain regions 52 are formed in the silicon substrate 10 on both sides of the gate electrode 26n. A nickel silicide film 56 is formed on the source / drain region 52.

  Thus, an N-type MISFET having the gate electrode 26n and the source / drain regions 52 is formed in the N-type MISFET formation region.

  A stressor film 58 for introducing a tensile stress into the channel region of the N-type MISFET is formed on the N-type MISFET.

  On the silicon substrate 10 in the P-type MISFET formation region, a gate electrode 26p is formed via a gate insulating film 18. The gate electrode 26p has a nickel silicide film 56b formed on the gate insulating film 18 and a nickel silicide film 56a formed on the nickel silicide film 56b. The nickel silicide film 56b contains more silicon than the nickel silicide film 56a.

  Sidewall spacers 32, 34, and 48 are formed on the side walls of the gate electrode 26p. Source / drain regions 54 are formed in the silicon substrate 10 on both sides of the gate electrode 26p. A nickel silicide film 56 is formed on the source / drain region 54.

  Thus, a P-type MISFET having the gate electrode 26p and the source / drain region 54 is formed in the P-type MISFET formation region.

  On the P-type MISFET, a stressor film 60 for introducing tensile stress into the channel region of the P-type MISFET is formed.

  As described above, the semiconductor device according to the present embodiment is the same as the semiconductor device according to the first embodiment shown in FIG. 1 except that the SiGe film 46 is not embedded in the source / drain regions 54 of the P-type MISFET.

  In the semiconductor device according to the first embodiment, a structure in which the SiGe film 46 is embedded in the source / drain region 54 in order to effectively apply stress to the channel region of the P-type MISFET so as to have a structure suitable for higher speed operation. However, when sufficient characteristics can be obtained without using the SiGe film 46, the SiGe film 46 is not necessarily required.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, in the same way as in the method for manufacturing the semiconductor device according to the first embodiment shown in FIGS. 6A to 8A, for example, the gate electrode 26n made of a laminated film of the amorphous silicon film 20n and the amorphous silicon film 24 is formed. Then, a gate electrode 26p made of a laminated film of the amorphous silicon film 20p and the amorphous silicon film 24 is formed. In the present embodiment, the silicon nitride film 25 may not be formed on the amorphous silicon film 24.

  Next, after forming a photoresist film (not shown) covering the P-type MISFET formation region by photolithography, ion implantation is performed using the photoresist film and the gate electrode 26n as a mask, and the inside of the silicon substrate 10 on both sides of the gate electrode 26n. Then, an impurity diffusion region 28 to be an extension region and a pocket region is formed.

  Similarly, after a photoresist film (not shown) covering the N-type MISFET formation region is formed by photolithography, ion implantation is performed using the photoresist film and the gate electrode 26p as a mask, and silicon substrates on both sides of the gate electrode 26p. An impurity diffusion region 30 to be an extension region and a pocket region is formed in 10 (FIG. 26A).

  Next, a silicon oxide film having a thickness of 10 nm and a silicon nitride film having a thickness of 40 nm, for example, are deposited on the entire surface by, eg, plasma CVD, and then the silicon oxide film and the silicon nitride film are etched back to form a gate electrode. Side wall spacers 32 made of a silicon oxide film and side wall spacers 34 made of a silicon nitride film are formed on the side walls 26n and 26p.

  Next, after forming a photoresist film (not shown) covering the P-type MISFET formation region by photolithography, ion implantation is performed using the photoresist film, the gate electrode 26n, and the side wall spacers 32 and 34 as a mask, and the gate electrode 26n. Impurity diffusion regions 36 to be source / drain regions are formed in the silicon substrates 10 on both sides of the substrate.

Similarly, after forming a photoresist film (not shown) covering the N-type MISFET formation region by photolithography, ion implantation is performed using the photoresist film, the gate electrode 26p and the side wall spacers 32 and 34 as a mask, and the gate Impurity diffusion regions 38 to be source / drain regions are formed in the silicon substrate 10 on both sides of the electrode 26p (FIG. 26B). The impurity diffusion region 38 is formed by ion-implanting a P-type impurity, for example, boron ions (B ⁺ ) under conditions of an acceleration energy of 8 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² .

  Next, after depositing, for example, a 40 nm-thickness silicon oxide film on the entire surface by, for example, LP plasma CVD, the silicon oxide film and the silicon oxide film 42 are etched back to form gate electrodes on which sidewall spacers 32 and 34 are formed. Side wall spacers 48 made of a silicon oxide film are formed on the side walls of 26n and 26p.

Next, after forming a photoresist film (not shown) covering the P-type MISFET formation region by photolithography, ion implantation is performed using the photoresist film, the gate electrode 26n, and the side wall spacers 32, 34, and 48 as a mask. Impurity diffusion regions 50 serving as source / drain regions are formed in the silicon substrate 10 on both sides of the electrode 26n. The impurity diffusion region 50 is formed by ion-implanting N-type impurities such as arsenic ions (As ⁺ ) or phosphorus ions (P ⁺ ) under the conditions of an acceleration energy of 25 keV and an injection amount of 8 × 10 ¹⁵ cm ⁻² .

Similarly, after forming a photoresist film (not shown) covering the N-type MISFET formation region by photolithography, ion implantation is performed using this photoresist film, gate electrode 26p and sidewall spacers 32, 34, and 48 as a mask. Then, impurity diffusion regions 40 serving as source / drain regions are formed in the silicon substrate 10 on both sides of the gate electrode 26p. The impurity diffusion region 40 is formed by ion-implanting a P-type impurity, for example, boron ions (B ⁺ ) under conditions of an acceleration energy of 3 keV and an implantation amount of 5 × 10 ¹⁵ cm ⁻² .

  The ion implantation process for forming the impurity diffusion regions 28, 30, 36, 38, 40, 50 also serves as doping to the gate electrodes 26n, 26p.

  Next, for example, annealing is performed at a short time of about 1000 ° C. to activate the impurities constituting the impurity diffusion regions 28, 30, 36, 38, 40 and 50. As a result, the source / drain regions 52 of the N-type MISFET composed of the impurity diffusion regions 28, 36, 50 are formed in the silicon substrate 10 on both sides of the gate electrode 26n, and in the silicon substrate 10 on both sides of the gate electrode 26p, A source / drain region 54 of the P-type MISFET composed of the impurity diffusion regions 30, 38, 40 is formed (FIG. 27A).

  Next, a nickel (Ni) film of, eg, a 20 nm-thickness is deposited on the entire surface by, eg, sputtering. A film for preventing oxidation of the nickel film, for example, a titanium nitride (TiN) film may be further formed on the nickel film.

Next, annealing is performed for a short time at a temperature of about 200 to 300 ° C. in an inert atmosphere, for example, a nitrogen atmosphere. By this heat treatment, nickel in a phase containing a large amount of nickel (for example, Ni ₂ Si) is formed in regions where the nickel film and the exposed portion of silicon are in contact (on the source / drain regions 52 and 54 and on the gate electrodes 26n and 26p). A silicide film 56 is selectively formed.

  Next, the unreacted nickel film is removed by wet etching using, for example, SPM (sulfuric acid / hydrogen peroxide) (FIG. 27B).

  Next, flash lamp annealing (FLA) is performed in an inert atmosphere, for example, a nitrogen atmosphere. By this heat treatment, the silicidation reaction proceeds, and the nickel silicide film 56 is formed deeper and is converted into a phase having a low resistance value (for example, NiSi).

  At this time, in the gate electrodes 26n and 26p, all of the amorphous silicon films 20 and 24 constituting the gate electrodes 26n and 26p are silicided. However, as shown in FIG. 12, the amorphous silicon constituting the gate electrodes 26n and 26p. Since the natural oxide film 22 is formed between the films 20 and 24, the diffusion of nickel to the amorphous silicon film 20 side is suppressed. Thereby, a nickel silicide film 56a having a low resistance value (for example, NiSi) is formed in the amorphous silicon film 24 portion, while a silicon-rich nickel silicide film 56b is formed in the amorphous silicon film 20 portion. As a result, the volume change accompanying the silicidation reaction in the amorphous silicon film 20 portion of the gate electrodes 26n and 26p is suppressed, and the characteristic deterioration of the N-type MISFET can be prevented.

  Next, a silicon nitride film of, eg, a 100 nm-thickness is deposited on the entire surface by, eg, plasma CVD, and a stressor film 58 for applying a tensile stress to the channel region of the N-type MISFET is formed.

  Next, the stressor film 58 in the P-type MISFET formation region is selectively removed by photolithography and dry etching.

  Next, a silicon nitride film of, eg, a 100 nm-thickness is deposited on the entire surface by, eg, plasma CVD, and a stressor film 60 for applying compressive stress to the channel region of the P-type MISFET is formed.

  Next, the stressor film 60 in the N-type MISFET formation region is selectively removed by photolithography and dry etching.

  Thereafter, the interlayer insulating film 62 covering the stressor films 58 and 60, the contact plug 64 connected to the nickel silicide film 56 formed on the source / drain regions 52 and 54, and the source / drain region via the contact plug 64. After forming the wiring layer 66 and the like connected to 52 and 54 (see FIG. 5), the semiconductor device is completed through a normal multilayer wiring process.

  As described above, according to the present embodiment, the amorphous silicon film for forming the gate electrode has a two-layer structure, and silicidation is performed using flash lamp annealing, so that the nickel silicide film containing excessive silicon in the lower layer portion. And a full silicide gate electrode having a low resistance nickel silicide film in the upper layer portion can be formed. Thus, the resistance value of the gate electrode can be reduced by the upper nickel silicide film, and the stress applied to the channel region of the N-type MISFET by the lower nickel silicide film can be reduced. Thereby, the gate electrode can be fully silicided without deteriorating the characteristics of the N-type MISFET.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.

  For example, in the first to third embodiments, amorphous silicon is used as the material of the semiconductor film (amorphous silicon film 20 and amorphous silicon film 24) that is the source of the gate electrode. However, these films are not necessarily amorphous silicon films. There is no need. As described above, amorphous silicon is used to prevent impurities from penetrating, and a polysilicon film may be used when impurities do not penetrate.

  Further, instead of a silicon film such as amorphous silicon or polysilicon film, another semiconductor film mainly composed of silicon, for example, a silicon germanium (SiGe) film may be used. Since the silicon germanium film has a lower melting point than silicon, the temperature required for silicidation is also lower than that of silicon. Therefore, by using a silicon germanium film as the gate material, the heat treatment temperature for silicidation can be lowered, and the gate electrode can be fully silicided while suppressing silicidation sufficiently in the source / drain regions. It becomes possible.

  The silicon germanium film may be used in place of either the amorphous silicon film 20 or the amorphous silicon film 24, or may be used in place of both the amorphous silicon film 20 and the amorphous silicon film 24.

  As the silicon germanium film, a silicon germanium film having a germanium concentration of about 15 to 25% can be applied, similar to the SiGe film 46 embedded in the source / drain regions 54 in the first embodiment.

  In the above embodiment, the gate electrode 26 is replaced and nickel silicide is used as the metal silicide formed on the source / drain regions 52 and 54. However, when other metal silicide such as platinum silicide is used. The present invention can be applied.

  Further, in the first to third embodiments, the sidewall spacer having the three-layer structure including the sidewall spacers 32, 34, and 48 is formed on the sidewall portion of the gate electrode 26. However, the structure of the sidewall spacer is not limited thereto. It is not limited. For example, a side wall spacer having a single layer structure or a double layer structure may be used, or a side wall spacer having a structure of four layers or more may be used. The constituent material of the sidewall spacer can also be selected as appropriate.

  Further, the configuration of the source / drain regions 52 and 54 is not limited to the above embodiment. For example, in the above embodiment, the source / drain regions 52 and 54 with pocket regions are formed, but the pocket regions need not be provided. In the above embodiment, the source / drain regions 52 and 54 are formed by ion implantation performed after the formation of the sidewall spacer 32, ion implantation performed after the formation of the sidewall spacer 34, and ion implantation performed after the formation of the sidewall spacer 48. However, the ion implantation process for forming the source / drain regions 52 and 54 may be appropriately deleted or added.

  In the first to third embodiments, the stressor films 58 and 60 covering the MISFET are formed. However, the stressor films 58 and 60 are not necessarily formed. For example, it is not necessary to form the stressor films 58 and 60 when sufficient characteristics can be obtained without forming the stressor films 58 and 60, or in a MISFET that does not require high-speed operation.

  In addition, the constituent materials and process conditions of the MISFET can be appropriately changed according to the generation of semiconductor devices, required characteristics, and the like.

  As described above in detail, the features of the present invention are summarized as follows.

(Supplementary note 1) a first gate insulating film formed on a first region of a semiconductor substrate;
A first metal silicide film formed on the first gate insulating film; and a second metal silicide film formed on the first metal silicide film. A first gate electrode in which a composition of silicon with respect to the metal element in the second metal silicide film is larger than a composition of silicon with respect to the metal element in the second metal silicide film;
A semiconductor device comprising: a first transistor having a first impurity diffusion region pair formed in the semiconductor substrate on both sides of the first gate electrode.

(Appendix 2) In the semiconductor device according to Appendix 1,
The semiconductor device characterized in that the first metal silicide film and the second metal silicide film are nickel silicide films.

(Appendix 3) In the semiconductor device according to Appendix 1 or 2,
A second gate insulating film formed in a second region on the semiconductor substrate;
A second gate electrode including a semiconductor film mainly composed of silicon formed on the second gate insulating film and a third metal silicide film formed on the semiconductor film;
A second impurity diffusion region pair formed in the semiconductor substrate on both sides of the second gate electrode, and further comprising a second transistor having the same conductivity type as the first transistor. Semiconductor device.

(Appendix 4) In the semiconductor device described in Appendix 3,
The composition of silicon with respect to the metal element in the first metal silicide film is larger than the composition of silicon with respect to the metal element in the third metal silicide film.

(Appendix 5) In the semiconductor device according to Appendix 3 or 4,
The semiconductor device, wherein the third metal silicide film is a nickel silicide film.

(Appendix 6) In the semiconductor device according to any one of appendices 1 to 5,
The semiconductor device is characterized in that a conductivity type of the first transistor is an N type.

(Appendix 7) In the semiconductor device according to any one of appendices 1 to 6,
A third gate insulating film formed in a third region on the semiconductor substrate;
A fourth metal silicide film formed on the third gate insulating film; a fifth metal silicide film formed on the fourth metal silicide film; and the fourth metal silicide film. A third gate electrode in which the composition of silicon with respect to the metal element is larger than the composition of silicon with respect to the metal element in the fifth metal silicide film;
A third impurity diffusion region pair formed in the semiconductor substrate on both sides of the third gate electrode, and further comprising a third transistor having a conductivity type different from that of the first transistor. A semiconductor device.

(Supplementary note 8) In the semiconductor device according to supplementary note 7,
The semiconductor device, wherein the fourth metal silicide film and the fifth metal silicide film are nickel silicide films.

(Additional remark 9) The process of forming a gate insulating film on a semiconductor substrate,
Forming a first semiconductor film made of a semiconductor material mainly composed of silicon on the gate insulating film;
Forming a second semiconductor film made of a semiconductor material mainly composed of silicon on the first semiconductor film via a natural oxide film;
Patterning the first semiconductor film and the second semiconductor film to form a gate electrode including the first semiconductor film and the second semiconductor film;
Depositing a metal film on the gate electrode;
A step of reacting the second semiconductor film of the gate electrode with the metal film by heat treatment to form a first metal silicide film on the upper surface of the second semiconductor film;
Removing the unreacted metal film;
And a step of causing the gate electrode and the first metal silicide film to react with each other by heat treatment to form a metal silicide of the entire gate electrode.

(Additional remark 10) In the manufacturing method of the semiconductor device of Additional remark 9,
In the step of converting the gate electrode into a metal silicide, the second semiconductor film is converted into a second metal silicide film, and the first semiconductor film has a composition of silicon with respect to a metal element so that the second metal A method of manufacturing a semiconductor device, comprising: converting to a third metal silicide film having a composition larger than that of silicon relative to a metal element in the silicide film.

(Additional remark 11) In the manufacturing method of the semiconductor device of Additional remark 9 or 10,
After the step of forming the gate electrode and before the step of depositing the metal film, the method further includes the step of forming an impurity diffusion region pair in the semiconductor substrate on both sides of the gate electrode,
In the step of forming the first metal silicide film, the first metal silicide film is also formed on the impurity diffusion region pair.

(Supplementary note 12) In the method for manufacturing a semiconductor device according to any one of supplementary notes 9 to 11,
The method of manufacturing a semiconductor device, wherein the step of siliciding the gate electrode is performed by flash lamp annealing.

(Additional remark 13) The process of forming a 1st gate insulating film on the 1st area | region of a semiconductor substrate, and forming a 2nd gate insulating film on the 2nd area | region of the said semiconductor substrate,
Forming a first semiconductor film made of a semiconductor material mainly composed of silicon on the first gate insulating film and the second gate insulating film;
Impurities are introduced at a first concentration into the first semiconductor film on the first region, and a second lower than the first concentration is introduced into the first semiconductor film on the second region. Introducing an impurity at a concentration of
Forming a second semiconductor film made of a semiconductor material mainly composed of silicon on the first semiconductor film into which the impurity has been introduced via a natural oxide film;
The first semiconductor film and the second semiconductor film are patterned, and a first gate electrode including the first semiconductor film and the second semiconductor film is formed on the first gate insulating film. Forming a second gate electrode including the first semiconductor film and the second semiconductor film on the second gate insulating film;
Depositing a metal film on the first gate electrode and the second gate electrode;
By the heat treatment, the second semiconductor film and the metal film are reacted to form a first metal silicide film on the upper surface of the second semiconductor film of the first gate electrode, and the second gate electrode Forming a second metal silicide film on the upper surface of the second semiconductor film;
Removing the unreacted metal film;
By reacting the first gate electrode and the first metal silicide film by heat treatment, the entire first gate electrode is converted into a metal silicide, and the second gate electrode and the second metal silicide film are reacted with each other. And a step of selectively converting the second semiconductor film of the second gate electrode into a metal silicide by reacting with a metal silicide film.

(Supplementary Note 14) In the method for manufacturing a semiconductor device according to Supplementary Note 13,
In the step of converting the first gate electrode into a metal silicide, the second semiconductor film is converted into a third metal silicide film, and the first semiconductor film has a silicon composition with respect to a metal element. 3. A method for manufacturing a semiconductor device, comprising: converting to a fourth metal silicide film having a composition larger than that of silicon with respect to the metal element in the metal silicide film of No. 3.

(Additional remark 15) In the manufacturing method of the semiconductor device of Additional remark 13 or 14,
After the step of forming the first gate electrode and the second gate electrode and before the step of depositing the metal film, the semiconductor substrate on both sides of the first gate electrode and the second gate electrode A step of forming a pair of impurity diffusion regions therein,
In the step of forming the first metal silicide film and the second metal silicide film, the fifth metal silicide film is also formed on the impurity diffusion region pair.

(Supplementary Note 16) In the method for manufacturing a semiconductor device according to any one of supplementary notes 13 to 15,
In the step of introducing an impurity into the first semiconductor film, the impurity is introduced into the first semiconductor film on the first region at a concentration of 2 × 10 ²¹ cm ⁻³ or more, and the second semiconductor film A method for manufacturing a semiconductor device, wherein the impurity is introduced into the first semiconductor film over a region at a concentration of less than 2 × 10 ²¹ cm ⁻³ .

(Supplementary note 17) In the method for manufacturing a semiconductor device according to any one of supplementary notes 13 to 16,
The method of manufacturing a semiconductor device, wherein the step of siliciding the first gate electrode and the second gate electrode is performed by flash lamp annealing.

(Supplementary note 18) In the method for manufacturing a semiconductor device according to any one of supplementary notes 9 to 17,
In the step of forming the first semiconductor film, the first semiconductor film made of a silicon film or a silicon germanium film is formed,
In the step of forming the second semiconductor film, the first semiconductor film made of a silicon film or a silicon germanium film is formed.

(Appendix 19) In the method for manufacturing a semiconductor device according to any one of appendices 9 to 18,
The method of manufacturing a semiconductor device, wherein the metal film is a nickel film.

It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device by the reference example of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor device by the reference example of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor device by the reference example of this invention. It is process sectional drawing (the 4) which shows the manufacturing method of the semiconductor device by the reference example of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor device by 1st Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device by 1st Embodiment of this invention. FIG. 9 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention; It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor device by 1st Embodiment of this invention. FIG. 9 is a process cross-sectional view (No. 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention; It is process sectional drawing (the 5) which shows the manufacturing method of the semiconductor device by 1st Embodiment of this invention. It is process sectional drawing (the 6) which shows the manufacturing method of the semiconductor device by 1st Embodiment of this invention. It is an expanded sectional view which shows the state of the interface of the amorphous silicon film of the two-layer structure which comprises a gate electrode. It is a graph (the 1) which shows the threshold voltage roll-off characteristic of N type MISFET. It is a graph (the 2) which shows the threshold voltage roll-off characteristic of N type MISFET. It is a graph which shows the relationship between the OFF current of N type MISFET, and ON current. It is a graph (the 1) which shows the threshold voltage roll-off characteristic of P-type MISFET. It is a graph (the 2) which shows the threshold voltage roll-off characteristic of P-type MISFET. It is a graph which shows the relationship between the OFF current of P-type MISFET, and an ON current. It is a schematic sectional drawing which shows the structure of the semiconductor device by 2nd Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device by 2nd Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor device by 2nd Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor device by 2nd Embodiment of this invention. It is process sectional drawing (the 4) which shows the manufacturing method of the semiconductor device by 2nd Embodiment of this invention. It is a figure which shows distribution in the wafer surface of the effective film thickness of the gate insulating film of N type MISFET. It is a schematic sectional drawing which shows the structure of the semiconductor device by 3rd Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device by 3rd Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor device by 3rd Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor device by 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12 ... Element isolation film 14 ... P type well 16 ... N type well 18 ... Gate insulating film 20, 24 ... Amorphous silicon film 22 ... Natural oxide film 26 ... Gate electrodes 28, 30, 36, 38, 40, 50 ... Impurity diffusion regions 32, 34, 48 ... Side wall spacer 42 ... Silicon oxide film 44 ... Recess region 46 ... SiGe film 52, 54 ... Source / drain region 56 ... Nickel silicide film 58, 60 ... Stressor film 62 ... Interlayer insulation Film 64 ... Contact plug 66 ... Wiring layer

Claims (10)

A first gate insulating film formed on the first region of the semiconductor substrate;
A first metal silicide film formed on the first gate insulating film; and a second metal silicide film formed on the first metal silicide film. A first gate electrode in which a composition of silicon with respect to the metal element in the second metal silicide film is larger than a composition of silicon with respect to the metal element in the second metal silicide film;
A semiconductor device comprising: a first transistor having a first impurity diffusion region pair formed in the semiconductor substrate on both sides of the first gate electrode. The semiconductor device according to claim 1,
A second gate insulating film formed in a second region on the semiconductor substrate;
A second gate electrode including a semiconductor film mainly composed of silicon formed on the second gate insulating film and a third metal silicide film formed on the semiconductor film;
A second impurity diffusion region pair formed in the semiconductor substrate on both sides of the second gate electrode, and further comprising a second transistor having the same conductivity type as the first transistor. Semiconductor device. The semiconductor device according to claim 1 or 2,
A third gate insulating film formed in a third region on the semiconductor substrate;
A fourth metal silicide film formed on the third gate insulating film; a fifth metal silicide film formed on the fourth metal silicide film; and the fourth metal silicide film. A third gate electrode in which the composition of silicon with respect to the metal element is larger than the composition of silicon with respect to the metal element in the fifth metal silicide film;
A third impurity diffusion region pair formed in the semiconductor substrate on both sides of the third gate electrode, and further comprising a third transistor having a conductivity type different from that of the first transistor. A semiconductor device. Forming a gate insulating film on the semiconductor substrate;
Forming a first semiconductor film made of a semiconductor material mainly composed of silicon on the gate insulating film;
Forming a second semiconductor film made of a semiconductor material mainly composed of silicon on the first semiconductor film via a natural oxide film;
Patterning the first semiconductor film and the second semiconductor film to form a gate electrode including the first semiconductor film and the second semiconductor film;
Depositing a metal film on the gate electrode;
A step of reacting the second semiconductor film of the gate electrode with the metal film by heat treatment to form a first metal silicide film on the upper surface of the second semiconductor film;
Removing the unreacted metal film;
And a step of causing the gate electrode and the first metal silicide film to react with each other by heat treatment to form a metal silicide of the entire gate electrode. In the manufacturing method of the semiconductor device according to claim 4,
In the step of converting the gate electrode into a metal silicide, the second semiconductor film is converted into a second metal silicide film, and the first semiconductor film has a composition of silicon with respect to a metal element so that the second metal A method of manufacturing a semiconductor device, comprising: converting to a third metal silicide film having a composition larger than that of silicon relative to a metal element in the silicide film. In the manufacturing method of the semiconductor device according to claim 4 or 5,
The method of manufacturing a semiconductor device, wherein the step of siliciding the gate electrode is performed by flash lamp annealing. Forming a first gate insulating film on the first region of the semiconductor substrate, and forming a second gate insulating film on the second region of the semiconductor substrate;
Forming a first semiconductor film made of a semiconductor material mainly composed of silicon on the first gate insulating film and the second gate insulating film;
Impurities are introduced at a first concentration into the first semiconductor film on the first region, and a second lower than the first concentration is introduced into the first semiconductor film on the second region. Introducing an impurity at a concentration of
Forming a second semiconductor film made of a semiconductor material mainly composed of silicon on the first semiconductor film into which the impurity has been introduced via a natural oxide film;
The first semiconductor film and the second semiconductor film are patterned, and a first gate electrode including the first semiconductor film and the second semiconductor film is formed on the first gate insulating film. Forming a second gate electrode including the first semiconductor film and the second semiconductor film on the second gate insulating film;
Depositing a metal film on the first gate electrode and the second gate electrode;
By the heat treatment, the second semiconductor film and the metal film are reacted to form a first metal silicide film on the upper surface of the second semiconductor film of the first gate electrode, and the second gate electrode Forming a second metal silicide film on the upper surface of the second semiconductor film;
Removing the unreacted metal film;
By reacting the first gate electrode and the first metal silicide film by heat treatment, the entire first gate electrode is converted into a metal silicide, and the second gate electrode and the second metal silicide film are reacted with each other. And a step of selectively converting the second semiconductor film of the second gate electrode into a metal silicide by reacting with a metal silicide film. The method of manufacturing a semiconductor device according to claim 7.
In the step of converting the first gate electrode into a metal silicide, the second semiconductor film is converted into a third metal silicide film, and the first semiconductor film has a silicon composition with respect to a metal element. 3. A method of manufacturing a semiconductor device, comprising: converting to a fourth metal silicide film having a composition larger than that of silicon with respect to the metal element in the metal silicide film of No. 3. In the manufacturing method of the semiconductor device according to claim 7 or 8,
In the step of introducing an impurity into the first semiconductor film, the impurity is introduced into the first semiconductor film on the first region at a concentration of 2 × 10 ²¹ cm ⁻³ or more, and the second semiconductor film A method for manufacturing a semiconductor device, wherein the impurity is introduced into the first semiconductor film over a region at a concentration of less than 2 × 10 ²¹ cm ⁻³ . In the manufacturing method of the semiconductor device according to any one of claims 7 to 9,
The method of manufacturing a semiconductor device, wherein the step of siliciding the first gate electrode and the second gate electrode is performed by flash lamp annealing.

Images