JP2009146978A - Manufacturing method of semiconductor optical element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor optical element, including quantum dots having uniform size. <P>SOLUTION: The temperature of a sample formed by sequentially stacking on a substrate, a buffer layer, a clad layer, a barrier layer, an active layer, a barrier layer, a clad layer and a contact layer is raised to a heat treatment temperature (= 700-950°C) from room temperature in one minute; the sample is heat-treated at the heat treatment temperature (= 700-950°C) for one minute; and thereafter, the sample is cooled to room temperature. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor optical device.

  With the progress of semiconductor manufacturing technology represented by microfabrication technology, devices such as quantum dot laser (Quantum Dot Laser) and single electron transistor (Single Electron Transistor) using quantum size effect in addition to improvement of integration degree Has been proposed.

  In particular, a quantum dot having the same size (size) as an electron de Broglie wavelength confines electrons in a zero-dimensional manner, discretizes the energy level of the electrons, that is, changes the density of states to a delta function. It becomes possible. Quantum dots are attracting attention as a basic structure of a device having performance exceeding the conventional frame because the electron confinement effect (quantum size effect) is manifested in various ways.

  As a method for forming such quantum dots, a self-forming method called a SK (Stransky-Krastanov) mode growth method is widely known (Non-Patent Document 1). Usually, when a thin film is formed on a substrate, it is necessary to use a substrate and a thin film that have the same lattice constant. This is because if the lattice constants are greatly different, a strain force is generated during epitaxial growth, resulting in defects and a non-uniform planar structure of the thin film.

  In the SK mode growth method, contrary to the principle of thin film formation described above, a material having a large lattice constant, for example, a thin film having a lattice constant larger than that of the substrate is epitaxially grown, and the strain force generated during the epitaxial growth is actively used. Thus, the quantum dots are self-grown on the substrate.

  Using the SK mode growth method, for example, an arsenic (As) molecule and an indium (In) molecule are formed on the surface of a gallium arsenide (GaAs) substrate which is a group III-V compound semiconductor by an MBE (Molecular Beam Epitaxy) method. Are continuously supplied, quantum dots having excellent uniformity can be formed.

  By such a method, a quantum dot laser using a quantum dot in which a quantum dot made of InAs is covered with a cap layer made of GaAs as an active layer is manufactured. The quantum dot laser has an oscillation wavelength in the range of 1.1 μm to 1.2 μm.

On the other hand, a quantum well semiconductor laser is known in which a quantum well is formed using indium gallium arsenide phosphorus (InGaAsP) on a substrate made of indium phosphide (InP), and the formed quantum well is used as an active layer. The quantum well semiconductor laser has an oscillation wavelength of 1.3 μm or 1.5 μm. The oscillation wavelength of 1.3 μm or 1.5 μm is an oscillation wavelength that enables long-distance communication for optical communication using an optical fiber.
D. Leonard and 4 other authors, “Applied Physics Letters Volume 63”, December 6, 1993, pp. 196 3203-3205.

  However, the conventional quantum dot laser has a problem that it is difficult to make the size of the quantum dots used in the active layer uniform.

  Accordingly, the present invention has been made to solve such a problem, and an object thereof is to provide a method of manufacturing a semiconductor optical device including quantum dots having a uniform size.

  According to this invention, the method for manufacturing a semiconductor optical device can ensure the presence of quantum dots in the first step of forming an active layer containing quantum dots on a substrate at a first temperature and the temperature of the active layer. A second step of raising the temperature to a second temperature higher than the first temperature at a temperature rise rate equal to or higher than a reference temperature rise rate; and a third step of heat-treating the quantum dots and the cap layer at the second temperature; Is provided.

  Preferably, the first step includes a first sub-step of forming quantum dots on the substrate at a first temperature, a second sub-step of forming a cap layer covering the quantum dots at the first temperature, And a third sub-step for repeatedly executing the first and second sub-steps a plurality of times.

  Preferably, in the first sub-step, quantum dots made of indium arsenide are formed. In the second sub-step, a cap layer made of gallium arsenide is formed.

  Preferably, in the first sub-step, quantum dots made of indium arsenide are formed. In the second sub-step, a cap layer made of indium gallium arsenide is formed.

  Preferably, the heat treatment time in the third step is substantially equal to the time required to raise the temperature of the active layer to the second temperature in the second step.

  In the present invention, the temperature of the sample is raised to the heat treatment temperature at a temperature rise rate equal to or higher than a reference temperature rise rate that can ensure the presence of quantum dots, and the sample is heat treated. As a result, diffusion of atoms occurs between the quantum dot and the cap layer while ensuring the presence of the quantum dot, and the quantum dot is reconfigured. And the half width of the peak of photoluminescence decreases.

  Therefore, according to the present invention, a semiconductor optical device including quantum dots having a uniform size can be manufactured.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 1 is a sectional structural view of a semiconductor optical device according to an embodiment of the present invention. The semiconductor optical device 10 according to the embodiment of the present invention includes a negative electrode 1, a substrate 2, a buffer layer 3, cladding layers 4 and 8, barrier layers 5 and 7, an active layer 6, and a contact layer 9. And a positive electrode 11.

  The negative electrode 1 is formed on one main surface of the substrate 2. The buffer layer 3 is formed on one main surface of the substrate 2 opposite to the negative electrode 1. The cladding layer 4 is formed on the buffer layer 3 in contact with the buffer layer 3.

  The barrier layer 5 is formed on the cladding layer 4 in contact with the cladding layer 4. The active layer 6 is formed on the barrier layer 5 in contact with the barrier layer 5. The barrier layer 7 is formed on the active layer 6 in contact with the active layer 6. The clad layer 8 is formed on the barrier layer 7 in contact with the barrier layer 7. The contact layer 9 is formed on the cladding layer 8 in contact with the cladding layer 8. The positive electrode 11 is formed on the contact layer 9 in contact with the contact layer 9.

The negative electrode 1 is made of AuGe / Ni / Au. The substrate 2 is made of GaAs having a (100) surface doped with silicon (Si). The buffer layer 3 is made of n-type GaAs doped with 1 × 10 ¹⁸ cm ⁻³ of Si. The clad layer 4 is made of n-type Al _0.28 Ga _0.72 As doped with 1 × 10 ¹⁷ cm ⁻³ of Si.

Each of the barrier layers 5 and 7 is made of non-doped GaAs. The clad layer 8 is made of p-type Al _0.28 Ga _0.72 As doped with 5 × 10 ¹⁷ cm ⁻³ beryllium (Be). The contact layer 9 is made of p-type GaAs doped with more Be than 2 × 10 ¹⁹ cm ⁻³ . The positive electrode 11 is made of Au / Zn / Au.

  The buffer layer 3 has a thickness of 200 nm, the cladding layer 4 has a thickness of 500 nm, the barrier layers 5 and 7 each have a thickness of 75 nm, and the cladding layer 8 has a thickness of 250 nm. The thickness of the contact layer 9 is 20 nm.

  The film thickness of the negative electrode 1 is 0.6 μm as a whole. The film thickness of AuGe constituting the negative electrode 1 is 0.15 μm, the film thickness of Ni is 0.05 μm, and the film thickness of Au is 0.4 μm. The film thickness of the positive electrode 11 is 0.32 μm as a whole. And the film thickness of Au which comprises the positive electrode 11 is 0.01 micrometer, the film thickness of Zn is 0.01 micrometer, and the film thickness of Au is 0.3 micrometer.

  FIG. 2 is an enlarged cross-sectional view of the active layer 6 shown in FIG. The active layer 6 is composed of six quantum dot layers 61. Then, the six quantum dot layers 61 are sequentially stacked.

  Each of the six quantum dot layers 61 includes a quantum dot 611 and a cap layer 612. The cap layer 612 covers the quantum dots 611. The quantum dot 611 is made of indium arsenide (InAs) and has a size in the range of 30 to 42 nm. The cap layer 612 is made of GaAs.

  The band gap of InAs is 0.36 eV, and the band gap of GaAs is 1.42 eV.

  The quantum dots 611 are formed by crystal growth of InAs in a 2.4 monolayer (1 monolayer: approximately 0.5 nm). The film thickness of the cap layer 612 is 35 nm.

FIG. 3 is a diagram showing refractive index distributions in the cladding layer 4, the barrier layer 5, the active layer 6, the barrier layer 7, and the cladding layer 8 of the semiconductor optical device 10. Since the clad layers 4 and 8 are made of Al _0.28 Ga _0.72 As, the refractive index is the smallest. Since the barrier layers 5 and 7 are made of GaAs, the barrier layers 5 and 7 have a higher refractive index than the cladding layers 4 and 8. Since the active layer 6 is made of InAs and GaAs, it has the highest refractive index.

  As described above, the refractive index distributions in the cladding layer 4, the barrier layer 5, the active layer 6, the barrier layer 7, and the cladding layer 8 are symmetrical about the active layer 6. As a result, light generated by stimulated emission in the active layer 6 is optically confined by the barrier layers 5 and 7 and the cladding layers 4 and 8 provided on both sides, and the threshold for laser oscillation is lowered.

  FIG. 4 is an energy band diagram in the quantum dot layer 61. In FIG. 4, the direction from the cap layer 612 to the quantum dots 611 to the cap layer 612 is not the direction perpendicular to the substrate 2 but the in-plane direction DR1 of the substrate 2 in the cross-sectional view shown in FIG.

  The energy difference between the conduction band Ec1 and valence band Ev1 of GaAs (cap layer 612) corresponds to the band gap Eg1, and the energy difference between the conduction band Ec2 and valence band Ev2 of InAs (quantum dot 611) is the band gap Eg2. It corresponds to.

  GaAs constituting the cap layer 612 has a band gap of Eg1 = 1.42 eV, and InAs constituting the quantum dot 611 has a band gap of Eg2 = 0.36 eV. The InAs conduction band Ec2 constituting the quantum dot 611 is lower in energy than the conduction band Ec1 of the cap layer 612, and the InAs valence band Ev2 constituting the quantum dot 611 is smaller than the valence band Ev1 of the cap layer 612. Is also low in energy.

  Then, the electrons existing in the conduction band Ec1 of the cap layer 612 (= GaAs) move to the energetically more stable quantum dot 611 (= InAs) and exist in the valence band Ev1 of the cap layer 612 (= GaAs). Holes move to energetically more stable quantum dots 611 (= InAs).

  Then, since the energy difference ΔEc exists on the conduction band side and the energy difference ΔEv exists on the valence band side, the electrons and holes that have moved to the quantum dot 611 (= InAs) are converted into the quantum dot 611 (= It cannot move from the InAs) to the cap layer 612 (= GaAs) and is confined in the quantum dot 611 (= InAs).

  As a result, an electron sublevel Esub1 is formed on the conduction band Ec2 side of the quantum dot 611 (= InAs), and a hole sublevel is formed on the valence band Ev2 side of the quantum dot 611 (= InAs). Esub2 is formed.

  The sub-level Esub1 and the sub-level Esub2 are represented by the following expressions (1) and (2), respectively.

  The electrons existing in the sub-level Esub1 recombine with holes existing in the sub-level Esub2, and emit light having an energy hν corresponding to the energy difference between the sub-level Esub1 and the sub-level Esub2. Then, stimulated radiation is generated by the light generated by the recombination, and finally laser oscillation occurs.

  As is clear from the equations (1) and (2), the sub-levels Esub1 and Esub2 are determined by the size d of the quantum dots 611. Therefore, if the sizes d of the plurality of quantum dots 611 vary, The sub-levels Esub1 and Esub2 in the dot 611 also vary, and the wavelength λ of light emitted in the quantum dot 611 varies.

  Therefore, in the present invention, the semiconductor optical device 10 having a uniform oscillation wavelength is manufactured by making the size of the quantum dots 611 uniform.

  FIGS. 5 to 7 are first to third process diagrams respectively showing manufacturing steps of the semiconductor optical device 10 shown in FIG.

The buffer layer 3, the cladding layers 4 and 8, the barrier layers 5 and 7, the active layer 6 and the contact layer 9 constituting the semiconductor optical device 10 are formed by MBE. First, a substrate 2 made of GaAs having a (100) surface doped with Si is introduced into a vacuum chamber, and the vacuum chamber is evacuated to about 1.33 × 10 ⁻⁸ Pa.

And the temperature of the board | substrate 2 is set to the range of 540 degreeC, and Ga, As, and Si are one main surface of the board | substrate 2 from solid Ga, solid As, and solid Si, respectively at the pressure of 1.17 * 10 < ^-3 > Pa. The n-type GaAs doped with 1 × 10 ¹⁸ cm ⁻³ of Si is crystal-grown on the substrate 2 until the film thickness reaches 200 nm. In this case, the growth rate of n-type GaAs is 550 nm / hour. As a result, the buffer layer 3 is formed on the substrate 2 (see FIG. 5A).

Thereafter, at a pressure of 1.17 × 10 ⁻³ Pa, Al, Ga, As and Si are irradiated onto the surface of the buffer layer 3 from solid Al, solid Ga, solid As and solid Si, respectively, and 1 × 10 ¹⁷ cm ^−. Crystal growth of n-type Al _0.28 Ga _0.72 As doped with ³ Si is performed on the buffer layer 3 to a thickness of 500 nm. In this case, the growth rate of n-type Al _0.28 Ga _0.72 As is 764 nm / hour.

When n-type Al _0.28 Ga _0.72 As is grown on the buffer layer 3 to a thickness of 500 nm, the irradiation of Al and Si is stopped by the shutter, and 1.17 × 10 ⁻³ Pa of Under pressure, crystals are grown until non-doped GaAs has a thickness of 75 nm. In this case, the growth rate of non-doped GaAs is 550 nm / hour.

  Thereby, the clad layer 4 and the barrier layer 5 are sequentially deposited on the buffer layer 3 (see FIG. 5B).

  Thereafter, the active layer 6 is formed on the barrier layer 5 by a method described in detail later (see FIG. 5C).

When the active layer 6 is formed, the surface of the active layer 6 is irradiated with Ga and As from the solid Ga and the solid As, respectively, at a pressure of 1.17 × 10 ⁻³ Pa, and non-doped GaAs is irradiated with the active layer 6. Crystals are grown on the film to a thickness of 75 nm. In this case, the growth rate of non-doped GaAs is 550 nm / hour. Thereby, the barrier layer 7 is formed on the active layer 6.

Thereafter, at a pressure of 1.17 × 10 ⁻³ Pa, Al, Ga, As, and Be are irradiated onto the surface of the barrier layer 7 from solid Al, solid Ga, solid As, and solid beryllium (Be), respectively, and 5 × 10 5. Crystal growth of p-type Al _0.28 Gs _0.72 As doped with ¹⁷ cm ⁻³ Be is performed on the barrier layer 7 until the film thickness becomes 250 nm. Thereby, the clad layer 8 is formed on the barrier layer 7. In this case, the growth rate of p-type Al _0.28 Gs _0.72 As is 764 nm / hour.

Subsequently, at a pressure of 1.17 × 10 ⁻³ Pa, Ga, As, and Be are irradiated onto the surface of the cladding layer 8 from solid Ga, solid As, and solid Be, respectively, and more than 2 × 10 ¹⁹ cm ^−3. A large amount of Be-doped p-type GaAs is grown on the cladding layer 8 until the film thickness reaches 20 nm. In this case, the growth rate of p-type GaAs is 550 nm / hour. As a result, the contact layer 9 is formed on the cladding layer 8 (see FIG. 6D).

  A sample comprising the substrate 2 / buffer layer 3 / cladding layer 4 / barrier layer 5 / active layer 6 / buffer layer 7 / cladding layer 8 / contact layer 9 is heat-treated by a method described later (FIG. 6 ( e)).

  Thereafter, the negative electrode 1 made of AuGe / Ni / Au is formed on the back surface of the substrate 2, and the positive electrode 11 made of Au / Zn / Au is formed on the contact layer 9.

  Thereby, the semiconductor optical device 10 is completed (see FIG. 7F).

  FIG. 8 is a process diagram showing a process of forming the active layer 6 performed in the process shown in FIG.

When the barrier layer 5 is formed by the step shown in FIG. 5B, As and In are continuously formed from the solid As and the solid In at a pressure of 6.65 × 10 ⁻⁴ Pa, respectively. And an InAs film 600 is deposited up to 1.7 monolayer (see (c1) in FIG. 8).

  This 1.7 monolayer is a critical layer that grows two-dimensionally in a state where InAs is uniformly subjected to biaxial crystal strain so as to match the lattice constant (0.56 nm) of GaAs of the underlying barrier layer 5. It is a film thickness (Tc).

When the crystal growth of InAs to 2.4 monolayers, it is crystallographically stabilized to generate grains locally rather than to produce strain on the entire surface of the InAs film 600. Accordingly, at a pressure of 6.65 × 10 ⁻⁴ Pa, As and In are continuously irradiated onto the surface of the barrier layer 5 until 1.9 monolayer InAs crystal grows.

  Then, a grain 610 is formed on the surface of the InAs film 600 (see (c2) in FIG. 8).

  Thereafter, the shutter attached to the solid In is opened and closed, and the supply / stop of the In to the surface of the barrier layer 5 is repeated until the shutter becomes a 2.4 monolayer in terms of InAs.

  Then, when the shutter attached to the solid In is opened, As and In are supplied to the surface of the barrier layer 5, the grain 610 generated on the surface of the InAs film 600 grows and is attached to the solid In. When the shutter is closed, only As is supplied to the surface of the barrier layer 5, the grain 610 does not grow.

  In this case, the stop time for stopping the supply of In to the surface of the barrier layer 5 is made longer than the supply time for supplying In to the surface of the barrier layer 5. As a result, the probability that In irradiated to the surface of the barrier layer 5 reaches the grain 610 increases, and the grain 610 grows greatly. Finally, quantum dots 611 are formed on the barrier layer 5 (see (c3) in FIG. 8). In this case, the growth rate of the quantum dots 611 (= InAs) is 0.118 monolayer / second.

  Thus, the quantum dot 611 is formed by continuous supply of As and In and intermittent supply of In.

When the quantum dot 611 is formed on the barrier layer 5, at a pressure of 1.33 × 10 ⁻³ Pa, Ga and As are respectively supplied from the solid Ga and the solid As to the surface of the quantum dot 611, and GaAs is 35 nm. The crystal is grown to a thickness of. Thus, the cap layer 612 is formed so as to cover the quantum dots 611 (see (c4) in FIG. 8).

  Thereafter, the steps (c1) to (c4) shown in FIG. 8 are repeated five times to form the active layer 6.

  FIG. 9 is a diagram showing a temperature profile in the heat treatment shown in FIG. In addition, the temperature profile shown in FIG. 9 is a temperature profile of the heat processing by RTA (Rapid Thermal Annealing).

  In FIG. 6 (e), the sample comprising the substrate 2 / buffer layer 3 / clad layer 4 / barrier layer 5 / active layer 6 / barrier layer 7 / clad layer 8 / contact layer 9 has the temperature profile shown in FIG. Heat treated.

  That is, the temperature of the sample is raised from room temperature to 700 to 950 ° C. in 1 minute, then held at 700 to 950 ° C. for 1 minute, and then rapidly cooled. In this case, the actual temperature of the sample reaches 700 to 950 ° C. with a delay time of 18 to 26 seconds, and after the heat treatment is completed, the temperature is decreased from 700 to 950 ° C. to 530 ° C. in 70 to 76 seconds. The temperature is lowered from 700 to 950 ° C. to room temperature with a delay time of minutes.

  Thus, in the present invention, the heat treatment is performed by setting the heat treatment time of the sample at 700 to 950 ° C. to be approximately equal to the time required to raise the temperature of the sample from room temperature to 700 to 950 ° C.

  In the present invention, the sample is heat-treated at a heat treatment temperature (= 700 to 950 ° C.) higher than the sample preparation temperature (= 540 ° C.).

  FIG. 10 is a diagram illustrating a relationship between PL (Photoluminescence) intensity and wavelength. In FIG. 10, the vertical axis represents the PL intensity, and the horizontal axis represents the wavelength. Curves k1 to k7 are respectively PL intensity of the sample not heat-treated, PL intensity of the sample heat-treated at 700 ° C., PL intensity of the sample heat-treated at 750 ° C., PL intensity of the sample heat-treated at 800 ° C., 850 ° C. The PL strength of the sample heat-treated at, the PL strength of the sample heat-treated at 900 ° C., and the PL strength of the sample heat-treated at 950 ° C. are shown.

  When heat treatment is not performed, the peak wavelength of photoluminescence is about 1070 nm (see curve k1 in FIG. 10), but when the heat treatment temperature is increased to 700 ° C., 750 ° C., 800 ° C., 850 ° C., 900 ° C. and 950 ° C. The peak wavelength of photoluminescence shifted to the short wavelength side, and a peak wavelength of about 850 nm was obtained in the sample heat-treated at 950 ° C. (see curves k2 to k7 in FIG. 10).

  Thus, by raising the temperature of the heat treatment by RTA from 700 ° C. to 950 ° C., the peak wavelength of photoluminescence is greatly shifted to the short wavelength side.

  FIG. 11 is an enlarged view of the curve k7 shown in FIG. In FIG. 10, the vertical axis represents the PL intensity, and the horizontal axis represents the wavelength. Note that the PL intensity shown in FIG. 11 is the PL intensity when the power of the excitation light is 12.5 mW.

  A curve k7 shown in FIG. 10 can be decomposed into a curve k71 and a curve k72. Curve k71 has a peak wavelength of about 848 nm, and curve k2 has a peak wavelength of about 840 nm.

  Thus, the photoluminescence of the sample heat treated at 950 ° C. has two peak wavelengths.

  The peak at about 840 nm is shifted to the high energy side by about 12 meV from the photoluminescence peak due to the ground state. This means that quantum dots exist even when heat treatment is performed at a high temperature of 950 ° C.

  As described above, by performing heat treatment with RTA, the peak wavelength of photoluminescence is shifted to the short wavelength side. This is because the quantum dots 611 and the cap layer 612 are secured while ensuring the existence of the quantum dots 611. This is because atoms such as Ga diffuse between them and the quantum dots 611 are reconfigured. More specifically, since the quantum dot 611 is made of InAs and the cap layer 612 is made of GaAs, Ga in the cap layer 612 diffuses into the quantum dot 611 by heat treatment, and the quantum dot 611 is regenerated by InGaAs. Composed. As a result, the band gap of the quantum dots 611 is increased, and the peak wavelength of photoluminescence is shifted to the short wavelength side.

  FIG. 12 is another enlarged view of the curve k7 shown in FIG. In FIG. 12, the vertical axis represents the PL intensity, and the horizontal axis represents the wavelength. Curves k81 to k87 indicate the PL intensities when the pump light power is 100I, 50I, 25I, 13I, 5I, 3I, and 1I, respectively. The pump light powers of 100I, 50I, 25I, 13I, 5I, 3I and 1I are 25 mW, 12.5 mW, 6.25 mW, 3.25 mW, 1.25 mW, 0.75 mW and 0.01 mW, respectively. It corresponds to.

  The PL intensity of the RTA-treated sample at 950 ° C. has a peak only at about 847 nm when the excitation light power is as low as 1I, 3I, 5I, and 13I (see curves k84 to k87). This peak at about 847 nm is emission from the ground state.

  The PL intensity of the sample treated with RTA at 950 ° C. has two peaks at the powers of excitation light of 25I, 50I, and 100I (see curves k81 to k83).

  In FIG. 12, the peak on the high energy side indicated by the arrow becomes stronger as the power of the excitation light becomes stronger at 25I, 50I, and 100I. This means that even if the sample is subjected to RTA treatment at a high temperature of 950 ° C., quantum dots are present.

  Thus, the sample containing quantum dots exhibits different optical properties than the sample containing quantum wells. This is due to the difference in the state density function, where the excitation level in the quantum dot is occupied by carriers and becomes an additional peak in the PL intensity, but in the quantum well, it exists continuously between subband edges. For this reason, no quantum dot effect is observed.

  FIG. 13 is a sectional structural view of another semiconductor optical device according to the embodiment of the present invention. The semiconductor optical device according to the embodiment of the present invention may be a semiconductor optical device 10A shown in FIG.

  The semiconductor optical device 10A is the same as the semiconductor optical device 10 except that the active layer 6 of the semiconductor optical device 10 shown in FIG. The active layer 6 </ b> A is formed between the barrier layers 5 and 7 in contact with the barrier layers 5 and 7.

  FIG. 14 is an enlarged cross-sectional view of the active layer 6A shown in FIG. The active layer 6 </ b> A includes six quantum dot layers 61 </ b> A and five gap layers 62. The six quantum dot layers 61A and the five gap layers 62 are alternately stacked.

Each of the six quantum dot layers 61A includes a quantum dot 611 and a cap layer 612A. The cap layer 612A covers the quantum dots 611. The cap layer 612A is made of indium gallium arsenide (In _y Ga _1-y As, y = 0.01 to 0.6).

The band gap of InAs is 0.36 eV, and the band gap of In _y Ga _1-y As is in the range of 1.413 to 0.7856 eV with respect to the indium In content y = 0.01 to 0.6. It is.

  The film thickness of the cap layer 612A is 6 nm.

  Each of the five gap layers 62 is made of GaAs and has a thickness of 35 nm.

  The refractive index distribution in the cladding layer 4, the barrier layer 5, the active layer 6A, the barrier layer 7 and the cladding layer 8 in the semiconductor optical device 10A is the same as the refractive index distribution shown in FIG.

  The semiconductor optical device 10A is manufactured according to the steps (a) to (f) shown in FIGS.

  FIG. 15 is a process diagram showing another process of forming the active layer performed in FIG. The active layer 6A shown in FIG. 14 is formed according to steps (c1) to (c3), (c5), and (c6) shown in FIG.

After the above-described steps (c1) to (c3) are sequentially performed, In, Ga, and As are changed from solid In, solid Ga, and solid As to quantum dots 611, respectively, at a pressure of 1.17 × 10 ⁻³ Pa. Supplied to the surface, In _y Ga _1-y As is crystal-grown to a thickness of 6 nm. Thus, the cap layer 612A is formed so as to cover the quantum dots 611 (see (c5) in FIG. 15).

Thereafter, at a pressure of 1.17 × 10 ⁻³ Pa, Ga and As are respectively supplied from the solid Ga and the solid As to the surface of the cap layer 612A, and GaAs is crystal-grown to a film thickness of 35 nm. Thereby, the gap layer 62 is formed (see (c6) in FIG. 15).

  Thereafter, the steps (c1) to (c3), (c5), and (c6) shown in FIG. 15 are repeated five times to form the active layer 6A.

  FIG. 16 is a diagram showing the PL intensity of the semiconductor optical device 10A shown in FIG. In FIG. 16, the vertical axis represents the PL intensity, and the horizontal axis represents the wavelength. Curve k8 shows the PL intensity of the sample not subjected to the heat treatment by RTA, and curves k9 to k14 show the heat treatment by RTA at 700 ° C., 750 ° C., 800 ° C., 850 ° C., 900 ° C. and 950 ° C., respectively. The PL intensity of each sample is shown.

  The sample not subjected to heat treatment with RTA has a photoluminescence peak wavelength of 1187 nm (see curve k8), and the sample subjected to heat treatment with RTA at 700 ° C. has a photoluminescence peak wavelength of 1185 nm (see curve k9). The sample subjected to the heat treatment by RTA at 750 ° C. has a photoluminescence peak wavelength of 1122 nm (see curve k10), and the sample subjected to the heat treatment by RTA at 800 ° C. has a peak wavelength of photoluminescence of 1077 nm ( (See curve k11).

  Samples subjected to RTA heat treatment at 850 ° C have photoluminescence peak wavelengths of 1013 nm and 984 nm (see curve k12), and samples subjected to RTA heat treatment at 900 ° C have a photoluminescence peak wavelength of 915 nm. And 904 nm (see curve k13), the sample subjected to the heat treatment by RTA at 950 ° C. has a photoluminescence peak wavelength of 870 nm (see curve k14).

  Thus, also in the semiconductor optical device 10A in which the quantum dots 611 made of InAs are capped with the cap layer 612A made of InGaAs, the peak wavelength of the photoluminescence is increased by increasing the temperature of the heat treatment by RTA from 700 ° C. to 950 ° C. Shift to short wavelength side.

  In the semiconductor optical device 10A, the reason why the peak wavelength of photoluminescence shifts to the short wavelength side by the heat treatment by RTA is the reason why the peak wavelength of photoluminescence shifts to the short wavelength side by the heat treatment by RTA in the semiconductor optical device 10 Is the same.

  FIG. 17 is a diagram showing the relationship between the integrated intensity of photoluminescence and the annealing temperature. In FIG. 17, the vertical axis represents the integrated intensity of photoluminescence, and the horizontal axis represents the annealing temperature. A curve k15 shows the relationship between the integrated intensity of photoluminescence and the annealing temperature in a sample in which the quantum dot 611 (= InAs) is capped with GaAs, and a curve kl6 shows the quantum dot 611 (= InAs) capped with InGaAs. The relationship between the integrated intensity | strength of the photoluminescence in a sample and annealing temperature is shown.

  When the quantum dots 611 (= InAs) are capped with GaAs, the sample subjected to the heat treatment by RTA at 800 ° C. has double the integrated intensity of photoluminescence compared to the sample not subjected to the heat treatment by RTA (see curve k15). ).

  On the other hand, when quantum dots 611 (= InAs) are capped with InGaAs, the sample subjected to heat treatment by RTA at 950 ° C. has a 1.6 times higher integrated intensity of photoluminescence than the sample not subjected to heat treatment by RTA. The sample subjected to heat treatment by RTA at 850 ° C. has a photoluminescence integrated intensity five times that of the sample not subjected to heat treatment by RTA (see curve k16).

  Thus, by performing the heat treatment by RTA, the integrated intensity of the photoluminescence of the sample including the quantum dots 611 is increased.

  FIG. 18 is a diagram showing the relationship between the half-value width of the peak of photoluminescence and the annealing temperature. In FIG. 18, the vertical axis represents the half width of the photoluminescence peak, and the horizontal axis represents the annealing temperature. Curve k17 shows the relationship between the half-value width of the photoluminescence peak and the annealing temperature in a sample in which quantum dots 611 (= InAs) are capped with GaAs, and curve kl8 shows quantum dots 611 (= InAs) with InGaAs. The relationship between the half value width of the peak of the photoluminescence in the capped sample and annealing temperature is shown.

  In both the sample in which the quantum dot 611 (= InAs) is capped with GaAs and the sample in which the quantum dot 611 (= InAs) is capped with InGaAs, the half width of the peak of the photoluminescence is 58 meV at an annealing temperature of 700 ° C. It becomes the highest at an annealing temperature of 750 ° C., decreases by increasing the annealing temperature above 750 ° C., and becomes 9 meV at an annealing temperature of 950 ° C. (see curves k17 and k18).

  Thus, the half width of the photoluminescence peak decreases from 58 meV to 9 meV by increasing the annealing temperature.

  This reduction in the half-value width of the photoluminescence peak means that the size of the quantum dots 611 is made uniform by annealing.

  FIG. 19 is a diagram showing the relationship between the peak energy of photoluminescence and the annealing temperature. In FIG. 19, the vertical axis represents the photoluminescence peak energy, and the horizontal axis represents the annealing temperature. A curve k19 shows the relationship between the peak energy of light emission in the ground state and the annealing temperature, and a curve k20 shows the relationship between the peak energy of light emission in the first excited state and the annealing temperature.

  The energy difference between the ground state and the first excited state is widely distributed from 75 meV to 16 meV depending on the annealing temperature (see curves k19 and k20). This is due to the diffusion of atoms at the interface between the quantum dots 611 and the cap layers 612 and 612A.

  Therefore, the semiconductor optical devices 10 and 10A can be used as a photodetector in the infrared region or a quantum dot laser.

  FIG. 20 is a perspective view of the wafer. The buffer layer 3, the cladding layer 4, the barrier layer 5, the active layers 6, 6A, the barrier layer 7, the cladding layer 8 and the contact layer 9 are formed on the substrate 20 in accordance with the steps (a) to (d) shown in FIGS. The wafers 20 are sequentially stacked.

  Then, for example, the chips 21 and 22 are cut out from the wafer 20, the chip 21 is annealed at 800 ° C., and the chip 22 is annealed at 850 ° C. Thereafter, the negative electrode 1 and the positive electrode 11 are formed on the back and front surfaces of the chips 21 and 22, respectively.

  As described above, since the peak wavelength of photoluminescence differs by changing the heat treatment temperature by RTA, the chips 21 and 22 produced by the above-described method become semiconductor optical devices having mutually different characteristics.

  Thus, a plurality of semiconductor optical elements having different characteristics can be produced from one wafer 20.

  In the above description, it has been described that when heat treatment by RTA is performed, the temperature is raised from room temperature to the heat treatment temperature (= 700 to 950 ° C.) in 1 minute. However, the present invention is not limited to this, and heat treatment by RTA is performed. The temperature increase rate may be equal to or higher than the temperature increase rate (= reference temperature increase rate) that can ensure the presence of the quantum dots 611.

  Since the heat treatment temperature (= 700 to 950 ° C.) is higher than the formation temperature (= 540 ° C.) of the quantum dots 611, when the rate of temperature rise is slow, between the quantum dots 611 and the cap layers 612 and 612A, such as Ga Atoms diffuse to each other and the quantum dots 611 are destroyed. Therefore, in order to ensure the presence of the quantum dots 611 and anneal, it is necessary to raise the temperature of the sample at a certain temperature increase rate.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

  The present invention is applied to a method for manufacturing a semiconductor optical device including quantum dots having a uniform size.

1 is a cross-sectional structure diagram of a semiconductor optical device according to an embodiment of the present invention. It is an expanded sectional view of the active layer shown in FIG. It is a figure which shows distribution of the refractive index in the clad layer of a semiconductor optical element, a barrier layer, an active layer, a barrier layer, and a clad layer. It is an energy band figure in a quantum dot layer. FIG. 3 is a first process diagram showing a manufacturing process of the semiconductor optical device shown in FIG. 1. FIG. 6 is a second process diagram showing a manufacturing process of the semiconductor optical device shown in FIG. 1. FIG. 6 is a third process diagram illustrating a manufacturing process of the semiconductor optical device illustrated in FIG. 1. It is process drawing which shows the formation process of the active layer performed in FIG.5 (c). It is a figure which shows the temperature profile in the heat processing shown to (e) of FIG. It is a figure which shows the relationship between PL (Photoluminescence) intensity | strength and a wavelength. It is an enlarged view of the curve k7 shown in FIG. It is another enlarged view of the curve k7 shown in FIG. It is sectional structure drawing of the other semiconductor optical element by embodiment of this invention. It is an expanded sectional view of the active layer shown in FIG. It is process drawing which shows the other formation process of the active layer performed in FIG.5 (c). It is a figure which shows PL intensity | strength of the semiconductor optical element shown in FIG. It is a figure which shows the relationship between the integrated intensity | strength of photoluminescence, and annealing temperature. It is a figure which shows the relationship between the half value width of the peak of photoluminescence, and annealing temperature. It is a figure which shows the relationship between the peak energy of photoluminescence, and annealing temperature. It is a perspective view of a wafer.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Negative electrode, 2 Substrate, 3 Buffer layer, 4,8 Clad layer, 5,7 Barrier layer, 6,6A Active layer, 9 Contact layer, 10,10A Semiconductor optical element, 11 Positive electrode, 20 Wafer, 21,22 Chip, 61, 61A quantum dot layer, 62 intermittent layer, 600 InAs film, 610 grain, 611 quantum dot, 612, 612A cap layer.

Claims (5)

Forming an active layer comprising quantum dots on a substrate at a first temperature;
A second step of increasing the temperature of the active layer to a second temperature higher than the first temperature at a temperature increase rate equal to or higher than a reference temperature increase rate capable of ensuring the presence of the quantum dots;
And a third step of heat-treating the quantum dots and the cap layer at the second temperature. The first step includes
A first sub-step of forming the quantum dots on the substrate at the first temperature;
A second sub-step of forming a cap layer covering the quantum dots at the first temperature;
The method of manufacturing a semiconductor optical device according to claim 1, further comprising a third sub-step of repeatedly executing the first and second sub-steps a plurality of times. In the first sub-step, quantum dots made of indium arsenide are formed,
The method of manufacturing a semiconductor optical device according to claim 2, wherein a cap layer made of gallium arsenide is formed in the second sub-step. In the first sub-step, quantum dots made of indium arsenide are formed,
3. The method of manufacturing a semiconductor optical device according to claim 2, wherein a cap layer made of indium gallium arsenide is formed in the second substep.   5. The heat treatment time in the third step is substantially equal to a time required for raising the temperature of the active layer to the second temperature in the second step. 6. A method for producing a semiconductor optical device according to claim 1.

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