JP2009031595A - Display device, electronic apparatus equipped with display device, and control method of display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of recovering an abnormal operational state back to the normal state without requiring a manual operation in the event of an abnormality in the operation of a panel without causing a display abnormality during the normal operation, and a control method thereof. <P>SOLUTION: An internal state of a logic circuit in a driver is initialized by a predetermined reset input. A display control circuit 200 has an operational state checking part 24 for determining the operational state of the driver based on a start pulse signal SP, a clock signal CK, and a signal OUT output from an output terminal of a shift register in the driver, and a reset signal output part 27 for providing a reset input to the driver. A host 900 acquires the determination result by the operational state checking part 24, and if the operational state of the driver is abnormal, outputs a reset command RC. The reset signal output part 27 provides a reset input to the driver based on the reset command RC. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device and a control method therefor, and more particularly to a method for returning an operation state to a normal state when the operation state of the display device becomes abnormal.

  Conventionally, a general display device is provided with a source driver that drives a source bus line (video signal line) and a gate driver that drives a gate bus line (scanning signal line). In recent years, a liquid crystal display device employing a CG silicon liquid crystal (Continuous Grain Silicon Liquid Crystal) panel has been developed. The CG silicon liquid crystal panel is a liquid crystal panel that employs a TFT (Thin Film Transistor) formed of a CG silicon film as a switching element. CG silicon has a regular arrangement of crystal interfaces and a continuous structure at the atomic level. For this reason, since electrons can move at high speed in CG silicon, a source driver or a gate driver (hereinafter collectively referred to as “driver”) can be mounted on the substrate of the liquid crystal panel. As a result, costs are reduced by reducing the number of necessary parts, and miniaturization of devices is progressing.

  The driver described above is composed of a logic circuit, and there is a driver provided with a reset terminal for initializing the internal state of the logic circuit. For example, the internal state of the logic circuit is initialized by giving a predetermined input to the reset terminal of the driver from the outside of the panel (control unit or the like) when the power is turned on. Hereinafter, the input given to the reset terminal in order to initialize the internal state of the logic circuit in the driver is referred to as “reset input”.

During the operation of the display device as described above, the internal state of the logic circuit may become abnormal due to, for example, the influence of external static electricity, and display abnormality may occur. In general, in such a case, in order to return the operation state of the panel to a normal state, the internal state of the logic circuit is initialized by giving a reset input to the driver from the outside of the panel. Japanese Patent Application Laid-Open No. 2001-75541 discloses an invention of a display device driving method capable of suppressing an afterimage when the power is turned off. Japanese Patent Laid-Open No. 2002-91389 discloses an invention of a liquid crystal display device capable of suppressing display abnormality.
JP 2001-75541 A JP 2002-91389 A

  By the way, when the operation state of the panel is abnormal, there is no problem even if the reset input is given to the driver at an arbitrary timing. However, if a reset input is given to the driver at an arbitrary timing in a display device in which the operation state of the panel cannot be detected by the control unit, a display abnormality may occur. This will be described with reference to FIG. In general, in a display device, a plurality of (m) gate bus lines GL1 to GLm connected to the gate driver 400 are sequentially scanned one by one, thereby displaying a display as shown in FIG. An image is displayed on the entire unit 100. However, when the panel is operating normally, if a reset input is given to the driver at the gate bus line scanning timing indicated by reference numeral GLx in FIG. Since the internal state of the circuit is initialized, image display in the area indicated by reference numeral 101 is not normally performed. As described above, when a reset input is given to the driver at an arbitrary timing, a display abnormality may be caused even though the operation state of the panel is normal. Further, according to the display devices disclosed in Japanese Patent Application Laid-Open Nos. 2001-75541 and 2002-91389, the display abnormality is suppressed, but when the operation state becomes abnormal, the operation state becomes a normal state. It cannot be returned to.

  Accordingly, the present invention provides a display device and a control method thereof that can return the operation state to a normal state without manual intervention when the operation state of the panel becomes abnormal without causing a display abnormality during normal operation. The purpose is to provide.

The first invention is a display device,
A display for displaying an image;
A plurality of signal lines arranged in the display unit;
A driving circuit for driving the plurality of signal lines, a plurality of logic circuits storing values for determining whether to drive the plurality of signal lines, respectively, and a predetermined reset input; A drive circuit having logic circuit initialization means for initializing values stored in the plurality of logic circuits;
An operation state inspection unit that determines whether the operation state of the drive circuit is normal or abnormal based on a predetermined test signal output from the drive circuit;
And a reset input providing unit that applies the reset input to the drive circuit when the operation state inspecting unit determines that the operation state of the drive circuit is abnormal.

According to a second invention, in the first invention,
The drive circuit includes a shift register that includes the plurality of logic circuits and sequentially shifts a predetermined pulse from an input terminal to an output terminal based on a predetermined timing signal, and the predetermined circuit starts from the output terminal of the shift register. Are output as the inspection signal,
The operation state inspection unit determines whether the operation state of the drive circuit is normal or abnormal based on the timing signal and the inspection signal.

According to a third invention, in the second invention,
The timing signal provides the shift register with a start pulse signal for applying the predetermined pulse to the shift register and a clock pulse for sequentially shifting the predetermined pulse from the input end to the output end of the shift register. And a clock signal.

According to a fourth invention, in the third invention,
The operating state inspection unit
A clock number counting unit that counts the number of clock pulses of the clock signal from the time when the predetermined pulse is applied to the input terminal of the shift register by the start pulse signal;
A timing determination unit that determines whether or not the predetermined pulse is output from the output terminal of the shift register based on the number of clock pulses counted by the clock number counting unit;
The drive circuit receives the inspection signal, and based on the value of the inspection signal when the timing determination unit determines that the predetermined pulse is output from the output terminal of the shift register, And an operation state determination unit that determines whether or not the device is operating normally.

According to a fifth invention, in any one of the first to fourth inventions,
The drive circuit is constituted by a thin film transistor using continuous grain boundary crystalline silicon.

According to a sixth invention, in any one of the first to fifth inventions,
It further includes an interface unit that transmits and receives data to and from the outside.
The reset input giving unit gives the reset input to the drive circuit when the interface unit receives a predetermined reset command from the outside.

A seventh invention is an electronic apparatus comprising the display device according to the sixth invention and a host device connected to the display device,
The host device receives a determination result from the operation state inspection unit from the interface unit, and gives the reset command to the interface unit if the determination result indicates that the operation state of the drive circuit is abnormal. It is characterized by that.

An eighth invention is an electronic device comprising a display device and a host device,
The display device
A display for displaying an image;
A plurality of signal lines arranged in the display unit;
A drive circuit for driving the plurality of signal lines;
An operation state inspection unit that determines whether the operation state of the drive circuit is normal or abnormal based on a predetermined test signal output from the drive circuit;
An interface unit for transmitting and receiving data to and from the host device;
A host command execution unit that executes a command given from the host device via the interface unit, the host device receives a determination result by the operation state inspection unit from the interface unit, and the determination result is the drive circuit If the operation state indicates that the operation state is abnormal, a predetermined command is given to the interface unit.

A ninth invention is a display device,
A display for displaying an image;
A plurality of signal lines arranged in the display unit;
A driving circuit for driving the plurality of signal lines, a plurality of logic circuits storing values for determining whether to drive the plurality of signal lines, respectively, and a predetermined reset input; A drive circuit having logic circuit initialization means for initializing values stored in the plurality of logic circuits;
And a reset input providing unit that applies the reset input to the drive circuit during a predetermined period and during a period in which the drive circuit is stopped.

A tenth invention is the ninth invention,
The plurality of signal lines include a plurality of video signal lines for transmitting a plurality of video signals representing the image, and a plurality of scanning signal lines intersecting the plurality of video signal lines,
The driving circuit includes a video signal line driving circuit for driving the plurality of video signal lines, and a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines,
The reset input giving unit is
Applying the reset input to the video signal line driving circuit during a horizontal blanking period,
The reset input is supplied to the scanning signal line driving circuit during a vertical blanking period.

In an eleventh aspect based on the ninth aspect,
The plurality of signal lines include a plurality of video signal lines for transmitting a plurality of video signals representing the image, and a plurality of scanning signal lines intersecting the plurality of video signal lines,
The driving circuit includes a video signal line driving circuit for driving the plurality of video signal lines, and a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines,
The reset input applying unit supplies the reset input to the video signal line driving circuit and the scanning signal line driving circuit during a vertical blanking period.

In a twelfth aspect based on the tenth or eleventh aspect,
A partial display function for displaying an image only in a partial area of the display unit;
When the image input by the partial display function is being performed, the reset input providing unit is configured so that the scanning signal line disposed in a region where no image is displayed in the display unit is selected. A reset input is provided to the video signal line driving circuit.

A thirteenth aspect of the invention is a drive circuit for driving a plurality of signal lines arranged in a display unit for displaying an image, and determines a value for determining whether or not to drive each of the plurality of signal lines. A control method of a display device including a drive circuit having a plurality of logic circuits to be stored,
A logic circuit initialization step for initializing values stored in the plurality of logic circuits based on a predetermined reset input given to the drive circuit;
An operation state inspection step for determining whether the operation state of the drive circuit is normal or abnormal based on a predetermined test signal output from the drive circuit;
And a reset input providing step of providing the reset input to the drive circuit when it is determined in the operation state inspection step that the operation state of the drive circuit is abnormal.

  Further, in the thirteenth invention, a modification grasped by referring to the embodiment and the drawings is considered as a means for solving the problem.

An eighteenth aspect of the invention is a drive circuit for driving a plurality of signal lines arranged in a display unit for displaying an image, and determines a value for determining whether or not to drive each of the plurality of signal lines. A control method of a display device including a drive circuit having a plurality of logic circuits to be stored,
A logic circuit initialization step for initializing values stored in the plurality of logic circuits based on a predetermined reset input given to the drive circuit;
And a reset input providing step of applying the reset input to the drive circuit every predetermined period and in a period in which the drive circuit is stopped.

  Moreover, the modification grasped | ascertained by referring embodiment and drawing in 18th invention is considered as a means for solving a subject.

  According to the first aspect, in the display device, the operation state of the drive circuit is detected based on the inspection signal output from the drive circuit. In addition, when the operation state of the drive circuit becomes abnormal, the reset input applying unit applies a reset input to the drive circuit, thereby initializing the logic circuit in the drive circuit. For this reason, even if an abnormality occurs in the operation state of the drive circuit, the operation state is restored to a normal state without human intervention. Here, since the operation state of the drive circuit is detected in the display device as described above, it is only necessary to apply a reset input to the drive circuit only when the operation state becomes abnormal, and the operation state is normal. Sometimes it is not necessary to give a reset input to the drive circuit. For this reason, a display device capable of recovering the operating state without human intervention when the operating state becomes abnormal without causing a display abnormality due to the application of the reset input to the drive circuit is realized.

  According to the second aspect of the invention, the operation state of the drive circuit is inspected based on the signal output from the output terminal of the shift register in the drive circuit and the timing signal for controlling the operation of the drive circuit. For this reason, the operation state of the drive circuit can be inspected with a relatively simple configuration.

  According to the third aspect of the present invention, in a display device having a general configuration, when the operation state becomes abnormal without causing display abnormality due to the application of the reset input to the drive circuit, the manual operation is not performed. The operating state can be recovered.

  According to the fourth aspect of the invention, it is determined based on the clock pulse whether or not the predetermined pulse is output from the output end of the shift register. For this reason, the operation state of the drive circuit is inspected at a reliable timing.

  According to the fifth aspect of the invention, in the display device in which the drive circuit is realized by the thin film transistor using the continuous grain boundary crystal silicon, the operation state is not caused without causing display abnormality due to the application of the reset input to the drive circuit. When the operation becomes abnormal, the operation state can be recovered without human intervention.

  According to the sixth aspect, since data is transmitted / received to / from the outside by the interface unit, the determination result by the operation state inspection unit can be transmitted from the display device to the outside via the interface unit. Further, the reset input giving unit gives a reset input to the drive circuit when a reset command is given from the outside. For this reason, when the operating state becomes abnormal, the operating state of the driving circuit can be restored to a normal state by giving a reset command to the display device from the outside.

  According to the seventh aspect of the present invention, in an electronic device composed of a display device and a host device, when the operation state of the drive circuit in the display device becomes abnormal, the host device gives a reset command to the display device. The operating state of the drive circuit can be restored to a normal state.

  According to the eighth aspect of the invention, in the electronic apparatus including the display device and the host device, the display device is provided with the interface unit for transmitting and receiving data to and from the host device. The operating state of the drive circuit is transmitted to the host device via Further, the display device is provided with a host command execution unit for executing a command given from the host device. Therefore, the host device can detect the operation state of the drive circuit in the display device, and can send a command to the display device when the operation state of the drive circuit becomes abnormal. The operation of the display device is controlled according to the command. As a result, when the operation state of the drive circuit becomes abnormal, the contents of the command from the host device to the display device are changed to perform desired processing such as power supply stop and initialization of the logic circuit in the drive circuit. be able to.

  According to the ninth aspect, the logic circuit in the drive circuit is initialized every predetermined period. For this reason, even if an abnormality occurs in the operation state of the drive circuit, the operation state is restored to a normal state without human intervention. The initialization of the logic circuit in the drive circuit is performed while the drive circuit is stopped. For this reason, display abnormality does not occur due to the initialization of the logic circuit.

  According to the tenth aspect, the logic circuit in the video signal line driving circuit is initialized during the horizontal blanking period, and the logic circuit in the scanning signal line driving circuit is initialized during the vertical blanking period. Here, the video signal line driving circuit is stopped during the horizontal blanking period, and the scanning signal line driving circuit is stopped during the vertical blanking period. This realizes a display device that can return the operating state to the normal state without human intervention when the operating state of the drive circuit becomes abnormal without causing display abnormality due to the initialization of the logic circuit. Is done.

  According to the eleventh aspect, the logic circuit in the video signal line driving circuit and the logic circuit in the scanning signal line driving circuit are initialized during the vertical blanking period. Here, the video signal line driving circuit and the scanning signal line driving circuit are stopped during the vertical blanking period. This realizes a display device that can return the operating state to the normal state without human intervention when the operating state of the drive circuit becomes abnormal without causing display abnormality due to the initialization of the logic circuit. Is done.

  According to the twelfth aspect of the invention, in the display device having a partial display function, the display circuit caused by the initialization of the logic circuit is not caused, and when the operation state of the drive circuit becomes abnormal, the manual operation is not performed. The operating state is returned to the normal state.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

<1. First Embodiment>
<1.1 Overall configuration and operation>
FIG. 2 is a block diagram showing the overall configuration of the monolithic CG silicon liquid crystal display device according to the first embodiment of the present invention. This liquid crystal display device includes a liquid crystal panel 1 and a display control circuit 200. The liquid crystal panel 1 includes a display unit 100, a source driver (video signal line driving circuit) 300, and a gate driver (scanning signal line driving circuit) 400. This liquid crystal display device is used for, for example, a mobile phone and is connected to a host 900 of the mobile phone.

  The display unit 100 includes a plurality (n) of source bus lines (video signal lines) SL1 to SLn, a plurality (m) of gate bus lines (scanning signal lines) GL1 to GLm, and source buses thereof. A plurality of (n × m) pixel forming portions provided corresponding to the intersections of the lines SL1 to SLn and the gate bus lines GL1 to GLm are included. These pixel forming portions are arranged in a matrix to form a pixel array, and each pixel forming portion is connected to a gate bus line GLj passing through a corresponding intersection and a source bus line passing through the intersection. The TFT 10 which is a switching element having a source terminal connected to SLi, the pixel electrode 11 connected to the drain terminal of the TFT 10, the common electrode Ec and the auxiliary capacitance electrode provided in common in the plurality of pixel forming portions A liquid crystal capacitor 12 formed by Cs, the pixel electrode 11 and the common electrode Ec, and an auxiliary capacitor 13 formed by the pixel electrode 11 and the auxiliary capacitor electrode Cs are included. The liquid crystal capacitor 12 and the auxiliary capacitor 13 constitute a pixel capacitor.

  The display control circuit 200 receives the image data DAT and the timing signal group TG sent from the external host 900, and receives the analog video signal AV and the source start pulse signal SSP for controlling the timing for displaying the image on the display unit 100. , The source clock signal SCK, the gate start pulse signal GSP, the gate clock signal GCK, and the reset signal RS for initializing the internal state of the logic circuits provided in the source driver 300 and the gate driver 400 are output. . In addition, the display control circuit 200 checks a signal output from the output terminal of the shift register in the source driver 300 (hereinafter referred to as “source output terminal signal” in order to check whether or not the liquid crystal panel 1 is operating normally. SOUT and a signal (hereinafter referred to as “gate output terminal signal”) GOUT output from the output terminal of the shift register in the gate driver 400 are received. Hereinafter, the source output terminal signal SOUT and the gate output terminal signal GOUT are collectively referred to as an output terminal signal OUT. The detailed configuration and operation of the display control circuit 200 will be described later.

  FIG. 3 is a block diagram illustrating a schematic configuration of the source driver 300. The source driver 300 includes a shift register 31 and a panel driving video signal output circuit 32. A source start pulse signal SSP, a source clock signal SCK, and a reset signal RS output from the display control circuit 200 are input to the shift register 31. The panel drive video signal output circuit 32 receives the analog video signal AV output from the display control circuit 200. When a reset input is given to the shift register 31 by the reset signal RS, the internal state of the logic circuit constituting the shift register 31 is initialized. The shift register 31 sequentially transfers pulses included in the source start pulse signal SSP from the input end to the output end based on the source clock signal SCK. In response to this pulse transfer, sampling pulses corresponding to the source bus lines SL1 to SLn are sequentially output from the shift register 31, and the sampling pulses are sequentially input to the panel drive video signal output circuit 32. A source output terminal signal SOUT is output from the output terminal of the shift register 31. The panel drive video signal output circuit 32 takes in the analog video signal AV based on the sampling pulse output from the shift register 31 and charges the pixel capacity of each pixel formation unit in the display unit 100. Applied to the source bus lines SL1 to SLn. In the present embodiment, the logic level of the reset signal RS changes from the low level to the high level is a reset input in each driver (source driver 300, gate driver 400).

  FIG. 4 is a block diagram showing a schematic configuration of the gate driver 400. The gate driver 400 includes a shift register 41 and a panel drive scanning signal output circuit 42. The shift register 41 receives the gate start pulse signal GSP, the gate clock signal GCK, and the reset signal RS output from the display control circuit 200. The panel drive scanning signal output circuit 42 receives the above-described voltage (TFT on voltage) VGH for turning on the TFT 10 and voltage (TFT off voltage) VGL for turning off the TFT 10. When a reset input is given to the shift register 41 by the reset signal RS, the internal state of the logic circuit constituting the shift register 41 is initialized. Based on the gate clock signal GCK, the shift register 41 sequentially transfers pulses included in the gate start pulse signal GSP from the input end to the output end. In response to this pulse transfer, high level signals are sequentially output from the shift register 41, and the high level signals are sequentially input to the panel drive scanning signal output circuit. A gate output terminal signal GOUT is output from the output terminal of the shift register 41. The panel drive scanning signal output circuit 42 applies the TFT on voltage VGH or the TFT off voltage VGL to each of the gate bus lines GL1 to GLm as a scanning signal in accordance with the logic level of the signal output from the shift register 41.

  As described above, driving video signals are applied to the source bus lines SL1 to SLn, and scanning signals are applied to the gate bus lines GL1 to GLm, whereby an image is displayed on the display unit 100. In the following description, the source start pulse signal SSP and the gate start pulse signal GSP are collectively referred to as a start pulse signal SP, and the source clock signal SCK and the gate clock signal GCK are collectively referred to as a clock signal CK.

<1.2 Configuration and operation of shift register>
FIG. 5 is a block diagram showing the configuration of the shift registers 31 and 41 included in the source driver 300 and the gate driver 400. The shift registers 31 and 41 include n registers R1 to Rn each storing 1-bit data. As described above, the shift registers 31 and 41 are supplied with the clock signal CK, the start pulse signal SP, and the reset signal RS, and the shift registers 31 and 41 output the output terminal signal OUT. The clock signal CK is applied to each of the registers R1 to Rn, the start pulse signal SP is applied only to the first-stage register R1, and the reset signal RS is applied to each of the registers R1 to Rn via a reset terminal.

  Next, the operation of the shift registers 31 and 41 will be described with reference to FIGS. Here, the reset signal RS having the waveform shown in FIG. 6A, the start pulse signal SP having the waveform shown in FIG. 6B, and the clock signal CK having the waveform shown in FIG. It will be described as being input.

  When the logic level of the reset signal RS changes from the low level to the high level at time t in FIG. 6, all the registers R1 to Rn receive a reset input. As a result, all the registers R1 to Rn are initialized, and the values of all the registers R1 to Rn are “0” as shown in FIG. In this embodiment, a logic circuit initialization unit is realized by the reset terminal and the internal circuits of the registers R1 to Rn.

  After the rising edge of the start pulse signal SP, the value of the first-stage register R1 becomes “1” as shown in FIG. 7B at the first rising edge of the clock signal CK. The values of R2 to Rn are maintained at “0”. As a result, only the signal output from the first stage of the shift registers 31 and 41 becomes high level. Thereafter, as shown in FIG. 7C, the value of the first-stage register R1 becomes “0” and the value of the second-stage register R2 becomes “1” at the rising edge of the second clock signal CK. The values of the other registers R3 to Rn are maintained at “0”. As a result, only the signal output from the second stage of the shift registers 31 and 41 is set to the high level. In this way, each time the pulse of the clock signal CK rises, the value of the register arranged in the subsequent stage becomes “1”, and only the signal output from the register whose value is “1”. Become high level.

  After the rise of the pulse of the start pulse signal SP, as shown in FIG. 7D, only the value of the n-th register Rn becomes “1” at the rise of the nth clock signal CK. As a result, only the signal output from the nth stage of the shift registers 31 and 41 is set to the high level. Thereafter, at the rising edge of the (n + 1) th clock signal CK, as shown in FIG. 7E, the output terminal signal OUT output from the output terminals of the shift registers 31 and 41 becomes high level.

  In this embodiment, as shown in FIG. 8A, initialization of the internal state of the logic circuit in the drivers 300 and 400 is started when the reset signal RS changes from low level to high level. However, the present invention is not limited to this. For example, as shown in FIG. 8B, the initialization may be started when the reset signal RS changes from a high level to a low level. Further, as shown in FIGS. 8C and 8D, the initialization is started when a predetermined period (reset signal recognition period) elapses from the time when the logic level of the reset signal RS changes. Also good.

  By the way, when a reset input is given to the drivers 300 and 400, the following operations are performed in the drivers 300 and 400. In the source driver 300, all of the analog switches 33 configured as shown in FIG. 9 are turned off, and the drive video signal AV is not applied to the source bus lines SL1 to SLn. In the gate driver 400, all the switches 43 configured as shown in FIG. 10 are turned off, and the TFT off voltage VGL is applied to all the gate bus lines GL1 to GLm.

<1.3 Configuration and operation of display control circuit>
<1.3.1 Overview>
FIG. 1 is a block diagram showing a configuration of a display control circuit 200 in the present embodiment. The display control circuit 200 includes a host interface unit 21, a video signal output unit 22, a timing generator 23, an operation state inspection unit 24, an operation state storage register 25, a command execution unit 26, and a reset signal output unit 27.

  The host interface unit 21 functions as an interface of the liquid crystal display device when data is transferred between the liquid crystal display device and the external host 900. The host interface unit 21 receives, for example, image data DAT, a timing signal group TG, an operation state confirmation request Req, which will be described later, and a reset command RC from the host 900, and gives an operation state confirmation response Ans, which will be described later, to the host 900. The video signal output unit 22 outputs an analog video signal AV to be supplied to the source driver 300 based on the image data DAT sent from the host 900. The timing generator 23 outputs a start pulse signal SP, a clock signal CK, and the like based on the timing signal group TG sent from the host 900.

  The operation state inspection unit 24 operates the liquid crystal panel 1 based on the output terminal signal OUT as the inspection signal output from the drivers 300 and 400, the start pulse signal SP and the clock signal CK output from the timing generator 23. Determine the state (whether it is operating normally). Then, the operation state inspection unit 24 outputs the determination result as an operation state signal K. The operation state storage register 25 stores the value of the operation state signal K. The command execution unit 26 performs processing on the operation state storage register 25 and the reset signal output unit 27 based on a command from the host interface unit 21.

  By the way, the value stored in the operation state storage register 25 is referred to by the host 900. Specifically, when the host interface unit 21 receives the operation state confirmation request Req from the host 900, the command execution unit 26 reads the value of the operation state storage register 25. The read value is given from the host interface unit 21 to the host 900 as an operation state confirmation response Ans. Thereby, the host 900 can detect the operation state of the liquid crystal panel 1. If the operation state of the liquid crystal panel 1 is abnormal, the host 900 gives a reset command RC to the host interface unit 21.

  The reset signal output unit 27 outputs a reset signal RS based on a command from the command execution unit 26. Specifically, when the host interface unit 21 receives a reset command RC from the host 900, the reset signal output unit 27 changes the logic level of the reset signal RS from a low level to a high level. Thereby, a reset input is given to each of the drivers 300 and 400. On the other hand, when the host interface unit 21 has not received the reset command RC from the host 900, the reset signal output unit 27 maintains the logic level of the reset signal RS at a low level. In the present embodiment, a reset input providing unit is realized by the reset signal output unit 27.

<1.3.2 Configuration and Operation of Operation State Inspection Unit>
As shown in FIG. 1, the operation state inspection unit 24 includes a counter 241 as a clock number counting unit, a timing determination circuit 242 as a timing determination unit, and a latch circuit 243 as an operation state determination unit. Yes.

  The counter 241 resets the internal counter when receiving the pulse of the start pulse signal SP, and adds “1” to the internal counter when receiving the pulse of the clock signal CK (hereinafter referred to as “clock pulse”). In other words, the counter 241 counts the number of clock pulses generated after the start pulse signal SP is generated. The counted number is output from the counter 241 as the count value CNT and is given to the timing determination circuit 242.

  The timing determination circuit 242 receives the count value CNT output from the counter 241 and determines whether the count value CNT is “n + 1”. Specifically, after the start pulse signal SP is generated, if the output terminal signal OUT is at a high level when the 256th clock pulse is generated, it is determined whether the count value CNT is “256” or not. The determination circuit 242 determines. If the count value CNT is “n + 1” as a result of the determination, a pulse of the trigger signal TRG is given from the timing determination circuit 242 to the latch circuit 243. On the other hand, if the count value CNT is not “n + 1”, the trigger signal TRG output from the timing determination circuit 242 is maintained at a low level.

  The latch circuit 243 receives the clock signal CK output from the timing generator 23, the trigger signal TRG output from the timing determination circuit 242, and the output terminal signal OUT output from the drivers 300 and 400, and the operation state of the liquid crystal panel 1 Is output. The value of the operation state signal K is stored in the operation state storage register 25 as described above.

<1.4 Host operation>
Next, the operation of the host 900 in this embodiment will be described. FIG. 11 is a flowchart showing a processing procedure of the host 900 regarding control of the operation state of the liquid crystal panel 1. After starting the operation, the host 900 gives an operation state confirmation request Req, which is a command for confirming the operation state of the liquid crystal panel 1, to the host interface unit 21 (step S110). Thereafter, the host 900 receives an operation state confirmation response Ans indicating the operation state of the liquid crystal panel 1 from the host interface unit 21 (step S120). After step S120 ends, the process proceeds to step S130.

  In step S130, the host 900 determines whether or not the operation state of the liquid crystal panel 1 is normal based on the operation state confirmation response Ans. If the operation state of the liquid crystal panel 1 is normal as a result of the determination, the process returns to step S110. At this time, no specific command is issued from the host 900 to the host interface unit 21. On the other hand, if the operation state of the liquid crystal panel 1 is abnormal, the process proceeds to step S140.

  In step S <b> 140, the host 900 gives a reset command RC to the host interface unit 21. Accordingly, in the display control circuit 200, the reset signal output unit 27 changes the logic level of the reset signal RS from the low level to the high level. As a result, a reset input is given to each driver 300, 400, and the internal state of the logic circuit in each driver 300, 400 is initialized. After step S140 ends, the process returns to step S110.

  As described above, the host 900 confirms (monitors) the operation state of the liquid crystal panel 1 as needed, and if the operation state becomes abnormal, returns the operation state of the drivers 300 and 400 in the liquid crystal panel 1 to a normal state. Therefore, a reset command is given to the liquid crystal display device.

<1.5 Effect>
According to this embodiment, the output terminal signal OUT output from the output terminals of the shift registers 31 and 41 provided in the drivers 300 and 400 that drive the display unit 100 is given to the display control circuit 200. Then, in the display control circuit 200, based on the timing signals (start pulse signal SP and clock signal CK) for controlling the operations of the drivers 300 and 400 and the output terminal signal OUT described above, the operating states of the drivers 300 and 400 are displayed. Is inspected. The inspection result is stored in the operation state storage register 25. The host 900 detects the operation state of the liquid crystal panel 1 by acquiring the inspection result stored in the operation state storage register 25 via the host interface unit 21. If the operation state of the liquid crystal panel 1 is abnormal, the host 900 gives a reset command RC to the liquid crystal display device. The reset signal output unit 27 gives a reset input to the drivers 300 and 400 based on the reset command RC.

  As described above, according to the present embodiment, since the operation state of the drivers 300 and 400 can be confirmed based on the value of the output terminal signal OUT output from the output terminals of the shift registers 31 and 41, it is relatively simple. With this configuration, the operation state of the liquid crystal panel 1 can be inspected. Further, it is not necessary to give a special signal for inspection to the drivers 300 and 400. Therefore, a liquid crystal display device that can initialize the logic circuits in the drivers 300 and 400 when the operation state of the liquid crystal panel 1 becomes abnormal is realized relatively easily.

  Further, a reset input is given to the drivers 300 and 400 based on a reset command RC given from the host 900 to the liquid crystal display device. For this reason, when the operation state of the liquid crystal panel 1 becomes abnormal, the operation state can be returned to a normal state without manual intervention.

<1.6 Modification>
In the above embodiment, the reset input is given to each driver 300, 400 based on the reset command RC from the host 900, but the present invention is not limited to this. The display control circuit 200 that controls the operation of the drivers 300 and 400 determines the operation state of the liquid crystal panel 1 and gives a reset input to the drivers 300 and 400 from the display control circuit 200 without receiving a command from the host 900. May be.

  FIG. 12 is a block diagram showing an overall configuration of a liquid crystal display device according to a modification of the embodiment. In this modification, unlike the embodiment shown in FIG. 1, the operation state storage register 25 is not provided. In this modification, an operation state signal K indicating the operation state of the liquid crystal panel 1 is output from the latch circuit 243 in the operation state inspection unit 24 and input to the reset signal output unit 27. Then, the reset signal output unit 27 outputs a reset signal RS based on the operation state signal K. Specifically, if the operation state signal K indicates that the operation state of the liquid crystal panel 1 is abnormal, the reset signal output unit 27 changes the logic level of the reset signal RS from a low level to a high level. Thereby, a reset input is given to each driver 300,400. On the other hand, if the operation state signal K indicates that the operation state of the liquid crystal panel 1 is normal, the reset signal output unit 27 maintains the logic level of the reset signal RS at a low level.

  FIG. 13 is a flowchart showing a processing procedure of the display control circuit 200 related to the control of the operation state of the liquid crystal panel 1 in this modification. The following steps are processes performed by the reset signal output unit 27. After starting the operation of the liquid crystal display device, the reset signal output unit 27 receives an operation state signal K indicating the operation state of the liquid crystal panel 1 (step S210). Thereafter, the reset signal output unit 27 determines whether or not the operation state of the liquid crystal panel 1 is normal based on the value of the operation state signal K (step S220). If the operation state of the liquid crystal panel 1 is normal as a result of the determination, the process returns to step S210. On the other hand, if the operation state of the liquid crystal panel 1 is abnormal, the process proceeds to step S230. In step S230, the reset signal output unit 27 changes the logic level of the reset signal RS from the low level to the high level. As a result, a reset input is given to each driver 300, 400, and the internal state of the logic circuit in each driver 300, 400 is initialized. After step S230 ends, the process returns to step S210.

  As described above, in this modification, the operation state of the liquid crystal panel 1 is confirmed (monitored) as needed by the display control circuit 200 that controls the operation of the drivers 300 and 400. If the operation state of the liquid crystal panel 1 becomes abnormal, the display control circuit 200 gives a reset command to each of the drivers 300 and 400 without receiving a command from the host 900.

<1.7 Others>
In the above embodiment, the internal state of the logic circuit in the drivers 300 and 400 is initialized when the operation state of the liquid crystal panel 1 becomes abnormal. However, the present invention is not limited to this. . For example, instead of the initialization, the power supply of the liquid crystal panel 1 can be stopped.

<2. Second Embodiment>
<2.1 Overall configuration>
Next, a second embodiment of the present invention will be described. FIG. 14 is a block diagram showing the overall configuration of the monolithic CG silicon liquid crystal display device according to this embodiment. This liquid crystal display device includes a liquid crystal panel 1 and a display control circuit 200. Since the configuration of the liquid crystal panel 1 is the same as that of the first embodiment, description thereof is omitted.

  As shown in FIG. 14, the display control circuit 200 includes a host interface unit 21, a video signal output unit 22, a timing generator 23, and a reset signal output unit 27. The host interface unit 21 functions as an interface of the liquid crystal display device when data is transferred between the liquid crystal display device and the external host 900. The video signal output unit 22 outputs an analog video signal AV to be supplied to the source driver 300 based on the image data DAT sent from the host 900. The timing generator 23 outputs a start pulse signal SP, a clock signal CK, a reset timing signal RTG, and the like based on the timing signal group TG sent from the host 900.

  The reset signal output unit 27 generates a source reset signal SRS for initializing the internal state of the logic circuit in the source driver 300 based on the reset timing signal RTG output from the timing generator 23, and the logic in the gate driver 400. A gate reset signal GRS for initializing the internal state of the circuit is output.

<2.2 Reset input timing>
Next, timing when reset input is given to the source driver 300 and the gate driver 400 will be described. FIG. 15 is a signal waveform diagram for explaining a method of driving the source driver 300 and the gate driver 400. Each signal waveform shown in FIG. 15 is a signal waveform in a general liquid crystal display device including the liquid crystal display device according to the present embodiment.

  As shown in FIG. 15A, the pulse of the gate start pulse signal GSP is generated every one vertical scanning period which is a period during which an image for one screen is displayed. In addition, as shown in FIG. 15B, each vertical scanning period includes a vertical blanking period, and one gate bus line of each vertical scanning period is a period other than the vertical blanking period. A pulse of the gate clock signal GCK is generated every horizontal scanning period, which is a period during which scanning is performed. Further, as shown in FIG. 15C, a pulse of the source start pulse signal SSP is generated every horizontal scanning period. Furthermore, as shown in FIG. 15D, each horizontal scanning period includes a horizontal blanking period, and one source bus line is included in each horizontal scanning period other than the horizontal blanking period. A pulse of the source clock signal SCK is generated at every timing when the drive video signal is applied to.

  FIG. 16 is a signal waveform diagram for explaining the timing at which a reset input is given to the source driver 300. As described above, each horizontal scanning period includes a horizontal blanking period. In this embodiment, as shown in FIG. 16C, the logic level of the source reset signal SRS is set during the horizontal blanking period. Change from low level to high level. That is, a reset input is given to the source driver 300 during the horizontal blanking period.

  FIG. 17 is a signal waveform diagram for explaining the timing at which a reset input is given to the gate driver 400. As described above, each vertical scanning period includes a vertical blanking period. In this embodiment, as shown in FIG. 17C, the logic level of the gate reset signal GRS is set during the vertical blanking period. Change from low level to high level. That is, a reset input is given to the gate driver 400 during the vertical blanking period.

<2.3 Effects>
According to the present embodiment, the source driver 300 is given a reset input during each horizontal blanking period, and the gate driver 400 is given a reset input during each vertical blanking period. Therefore, regardless of whether the operation state of the panel is normal or abnormal, the logic circuit in the source driver 300 is initialized in each horizontal blanking period, and the logic in the gate driver 400 in each vertical blanking period. The circuit is initialized. Here, during each horizontal blanking period, pulses of the source start pulse signal SSP and the source clock signal SCK supplied to the source driver 300 do not occur. For this reason, the source driver 300 is stopped during the horizontal blanking period, and even if a reset input is given to the source driver 300 during the period, the image display is not affected. Further, the gate start pulse signal GSP and the gate clock signal GCK that are supplied to the gate driver 400 are not generated in each vertical blanking period. Therefore, the gate driver 400 is stopped during the vertical blanking period, and even if a reset input is given to the gate driver 400 during the period, the image display is not affected.

  As described above, when the operation state of the panel becomes abnormal, the logic circuit in the driver is initialized during the blanking period, so that the operation state is returned to the normal state without any manual intervention. Further, there is no display abnormality caused by the initialization of the logic circuit in the drivers 300 and 400 during each blanking period.

  Since not only the gate driver 400 but also the source driver 300 is stopped during the vertical blanking period, a configuration may be adopted in which a reset input is given to the gate driver 400 and the source driver 300 during the vertical blanking period.

<2.4 Modification>
Although the second embodiment has been described on the assumption that image display is performed on the entire display unit 100, the present invention is not limited to this. The present invention can also be applied when an image is displayed on a part of the display unit 100 (hereinafter referred to as “partial display”). The partial display is a display method performed when, for example, a standby screen is displayed on a mobile phone, and an image is displayed only in a partial area (drawing area) of the entire display unit 100 as shown in FIG. This is a display method in which display is performed and image display is not performed in other regions (non-drawing regions).

  19 to 21 are signal waveform diagrams for explaining a method of driving the source driver 300 and the gate driver 400 when partial display is performed in the liquid crystal display device. When the partial display is performed, as in the case where the image display is performed on the entire display unit 100, as shown in FIG. 19A, the pulse of the gate start pulse signal GSP is generated every one vertical scanning period. As shown in FIG. 19B, a pulse of the gate clock signal GCK is generated every horizontal scanning period in each vertical scanning period other than the vertical blanking period. Here, for example, a display control signal CTL having a waveform as shown in FIG. During the period when the logical level of the display control signal CTL is high, as shown in FIG. 20A, the pulse of the source start pulse signal SSP is generated every one horizontal scanning period, as shown in FIG. As shown, a pulse of the source clock signal SCK occurs in a period other than the horizontal blanking period in each horizontal scanning period. On the other hand, during the period when the logic level of the display control signal CTL is low, the pulses of the source start pulse signal SSP and the source clock signal SCK are as shown in FIGS. 21 (a) and (b). Does not occur.

  In the present modification, the source driver 300 can be given a reset input during any one of the non-drawing period, the horizontal blanking period, and the vertical blanking period. Further, similarly to the second embodiment, the gate driver 400 can be given a reset input during the vertical blanking period.

<3. Other>
In each of the above embodiments, the example in which the drivers 300 and 400 are included in the liquid crystal panel 1 has been described, but the present invention is not limited to this. The present invention can also be applied to a liquid crystal display device in which the drivers 300 and 400 are arranged outside the liquid crystal panel 1. In each of the above embodiments, the liquid crystal display device has been described as an example, but the present invention is not limited to this. The present invention can also be applied to other display devices such as organic EL (Electro Luminescnet).

1 is a block diagram illustrating a configuration of a display control circuit in a liquid crystal display device according to a first embodiment of the present invention. In the said 1st Embodiment, it is a block diagram which shows the whole structure of a CG silicon | silicone liquid crystal display device. FIG. 3 is a block diagram illustrating a schematic configuration of a source driver in the first embodiment. FIG. 3 is a block diagram illustrating a schematic configuration of a gate driver in the first embodiment. FIG. 3 is a block diagram showing a configuration of a shift register in the first embodiment. FIG. 6 is a signal waveform diagram for describing the operation of the shift register in the first embodiment. FIG. 6 is a diagram for explaining the operation of the shift register in the first embodiment. In the said 1st Embodiment, it is a figure for demonstrating reset input. FIG. 6 is a diagram for describing an operation of the source driver when a reset input is given to the source driver in the first embodiment. FIG. 6 is a diagram for explaining an operation of the gate driver when a reset input is given to the gate driver in the first embodiment. 5 is a flowchart illustrating a processing procedure of a host related to control of an operation state of a liquid crystal panel in the first embodiment. It is a block diagram which shows the whole structure of the liquid crystal display device in the modification of the said 1st Embodiment. It is a flowchart which shows the process sequence of the display control circuit regarding control of the operation state of the liquid crystal panel in the said modification. It is a block diagram which shows the whole structure of the CG silicon liquid crystal display device which concerns on the 2nd Embodiment of this invention. In the said 2nd Embodiment, it is a signal waveform diagram for demonstrating the drive method of a source driver and a gate driver. In the said 2nd Embodiment, it is a signal waveform diagram for demonstrating the timing which gives a reset input to a source driver. In the said 2nd Embodiment, it is a signal waveform diagram for demonstrating the timing which gives a reset input to a gate driver. It is a figure for demonstrating a partial display. It is a signal waveform diagram for demonstrating the drive method at the time of performing a partial display with a liquid crystal display device. FIG. 6 is a signal waveform diagram during a drawing period when partial display is performed in the liquid crystal display device. FIG. 6 is a signal waveform diagram during a non-drawing period when partial display is performed in the liquid crystal display device. It is a figure for demonstrating a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal panel 21 ... Host interface part 22 ... Video signal output part 23 ... Timing generator 24 ... Operation state inspection part 25 ... Operation state storage register 26 ... Command execution part 27 ... Reset signal output part 31, 41 ... Shift register 100 ... Display unit 200 ... display control circuit 300 ... source driver (video signal line drive circuit)
400: Gate driver (scanning signal line driving circuit)
900 ... Host R1-Rn ... Register CK ... Clock signal SP ... Start pulse signal OUT ... Output terminal signal RC ... Reset command RS ... Reset signal

Claims (21)

A display for displaying an image;
A plurality of signal lines arranged in the display unit;
A driving circuit for driving the plurality of signal lines, a plurality of logic circuits storing values for determining whether to drive the plurality of signal lines, respectively, and a predetermined reset input; A drive circuit having logic circuit initialization means for initializing values stored in the plurality of logic circuits;
An operation state inspection unit that determines whether the operation state of the drive circuit is normal or abnormal based on a predetermined test signal output from the drive circuit;
A display device comprising: a reset input providing unit that provides the reset input to the drive circuit when the operation state inspecting unit determines that the operation state of the drive circuit is abnormal. The drive circuit includes a shift register that includes the plurality of logic circuits and sequentially shifts a predetermined pulse from an input terminal to an output terminal based on a predetermined timing signal, and the predetermined circuit starts from the output terminal of the shift register. Is output as the inspection signal,
The operation state inspection unit determines whether the operation state of the drive circuit is normal or abnormal based on the timing signal and the inspection signal. Display device.   The timing signal provides the shift register with a start pulse signal for applying the predetermined pulse to the shift register and a clock pulse for sequentially shifting the predetermined pulse from the input end to the output end of the shift register. The display device according to claim 2, wherein the display device comprises a clock signal. The operating state inspection unit
A clock number counting unit that counts the number of clock pulses of the clock signal from the time when the predetermined pulse is applied to the input terminal of the shift register by the start pulse signal;
A timing determination unit that determines whether or not the predetermined pulse is output from the output terminal of the shift register based on the number of clock pulses counted by the clock number counting unit;
The drive circuit receives the inspection signal, and based on the value of the inspection signal when the timing determination unit determines that the predetermined pulse is output from the output terminal of the shift register, The display device according to claim 3, further comprising an operation state determination unit that determines whether or not the device is operating normally.   5. The display device according to claim 1, wherein the drive circuit includes a thin film transistor using continuous grain boundary crystalline silicon. 6. It further includes an interface unit that transmits and receives data to and from the outside.
The said reset input provision part gives the said reset input to the said drive circuit, when the said interface part receives the predetermined reset command from the outside, The any one of Claim 1-5 characterized by the above-mentioned. The display device described. An electronic apparatus comprising the display device according to claim 6 and a host device connected to the display device,
The host device receives a determination result from the operation state inspection unit from the interface unit, and gives the reset command to the interface unit if the determination result indicates that the operation state of the drive circuit is abnormal. An electronic device characterized by that. An electronic device comprising a display device and a host device,
The display device
A display for displaying an image;
A plurality of signal lines arranged in the display unit;
A drive circuit for driving the plurality of signal lines;
An operation state inspection unit that determines whether the operation state of the drive circuit is normal or abnormal based on a predetermined test signal output from the drive circuit;
An interface unit for transmitting and receiving data to and from the host device;
A host command execution unit that executes a command given from the host device via the interface unit, the host device receives a determination result by the operation state inspection unit from the interface unit, and the determination result is the drive circuit An electronic device, wherein a predetermined command is given to the interface unit if the operation state of the device indicates an abnormal state. A display for displaying an image;
A plurality of signal lines arranged in the display unit;
A driving circuit for driving the plurality of signal lines, a plurality of logic circuits storing values for determining whether to drive the plurality of signal lines, respectively, and a predetermined reset input; A drive circuit having logic circuit initialization means for initializing values stored in the plurality of logic circuits;
A display device, comprising: a reset input providing unit that applies the reset input to the drive circuit during a predetermined period and during a period in which the drive circuit is stopped. The plurality of signal lines include a plurality of video signal lines for transmitting a plurality of video signals representing the image, and a plurality of scanning signal lines intersecting the plurality of video signal lines,
The driving circuit includes a video signal line driving circuit for driving the plurality of video signal lines, and a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines,
The reset input giving unit is
Applying the reset input to the video signal line driving circuit during a horizontal blanking period,
The display device according to claim 9, wherein the reset input is supplied to the scanning signal line driving circuit during a vertical blanking period. The plurality of signal lines include a plurality of video signal lines for transmitting a plurality of video signals representing the image, and a plurality of scanning signal lines intersecting the plurality of video signal lines,
The driving circuit includes a video signal line driving circuit for driving the plurality of video signal lines, and a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines,
10. The display device according to claim 9, wherein the reset input applying unit supplies the reset input to the video signal line driving circuit and the scanning signal line driving circuit during a vertical blanking period. A partial display function for displaying an image only in a partial area of the display unit;
When the image input by the partial display function is being performed, the reset input providing unit is configured so that the scanning signal line disposed in a region where no image is displayed in the display unit is selected. The display device according to claim 10, wherein a reset input is given to the video signal line driving circuit. A plurality of logic circuits for driving a plurality of signal lines arranged in a display unit for displaying an image and storing values for determining whether or not each of the plurality of signal lines is driven A control method for a display device comprising a drive circuit having
A logic circuit initialization step for initializing values stored in the plurality of logic circuits based on a predetermined reset input given to the drive circuit;
An operation state inspection step for determining whether the operation state of the drive circuit is normal or abnormal based on a predetermined test signal output from the drive circuit;
A control method comprising: a reset input providing step of providing the reset input to the drive circuit when it is determined in the operation state inspection step that the operation state of the drive circuit is abnormal. The drive circuit includes a shift register that includes the plurality of logic circuits and sequentially shifts a predetermined pulse from an input terminal to an output terminal based on a predetermined timing signal, and the predetermined circuit starts from the output terminal of the shift register. Are output as the inspection signal,
The operation state inspection step determines whether the operation state of the drive circuit is normal or abnormal based on the timing signal and the inspection signal. Control method.   The timing signal provides the shift register with a start pulse signal for applying the predetermined pulse to the shift register and a clock pulse for sequentially shifting the predetermined pulse from the input end to the output end of the shift register. The control method according to claim 14, further comprising: The operation state inspection step includes:
A clock number counting step for counting the number of clock pulses of the clock signal from the time when the predetermined pulse is applied to the input terminal of the shift register by the start pulse signal;
A timing determination step of determining whether or not the predetermined pulse is output from the output terminal of the shift register based on the number of clock pulses counted in the clock number counting step;
The drive circuit receives the inspection signal, and based on the value of the inspection signal when the timing determination step determines that the predetermined pulse is output from the output terminal of the shift register, The control method according to claim 15, further comprising an operation state determination step of determining whether or not the device is operating normally.   The reset input is given to the drive circuit in the reset input giving step when an interface unit that transmits / receives data to / from the outside receives a predetermined reset command from the outside. The control method according to any one of 13 to 16. A plurality of logic circuits for driving a plurality of signal lines arranged in a display unit for displaying an image and storing values for determining whether or not each of the plurality of signal lines is driven A control method for a display device comprising a drive circuit having
A logic circuit initialization step for initializing values stored in the plurality of logic circuits based on a predetermined reset input given to the drive circuit;
And a reset input applying step of applying the reset input to the drive circuit during a predetermined period and during a period in which the drive circuit is stopped. The plurality of signal lines include a plurality of video signal lines for transmitting a plurality of video signals representing the image, and a plurality of scanning signal lines intersecting the plurality of video signal lines,
The driving circuit includes a video signal line driving circuit for driving the plurality of video signal lines, and a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines,
In the reset input giving step,
The reset input is given to the video signal line driving circuit during a horizontal blanking period,
19. The control method according to claim 18, wherein the reset input is supplied to the scanning signal line driving circuit during a vertical blanking period. The plurality of signal lines include a plurality of video signal lines for transmitting a plurality of video signals representing the image, and a plurality of scanning signal lines intersecting the plurality of video signal lines,
The driving circuit includes a video signal line driving circuit for driving the plurality of video signal lines, and a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines,
19. The control method according to claim 18, wherein in the reset input giving step, the reset input is given to the video signal line driving circuit and the scanning signal line driving circuit during a vertical blanking period. A partial display step of displaying an image only in a partial region of the display unit;
When image display is performed in the partial display step, the reset input is applied in the reset input applying step during a period in which a scanning signal line disposed in a region where no image is displayed in the display unit is selected. 21. The control method according to claim 19, wherein an input is given to the video signal line driving circuit.

Images