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JP2009010213A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device Download PDF

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Publication number
JP2009010213A
JP2009010213A JP2007170851A JP2007170851A JP2009010213A JP 2009010213 A JP2009010213 A JP 2009010213A JP 2007170851 A JP2007170851 A JP 2007170851A JP 2007170851 A JP2007170851 A JP 2007170851A JP 2009010213 A JP2009010213 A JP 2009010213A
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metal substrate
conductive pattern
hybrid integrated
integrated circuit
resin layer
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JP2007170851A
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Inventor
Yukinao Sakuma
幸直 佐久間
Junichi Ichihashi
純一 市橋
Hiroyuki Kataoka
弘行 片岡
Toshiyuki Iimura
敏之 飯村
Shinichi Tsuyuki
真一 露木
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Sanyo Electric Co Ltd
System Solutions Co Ltd
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Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
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Priority to JP2007170851A priority Critical patent/JP2009010213A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of size bulkiness of a hybrid IC device using a metal substrate with the backside of the metal substrate exposed and a heat radiating film provided on the exposed surface. <P>SOLUTION: A desired circuit is achieved by providing a first circuit element group on the surface of a metal substrate 13, and a second circuit element group on the backside of the metal substrate. The surface and backside coating resins, and the side covering resin are formed integrally with a transfer mold. A third arrangement region B on the backside has the substrate backside exposed with a heat radiating film 21 provided therein. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、混成集積回路装置に関するものである。   The present invention relates to a hybrid integrated circuit device.

CuやAlを主材料として形成された金属基板は、放熱性に優れるため混成集積回路装置として採用されている。例えば、パワー系のデバイスは、デバイス自体が温度上昇し、駆動能力が低下するが、金属基板を採用することにより温度上昇を抑止でき、結局は、その分、エネルギー損失を抑えながら、駆動能力を向上できるため、電力の削減、環境負荷の低減が可能となる。   A metal substrate formed using Cu or Al as a main material is adopted as a hybrid integrated circuit device because of its excellent heat dissipation. For example, power-related devices increase the temperature of the device itself and drive capacity decreases, but by adopting a metal substrate, the temperature rise can be suppressed, and eventually, the drive capacity is reduced while suppressing energy loss. Therefore, it is possible to reduce electric power and environmental load.

図6に、その一例を示す。例えばAl基板1があり、その両面にはアルマイト処理されてなる酸化膜2が形成されている。そして基板1の表面には、絶縁樹脂層3が更に被覆され、その上に配線パターン4が設けられている。この配線パターン4は、アイランド、配線、電極パッド、リードパッド等からなる。そして前記アイランドの上には、半導体素子5が固着され、半導体素子5の電極と前記電極パッドとは、金属細線を介して電気的に接続されている。更には、受動素子としてチップコンデンサやチップ抵抗が電極パッドと半田付けされている。   An example is shown in FIG. For example, there is an Al substrate 1, and an oxide film 2 formed by alumite treatment is formed on both surfaces thereof. The surface of the substrate 1 is further covered with an insulating resin layer 3, and a wiring pattern 4 is provided thereon. The wiring pattern 4 includes islands, wirings, electrode pads, lead pads, and the like. The semiconductor element 5 is fixed on the island, and the electrode of the semiconductor element 5 and the electrode pad are electrically connected through a fine metal wire. Further, chip capacitors and chip resistors are soldered to the electrode pads as passive elements.

よって半導体素子、受動素子および配線パターン4により混成集積回路が実現される。また必要によりリードパッドにリードが接続され、全体が絶縁樹脂6で封止されて完成される。   Therefore, a hybrid integrated circuit is realized by the semiconductor element, the passive element, and the wiring pattern 4. Further, if necessary, the lead is connected to the lead pad, and the whole is sealed with the insulating resin 6 to be completed.

関連した技術文献としては、例えば以下の特許文献が挙げられる。
特開2003−318333号公報
Examples of related technical literatures include the following patent literatures.
JP 2003-318333 A

しかしながら放熱性を向上しようとすれば、放熱フィン7が金属基板1の裏面に実装されている。   However, in order to improve heat dissipation, the heat dissipation fins 7 are mounted on the back surface of the metal substrate 1.

これは、金属基板1の裏面は、アルマイト面またはアルマイトが取り除かれたAl面が露出しているため、放熱フィン7を取り付ければ、金属基板1の上に載置された半導体素子5の温度上昇を抑止できる。   This is because the alumite surface or the Al surface from which the alumite has been removed is exposed on the back surface of the metal substrate 1, so that if the radiation fins 7 are attached, the temperature rise of the semiconductor element 5 placed on the metal substrate 1 Can be suppressed.

しかしながら、図5に示すように、放熱フィン7が金属基板1(図面では点線で示す)裏面全体を覆うように大きいため、混成集積回路装置自体のサイズが大きくなり、この混成集積回路装置が実装されるセット8自体の小型化ができない問題を有している。   However, as shown in FIG. 5, since the radiation fins 7 are large so as to cover the entire back surface of the metal substrate 1 (shown by dotted lines), the size of the hybrid integrated circuit device itself increases, and this hybrid integrated circuit device is mounted. The set 8 itself cannot be reduced in size.

更には、金属基板1の裏面が露出するタイプは、金属基板1と絶縁樹脂6の熱膨張係数αの違いにより、裏面において金属基板と絶縁樹脂6との界面が剥離し、湿気等の浸入から信頼性が低下する問題もあった。   Further, in the type in which the back surface of the metal substrate 1 is exposed, the interface between the metal substrate and the insulating resin 6 is peeled off on the back surface due to the difference in the thermal expansion coefficient α between the metal substrate 1 and the insulating resin 6, and moisture and the like enter. There was also a problem that reliability was lowered.

上記に鑑み、本発明の混成集積回路装置は、
第1に、表面、裏面および側面を有する金属基板と、
前記表面を被覆する第1の絶縁樹脂層と、前記裏面の一領域を被覆する第2の絶縁樹脂層と、
前記第1の絶縁樹脂層に設けられた第1の導電パターンと、前記第2の絶縁樹脂層に設けられた第2の導電パターンと、
前記第1の導電パターンと電気的に接続され、固着された複数の第1の回路素子と、
前記第2の導電パターンと電気的に接続され、固着された複数の第2の回路素子と、
前記第1の導電パターンと前記第2の導電パターンを電気的に接続し、前記金属基板の側面をまたいで設けられるリードと、
前記第1の回路素子を被覆する第1の被覆樹脂と、前記第2の回路素子を被覆する第2の被覆樹脂とから成る事で解決するものである。
裏面は、放熱フィンと第2の回路素子が実装されるため、実装効率が向上する。
In view of the above, the hybrid integrated circuit device of the present invention is
First, a metal substrate having a front surface, a back surface and side surfaces;
A first insulating resin layer covering the surface; a second insulating resin layer covering a region of the back surface;
A first conductive pattern provided on the first insulating resin layer; a second conductive pattern provided on the second insulating resin layer;
A plurality of first circuit elements electrically connected and fixed to the first conductive pattern;
A plurality of second circuit elements electrically connected and fixed to the second conductive pattern;
A lead that electrically connects the first conductive pattern and the second conductive pattern and is provided across a side surface of the metal substrate;
The problem is solved by comprising a first coating resin for coating the first circuit element and a second coating resin for coating the second circuit element.
Since the heat radiation fin and the second circuit element are mounted on the back surface, the mounting efficiency is improved.

第2に、前記被覆樹脂は、トランスファーモールドにより被覆される事で解決するものである。
第3に、前記第1の被覆樹脂と前記第2の被覆樹脂は、前記側面を介して一体で成る事で、金属基板を表と裏で挟むことに成り、反りの抑制が可能である。
Second, the coating resin is solved by being coated with a transfer mold.
Third, the first coating resin and the second coating resin are integrated with each other through the side surface, so that the metal substrate is sandwiched between the front and the back, and warpage can be suppressed.

第4に、前記裏面の他方の領域には、放熱フィンが取り付けられることで解決するものである。
第5に、前記金属基板が垂直配置され、この垂直配置の金属基板の下方に前記第2の被覆樹脂が位置し、上方に前記放熱フィンが位置する事で解決するものである。
Fourthly, the problem is solved by attaching a radiation fin to the other region of the back surface.
Fifth, the metal substrate is arranged vertically, the second coating resin is located below the vertically arranged metal substrate, and the heat dissipating fin is located above.

フィンから放出される熱は、上昇するため、この上昇するパスに回路素子が配置されないため、温度の影響を抑制することができる。   Since the heat released from the fins rises, the circuit element is not arranged in this rising path, so that the influence of temperature can be suppressed.

金属基板の表裏面に回路素子と放熱フィンが取り付けられるため、実装密度の高い混成集積回路装置を実現できる。   Since circuit elements and heat radiation fins are attached to the front and back surfaces of the metal substrate, a hybrid integrated circuit device having a high mounting density can be realized.

また混成集積回路装置を立てて実装すると、裏面には、下方に回路素子、上には放熱フィンが配置され、放熱フィンから出てきる熱は、回路素子を通過せずに上昇するため、温度の影響を抑制することができる。   When a hybrid integrated circuit device is mounted upright, a circuit element is disposed on the lower surface and a heat radiation fin is disposed on the back surface. The heat generated from the heat radiation fin rises without passing through the circuit element. The influence of can be suppressed.

またトランスファーモールドで表と裏を一体で封止するので、実質同じ熱膨張係数でサンドウィッチした形と成り、反りの抑止が働く。よって金属基板裏面において、絶縁樹脂と金属基板の界面が有っても、剥離を抑止することができる。   In addition, since the front and back surfaces are integrally sealed with a transfer mold, the shape is sandwiched with substantially the same thermal expansion coefficient, and warpage is suppressed. Therefore, even if there is an interface between the insulating resin and the metal substrate on the rear surface of the metal substrate, peeling can be suppressed.

以下、本発明の最良の形態を説明する。   Hereinafter, the best mode of the present invention will be described.

図1(A)は、混成集積回路装置10がプリント基板等の実装基板11に装着されたもので、一般にはモジュール12と呼ばれている。   FIG. 1A shows a hybrid integrated circuit device 10 mounted on a mounting board 11 such as a printed board, and is generally called a module 12.

まずは、混成集積回路装置10について説明する。まず基板13は、Cu、AlまたはFeを主材料とした金属基板である。必要によっては、ステンレス等の合金でも良い。   First, the hybrid integrated circuit device 10 will be described. First, the substrate 13 is a metal substrate whose main material is Cu, Al or Fe. If necessary, an alloy such as stainless steel may be used.

例えばAl基板を金属基板13として採用した場合、一般には、絶縁耐量、耐摩耗性が考慮されて、表面にはアルマイト処理または酸化処理が施される。しかもこの酸化膜は、更に積層される絶縁樹脂層14との密着性も良好である。ただし、酸化膜の無いAl面に直接絶縁樹脂層13を積層しても良い。   For example, when an Al substrate is employed as the metal substrate 13, in general, the surface is subjected to alumite treatment or oxidation treatment in consideration of insulation resistance and wear resistance. Moreover, this oxide film also has good adhesion to the insulating resin layer 14 to be further laminated. However, you may laminate | stack the insulating resin layer 13 directly on Al surface without an oxide film.

この酸化膜の形成された金属基板13は、大板からプレスにより固片化されるため、平面で見ると矩形で、表と裏の周囲から延在される4つの側面は、Al金属が露出される。   The metal substrate 13 on which the oxide film is formed is solidified by pressing from a large plate, so that it is rectangular when viewed in plan, and the four side surfaces extending from the front and back periphery are exposed to Al metal. Is done.

一方、Cuの場合、酸化膜は、Alの酸化膜と比較して、自分自身の金属との密着性が悪いため、実質形成されない。   On the other hand, in the case of Cu, the oxide film is not substantially formed because it has poor adhesion to its own metal compared to the Al oxide film.

この金属基板13の表面には、導電パターンの絶縁性が考慮されて、前述した絶縁樹脂層14が被覆される。この絶縁樹脂層14は、耐圧、熱膨張係数α等が考慮されて一般には、Si、Al2O3等のフィラーが選択されて混ぜられたり、ガラス繊維等が織り込まれている。   The surface of the metal substrate 13 is covered with the insulating resin layer 14 described above in consideration of the insulation of the conductive pattern. The insulating resin layer 14 is generally selected and mixed with fillers such as Si and Al2O3 in consideration of pressure resistance, thermal expansion coefficient α, and the like, or glass fibers and the like are woven.

ここで金属基板13の表面に被覆された絶縁樹脂層を第1の絶縁樹脂層14F、裏面に被覆された絶縁樹脂層を第2の絶縁樹脂層14Bとする。   Here, the insulating resin layer coated on the surface of the metal substrate 13 is referred to as a first insulating resin layer 14F, and the insulating resin layer coated on the back surface is referred to as a second insulating resin layer 14B.

前記第1の絶縁樹脂層14Fには、第1の導電パターン15Fが設けられている。この導電パターン15Fは、一般にはCuから成り、接着剤の設けられた全面Cu箔が熱圧着により貼り合わされた後に、エッチングにより所望のパターンに形成される。ただし、導電ペーストをスクリーン印刷で印刷し、導電パターンを形成しても良い。   A first conductive pattern 15F is provided on the first insulating resin layer 14F. The conductive pattern 15F is generally made of Cu, and is formed into a desired pattern by etching after the entire surface Cu foil provided with an adhesive is bonded by thermocompression bonding. However, the conductive paste may be printed by screen printing to form a conductive pattern.

一方、前記第2の絶縁樹脂層14Bも、第1の絶縁樹脂層14Fと同様な材料を用いて貼り合わされ、同じ方法にて導電パターン15Bが形成される。   On the other hand, the second insulating resin layer 14B is also bonded using the same material as the first insulating resin layer 14F, and the conductive pattern 15B is formed by the same method.

これら第1および第2の導電パターン14は、アイランド16、電極パッド17、前記アイランドまたは電極パッドと一体またはアイランド状の配線、受動素子を実装するための電極18、リード用パッド19等が設けられる。   These first and second conductive patterns 14 are provided with an island 16, an electrode pad 17, a wiring integral with the island or the electrode pad or an island shape, an electrode 18 for mounting a passive element, a lead pad 19, and the like. .

更に、アイランド16には、半導体素子20が固着され、半導体素子の表面に設けられたパッド電極と電極パッド17とは、金属細線を介して電気的に接続されている。ここで半導体素子としては、ディスクリート型半導体素子、LSI等が考えられる。ここで金属基板13の表側に配置されるこれらの素子を第1の回路素子群と呼び、表側の実質全面を第1の配置領域とする。さらに基板13の裏面に配置される能動素子、受動素子を第2の回路素子群と呼び、これら第2の回路素子群が配置される領域を第2の配置領域と呼ぶ。更に、放熱フィン21の配置領域を第3の配置領域とする。   Furthermore, the semiconductor element 20 is fixed to the island 16, and the pad electrode provided on the surface of the semiconductor element and the electrode pad 17 are electrically connected through a fine metal wire. Here, as the semiconductor element, a discrete semiconductor element, an LSI, or the like can be considered. Here, these elements arranged on the front side of the metal substrate 13 are referred to as a first circuit element group, and a substantially entire surface on the front side is defined as a first arrangement region. Furthermore, the active element and the passive element arranged on the back surface of the substrate 13 are referred to as a second circuit element group, and the region in which these second circuit element groups are arranged is referred to as a second arrangement region. Furthermore, let the arrangement | positioning area | region of the radiation fin 21 be a 3rd arrangement | positioning area | region.

後述する放熱フィン21の設置部分に対応する金属基板13の表面には、パワー系の半導体素子22が実装される。これは、放熱フィン21を介して、パワー系の半導体素子22の熱を外部に放出し、半導体素子22自体の発熱を抑止している。これにより駆動能力が高められ、無駄な電力を省くことができる。一例としては、パワー系のディスクリート素子、パワーMOS、パワーTR、IGBT、GTBT、パワー系のLSI等が考えられる。   A power-type semiconductor element 22 is mounted on the surface of the metal substrate 13 corresponding to an installation portion of the radiating fins 21 described later. This releases the heat of the power semiconductor element 22 to the outside through the heat radiation fin 21 and suppresses the heat generation of the semiconductor element 22 itself. As a result, the driving capability is increased, and wasteful power can be saved. As an example, a power system discrete element, a power MOS, a power TR, an IGBT, a GTBT, a power system LSI, or the like can be considered.

別の表現をすれば、第1の回路素子群は、放熱器を必要とする回路素子、例えば前述したパワー系の半導体素子、そして放熱器を必要としない回路素子、例えば制御回路、保護回路、受動素子等に区分けできる。   In other words, the first circuit element group includes circuit elements that require a radiator, such as the power semiconductor elements described above, and circuit elements that do not require a radiator, such as a control circuit, a protection circuit, It can be divided into passive elements.

一方、本混成集積回路装置10は、図1の如く、実装基板11に対して縦差しで実装されるため、この熱的な事を考慮して配置させる必要がある。   On the other hand, the hybrid integrated circuit device 10 is mounted vertically with respect to the mounting substrate 11 as shown in FIG.

つまり放熱フィン21の温められた気体のルートにより好ましい配置が決定される。ここで放熱フィン21は、図1(A)では、溝23が紙面に対して表から裏に走っているように図示されているが、これは、図1(A)に於いて放熱フィンである事を示したいために書いたものである。実際は、図4の様に配置される。これは、例えば、プラズマTV、液晶TVの背面を開け、そこに見える金属のシャーシーSHの上に配置される。つまりシャーシーSHは、矢印の基点が下、矢印の先が上方を向き、床に対して垂直に配置されたもの手である。図からも明らかなように、溝23が紙面に対して下から上に走っている。この方が、空気が、矢印の様に、下から上に流れ方熱効率が高いからである。   That is, a preferable arrangement is determined by the route of the heated gas of the radiating fins 21. Here, the radiating fin 21 is shown in FIG. 1A so that the groove 23 runs from the front to the back with respect to the paper surface. This is the radiating fin in FIG. I wrote this to show you something. Actually, they are arranged as shown in FIG. For example, the rear surface of the plasma TV or the liquid crystal TV is opened and placed on the metal chassis SH that can be seen there. That is, the chassis SH is a hand that is arranged perpendicular to the floor, with the base point of the arrow pointing downward and the tip of the arrow pointing upward. As is apparent from the drawing, the groove 23 runs from the bottom to the top with respect to the paper surface. This is because air flows from the bottom to the top as indicated by the arrows, and the heat efficiency is high.

この構造であれば、当然下の空気が放熱フィン21で暖められ、その暖められた空気は、そのまま上昇する。よって空気が暖められて上昇する側に回路素子が配置されれば、回路素子の温度上昇を招くが、本発明は、逆である。   If it is this structure, naturally the lower air is warmed by the radiation fin 21, and the warmed air rises as it is. Therefore, if the circuit element is arranged on the side where the air is warmed and raised, the temperature of the circuit element is increased, but the present invention is reversed.

また混成集積回路装置10が実装基板11に対して、縦ざし(垂直配置)された場合、放熱フィン21は、金属基板裏面の上側に配置される。金属基板の周囲には、マージンが設けられたりするため。金属基板の裏面は、第2の配置領域と放熱フィン21の第3の配置領域で100%占める訳ではないが、第2の回路素子配置領域と放熱フィン21の配置領域でほぼ2分できる。
よって、図1(B)左の如く、第2の配置領域をA、放熱フィン21の第3の配置領域をBとし、放熱フィン21が金属基板13の幅より大きいとすれば、縦ざし基板裏面に於いて、第2の配置領域Aを下方に、第3の配置領域Bを上方に配置することが重要と成る。また放熱フィン21が金属基板13の幅より小さいとすれば、図1(B)右と成る。この場合、放熱フィン21の左右に第2の配置領域として若干のスペースができ、ここにも第2の回路素子群の一部が配置されても良い。
Further, when the hybrid integrated circuit device 10 is vertically (vertically arranged) with respect to the mounting substrate 11, the radiation fins 21 are arranged on the upper side of the back surface of the metal substrate. A margin is provided around the metal substrate. Although the back surface of the metal substrate does not occupy 100% in the second arrangement region and the third arrangement region of the radiation fins 21, it can be almost divided into two in the second circuit element arrangement region and the arrangement region of the radiation fins 21.
Therefore, as shown in the left of FIG. 1B, if the second arrangement region is A, the third arrangement region of the radiation fins 21 is B, and the radiation fins 21 are larger than the width of the metal substrate 13, the vertical substrate On the back surface, it is important to arrange the second arrangement area A downward and the third arrangement area B upward. If the heat dissipating fins 21 are smaller than the width of the metal substrate 13, the right side of FIG. In this case, a slight space is formed as the second arrangement region on the left and right of the heat radiation fin 21, and a part of the second circuit element group may also be arranged here.

続いて、図1に於いて、基板の表と裏の下端には、リード用パッド19があり、ここには、リード24が設けられる。このリード24は、基板の表の回路と裏の回路を電気的に接続し、更に実装基板との電気的接続を担う。またこのリードにより、実装基板11に対して、縦挿しが可能となる。図面では、クリップ端子を採用した。このクリップ端子は、金属基板13の表裏からそれぞれ導電部材が延在され、金属基板下端の外側で一体となり、1本のリードとなっている。しかし縦挿しを可能とするならば、金属基板13の表裏からそれぞれ導電部材が延在され、そのまま金属基板下端の外側に延在されても良い。この場合、表と裏の電気的接続は、実装基板11側で接続される。当然であるが、これらリードは、表裏に複数本設けられる。   Subsequently, in FIG. 1, there are lead pads 19 on the lower ends of the front and back of the substrate, and leads 24 are provided here. The lead 24 electrically connects the circuit on the front side and the circuit on the back side of the board, and further carries out electrical connection with the mounting board. Further, this lead enables vertical insertion with respect to the mounting substrate 11. In the drawing, clip terminals are adopted. In this clip terminal, conductive members extend from the front and back sides of the metal substrate 13, and are integrated into one lead outside the lower end of the metal substrate. However, if vertical insertion is possible, the conductive members may be extended from the front and back sides of the metal substrate 13 and may be extended to the outside of the lower end of the metal substrate as they are. In this case, the front and back electrical connections are made on the mounting substrate 11 side. As a matter of course, a plurality of these leads are provided on the front and back sides.

更に、金属基板13の第1の配置領域、第2の配置領域には、前述したように第1の回路素子群、第2の回路素子群が配置されるため、耐環境性のために絶縁性の被覆樹脂25が被覆される。方法としては、ポッティング、ディッピング、上下金型を用いたトランスファーモールド、インジェクションモールド等があるが、ここでは信頼性も考えトランスファーモールドで実現される。上下金型でモールドする場合、第1、第2の配置領域の部分が金型のキャビィティとなり、第3の配置領域Bは、上または下の金型と当接させることになる。   Furthermore, since the first circuit element group and the second circuit element group are arranged in the first arrangement area and the second arrangement area of the metal substrate 13 as described above, insulation is provided for environmental resistance. Coating resin 25 is coated. Methods include potting, dipping, transfer mold using upper and lower molds, injection mold, and the like. Here, transfer mold is realized in consideration of reliability. When molding with the upper and lower molds, the first and second arrangement regions become mold cavities, and the third arrangement region B is brought into contact with the upper or lower mold.

よって第3の配置領域Bは、Al基板のAl、その表面の酸化膜、または絶縁樹脂層14が露出することになる。当然放熱フィン21と熱的に結合させる場合、露出される面がAl、酸化膜、絶縁樹脂層14の順で熱抵抗が増大していく。よって回路の熱の大きさ、放熱フィンの絶縁性が考慮されて選択されるが、一般的には、Alまたは酸化膜が露出する。   Therefore, in the third arrangement region B, Al of the Al substrate, the oxide film on the surface thereof, or the insulating resin layer 14 is exposed. Of course, when thermally coupled to the radiating fin 21, the thermal resistance increases in the order of the exposed surface of Al, oxide film, and insulating resin layer 14. Therefore, it is selected in consideration of the amount of heat of the circuit and the insulation of the radiating fin, but generally Al or an oxide film is exposed.

この露出させる点は、本発明の特徴である。図1で説明すれば、混成集積回路装置10を実装基板11に立てて実装すると、金属基板裏面には、下方に回路素子、上には放熱フィン21が配置され、放熱フィン21から出てきる熱は、回路素子を通過せずに上昇するため、温度の影響を抑制することができる。よって金属基板の表側の第1の回路素子群の、特に自ら発熱し、他の素子よりもその発熱量が多い半導体素子を、放熱フィンの裏側に配置すれば、この半導体素子の駆動能力を向上できる。しかも放熱フィン21から発生する熱は、他の素子に影響を与えない。   This exposure point is a feature of the present invention. Referring to FIG. 1, when the hybrid integrated circuit device 10 is mounted upright on the mounting substrate 11, a circuit element is disposed on the lower surface of the metal substrate, and a radiation fin 21 is disposed on the lower surface. Since heat rises without passing through the circuit elements, the influence of temperature can be suppressed. Therefore, if the semiconductor element of the first circuit element group on the front side of the metal substrate, which generates heat, and generates more heat than other elements, is placed on the back side of the heat dissipation fin, the driving capability of this semiconductor element is improved. it can. In addition, the heat generated from the radiation fins 21 does not affect other elements.

図2、図7は、第3の配置領域Bを除いて、金属基板の表面、裏面、そして側面が全て封止される例を説明したものである。図2Aは、断面図であり、図2Bは、斜視図である。Alの金属基板のαが25×10−6/度C、チップコンンデンサ、チップ抵抗が7〜10×10−6/度C、半導体チップが3.5×10−6、被覆樹脂である通常のエポキシ樹脂が50×10−6/度Cである。特に金属基板と被覆樹脂は、αが大きく異なり、半導体チップや受動素子の電気的接続部分が破断したり、クラックが入ったりする。そのため、無機フィラーの量を調整し、封止用エポキシ樹脂は、15〜20×10−6程度に調整される。これは、金属基板のαと載せられる素子のαを考慮すると、エポキシ樹脂のαを15〜20×10−6程度が良い。よってαの違いによる応力は、かなり無くすことができる。   2 and 7 illustrate an example in which the front surface, the back surface, and the side surfaces of the metal substrate are all sealed except for the third arrangement region B. FIG. 2A is a cross-sectional view and FIG. 2B is a perspective view. Al of metal substrate of Al is 25 × 10 −6 / degree C, chip capacitor, chip resistance is 7 to 10 × 10 −6 / degree C, semiconductor chip is 3.5 × 10 −6, and is a coating resin The epoxy resin is 50 × 10 −6 / degree C. In particular, α differs greatly between the metal substrate and the coating resin, and the electrical connection portions of the semiconductor chip and the passive element are broken or cracked. Therefore, the amount of the inorganic filler is adjusted, and the sealing epoxy resin is adjusted to about 15 to 20 × 10 −6. In consideration of α of the metal substrate and α of the element to be mounted, α of the epoxy resin is preferably about 15 to 20 × 10 −6. Therefore, the stress due to α difference can be considerably eliminated.

次に、樹脂と基板の密着性を考えると、Al、酸化膜、絶縁樹脂層14の順で密着性は向上する。また酸化膜であるアルマイト膜は、陽極酸化により実現されるため、Alの表面に生成されるため、密着性に優れる。しかしAlから比べると熱抵抗が大きいこと、更には、Alや樹脂層14と比べ硬度が高く、プレス機、ドリル等の加工でプレスの刃、ドリルの磨耗が激しい。しかも金属基板の裏と表は、同時にアルマイト処理が成されるため、基本的には、裏面にも同時に生成される。よって金属基板13の裏面の第3の配置領域Bは、アルマイト膜をそのまま残し、トランスファーモールド後は、このアルマイト膜が露出される。   Next, considering the adhesion between the resin and the substrate, the adhesion improves in the order of Al, oxide film, and insulating resin layer 14. In addition, since the alumite film, which is an oxide film, is realized by anodic oxidation, it is generated on the surface of Al, and therefore has excellent adhesion. However, the heat resistance is higher than that of Al, and the hardness is higher than that of Al or the resin layer 14, and the wear of the press blade and the drill is severe in the processing of a press machine, a drill or the like. Moreover, since the back and front of the metal substrate are subjected to alumite treatment at the same time, basically, they are simultaneously generated on the back surface. Therefore, the third arrangement region B on the back surface of the metal substrate 13 leaves the alumite film as it is, and this alumite film is exposed after the transfer molding.

またAlを第3の配置領域として残す場合、金属基板13の裏面を酸化保護膜でカバーし、金属基板13の表面のみを陽極酸化すれば、金属基板の裏面は、Alとなり、その内、第2の配置領域Aに絶縁樹脂層14を形成し、トランスファーモールドすることにより、第3の配置領域Bは、Alが露出することになる。
この場合、Alと絶縁樹脂層との密着性が悪く、対策が必要となる。
Further, when Al is left as the third arrangement region, if the back surface of the metal substrate 13 is covered with an oxidation protection film and only the surface of the metal substrate 13 is anodized, the back surface of the metal substrate becomes Al. By forming the insulating resin layer 14 in the second arrangement area A and performing transfer molding, Al is exposed in the third arrangement area B.
In this case, the adhesion between Al and the insulating resin layer is poor, and countermeasures are required.

よって、図2でも説明するように、本発明は、第3の配置領域Bを露出させ、他全体を封止している。   Therefore, as will be described with reference to FIG. 2, the present invention exposes the third arrangement region B and seals the other parts.

図7は、この製造方法を説明するものである。金属基板上には、第1の回路素子群、第2の回路素子群が既に配置され、更にリード24も設けられている。この金属基板をトランスファーモールド(またはインジェクション)用の金型に配置して樹脂封止される。ここでは、上金型30Aと下金型30Bがあり、両者が嵌合されて、キャビティ31が形成される。またここではクリップ端子24を採用している。このクリップ端子は、金属基板13の表裏からそれぞれ導電部材32、33が延在され、金属基板下端の外側で連結部材34と一体となり、1本のリードとなっている。   FIG. 7 illustrates this manufacturing method. On the metal substrate, the first circuit element group and the second circuit element group are already arranged, and leads 24 are also provided. This metal substrate is placed in a transfer mold (or injection) mold and resin-sealed. Here, there are an upper mold 30A and a lower mold 30B, and both are fitted to form a cavity 31. Here, the clip terminal 24 is employed. In this clip terminal, conductive members 32 and 33 extend from the front and back of the metal substrate 13, respectively, and are integrated with the connecting member 34 outside the lower end of the metal substrate to form one lead.

本発明は、この連結部材34も含めて樹脂封止されている。更に第3の配置領域Bを除き、金属基板13の表面、裏面および側面も含めて封止される。第1の回路素子群を封止する第1の被覆樹脂、第2の回路素子群を封止する第2の被覆樹脂は、4つの側面に封止された樹脂で一体となる。よってクリップリードの接続信頼性が向上し、更には4つの側面も含め、被覆樹脂が一体となっているので、基板から被覆樹脂が剥がれることも無い。また基板の側面は、基板を分離する際、上と下に分離溝を形成し、この溝を介して分離している。よって断面で見ると、右側側面はV字が90度時計回りと逆に、左側はV字が90度時計回りの形状となっている。つまり全ての側面は、基板の表面および裏面から鈍角をなして外側に向かい凸形状となっている。よって図2に於いて符号40は、その側面の断面形状であり、そこに被覆樹脂が設けられているので、ここでもアンカーが働く構造になっている。   In the present invention, this connecting member 34 is also resin-sealed. Further, except for the third arrangement region B, the metal substrate 13 is sealed including the front surface, the back surface, and the side surfaces. The first coating resin for sealing the first circuit element group and the second coating resin for sealing the second circuit element group are integrated with the resin sealed on the four side surfaces. Therefore, the connection reliability of the clip lead is improved, and furthermore, since the coating resin is integrated including the four side surfaces, the coating resin is not peeled off from the substrate. Further, when the substrate is separated from the side surface of the substrate, separation grooves are formed above and below, and the substrate is separated through the groove. Therefore, when viewed in cross section, the right side surface has a V-shape that is 90 degrees clockwise and the left side has a V-shape that is 90 degrees clockwise. That is, all the side surfaces are convex toward the outside at an obtuse angle from the front surface and the back surface of the substrate. Therefore, the reference numeral 40 in FIG. 2 is the cross-sectional shape of the side surface, and since the coating resin is provided there, the anchor works here as well.

更に、金属基板を中心にして表、裏にαの同じ被覆樹脂が設けられてあるので、モジュール全体の反りは、かなり軽減される。
図3は、第2の実施の形態であり、図1と異なる部分は、封止手段とリードの形状であり、他は図1の説明と同じある。よってここでは、異なる点のみを説明する。本発明は、封止手段としてケーシングを用いた。これは、中空構造であるため、金属基板αとの違いによる反りを軽減できる。
Further, since the same coating resin α is provided on the front and back with the metal substrate as the center, the warpage of the entire module is considerably reduced.
FIG. 3 shows the second embodiment. The difference from FIG. 1 is the shape of the sealing means and the leads, and the rest is the same as the description of FIG. Therefore, only a different point is demonstrated here. In the present invention, a casing is used as the sealing means. Since this is a hollow structure, the curvature by the difference with the metal substrate (alpha) can be reduced.

またこのケーシングの代わりに、被覆樹脂で形成しても良い、しかしこの場合、金属基板の表裏に、樹脂の塊が貼りあわされている格好になるため、第1の実施例と比較すると、その界面で剥がれが発生する可能性が高い。
放熱フィン21は、Al、陽極酸化膜と直接接触されても良いが、絶縁性を有し、熱伝導性の優れた材料が、両者の間に設けられても良い。また放熱フィンは、図1では、ベースとなる金属に金属からなるフィンが縦に付いたものである。
Further, instead of this casing, it may be formed of a coating resin. However, in this case, since a lump of resin is pasted on the front and back of the metal substrate, compared with the first embodiment, There is a high possibility of peeling at the interface.
Although the heat radiation fin 21 may be in direct contact with Al or the anodic oxide film, a material having insulating properties and excellent thermal conductivity may be provided between the two. In FIG. 1, the heat dissipating fins are metal base fins vertically attached to metal.

本発明の混成集積回路装置を説明する図である。It is a figure explaining the hybrid integrated circuit device of this invention. 本発明の混成集積回路装置を説明する図である。It is a figure explaining the hybrid integrated circuit device of this invention. 本発明の混成集積回路装置を説明する図である。It is a figure explaining the hybrid integrated circuit device of this invention. 本発明の混成集積回路装置をパネルに取り付けたときの図である。It is a figure when the hybrid integrated circuit device of this invention is attached to the panel. 従来の混成集積回路装置をパネルに取り付けたときの図である。It is a figure when the conventional hybrid integrated circuit device is attached to the panel. 従来技術に係る混成集積回路装置を説明する図である。It is a figure explaining the hybrid integrated circuit device concerning a prior art. 本発明に係わり、上下金型を用いてトランスファーモールドする際の図である。It is a figure at the time of carrying out transfer molding using the upper and lower molds according to the present invention.

符号の説明Explanation of symbols

10:混成集積回路装置
11:実装基板
12:実装基板に混成集積回路装置が縦挿しされたモジュール
13:金属基板
14:絶縁樹脂層
21:放熱フィン
10: Hybrid integrated circuit device 11: Mounting substrate 12: Module in which the hybrid integrated circuit device is vertically inserted on the mounting substrate 13: Metal substrate 14: Insulating resin layer 21: Radiation fin

Claims (8)

表面、裏面および側面を有する金属基板と、前記表面を被覆する第1の絶縁樹脂層と、前記裏面の一領域を被覆する第2の絶縁樹脂層と、前記第1の絶縁樹脂層に設けられた第1の導電パターンと、前記第2の絶縁樹脂層に設けられた第2の導電パターンと、前記第1の導電パターンと電気的に接続され、固着された複数の第1の回路素子と、前記第2の導電パターンと電気的に接続され、固着された複数の第2の回路素子と、前記第1の導電パターンと前記第2の導電パターンを電気的に接続するリードと、前記第1の回路素子を被覆する第1の被覆樹脂と、前記第2の回路素子を被覆する第2の被覆樹脂とから成る事を特徴とした混成集積回路装置。 A metal substrate having a front surface, a back surface, and a side surface, a first insulating resin layer covering the surface, a second insulating resin layer covering a region of the back surface, and the first insulating resin layer. A first conductive pattern, a second conductive pattern provided on the second insulating resin layer, and a plurality of first circuit elements electrically connected and fixed to the first conductive pattern; A plurality of second circuit elements electrically connected and fixed to the second conductive pattern, leads for electrically connecting the first conductive pattern and the second conductive pattern, and the first A hybrid integrated circuit device comprising: a first coating resin that covers one circuit element; and a second coating resin that covers the second circuit element. 前記被覆樹脂は、トランスファーモールドにより被覆される請求項1に記載の混成集積回路装置。 The hybrid integrated circuit device according to claim 1, wherein the coating resin is coated with a transfer mold. 前記第1の被覆樹脂と前記第2の被覆樹脂は、前記側面を介して一体で成る請求項1または請求項2に記載の混成集積回路装置。 The hybrid integrated circuit device according to claim 1, wherein the first coating resin and the second coating resin are integrated with each other through the side surface. 前記裏面の他方の領域には、放熱フィンが取り付けられる請求項1に記載の混成集積回路装置。 The hybrid integrated circuit device according to claim 1, wherein a radiation fin is attached to the other region of the back surface. 前記金属基板が垂直配置され、この垂直配置の金属基板の下方に前記第2の被覆樹脂が位置し、上方に前記放熱フィンが位置する事を特徴とした請求項4に記載の混成集積回路装置。 5. The hybrid integrated circuit device according to claim 4, wherein the metal substrate is arranged vertically, the second coating resin is located below the vertically arranged metal substrate, and the heat radiating fins are located above the metal substrate. . 前記金属基板は、Alを主材料とする金属から成り、表面には酸化膜が形成される請求項1に記載の混成集積回路装置。 The hybrid integrated circuit device according to claim 1, wherein the metal substrate is made of a metal whose main material is Al, and an oxide film is formed on a surface thereof. 表面、裏面および側面を有する金属基板と、前記表面を被覆する第1の絶縁樹脂層と、前記裏面の一領域を被覆する第2の絶縁樹脂層と、前記第1の絶縁樹脂層に設けられた第1の導電パターンと、前記第2の絶縁樹脂層に設けられた第2の導電パターンと、前記第1の導電パターンと電気的に接続され、固着された複数の第1の回路素子と、前記第2の導電パターンと電気的に接続され、固着された複数の第2の回路素子と、前記第1の導電パターンと前記第2の導電パターンを電気的に接続するリードと、前記第1の回路素子と前記第2の回路素子を被覆し一体で成る被覆樹脂とから成り、
前記金属基板は、垂直に配置され、この垂直配置の上方に位置する前記第1の回路素子は、BIPまたはMOS型のパワートランジスタ、IGBTまたはGTBTから成り、この第1の回路素子の配置領域の前記裏面には、放熱フィンが設けられる事を特徴とした混成集積回路装置。
A metal substrate having a front surface, a back surface, and a side surface, a first insulating resin layer covering the surface, a second insulating resin layer covering a region of the back surface, and the first insulating resin layer. A first conductive pattern, a second conductive pattern provided on the second insulating resin layer, and a plurality of first circuit elements electrically connected and fixed to the first conductive pattern; A plurality of second circuit elements that are electrically connected and fixed to the second conductive pattern, leads that electrically connect the first conductive pattern and the second conductive pattern, and the first 1 circuit element and a coating resin that covers and integrally covers the second circuit element,
The metal substrate is arranged vertically, and the first circuit element located above the vertical arrangement is composed of a BIP or MOS type power transistor, IGBT or GTBT, and the first circuit element is arranged in an arrangement region of the first circuit element. A hybrid integrated circuit device, wherein a heat radiating fin is provided on the back surface.
前記金属基板の両面には、酸化膜が形成され、前記放熱フィンは、前記酸化膜の上に設けられた熱伝導性材料を介して熱的に結合される請求項7に記載の混成集積回路装置。 The hybrid integrated circuit according to claim 7, wherein oxide films are formed on both surfaces of the metal substrate, and the heat radiation fins are thermally coupled via a heat conductive material provided on the oxide film. apparatus.
JP2007170851A 2007-06-28 2007-06-28 Hybrid integrated circuit device Pending JP2009010213A (en)

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JP2011096995A (en) * 2009-10-29 2011-05-12 Samsung Electro-Mechanics Co Ltd Heat dissipation structure and method for manufacturing the same
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JP2018152613A (en) * 2014-11-20 2018-09-27 日本精工株式会社 Heat dissipation substrate mounted with electronic component
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