JP2009094148A - Heterojunction bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that a heterojunction bipolar transistor applied to a high-frequency transmission power amplifier is required to have a high breakdown voltage. <P>SOLUTION: The heterojunction bipolar transistor has, in order from a GaAs substrate 101, an n<SP>+</SP>-type GaAs subcollector layer 102, an n-type GaAs collector layer 103, a p-type GaAs base layer 104, an n-type InGaP emitter layer 105, an n-type GaAs breakdown voltage adjusting layer 106 having lower doping concentration than an N-type GaAs emitter cap layer 107, the n-type GaAs emitter cap layer 107, and an n<SP>+</SP>-type InGaA contact layer 108. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a heterojunction bipolar transistor, and more particularly to a heterojunction bipolar transistor that requires a high breakdown voltage.

  A compound semiconductor device such as a field effect transistor (hereinafter referred to as “FET”) or a heterojunction bipolar transistor (hereinafter referred to as “HBT”) is, for example, one of the components of a mobile phone. Used in high power amplifiers.

  Therefore, in recent years, high output characteristics, high gain characteristics, and low distortion characteristics have been demanded for HBTs. In order to realize these, HBTs having high breakdown voltage and low on-resistance have been realized. It is requested. In particular, when GSM (Global System for Mobile Communications) is used, a high breakdown voltage is particularly required.

  As a material used for the emitter layer of HBT, InGaP has recently become mainstream instead of AlGaAs. Advantages of InGaP include lattice matching with GaAs when the In composition is near 0.5, selectivity of wet etching for GaAs, and when the valence band discontinuity when bonded to the GaAs base layer is AlGaAs. It is comparatively large, there is no deep impurity like the DX center found in AlGaAs, and the surface recombination velocity is low.

  Furthermore, InGaP has the property that the arrangement state of atoms and the band gap in the crystal change depending on the growth conditions. When the growth temperature of InGaP is changed, the group III elements In and Ga are regularly arranged in the group III atomic layer surface to form an ordered arrangement structure that is a CuPt-type natural superlattice structure, and irregularly arranged. As a result, a disordered structure can be formed. Accordingly, the band gap of InGaP changes in the range of approximately 1.84 to 1.90 eV.

  FIG. 4A is a schematic diagram of a unit crystal lattice of a group III-V mixed crystal semiconductor. III-V mixed crystal semiconductors are formed of IIIa-IIIb-V type mixed crystals, and two types IIIa and IIIb of IIIa and IIIb are arranged almost randomly on a crystal lattice (sublattice) consisting of only the members of the same group. It is known that The structure will be described with reference to FIG. 1. Two types of different atoms of IIIa or IIIb are randomly arranged at the sites of group III atoms 3a to 3n, and group V atoms 5a to 5d are group III atoms 3a to 3a. Arranged to bind to 3n. However, it is known that IIIa and IIIb form an ordered arrangement structure on the group III sublattice at a specific growth temperature.

  FIG. 4B is a crystal structure diagram of InGaP viewed perpendicularly to the growth direction as an example of a group III-V mixed crystal semiconductor having an ordered arrangement structure. Specifically, the figure shows a crystal structure diagram viewed from the normal direction of the plane formed by the group III atoms 3a, 3b, 3c, and 3n in FIG. If group III atoms 3a, 3e, 3f, 3g, 3h, and 3i in FIG. 4 (a) are Ga atoms in FIG. 4 (b), group III atoms 3c, 3d, 3j, FIG. 3k, 3l, and 3m are In atoms in FIG. 4B. As can be seen in FIG. 4B, in the ordered arrangement structure, the arrangement of IIIa-V (In-P) and IIIb-V (Ga-P) are adjacent to each other.

  FIG. 5 is a graph showing the growth temperature dependence of the band gap of InGaP. As described above, the band gap of InGaP changes depending on the growth temperature. That is, the band gap becomes smaller as the ordered arrangement structure is formed, and the band gap becomes larger as the disordered arrangement structure is formed.

  In addition, it is known that when GaAs is grown across InGaP with an ordered arrangement structure, anomalies in the carrier concentration distribution state occur at the interface, which is thought to be caused by distortion of the atomic arrangement state at the interface. .

The experimental results reproducing this phenomenon will be described with reference to FIGS. 6 (a) and 6 (b). FIG. 6A is a cross-sectional view of the device used in the experiment for examining the carrier concentration distribution at the interface. FIG. 6B is a graph showing experimental results obtained by examining the carrier concentration distribution at the interface. As shown in FIG. 6 (a), the device used in the experiment is an n-type GaAs layer having a doping concentration of 3 × 10 ¹⁷ cm ⁻³ and a film thickness of 100 nm, a doping concentration of 3 on the GaAs substrate. × 10 ¹⁷ cm ^-3, ordered array structure n-type InGaP layer having a thickness of 100nm, the doping concentration of 3 × 10 ¹⁷ cm ^-3, n-type GaAs layer having a thickness of 100nm is formed. Thereafter, an electrode for measurement is formed, and the carrier concentration distribution is measured by the CV method.

  As shown in the experimental results of FIG. 6B, carrier depletion occurs at the interface between the ordered n-type InGaP layer and the upper n-type GaAs layer, while at the interface with the lower n-type GaAs layer. Career accumulation is happening.

  When InGaP with an ordered arrangement structure is used for the emitter layer, the conduction band discontinuity between the emitter and the base becomes smaller than in the case of the disordered arrangement structure, so that the energy barrier against electrons injected from the emitter to the base becomes a problem. There is an advantage to disappear. On the other hand, depletion of carriers reduces the energy barrier in the valence band of InGaP with respect to holes in the base layer, thereby increasing the base current. As a result, a problem of a decrease in the current amplification factor hfe occurs.

FIG. 7 is a structural cross-sectional view of a conventional HBT. On the GaAs substrate 701, an n ⁺ -type GaAs subcollector layer 702 having an electron concentration of 5 × 10 ¹⁸ cm ⁻³ and a film thickness of 600 nm, and an n-type GaAs collector having an electron concentration of 1 × 10 ¹⁶ cm ⁻³ and a film thickness of 600 nm. Layer 703, hole concentration 4 × 10 ¹⁹ cm ⁻³ , p-type GaAs base layer 704 having a thickness of 80 nm, electron concentration 3 × 10 ¹⁷ cm ⁻³ , n-type InGaP emitter layer 705 having a thickness of 30 nm, electron concentration 3 × 10 An n-type GaAs emitter cap layer 707 having a thickness of ¹⁸ cm ⁻³ and a thickness of 200 nm and an n ⁺ -type InGaAs contact layer 708 having an electron concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 100 nm are formed by MOCVD (Metal Organic Chemical Vapor Deposition: Organic). Metallic chemical vapor deposition method) or MBE method (Molecular Beam Epitaxy: molecular beam) (Epitaxial growth method). When the n-type InGaP emitter layer is grown in an ordered arrangement structure, carrier depletion occurs at the interface with the GaAs layer as described above. As a result, the base current increases and the current amplification factor hfe decreases.

  As a method for solving this problem, for example, there is a method described in Patent Document 1.

FIG. 8 is a structural cross-sectional view of the HBT described in Patent Document 1. In FIG. The HBT shown in FIG. 8 is formed by sequentially growing a buffer layer 802, an n ⁺ -type GaAs collector contact A layer 803, an n-type or i-type GaAs collector layer on a GaAs substrate 801 by crystal growth by MOCVD or MBE. 804, p-type GaAs base layer 805, electron concentration 3 × 10 ¹⁷ cm ⁻³ , n-type In _x Ga _1-x P emitter A layer 806 with a film thickness of 30 nm, electron concentration 3 × 10 ¹⁸ cm ⁻³ , film thickness 3 nm A charge compensation layer 807, an n-type GaAs emitter B layer 808, an n ⁺ -type GaAs emitter contact A layer 809, and an n ⁺ -type InGaAs emitter contact B layer 810 having an electron concentration of 3 × 10 ¹⁷ cm ⁻³ and a film thickness of 100 nm. Has been.

If the n _- type GaAs emitter B layer 808 is directly stacked on the n-type In _x Ga _1-x P emitter A layer 806, carrier depletion occurs at the interface between the two layers. As a result, the base current increases, and the current amplification factor hfe (hereinafter referred to as hfe) decreases in the region where the collector current Ic is small, that is, in the low Ic region. Therefore, the charge compensation layer 807 with an increased electron concentration is introduced so that carrier depletion does not occur, and hfe is prevented from decreasing.

Other techniques for preventing carrier depletion include planar doping at the interface between the InGaP layer and GaAs as described in Patent Document 2, and InGaP layer as described in Patent Document 3. In addition, there is a method of doping Sb into the semiconductor layer, and as described in Patent Document 4, the lower part of the InGaP layer has an ordered arrangement structure and the upper InGaP layer in contact with the GaAs layer has a disordered arrangement structure.
JP 2003-86603 A JP-A-8-293505 JP 2001-203215 A JP 2001-345328 A

However, according to the above prior art, an increase in base current in the low Ic region is prevented by preventing carrier depletion in the emitter layer, and as a result, a decrease in hfe is suppressed. There arises a problem that the inter-voltage BV _CEO is lowered.

BV _CEO is a parameter for evaluating the breakdown voltage of the transistor. The larger BV _CEO is, the higher the breakdown voltage of the transistor is.

As a relational expression between the current amplification factor hfe and the base open collector emitter breakdown voltage BV _CEO , the following expression is known.

BV _CEO = BV _CBO / (hfe ^{1 / n} ) (Formula 1)

Here, BV _CBO represents the breakdown voltage between the emitter open collector base. n is a positive number of 4 or less. From this equation, it can be seen that an increase in hfe in the low Ic region leads to a decrease in BV _CEO .

When an HBT is used as a transmission power amplifier, the BV _CEO should not be lowered in an application that requires a particularly high breakdown voltage, such as GSM.

In actual device operation, the base current in the region where hfe is almost in the peak is used. Therefore, it is not so important that hfe is low in the low Ic region, but rather, the decrease in BV _CEO , which is a pressure resistance parameter, is prevented. It is important to do.

  The present invention has been made in view of the above problems, and an object thereof is to provide an HBT having a high breakdown voltage.

  In order to achieve the above object, a heterojunction bipolar transistor according to the present invention is a heterojunction bipolar transistor in which a collector layer made of a III-V compound semiconductor, a base layer, and an emitter layer are stacked on a semiconductor substrate. The emitter layer includes first to third emitter layers stacked in order from the base layer, and the second emitter layer has a lower doping concentration than the third emitter layer. And

With this configuration, hfe in the low Ic region, which is not the actual operating point of the device, can be actively reduced, and the base open collector-emitter breakdown voltage BV _CEO increases. As a result, a heterojunction bipolar transistor having a high breakdown voltage is realized.

  The first emitter layer is an n-type InGaP emitter layer, the second emitter layer is an n-type low-concentration GaAs layer, and the third emitter layer is an n-type GaAs emitter cap layer. Preferably there is.

  The combination of n-type InGaP and n-type GaAs is used as an emitter layer, so that the In composition is lattice matched to GaAs near 0.5, wet etching selectivity to GaAs-based materials, AlGaAs Advantages such as the absence of deep impurities as seen in the DX center and a low surface recombination speed are obtained, and the heterogeneity has a simplified manufacturing process, high crystallinity, high speed operation, and high pressure resistance. A junction bipolar transistor is realized.

  The second emitter layer is preferably a GaAs layer having a doping concentration of 0 or more.

Thus, the charge depletion layer at the interface between the emitter layer and the emitter cap layer can be further increased, and the base open collector emitter breakdown voltage BV _CEO is increased. As a result, a higher junction voltage heterojunction bipolar transistor is realized.

  The heterojunction bipolar transistor according to the present invention is a heterojunction bipolar transistor in which a collector layer made of a group III-V compound semiconductor, a base layer, and an emitter layer are stacked on a semiconductor substrate, the emitter layer Includes first and third emitter layers stacked in order from the base layer, and the first emitter layer has a level as a recombination center formed at the interface with the third emitter layer. It is characterized by.

With this configuration, the charge depletion layer at the emitter layer-emitter cap layer interface can be actively increased, and hfe in the low Ic region that is not the actual operating point of the device can be actively reduced. As a result, the base open collector-emitter breakdown voltage BV _CEO increases and a high breakdown voltage heterojunction bipolar transistor is realized.

  Preferably, the first emitter layer is an n-type InGaP emitter layer, and the third emitter layer is an n-type GaAs emitter cap layer.

  By using a combination of n-type InGaP and n-type GaAs as an emitter layer, as described above, a heterojunction bipolar transistor having a simplified manufacturing process, high crystallinity, high-speed operation, and high withstand voltage can be obtained. Realized.

Further, the level serving as the recombination center may be formed by applying a H ₂ gas flow to the surface of the n-type InGaP emitter layer after forming the n-type InGaP emitter layer.

  Thereby, the level of the interface between the emitter layer and the emitter cap layer can be easily controlled by adding a simple process to the intermediate stage of the manufacturing process of the laminated device.

The semiconductor substrate is a GaAs substrate, the collector layer includes an n ⁺ -type GaAs subcollector layer and an n-type GaAs collector layer in order from the GaAs substrate, and the base layer is the n-type GaAs. A p-type GaAs base layer bonded to the collector layer is preferred.

  Use a consistent manufacturing process such as MOCVD and MBE by taking a stacked structure of collector, base and emitter cap layers made of GaAs-based material and emitter layers made of InGaP-based material In addition, as described above, a heterojunction bipolar transistor having a simplified manufacturing process, high crystallinity, high speed operation, and high withstand voltage is realized.

  The n-type InGaP emitter layer preferably has a CuPt-type natural superlattice partially or completely formed.

As a result, the n-type InGaP that is the emitter layer has an ordered arrangement structure, and the conduction band discontinuity between the emitter and the base becomes smaller than that in the disordered arrangement structure, so that the energy barrier against electrons injected from the emitter to the base is reduced. There is an advantage that it does not become a problem. On the other hand, the increase in carrier depletion reduces the energy barrier in the valence band of InGaP with respect to holes in the base layer, thereby increasing the base current. As a result, the current amplification factor hfe is reduced, but from the viewpoint of high voltage resistance, BV _CEO is increased, which is convenient.

  The present invention can be realized not only as a heterojunction bipolar transistor having such characteristic means, but also as a method of manufacturing a heterojunction bipolar transistor having the characteristic means included in the heterojunction bipolar transistor as a step. Can be realized.

As described above, according to the heterojunction bipolar transistor of the present invention, by reducing the current amplification factor hfe in the low Ic region, the base open collector emitter breakdown voltage BV _CEO is improved. A junction bipolar transistor can be realized.

(Embodiment 1)
The heterojunction bipolar transistor (hereinafter referred to as HBT) in the first embodiment includes a collector layer, a base layer, and an emitter layer on a GaAs substrate, and the emitter layer is sequentially formed from the surface of the base layer. The n-type InGaP emitter layer, the n-type low-concentration GaAs layer, and the n-type GaAs emitter cap layer are characterized in that the n-type low-concentration GaAs layer has a lower doping concentration than the n-type GaAs emitter cap layer. As a result, the current amplification factor hfe in the region where the collector current Ic is small, that is, the low Ic region is reduced, and the base open collector-emitter breakdown voltage BV _CEO is increased. Therefore, an HBT having a high breakdown voltage is realized.

  Hereinafter, an HBT according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a structural cross-sectional view of an HBT according to Embodiment 1 of the present invention. In the figure, the HBT includes a GaAs substrate 101, an n ⁺ -type GaAs subcollector layer 102, an n-type GaAs collector layer 103, a p-type GaAs base layer 104, an n-type InGaP emitter layer 105, and an n-type GaAs breakdown voltage adjustment. A layer 106, an n-type GaAs emitter cap layer 107, an n ⁺ -type InGaAs contact layer 108, a collector electrode 110, a base electrode 120, and an emitter electrode 130 are provided.

Each layer other than the collector electrode 110, the base electrode 120, and the emitter electrode 130 is formed by GaAs by MOCVD (Metal Organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy). On the substrate 101, an n ⁺ -type GaAs subcollector layer 102, an n-type GaAs collector layer 103, a p-type GaAs base layer 104, an n-type InGaP emitter layer 105, an n-type GaAs breakdown voltage adjustment layer 106, and an n-type GaAs emitter cap layer 107 And the n ⁺ -type InGaAs contact layer 108 are stacked in this order.

The n ⁺ -type GaAs subcollector layer 102 has, for example, an electron concentration of 5 × 10 ¹⁸ cm ⁻³ and a film thickness of 600 nm.

For example, the n-type GaAs collector layer 103 has an electron concentration of 1 × 10 ¹⁶ cm ⁻³ and a film thickness of 600 nm.

The n ⁺ -type GaAs subcollector layer 102 and the n-type GaAs collector layer 103 function as an n-type collector layer.

The p-type GaAs base layer 104 functions as a p-type base layer, and has a hole concentration of 4 × 10 ¹⁹ cm ⁻³ and a film thickness of 80 nm, for example.

The n-type InGaP emitter layer 105 constitutes a first emitter layer, forms a CuPt-type natural superlattice, and has an ordered arrangement structure. For example, the electron concentration is 3 × 10 ¹⁷ cm ⁻³ , The film thickness is 30 nm.

The n-type GaAs withstand voltage adjusting layer 106 constitutes a second emitter layer and is an n-type low-concentration GaAs layer having a doping concentration lower than that of the n-type GaAs emitter cap layer 107. For example, the electron concentration is 3 × 10 ¹⁶ cm. ^-3 , and the film thickness is 30 nm.

The n-type GaAs emitter cap layer 107 constitutes a third emitter layer, and has an electron concentration of 3 × 10 ¹⁸ cm ⁻³ and a film thickness of 200 nm, for example.

  The n-type InGaP emitter layer 105, the n-type GaAs withstand voltage adjustment layer 106, and the n-type GaAs emitter cap layer 107 function as an n-type emitter layer.

The n ⁺ -type InGaAs contact layer 108 has, for example, an electron concentration of 1 × 10 ¹⁹ cm ⁻³ and a film thickness of 100 nm.

  The doping concentration of each layer is determined by the amount of dopant such as Si or C used as a dopant, and the film thickness or area of each layer.

After the layers from the n ⁺ type GaAs subcollector layer 102 to the n ⁺ type InGaAs contact layer 108 are formed, the collector electrode 110 is formed on the surface of the n ⁺ type GaAs subcollector layer 102 and the surface of the p type GaAs base layer 104. The base electrode 120 and the emitter electrode 130 are formed on the n ⁺ -type InGaAs contact layer 108, respectively.

  Even when the n-type GaAs emitter cap layer 107 is grown directly on the n-type InGaP emitter layer 105 having an ordered arrangement structure, a charge depletion region of carriers is generated at the interface between the two layers, but it is lower than the n-type GaAs emitter cap layer 107. When the n-type GaAs breakdown voltage adjusting layer 106 having a concentration is positively introduced between the n-type InGaP emitter layer 105 and the n-type GaAs emitter cap layer 107, the charge depletion region is further expanded.

As a result, the base current increases and hfe in the low Ic region decreases, resulting in an increase in BV _CEO .

  When the n-type GaAs withstand voltage adjusting layer 106 is undoped, that is, when the doping concentration is approximately 0, the withstand voltage effect is further increased.

  Here, a manufacturing process for the HBT according to the first embodiment of the present invention will be described.

  As described above, each layer is formed in a consistent manner by, for example, the MOCVD method or the MBE method.

First, an n ⁺ type GaAs subcollector layer 102 having a thickness of 600 nm is formed on the GaAs substrate 101, and an n type GaAs collector layer 103 having a thickness of 600 nm is formed on the n ⁺ type GaAs subcollector layer 102 on the n type GaAs collector layer 103. The p-type GaAs base layer 104 with a thickness of 80 nm, the n-type InGaP emitter layer 105 with a thickness of 30 nm on the p-type GaAs base layer 104, and the n-type GaAs withstand voltage adjustment layer 106 with a thickness of 30 nm on the n-type InGaP emitter layer 105. However, an n-type GaAs emitter cap layer 107 having a thickness of 200 nm is sequentially stacked on the n-type GaAs withstand voltage adjusting layer 106, and an n ⁺ -type InGaAs contact layer 108 having a thickness of 100 nm is sequentially stacked on the n-type GaAs emitter cap layer 107.

  Next, the collector electrode 110, the base electrode 120, and the emitter electrode 130 are formed as ohmic electrodes by appropriate etching and electrode deposition processing on the laminate.

  Hereinafter, the results of measuring the electrical characteristics of the HBT according to Embodiment 1 of the present invention shown in FIG. 1 will be described.

  FIG. 3A is a comparison diagram of Gummel plots for the HBT according to the first embodiment and the second embodiment of the present invention and the HBT having the conventional structure.

  Here, the Gummel plot represents the relationship between the collector current and the base current measured by increasing the base-emitter voltage while the base collector is short-circuited.

3 (a), (i) shows the conventional structure shown in FIG. 7 and the n-type InGaP emitter layer 705 has a disordered arrangement structure, and (ii) shows the conventional structure shown in FIG. 7 and an n-type InGaP emitter. When the layer 705 has an ordered arrangement structure, and (iii) shows that the n-type InGaP emitter layer has an ordered arrangement structure and the n-type GaAs breakdown voltage adjusting layer 106 is introduced, or the n-type InGaP described in the second embodiment FIG. 4 is a Gummel plot when H ₂ gas flow is introduced to the surface of the emitter layer 205.

  From the comparison results of the Gummel plots in the figure, in the region where the base-emitter voltage is low, that is, in the low Ic region, the base current is larger in (iii) than in (i) and (ii).

  FIG. 3B is a graph showing the relationship between the current amplification factor hfe (= collector current Ic / base current Ib) obtained from FIG. 3A and the collector current Ic. (I) to (iii) in the figure correspond to (i) to (iii) in FIG.

  In the low Ic region, the current gain hfe is lower in (iii) than in (i) and (ii), because of the collector current Ic dependence of the current gain hfe in FIG.

Further, FIG. 3C is a graph in which the relationship between the collector current Ic and the collector voltage V _CE is measured for each different base current Ib. (I) to (iii) in the figure correspond to (i) to (iii) in FIGS. 3 (a) and 3 (b).

In FIG. 3C, BV _CEO corresponds to the collector voltage V _CE when the collector current Ic increases rapidly when the collector voltage V _CE is increased when the base current Ib is 0 (open) _. That is.

The collector voltage in FIG - from current characteristic, when the base current Ib is 0, BV _CEO is greater than towards the (iii) is (i) and (ii).

From these results, a low-concentration n-type GaAs breakdown voltage adjusting layer is positively introduced between the n-type InGaP emitter layer and the n-type GaAs emitter cap layer, and the n-type InGaP emitter layer has an ordered arrangement structure. As a result, the base current Ib increases and the current amplification factor hfe decreases in the low Ic region, resulting in an improvement in BV _CEO . As a result, the current amplification factor hfe in the high Ic region, which is the actual operating point of the transmission power amplifier, does not decrease, and a high breakdown voltage HBT is realized.

(Embodiment 2)
The HBT according to the second embodiment includes a collector layer, a base layer, and an emitter layer on a GaAs substrate. The emitter layer includes an n-type InGaP emitter layer and an n-type GaAs emitter cap layer in order from the surface of the base layer. And a level serving as a recombination center is formed at the interface between the two layers. As a result, the charge depletion layer at the interface increases, the current amplification factor hfe in the low Ic region decreases, and the base open collector emitter breakdown voltage BV _CEO increases. Therefore, an HBT having a high breakdown voltage is realized.

  Hereinafter, an HBT according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a structural cross-sectional view of the HBT according to the second embodiment of the present invention. In the figure, the HBT includes a GaAs substrate 201, an n ⁺ -type GaAs subcollector layer 202, an n-type GaAs collector layer 203, a p-type GaAs base layer 204, an n-type InGaP emitter layer 205, and an n-type GaAs emitter cap. A layer 207, an n ⁺ -type InGaAs contact layer 208, a collector electrode 210, a base electrode 220, and an emitter electrode 230 are provided.

Each layer other than the collector electrode 210, the base electrode 220, and the emitter electrode 230 is formed on the GaAs substrate 201 by MOCVD or MBE on the n ⁺ -type GaAs subcollector layer 202, the n-type GaAs collector layer 203, and the p-type GaAs base layer 204. , An n-type InGaP emitter layer 205, an n-type GaAs emitter cap layer 207, and an n ⁺ -type InGaAs contact layer 208 are stacked in this order.

The doping concentration and film thickness of each layer from the n ⁺ -type GaAs subcollector layer 202 to the n ⁺ -type InGaAs contact layer 208 are, for example, the doping concentration and film thickness of each layer of the HBT of the first embodiment shown in FIG. It is the same.

In addition, after each of the above layers is formed, an ohmic electrode is formed by etching and electrode deposition treatment. Specifically, the collector electrode 210 is formed on the surface of the n ⁺ -type GaAs subcollector layer 202, the base electrode 220 is formed on the surface of the p-type GaAs base layer 204, and the emitter electrode 230 is formed on the n ⁺ -type InGaAs contact layer 208. It is formed.

The n ⁺ -type GaAs subcollector layer 202 and the n-type GaAs collector layer 203 function as an n-type collector layer.

  The p-type GaAs base layer 204 functions as a p-type base layer.

  The n-type InGaP emitter layer 205 functions as a first emitter layer, forms a CuPt-type natural superlattice, and forms an ordered arrangement structure.

  The n-type GaAs emitter cap layer 207 functions as a third emitter layer.

  The n-type InGaP emitter layer 205 and the n-type GaAs emitter cap layer 207 function as an n-type emitter layer.

On the surface of the n-type InGaP emitter layer 205, an H ₂ gas flow is performed for ³ minutes at a rate of, for example, 200 cm ³ / min after the film formation and before the film formation of the n-type GaAs emitter cap layer 207. .

In the second embodiment of the present invention, an n-type InGaP layer is generated by generating many interface states as recombination centers on the surface of the n-type InGaP emitter layer 205 using the etching action by the H ₂ gas flow. The charge depletion layer at the interface between the emitter layer 205 and the n-type GaAs emitter cap layer 207 increases, and as a result, the base current increases.

  Here, the deposition process of the emitter layer will be described.

  First, an n-type InGaP emitter layer 205 having a thickness of 30 nm is stacked on the p-type GaAs base layer 204.

Next, H ₂ gas flow is applied to the surface of the n-type InGaP emitter layer 205 at a rate of 200 cm ³ / min for 3 minutes.

Next, an n-type GaAs emitter cap layer 207 having a thickness of 200 nm is stacked on the surface of the n-type InGaP emitter layer 205 to which the H ₂ gas flow has been applied.

  The collector layer and base layer before the emitter layer is formed, and the contact layer and each electrode after the emitter layer are formed are the same as those in the first embodiment, and the description thereof is omitted here. .

3A to 3C, (i) is the conventional structure shown in FIG. 7 and the n-type InGaP emitter layer 705 has a disordered arrangement structure, and (ii) is the conventional structure shown in FIG. In the structure, when the n-type InGaP emitter layer 705 has an ordered arrangement structure, and (iii) is the HBT according to the first and second embodiments of the present invention described in FIG. 1 and FIG. It is a Gummel plot when the InGaP emitter layer has an ordered arrangement structure and the n-type GaAs breakdown voltage adjusting layer 106 is introduced, or when the H ₂ gas flow is introduced on the surface of the n-type InGaP emitter layer 205.

  Also in the structure in the second embodiment, the same electrical characteristics as those obtained in the structure in the first embodiment can be obtained.

  That is, in the low Ic region, the base current is larger in (iii) than in (i) and (ii).

  Accordingly, in the low Ic region, (iii) has a lower current amplification factor hfe than (i) and (ii).

Therefore, when the base current Ib is 0, the BV _CEO is larger in (iii) than in (i) and (ii).

From these results, an interface state serving as a recombination center by H ₂ gas flow is positively formed at the interface between the n-type InGaP emitter layer and the n-type GaAs emitter cap layer, and the n-type InGaP emitter layer is ordered. By adopting the array structure, the base current Ib increases and the current amplification factor hfe decreases in the low Ic region, and as a result, BV _CEO improves. As a result, hfe in the high Ic region, which is the actual operating point of the transmission power amplifier, does not decrease, and a high breakdown voltage HBT is realized.

  As described above, according to the present invention, in an HBT used for a transmission power amplifier or the like, a high Ic region that is an actual operating point is considered from the viewpoint that hfe in a low Ic region that is not an actual operating point is not important. A high breakdown voltage HBT is realized by actively lowering only hfe in the low Ic region without lowering hfe.

  The HBT according to the present invention is not limited to the above embodiment. Other embodiments realized by combining arbitrary components in the first and second embodiments, and various modifications conceivable by those skilled in the art without departing from the gist of the present invention to the first and second embodiments. Variations obtained and various devices incorporating the HBT according to the present invention are also included in the present invention.

  For example, through Embodiments 1 and 2, the doping concentration, film thickness, and composition of each stacked film that is a constituent element of the HBT according to the present invention are arbitrary as long as they are suitable for the purpose of this structure.

  Further, as the substrate, not only GaAs but also Si may be used.

  Further, for controlling the doping concentration of each laminated film, not only Si and C but also other elements that meet the gist of the present invention can be used.

  Further, the HBT stacking method according to the present invention is not limited to the MOCVD method and the MBE method, and may be other film forming methods.

  The present invention is particularly useful for a transmission power amplifier for a mobile phone incorporating a heterojunction bipolar transistor, and is particularly suitable for use in a heterojunction bipolar transistor requiring a high breakdown voltage.

1 is a structural cross-sectional view of an HBT according to Embodiment 1 of the present invention. It is structural sectional drawing of HBT which concerns on Embodiment 2 of this invention. (A) is the comparison figure of the Gummel plot about HBT which concerns on Embodiment 1 and Embodiment 2 of this invention, and HBT of a conventional structure. FIG. 3B is a graph showing the relationship between the current amplification factor hfe and the collector current Ic obtained from FIG. (C) shows the relationship between the collector current Ic and the collector voltage V _CE, it is a graph illustrating for different base currents Ib. (A) is a schematic diagram of a unit crystal lattice of a group III-V mixed crystal semiconductor. (B) is the crystal structure figure which looked at InGaP perpendicularly | vertically with respect to the growth direction as an example of the III-V group mixed crystal semiconductor which has an ordered arrangement structure. It is a graph which shows the growth temperature dependence of the band gap of InGaP. (A) is sectional drawing of the device used for the experiment which investigates the carrier concentration distribution of an interface. (B) is a graph which shows the experimental result which investigated the carrier concentration distribution of an interface. It is structural sectional drawing of the conventional HBT. FIG. 6 is a structural cross-sectional view of an HBT described in Patent Document 1.

Explanation of symbols

3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h, 3i, 3j, 3k, 3l, 3n, 3n Group III atoms 5a, 5b, 5c, 5d Group V atoms 101, 201, 701, 801 GaAs substrate 102 , 202, 702 n ⁺ -type GaAs subcollector layer 103, 203, 703 n-type GaAs collector layer 104, 204, 704, 805 p-type GaAs base layer 105, 205, 705 n-type InGaP emitter layer 106 n-type GaAs breakdown voltage adjustment layer 107, 207, 707 n-type GaAs emitter cap layer 108, 208, 708 n ⁺ -type InGaAs contact layer 110, 210, 710 Collector electrode 120, 220, 720 Base electrode 130, 230, 730 Emitter electrode 802 Buffer layer 803 n ⁺ -type GaAs collector contact A layer 804 Type or i-type GaAs collector layer 806 n-type In _x Ga _1-x P emitter A layer 807 the charge compensation layer 808 n-type GaAs emitter B layer 809 n ⁺ -type GaAs emitter contact A layer 810 n ⁺ -type InGaAs emitter contact B layer

Claims (11)

A heterojunction bipolar transistor in which a collector layer made of a III-V compound semiconductor, a base layer, and an emitter layer are stacked on a semiconductor substrate,
The emitter layer is
First to third emitter layers stacked in order from the base layer,
The heterojunction bipolar transistor, wherein the second emitter layer has a lower doping concentration than the third emitter layer. The first emitter layer is an n-type InGaP emitter layer;
The second emitter layer is an n-type low concentration GaAs layer;
The heterojunction bipolar transistor according to claim 1, wherein the third emitter layer is an n-type GaAs emitter cap layer. The heterojunction bipolar transistor according to claim 2, wherein the second emitter layer is a GaAs layer having a doping concentration of 0 or more. A heterojunction bipolar transistor in which a collector layer made of a III-V compound semiconductor, a base layer, and an emitter layer are stacked on a semiconductor substrate,
The emitter layer is
First and third emitter layers stacked in order from the base layer,
The heterojunction bipolar transistor, wherein the first emitter layer has a level as a recombination center at an interface with the third emitter layer. The first emitter layer is an n-type InGaP emitter layer;
The heterojunction bipolar transistor according to claim 4, wherein the third emitter layer is an n-type GaAs emitter cap layer. 6. The level as the recombination center is formed by applying an H ₂ gas flow to the surface of the n-type InGaP emitter layer after the formation of the n-type InGaP emitter layer. Heterojunction bipolar transistor. The semiconductor substrate is a GaAs substrate;
The collector layer includes an n ⁺ -type GaAs subcollector layer and an n-type GaAs collector layer in order from the GaAs substrate,
The heterojunction bipolar transistor according to any one of claims 2, 3, 5, and 6, wherein the base layer is a p-type GaAs base layer joined to the n-type GaAs collector layer. The n-type InGaP emitter layer is partially or completely formed with a CuPt-type natural superlattice. 8. Heterojunction bipolar transistor. A method of manufacturing a heterojunction bipolar transistor in which a collector layer made of a III-V group compound semiconductor, a base layer, and an emitter layer are stacked on a GaAs substrate,
A collector stacking step of sequentially stacking an n ⁺ -type GaAs subcollector layer and an n-type GaAs collector layer as the collector layer on the GaAs substrate;
After the collector stacking step, a base stacking step of stacking a p-type GaAs base layer as the base layer;
After the base stacking step, as the emitter layer, an n-type InGaP emitter layer, an n-type low-concentration GaAs layer, and an n-type GaAs emitter cap layer having a doping concentration higher than that of the n-type low-concentration GaAs layer are sequentially provided. A method of manufacturing a heterojunction bipolar transistor, comprising: an emitter stacking step of stacking. A method of manufacturing a heterojunction bipolar transistor in which a collector layer made of a III-V group compound semiconductor, a base layer, and an emitter layer are stacked on a GaAs substrate,
A collector stacking step of sequentially stacking an n ⁺ -type GaAs subcollector layer and an n-type GaAs collector layer as the collector layer on the GaAs substrate;
After the collector stacking step, a base stacking step of stacking a p-type GaAs base layer as the base layer;
After the base stacking step, an n-type InGaP emitter layer is stacked as the emitter layer, an H ₂ gas flow is applied to the surface of the n-type InGaP emitter layer, and the n-type InGaP subjected to the H ₂ gas flow is applied. A method of manufacturing a heterojunction bipolar transistor, comprising: an emitter stacking step of stacking an n-type GaAs emitter cap layer on a surface of the emitter layer. 11. The method of manufacturing a heterojunction bipolar transistor according to claim 9, wherein the n-type InGaP emitter layer is partially or completely formed with a CuPt-type natural superlattice.

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